4 files changed, 33 insertions, 7 deletions

diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index af064d28b365..31d021506d21 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -610,6 +610,31 @@ out_and_saveregs:
         tm_save_sprs(thr);
 }
 
+extern void __tm_recheckpoint(struct thread_struct *thread,
+                              unsigned long orig_msr);
+
+void tm_recheckpoint(struct thread_struct *thread,
+                     unsigned long orig_msr)
+{
+        unsigned long flags;
+
+        /* We really can't be interrupted here as the TEXASR registers can't
+         * change and later in the trecheckpoint code, we have a userspace R1.
+         * So let's hard disable over this region.
+         */
+        local_irq_save(flags);
+        hard_irq_disable();
+
+        /* The TM SPRs are restored here, so that TEXASR.FS can be set
+         * before the trecheckpoint and no explosion occurs.
+         */
+        tm_restore_sprs(thread);
+
+        __tm_recheckpoint(thread, orig_msr);
+
+        local_irq_restore(flags);
+}
+
 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 {
         unsigned long msr;
@@ -628,13 +653,10 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new)
         if (!new->thread.regs)
                 return;
 
-        /* The TM SPRs are restored here, so that TEXASR.FS can be set
-         * before the trecheckpoint and no explosion occurs.
-         */
-        tm_restore_sprs(&new->thread);
-
-        if (!MSR_TM_ACTIVE(new->thread.regs->msr))
+        if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
+                tm_restore_sprs(&new->thread);
                 return;
+        }
         msr = new->thread.tm_orig_msr;
         /* Recheckpoint to restore original checkpointed register state. */
         TM_DEBUG("*** tm_recheckpoint of pid %d "
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index a67e00aa3caa..4e47db686b5d 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -881,6 +881,8 @@ static long restore_tm_user_regs(struct pt_regs *regs,
          * transactional versions should be loaded.
          */
         tm_enable();
+        /* Make sure the transaction is marked as failed */
+        current->thread.tm_texasr |= TEXASR_FS;
         /* This loads the checkpointed FP/VEC state, if used */
         tm_recheckpoint(&current->thread, msr);
         /* Get the top half of the MSR */
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 8d253c29649b..d501dc4dc3e6 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -527,6 +527,8 @@ static long restore_tm_sigcontexts(struct pt_regs *regs,
         }
 #endif
         tm_enable();
+        /* Make sure the transaction is marked as failed */
+        current->thread.tm_texasr |= TEXASR_FS;
         /* This loads the checkpointed FP/VEC state, if used */
         tm_recheckpoint(&current->thread, msr);
 
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index ef47bcbd4352..03567c05950a 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -307,7 +307,7 @@ dont_backup_fp:
          *      Call with IRQs off, stacks get all out of sync for
          *      some periods in here!
          */
-_GLOBAL(tm_recheckpoint)
+_GLOBAL(__tm_recheckpoint)
         mfcr    r5
         mflr    r0
         stw     r5, 8(r1)