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-rw-r--r--arch/x86/include/asm/apic.h314
-rw-r--r--arch/x86/include/asm/genapic.h312
2 files changed, 310 insertions, 316 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 4f56e053d347..c07f5fbf43c8 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -1,15 +1,18 @@
1#ifndef _ASM_X86_APIC_H 1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H 2#define _ASM_X86_APIC_H
3 3
4#include <linux/pm.h> 4#include <linux/cpumask.h>
5#include <linux/delay.h> 5#include <linux/delay.h>
6#include <linux/pm.h>
6 7
7#include <asm/alternative.h> 8#include <asm/alternative.h>
8#include <asm/fixmap.h> 9#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <asm/processor.h> 10#include <asm/processor.h>
11#include <asm/apicdef.h>
12#include <asm/atomic.h>
13#include <asm/fixmap.h>
14#include <asm/mpspec.h>
11#include <asm/system.h> 15#include <asm/system.h>
12#include <asm/cpufeature.h>
13#include <asm/msr.h> 16#include <asm/msr.h>
14 17
15#define ARCH_APICTIMER_STOPS_ON_C3 1 18#define ARCH_APICTIMER_STOPS_ON_C3 1
@@ -235,4 +238,307 @@ static inline void disable_local_APIC(void) { }
235 238
236#endif 239#endif
237 240
241/*
242 * Copyright 2004 James Cleverdon, IBM.
243 * Subject to the GNU Public License, v.2
244 *
245 * Generic APIC sub-arch data struct.
246 *
247 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
248 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
249 * James Cleverdon.
250 */
251struct genapic {
252 char *name;
253
254 int (*probe)(void);
255 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
256 int (*apic_id_registered)(void);
257
258 u32 irq_delivery_mode;
259 u32 irq_dest_mode;
260
261 const struct cpumask *(*target_cpus)(void);
262
263 int disable_esr;
264
265 int dest_logical;
266 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
267 unsigned long (*check_apicid_present)(int apicid);
268
269 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
270 void (*init_apic_ldr)(void);
271
272 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
273
274 void (*setup_apic_routing)(void);
275 int (*multi_timer_check)(int apic, int irq);
276 int (*apicid_to_node)(int logical_apicid);
277 int (*cpu_to_logical_apicid)(int cpu);
278 int (*cpu_present_to_apicid)(int mps_cpu);
279 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
280 void (*setup_portio_remap)(void);
281 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
282 void (*enable_apic_mode)(void);
283 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
284
285 /*
286 * When one of the next two hooks returns 1 the genapic
287 * is switched to this. Essentially they are additional
288 * probe functions:
289 */
290 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
291
292 unsigned int (*get_apic_id)(unsigned long x);
293 unsigned long (*set_apic_id)(unsigned int id);
294 unsigned long apic_id_mask;
295
296 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
297 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
298 const struct cpumask *andmask);
299
300 /* ipi */
301 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
302 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
303 int vector);
304 void (*send_IPI_allbutself)(int vector);
305 void (*send_IPI_all)(int vector);
306 void (*send_IPI_self)(int vector);
307
308 /* wakeup_secondary_cpu */
309 int (*wakeup_cpu)(int apicid, unsigned long start_eip);
310
311 int trampoline_phys_low;
312 int trampoline_phys_high;
313
314 void (*wait_for_init_deassert)(atomic_t *deassert);
315 void (*smp_callin_clear_local_apic)(void);
316 void (*store_NMI_vector)(unsigned short *high, unsigned short *low);
317 void (*inquire_remote_apic)(int apicid);
318
319 /* apic ops */
320 u32 (*read)(u32 reg);
321 void (*write)(u32 reg, u32 v);
322 u64 (*icr_read)(void);
323 void (*icr_write)(u32 low, u32 high);
324 void (*wait_icr_idle)(void);
325 u32 (*safe_wait_icr_idle)(void);
326};
327
328extern struct genapic *apic;
329
330static inline u32 apic_read(u32 reg)
331{
332 return apic->read(reg);
333}
334
335static inline void apic_write(u32 reg, u32 val)
336{
337 apic->write(reg, val);
338}
339
340static inline u64 apic_icr_read(void)
341{
342 return apic->icr_read();
343}
344
345static inline void apic_icr_write(u32 low, u32 high)
346{
347 apic->icr_write(low, high);
348}
349
350static inline void apic_wait_icr_idle(void)
351{
352 apic->wait_icr_idle();
353}
354
355static inline u32 safe_apic_wait_icr_idle(void)
356{
357 return apic->safe_wait_icr_idle();
358}
359
360
361static inline void ack_APIC_irq(void)
362{
363 /*
364 * ack_APIC_irq() actually gets compiled as a single instruction
365 * ... yummie.
366 */
367
368 /* Docs say use 0 for future compatibility */
369 apic_write(APIC_EOI, 0);
370}
371
372static inline unsigned default_get_apic_id(unsigned long x)
373{
374 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
375
376 if (APIC_XAPIC(ver))
377 return (x >> 24) & 0xFF;
378 else
379 return (x >> 24) & 0x0F;
380}
381
382/*
383 * Warm reset vector default position:
384 */
385#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
386#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
387
388#ifdef CONFIG_X86_32
389extern void es7000_update_genapic_to_cluster(void);
390#else
391extern struct genapic apic_flat;
392extern struct genapic apic_physflat;
393extern struct genapic apic_x2apic_cluster;
394extern struct genapic apic_x2apic_phys;
395extern int default_acpi_madt_oem_check(char *, char *);
396
397extern void apic_send_IPI_self(int vector);
398
399extern struct genapic apic_x2apic_uv_x;
400DECLARE_PER_CPU(int, x2apic_extra_bits);
401
402extern int default_cpu_present_to_apicid(int mps_cpu);
403extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
404#endif
405
406static inline void default_wait_for_init_deassert(atomic_t *deassert)
407{
408 while (!atomic_read(deassert))
409 cpu_relax();
410 return;
411}
412
413extern void generic_bigsmp_probe(void);
414
415
416#ifdef CONFIG_X86_LOCAL_APIC
417
418#include <asm/smp.h>
419
420#define APIC_DFR_VALUE (APIC_DFR_FLAT)
421
422static inline const struct cpumask *default_target_cpus(void)
423{
424#ifdef CONFIG_SMP
425 return cpu_online_mask;
426#else
427 return cpumask_of(0);
428#endif
429}
430
431DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
432
433
434static inline unsigned int read_apic_id(void)
435{
436 unsigned int reg;
437
438 reg = apic_read(APIC_ID);
439
440 return apic->get_apic_id(reg);
441}
442
443extern void default_setup_apic_routing(void);
444
445#ifdef CONFIG_X86_32
446/*
447 * Set up the logical destination ID.
448 *
449 * Intel recommends to set DFR, LDR and TPR before enabling
450 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
451 * document number 292116). So here it goes...
452 */
453extern void default_init_apic_ldr(void);
454
455static inline int default_apic_id_registered(void)
456{
457 return physid_isset(read_apic_id(), phys_cpu_present_map);
458}
459
460static inline unsigned int
461default_cpu_mask_to_apicid(const struct cpumask *cpumask)
462{
463 return cpumask_bits(cpumask)[0];
464}
465
466static inline unsigned int
467default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
468 const struct cpumask *andmask)
469{
470 unsigned long mask1 = cpumask_bits(cpumask)[0];
471 unsigned long mask2 = cpumask_bits(andmask)[0];
472 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
473
474 return (unsigned int)(mask1 & mask2 & mask3);
475}
476
477static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
478{
479 return cpuid_apic >> index_msb;
480}
481
482extern int default_apicid_to_node(int logical_apicid);
483
484#endif
485
486static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
487{
488 return physid_isset(apicid, bitmap);
489}
490
491static inline unsigned long default_check_apicid_present(int bit)
492{
493 return physid_isset(bit, phys_cpu_present_map);
494}
495
496static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
497{
498 return phys_map;
499}
500
501/* Mapping from cpu number to logical apicid */
502static inline int default_cpu_to_logical_apicid(int cpu)
503{
504 return 1 << cpu;
505}
506
507static inline int __default_cpu_present_to_apicid(int mps_cpu)
508{
509 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
510 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
511 else
512 return BAD_APICID;
513}
514
515static inline int
516__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
517{
518 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
519}
520
521#ifdef CONFIG_X86_32
522static inline int default_cpu_present_to_apicid(int mps_cpu)
523{
524 return __default_cpu_present_to_apicid(mps_cpu);
525}
526
527static inline int
528default_check_phys_apicid_present(int boot_cpu_physical_apicid)
529{
530 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
531}
532#else
533extern int default_cpu_present_to_apicid(int mps_cpu);
534extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
535#endif
536
537static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
538{
539 return physid_mask_of_physid(phys_apicid);
540}
541
542#endif /* CONFIG_X86_LOCAL_APIC */
543
238#endif /* _ASM_X86_APIC_H */ 544#endif /* _ASM_X86_APIC_H */
diff --git a/arch/x86/include/asm/genapic.h b/arch/x86/include/asm/genapic.h
index 9b874a386837..4b8b98fa7f25 100644
--- a/arch/x86/include/asm/genapic.h
+++ b/arch/x86/include/asm/genapic.h
@@ -1,313 +1 @@
1#ifndef _ASM_X86_GENAPIC_H
2#define _ASM_X86_GENAPIC_H
3
4#include <linux/cpumask.h>
5
6#include <asm/mpspec.h>
7#include <asm/atomic.h>
8#include <asm/apic.h> #include <asm/apic.h>
9
10/*
11 * Copyright 2004 James Cleverdon, IBM.
12 * Subject to the GNU Public License, v.2
13 *
14 * Generic APIC sub-arch data struct.
15 *
16 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
17 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
18 * James Cleverdon.
19 */
20struct genapic {
21 char *name;
22
23 int (*probe)(void);
24 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
25 int (*apic_id_registered)(void);
26
27 u32 irq_delivery_mode;
28 u32 irq_dest_mode;
29
30 const struct cpumask *(*target_cpus)(void);
31
32 int disable_esr;
33
34 int dest_logical;
35 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
36 unsigned long (*check_apicid_present)(int apicid);
37
38 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
39 void (*init_apic_ldr)(void);
40
41 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
42
43 void (*setup_apic_routing)(void);
44 int (*multi_timer_check)(int apic, int irq);
45 int (*apicid_to_node)(int logical_apicid);
46 int (*cpu_to_logical_apicid)(int cpu);
47 int (*cpu_present_to_apicid)(int mps_cpu);
48 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
49 void (*setup_portio_remap)(void);
50 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
51 void (*enable_apic_mode)(void);
52 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
53
54 /*
55 * When one of the next two hooks returns 1 the genapic
56 * is switched to this. Essentially they are additional
57 * probe functions:
58 */
59 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
60
61 unsigned int (*get_apic_id)(unsigned long x);
62 unsigned long (*set_apic_id)(unsigned int id);
63 unsigned long apic_id_mask;
64
65 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
66 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
67 const struct cpumask *andmask);
68
69 /* ipi */
70 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
71 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
72 int vector);
73 void (*send_IPI_allbutself)(int vector);
74 void (*send_IPI_all)(int vector);
75 void (*send_IPI_self)(int vector);
76
77 /* wakeup_secondary_cpu */
78 int (*wakeup_cpu)(int apicid, unsigned long start_eip);
79
80 int trampoline_phys_low;
81 int trampoline_phys_high;
82
83 void (*wait_for_init_deassert)(atomic_t *deassert);
84 void (*smp_callin_clear_local_apic)(void);
85 void (*store_NMI_vector)(unsigned short *high, unsigned short *low);
86 void (*inquire_remote_apic)(int apicid);
87
88 /* apic ops */
89 u32 (*read)(u32 reg);
90 void (*write)(u32 reg, u32 v);
91 u64 (*icr_read)(void);
92 void (*icr_write)(u32 low, u32 high);
93 void (*wait_icr_idle)(void);
94 u32 (*safe_wait_icr_idle)(void);
95};
96
97extern struct genapic *apic;
98
99static inline u32 apic_read(u32 reg)
100{
101 return apic->read(reg);
102}
103
104static inline void apic_write(u32 reg, u32 val)
105{
106 apic->write(reg, val);
107}
108
109static inline u64 apic_icr_read(void)
110{
111 return apic->icr_read();
112}
113
114static inline void apic_icr_write(u32 low, u32 high)
115{
116 apic->icr_write(low, high);
117}
118
119static inline void apic_wait_icr_idle(void)
120{
121 apic->wait_icr_idle();
122}
123
124static inline u32 safe_apic_wait_icr_idle(void)
125{
126 return apic->safe_wait_icr_idle();
127}
128
129
130static inline void ack_APIC_irq(void)
131{
132 /*
133 * ack_APIC_irq() actually gets compiled as a single instruction
134 * ... yummie.
135 */
136
137 /* Docs say use 0 for future compatibility */
138 apic_write(APIC_EOI, 0);
139}
140
141static inline unsigned default_get_apic_id(unsigned long x)
142{
143 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
144
145 if (APIC_XAPIC(ver))
146 return (x >> 24) & 0xFF;
147 else
148 return (x >> 24) & 0x0F;
149}
150
151/*
152 * Warm reset vector default position:
153 */
154#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
155#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
156
157#ifdef CONFIG_X86_32
158extern void es7000_update_genapic_to_cluster(void);
159#else
160extern struct genapic apic_flat;
161extern struct genapic apic_physflat;
162extern struct genapic apic_x2apic_cluster;
163extern struct genapic apic_x2apic_phys;
164extern int default_acpi_madt_oem_check(char *, char *);
165
166extern void apic_send_IPI_self(int vector);
167
168extern struct genapic apic_x2apic_uv_x;
169DECLARE_PER_CPU(int, x2apic_extra_bits);
170
171extern int default_cpu_present_to_apicid(int mps_cpu);
172extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
173#endif
174
175static inline void default_wait_for_init_deassert(atomic_t *deassert)
176{
177 while (!atomic_read(deassert))
178 cpu_relax();
179 return;
180}
181
182extern void generic_bigsmp_probe(void);
183
184
185#ifdef CONFIG_X86_LOCAL_APIC
186
187#include <asm/smp.h>
188
189#define APIC_DFR_VALUE (APIC_DFR_FLAT)
190
191static inline const struct cpumask *default_target_cpus(void)
192{
193#ifdef CONFIG_SMP
194 return cpu_online_mask;
195#else
196 return cpumask_of(0);
197#endif
198}
199
200DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
201
202
203static inline unsigned int read_apic_id(void)
204{
205 unsigned int reg;
206
207 reg = apic_read(APIC_ID);
208
209 return apic->get_apic_id(reg);
210}
211
212extern void default_setup_apic_routing(void);
213
214#ifdef CONFIG_X86_32
215/*
216 * Set up the logical destination ID.
217 *
218 * Intel recommends to set DFR, LDR and TPR before enabling
219 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
220 * document number 292116). So here it goes...
221 */
222extern void default_init_apic_ldr(void);
223
224static inline int default_apic_id_registered(void)
225{
226 return physid_isset(read_apic_id(), phys_cpu_present_map);
227}
228
229static inline unsigned int
230default_cpu_mask_to_apicid(const struct cpumask *cpumask)
231{
232 return cpumask_bits(cpumask)[0];
233}
234
235static inline unsigned int
236default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
237 const struct cpumask *andmask)
238{
239 unsigned long mask1 = cpumask_bits(cpumask)[0];
240 unsigned long mask2 = cpumask_bits(andmask)[0];
241 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
242
243 return (unsigned int)(mask1 & mask2 & mask3);
244}
245
246static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
247{
248 return cpuid_apic >> index_msb;
249}
250
251extern int default_apicid_to_node(int logical_apicid);
252
253#endif
254
255static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
256{
257 return physid_isset(apicid, bitmap);
258}
259
260static inline unsigned long default_check_apicid_present(int bit)
261{
262 return physid_isset(bit, phys_cpu_present_map);
263}
264
265static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
266{
267 return phys_map;
268}
269
270/* Mapping from cpu number to logical apicid */
271static inline int default_cpu_to_logical_apicid(int cpu)
272{
273 return 1 << cpu;
274}
275
276static inline int __default_cpu_present_to_apicid(int mps_cpu)
277{
278 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
279 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
280 else
281 return BAD_APICID;
282}
283
284static inline int
285__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
286{
287 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
288}
289
290#ifdef CONFIG_X86_32
291static inline int default_cpu_present_to_apicid(int mps_cpu)
292{
293 return __default_cpu_present_to_apicid(mps_cpu);
294}
295
296static inline int
297default_check_phys_apicid_present(int boot_cpu_physical_apicid)
298{
299 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
300}
301#else
302extern int default_cpu_present_to_apicid(int mps_cpu);
303extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
304#endif
305
306static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
307{
308 return physid_mask_of_physid(phys_apicid);
309}
310
311#endif /* CONFIG_X86_LOCAL_APIC */
312
313#endif /* _ASM_X86_GENAPIC_64_H */
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