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-rw-r--r--arch/powerpc/boot/dts/a3m071.dts6
-rw-r--r--arch/powerpc/boot/dts/a4m072.dts27
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts6
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts14
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts23
-rw-r--r--arch/powerpc/boot/dts/media5200.dts6
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts26
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi410
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts319
-rw-r--r--arch/powerpc/boot/dts/mpc5200b.dtsi25
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts48
-rw-r--r--arch/powerpc/boot/dts/o2d.dtsi27
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts48
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts45
-rw-r--r--arch/powerpc/boot/dts/pdm360ng.dts273
-rw-r--r--arch/powerpc/boot/dts/uc101.dts52
-rw-r--r--arch/powerpc/include/asm/mpc5121.h17
-rw-r--r--arch/powerpc/platforms/512x/clock.c34
-rw-r--r--arch/powerpc/platforms/512x/mpc512x_shared.c32
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c6
-rw-r--r--arch/powerpc/platforms/Kconfig2
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/bestcomm/Kconfig36
-rw-r--r--arch/powerpc/sysdev/bestcomm/Makefile14
-rw-r--r--arch/powerpc/sysdev/bestcomm/ata.c157
-rw-r--r--arch/powerpc/sysdev/bestcomm/ata.h30
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_ata_task.c67
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c78
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c91
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c63
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c69
-rw-r--r--arch/powerpc/sysdev/bestcomm/bestcomm.c531
-rw-r--r--arch/powerpc/sysdev/bestcomm/bestcomm.h213
-rw-r--r--arch/powerpc/sysdev/bestcomm/bestcomm_priv.h350
-rw-r--r--arch/powerpc/sysdev/bestcomm/fec.c270
-rw-r--r--arch/powerpc/sysdev/bestcomm/fec.h61
-rw-r--r--arch/powerpc/sysdev/bestcomm/gen_bd.c354
-rw-r--r--arch/powerpc/sysdev/bestcomm/gen_bd.h53
-rw-r--r--arch/powerpc/sysdev/bestcomm/sram.c178
-rw-r--r--arch/powerpc/sysdev/bestcomm/sram.h54
-rw-r--r--arch/powerpc/sysdev/mpc5xxx_clocks.c4
41 files changed, 656 insertions, 3464 deletions
diff --git a/arch/powerpc/boot/dts/a3m071.dts b/arch/powerpc/boot/dts/a3m071.dts
index 877a28cb77e4..bf81b8f9704c 100644
--- a/arch/powerpc/boot/dts/a3m071.dts
+++ b/arch/powerpc/boot/dts/a3m071.dts
@@ -17,6 +17,8 @@
17 17
18/include/ "mpc5200b.dtsi" 18/include/ "mpc5200b.dtsi"
19 19
20&gpt0 { fsl,has-wdt; };
21
20/ { 22/ {
21 model = "anonymous,a3m071"; 23 model = "anonymous,a3m071";
22 compatible = "anonymous,a3m071"; 24 compatible = "anonymous,a3m071";
@@ -30,10 +32,6 @@
30 bus-frequency = <0>; /* From boot loader */ 32 bus-frequency = <0>; /* From boot loader */
31 system-frequency = <0>; /* From boot loader */ 33 system-frequency = <0>; /* From boot loader */
32 34
33 timer@600 {
34 fsl,has-wdt;
35 };
36
37 spi@f00 { 35 spi@f00 {
38 status = "disabled"; 36 status = "disabled";
39 }; 37 };
diff --git a/arch/powerpc/boot/dts/a4m072.dts b/arch/powerpc/boot/dts/a4m072.dts
index fabe7b7d5f13..1f02034c7e99 100644
--- a/arch/powerpc/boot/dts/a4m072.dts
+++ b/arch/powerpc/boot/dts/a4m072.dts
@@ -15,6 +15,11 @@
15 15
16/include/ "mpc5200b.dtsi" 16/include/ "mpc5200b.dtsi"
17 17
18&gpt0 { fsl,has-wdt; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22
18/ { 23/ {
19 model = "anonymous,a4m072"; 24 model = "anonymous,a4m072";
20 compatible = "anonymous,a4m072"; 25 compatible = "anonymous,a4m072";
@@ -34,28 +39,6 @@
34 fsl,init-fd-counters = <0x3333>; 39 fsl,init-fd-counters = <0x3333>;
35 }; 40 };
36 41
37 timer@600 {
38 fsl,has-wdt;
39 };
40
41 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
42 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
43 gpio-controller;
44 #gpio-cells = <2>;
45 };
46
47 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
48 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
49 gpio-controller;
50 #gpio-cells = <2>;
51 };
52
53 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
54 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 spi@f00 { 42 spi@f00 {
60 status = "disabled"; 43 status = "disabled";
61 }; 44 };
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index ad3a4f4a2b04..fb580dd84ddf 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -12,15 +12,13 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16
15/ { 17/ {
16 model = "schindler,cm5200"; 18 model = "schindler,cm5200";
17 compatible = "schindler,cm5200"; 19 compatible = "schindler,cm5200";
18 20
19 soc5200@f0000000 { 21 soc5200@f0000000 {
20 timer@600 { // General Purpose Timer
21 fsl,has-wdt;
22 };
23
24 can@900 { 22 can@900 {
25 status = "disabled"; 23 status = "disabled";
26 }; 24 };
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index a7511f2d844d..955bff629df3 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -13,6 +13,9 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { gpio-controller; fsl,has-wdt; };
17&gpt1 { gpio-controller; };
18
16/ { 19/ {
17 model = "intercontrol,digsy-mtc"; 20 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc"; 21 compatible = "intercontrol,digsy-mtc";
@@ -22,17 +25,6 @@
22 }; 25 };
23 26
24 soc5200@f0000000 { 27 soc5200@f0000000 {
25 timer@600 { // General Purpose Timer
26 #gpio-cells = <2>;
27 fsl,has-wdt;
28 gpio-controller;
29 };
30
31 timer@610 {
32 #gpio-cells = <2>;
33 gpio-controller;
34 };
35
36 rtc@800 { 28 rtc@800 {
37 status = "disabled"; 29 status = "disabled";
38 }; 30 };
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index fb288bb882b6..5abb46c5cc95 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -12,19 +12,34 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16&gpt2 { gpio-controller; };
17&gpt3 { gpio-controller; };
18
15/ { 19/ {
16 model = "fsl,lite5200b"; 20 model = "fsl,lite5200b";
17 compatible = "fsl,lite5200b"; 21 compatible = "fsl,lite5200b";
18 22
23 leds {
24 compatible = "gpio-leds";
25 tmr2 {
26 gpios = <&gpt2 0 1>;
27 };
28 tmr3 {
29 gpios = <&gpt3 0 1>;
30 linux,default-trigger = "heartbeat";
31 };
32 led1 { gpios = <&gpio_wkup 2 1>; };
33 led2 { gpios = <&gpio_simple 3 1>; };
34 led3 { gpios = <&gpio_wkup 3 1>; };
35 led4 { gpios = <&gpio_simple 2 1>; };
36 };
37
19 memory { 38 memory {
20 reg = <0x00000000 0x10000000>; // 256MB 39 reg = <0x00000000 0x10000000>; // 256MB
21 }; 40 };
22 41
23 soc5200@f0000000 { 42 soc5200@f0000000 {
24 timer@600 { // General Purpose Timer
25 fsl,has-wdt;
26 };
27
28 psc@2000 { // PSC1 43 psc@2000 { // PSC1
29 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 44 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
30 cell-index = <0>; 45 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 48d72f38e5ed..b5413cb85f13 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -13,6 +13,8 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { fsl,has-wdt; };
17
16/ { 18/ {
17 model = "fsl,media5200"; 19 model = "fsl,media5200";
18 compatible = "fsl,media5200"; 20 compatible = "fsl,media5200";
@@ -41,10 +43,6 @@
41 soc5200@f0000000 { 43 soc5200@f0000000 {
42 bus-frequency = <132000000>;// 132 MHz 44 bus-frequency = <132000000>;// 132 MHz
43 45
44 timer@600 { // General Purpose Timer
45 fsl,has-wdt;
46 };
47
48 psc@2000 { // PSC1 46 psc@2000 { // PSC1
49 status = "disabled"; 47 status = "disabled";
50 }; 48 };
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 0b78e89ac69b..bbabd97492ad 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -12,26 +12,22 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16&gpt6 { // Motion-PRO status LED
17 compatible = "promess,motionpro-led";
18 label = "motionpro-statusled";
19 blink-delay = <100>; // 100 msec
20};
21&gpt7 { // Motion-PRO ready LED
22 compatible = "promess,motionpro-led";
23 label = "motionpro-readyled";
24};
25
15/ { 26/ {
16 model = "promess,motionpro"; 27 model = "promess,motionpro";
17 compatible = "promess,motionpro"; 28 compatible = "promess,motionpro";
18 29
19 soc5200@f0000000 { 30 soc5200@f0000000 {
20 timer@600 { // General Purpose Timer
21 fsl,has-wdt;
22 };
23
24 timer@660 { // Motion-PRO status LED
25 compatible = "promess,motionpro-led";
26 label = "motionpro-statusled";
27 blink-delay = <100>; // 100 msec
28 };
29
30 timer@670 { // Motion-PRO ready LED
31 compatible = "promess,motionpro-led";
32 label = "motionpro-readyled";
33 };
34
35 can@900 { 31 can@900 {
36 status = "disabled"; 32 status = "disabled";
37 }; 33 };
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
new file mode 100644
index 000000000000..723e292b6b4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -0,0 +1,410 @@
1/*
2 * base MPC5121 Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "mpc5121";
16 compatible = "fsl,mpc5121";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
20
21 aliases {
22 ethernet0 = &eth0;
23 pci = &pci;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,5121@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <0x20>; /* 32 bytes */
34 i-cache-line-size = <0x20>; /* 32 bytes */
35 d-cache-size = <0x8000>; /* L1, 32K */
36 i-cache-size = <0x8000>; /* L1, 32K */
37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
38 bus-frequency = <198000000>; /* 198 MHz csb bus */
39 clock-frequency = <396000000>; /* 396 MHz ppc core */
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
46 };
47
48 mbx@20000000 {
49 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>;
52 };
53
54 sram@30000000 {
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
57 };
58
59 nfc@40000000 {
60 compatible = "fsl,mpc5121-nfc";
61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
62 interrupts = <6 8>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 };
66
67 localbus@80000020 {
68 compatible = "fsl,mpc5121-localbus";
69 #address-cells = <2>;
70 #size-cells = <1>;
71 reg = <0x80000020 0x40>;
72 interrupts = <7 0x8>;
73 ranges = <0x0 0x0 0xfc000000 0x04000000>;
74 };
75
76 soc@80000000 {
77 compatible = "fsl,mpc5121-immr";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 #interrupt-cells = <2>;
81 ranges = <0x0 0x80000000 0x400000>;
82 reg = <0x80000000 0x400000>;
83 bus-frequency = <66000000>; /* 66 MHz ips bus */
84
85
86 /*
87 * IPIC
88 * interrupts cell = <intr #, sense>
89 * sense values match linux IORESOURCE_IRQ_* defines:
90 * sense == 8: Level, low assertion
91 * sense == 2: Edge, high-to-low change
92 */
93 ipic: interrupt-controller@c00 {
94 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
95 interrupt-controller;
96 #address-cells = <0>;
97 #interrupt-cells = <2>;
98 reg = <0xc00 0x100>;
99 };
100
101 /* Watchdog timer */
102 wdt@900 {
103 compatible = "fsl,mpc5121-wdt";
104 reg = <0x900 0x100>;
105 };
106
107 /* Real time clock */
108 rtc@a00 {
109 compatible = "fsl,mpc5121-rtc";
110 reg = <0xa00 0x100>;
111 interrupts = <79 0x8 80 0x8>;
112 };
113
114 /* Reset module */
115 reset@e00 {
116 compatible = "fsl,mpc5121-reset";
117 reg = <0xe00 0x100>;
118 };
119
120 /* Clock control */
121 clock@f00 {
122 compatible = "fsl,mpc5121-clock";
123 reg = <0xf00 0x100>;
124 };
125
126 /* Power Management Controller */
127 pmc@1000{
128 compatible = "fsl,mpc5121-pmc";
129 reg = <0x1000 0x100>;
130 interrupts = <83 0x8>;
131 };
132
133 gpio@1100 {
134 compatible = "fsl,mpc5121-gpio";
135 reg = <0x1100 0x100>;
136 interrupts = <78 0x8>;
137 };
138
139 can@1300 {
140 compatible = "fsl,mpc5121-mscan";
141 reg = <0x1300 0x80>;
142 interrupts = <12 0x8>;
143 };
144
145 can@1380 {
146 compatible = "fsl,mpc5121-mscan";
147 reg = <0x1380 0x80>;
148 interrupts = <13 0x8>;
149 };
150
151 sdhc@1500 {
152 compatible = "fsl,mpc5121-sdhc";
153 reg = <0x1500 0x100>;
154 interrupts = <8 0x8>;
155 };
156
157 i2c@1700 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
161 reg = <0x1700 0x20>;
162 interrupts = <9 0x8>;
163 };
164
165 i2c@1720 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
169 reg = <0x1720 0x20>;
170 interrupts = <10 0x8>;
171 };
172
173 i2c@1740 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
177 reg = <0x1740 0x20>;
178 interrupts = <11 0x8>;
179 };
180
181 i2ccontrol@1760 {
182 compatible = "fsl,mpc5121-i2c-ctrl";
183 reg = <0x1760 0x8>;
184 };
185
186 axe@2000 {
187 compatible = "fsl,mpc5121-axe";
188 reg = <0x2000 0x100>;
189 interrupts = <42 0x8>;
190 };
191
192 display@2100 {
193 compatible = "fsl,mpc5121-diu";
194 reg = <0x2100 0x100>;
195 interrupts = <64 0x8>;
196 };
197
198 can@2300 {
199 compatible = "fsl,mpc5121-mscan";
200 reg = <0x2300 0x80>;
201 interrupts = <90 0x8>;
202 };
203
204 can@2380 {
205 compatible = "fsl,mpc5121-mscan";
206 reg = <0x2380 0x80>;
207 interrupts = <91 0x8>;
208 };
209
210 viu@2400 {
211 compatible = "fsl,mpc5121-viu";
212 reg = <0x2400 0x400>;
213 interrupts = <67 0x8>;
214 };
215
216 mdio@2800 {
217 compatible = "fsl,mpc5121-fec-mdio";
218 reg = <0x2800 0x800>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 eth0: ethernet@2800 {
224 device_type = "network";
225 compatible = "fsl,mpc5121-fec";
226 reg = <0x2800 0x800>;
227 local-mac-address = [ 00 00 00 00 00 00 ];
228 interrupts = <4 0x8>;
229 };
230
231 /* USB1 using external ULPI PHY */
232 usb@3000 {
233 compatible = "fsl,mpc5121-usb2-dr";
234 reg = <0x3000 0x600>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 interrupts = <43 0x8>;
238 dr_mode = "otg";
239 phy_type = "ulpi";
240 };
241
242 /* USB0 using internal UTMI PHY */
243 usb@4000 {
244 compatible = "fsl,mpc5121-usb2-dr";
245 reg = <0x4000 0x600>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 interrupts = <44 0x8>;
249 dr_mode = "otg";
250 phy_type = "utmi_wide";
251 };
252
253 /* IO control */
254 ioctl@a000 {
255 compatible = "fsl,mpc5121-ioctl";
256 reg = <0xA000 0x1000>;
257 };
258
259 /* LocalPlus controller */
260 lpc@10000 {
261 compatible = "fsl,mpc5121-lpc";
262 reg = <0x10000 0x200>;
263 };
264
265 pata@10200 {
266 compatible = "fsl,mpc5121-pata";
267 reg = <0x10200 0x100>;
268 interrupts = <5 0x8>;
269 };
270
271 /* 512x PSCs are not 52xx PSC compatible */
272
273 /* PSC0 */
274 psc@11000 {
275 compatible = "fsl,mpc5121-psc";
276 reg = <0x11000 0x100>;
277 interrupts = <40 0x8>;
278 fsl,rx-fifo-size = <16>;
279 fsl,tx-fifo-size = <16>;
280 };
281
282 /* PSC1 */
283 psc@11100 {
284 compatible = "fsl,mpc5121-psc";
285 reg = <0x11100 0x100>;
286 interrupts = <40 0x8>;
287 fsl,rx-fifo-size = <16>;
288 fsl,tx-fifo-size = <16>;
289 };
290
291 /* PSC2 */
292 psc@11200 {
293 compatible = "fsl,mpc5121-psc";
294 reg = <0x11200 0x100>;
295 interrupts = <40 0x8>;
296 fsl,rx-fifo-size = <16>;
297 fsl,tx-fifo-size = <16>;
298 };
299
300 /* PSC3 */
301 psc@11300 {
302 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
303 reg = <0x11300 0x100>;
304 interrupts = <40 0x8>;
305 fsl,rx-fifo-size = <16>;
306 fsl,tx-fifo-size = <16>;
307 };
308
309 /* PSC4 */
310 psc@11400 {
311 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
312 reg = <0x11400 0x100>;
313 interrupts = <40 0x8>;
314 fsl,rx-fifo-size = <16>;
315 fsl,tx-fifo-size = <16>;
316 };
317
318 /* PSC5 */
319 psc@11500 {
320 compatible = "fsl,mpc5121-psc";
321 reg = <0x11500 0x100>;
322 interrupts = <40 0x8>;
323 fsl,rx-fifo-size = <16>;
324 fsl,tx-fifo-size = <16>;
325 };
326
327 /* PSC6 */
328 psc@11600 {
329 compatible = "fsl,mpc5121-psc";
330 reg = <0x11600 0x100>;
331 interrupts = <40 0x8>;
332 fsl,rx-fifo-size = <16>;
333 fsl,tx-fifo-size = <16>;
334 };
335
336 /* PSC7 */
337 psc@11700 {
338 compatible = "fsl,mpc5121-psc";
339 reg = <0x11700 0x100>;
340 interrupts = <40 0x8>;
341 fsl,rx-fifo-size = <16>;
342 fsl,tx-fifo-size = <16>;
343 };
344
345 /* PSC8 */
346 psc@11800 {
347 compatible = "fsl,mpc5121-psc";
348 reg = <0x11800 0x100>;
349 interrupts = <40 0x8>;
350 fsl,rx-fifo-size = <16>;
351 fsl,tx-fifo-size = <16>;
352 };
353
354 /* PSC9 */
355 psc@11900 {
356 compatible = "fsl,mpc5121-psc";
357 reg = <0x11900 0x100>;
358 interrupts = <40 0x8>;
359 fsl,rx-fifo-size = <16>;
360 fsl,tx-fifo-size = <16>;
361 };
362
363 /* PSC10 */
364 psc@11a00 {
365 compatible = "fsl,mpc5121-psc";
366 reg = <0x11a00 0x100>;
367 interrupts = <40 0x8>;
368 fsl,rx-fifo-size = <16>;
369 fsl,tx-fifo-size = <16>;
370 };
371
372 /* PSC11 */
373 psc@11b00 {
374 compatible = "fsl,mpc5121-psc";
375 reg = <0x11b00 0x100>;
376 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16>;
378 fsl,tx-fifo-size = <16>;
379 };
380
381 pscfifo@11f00 {
382 compatible = "fsl,mpc5121-psc-fifo";
383 reg = <0x11f00 0x100>;
384 interrupts = <40 0x8>;
385 };
386
387 dma@14000 {
388 compatible = "fsl,mpc5121-dma";
389 reg = <0x14000 0x1800>;
390 interrupts = <65 0x8>;
391 };
392 };
393
394 pci: pci@80008500 {
395 compatible = "fsl,mpc5121-pci";
396 device_type = "pci";
397 interrupts = <1 0x8>;
398 clock-frequency = <0>;
399 #address-cells = <3>;
400 #size-cells = <2>;
401 #interrupt-cells = <1>;
402
403 reg = <0x80008500 0x100 /* internal registers */
404 0x80008300 0x8>; /* config space access registers */
405 bus-range = <0x0 0x0>;
406 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
407 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
408 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
409 };
410};
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c9ef6bbe26cf..f269b1382ef7 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC5121E ADS Device Tree Source 2 * MPC5121E ADS Device Tree Source
3 * 3 *
4 * Copyright 2007,2008 Freescale Semiconductor Inc. 4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,74 +9,26 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc5121.dtsi"
13 13
14/ { 14/ {
15 model = "mpc5121ads"; 15 model = "mpc5121ads";
16 compatible = "fsl,mpc5121ads"; 16 compatible = "fsl,mpc5121ads";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 pci = &pci;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5121@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <0x8000>; // L1, 32K
34 i-cache-size = <0x8000>; // L1, 32K
35 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
36 bus-frequency = <198000000>; // 198 MHz csb bus
37 clock-frequency = <396000000>; // 396 MHz ppc core
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>; // 256MB at 0
44 };
45
46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
50 interrupt-parent = < &ipic >;
51 };
52
53 sram@30000000 {
54 compatible = "fsl,mpc5121-sram";
55 reg = <0x30000000 0x20000>; // 128K at 0x30000000
56 };
57 17
58 nfc@40000000 { 18 nfc@40000000 {
59 compatible = "fsl,mpc5121-nfc"; 19 /*
60 reg = <0x40000000 0x100000>; // 1M at 0x40000000 20 * ADS has two Hynix 512MB Nand flash chips in a single
61 interrupts = <6 8>; 21 * stacked package.
62 interrupt-parent = < &ipic >; 22 */
63 #address-cells = <1>;
64 #size-cells = <1>;
65 // ADS has two Hynix 512MB Nand flash chips in a single
66 // stacked package.
67 chips = <2>; 23 chips = <2>;
24
68 nand@0 { 25 nand@0 {
69 label = "nand"; 26 label = "nand";
70 reg = <0x00000000 0x40000000>; // 512MB + 512MB 27 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
71 }; 28 };
72 }; 29 };
73 30
74 localbus@80000020 { 31 localbus@80000020 {
75 compatible = "fsl,mpc5121-localbus";
76 #address-cells = <2>;
77 #size-cells = <1>;
78 reg = <0x80000020 0x40>;
79
80 ranges = <0x0 0x0 0xfc000000 0x04000000 32 ranges = <0x0 0x0 0xfc000000 0x04000000
81 0x2 0x0 0x82000000 0x00008000>; 33 0x2 0x0 0x82000000 0x00008000>;
82 34
@@ -87,6 +39,7 @@
87 #size-cells = <1>; 39 #size-cells = <1>;
88 bank-width = <4>; 40 bank-width = <4>;
89 device-width = <2>; 41 device-width = <2>;
42
90 protected@0 { 43 protected@0 {
91 label = "protected"; 44 label = "protected";
92 reg = <0x00000000 0x00040000>; // first sector is protected 45 reg = <0x00000000 0x00040000>; // first sector is protected
@@ -121,91 +74,18 @@
121 interrupt-controller; 74 interrupt-controller;
122 #interrupt-cells = <2>; 75 #interrupt-cells = <2>;
123 reg = <0x2 0xa 0x5>; 76 reg = <0x2 0xa 0x5>;
124 interrupt-parent = < &ipic >; 77 /* irq routing:
125 // irq routing 78 * all irqs but touch screen are routed to irq0 (ipic 48)
126 // all irqs but touch screen are routed to irq0 (ipic 48) 79 * touch screen is statically routed to irq1 (ipic 17)
127 // touch screen is statically routed to irq1 (ipic 17) 80 * so don't use it here
128 // so don't use it here 81 */
129 interrupts = <48 0x8>; 82 interrupts = <48 0x8>;
130 }; 83 };
131 }; 84 };
132 85
133 soc@80000000 { 86 soc@80000000 {
134 compatible = "fsl,mpc5121-immr";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 #interrupt-cells = <2>;
138 ranges = <0x0 0x80000000 0x400000>;
139 reg = <0x80000000 0x400000>;
140 bus-frequency = <66000000>; // 66 MHz ips bus
141
142
143 // IPIC
144 // interrupts cell = <intr #, sense>
145 // sense values match linux IORESOURCE_IRQ_* defines:
146 // sense == 8: Level, low assertion
147 // sense == 2: Edge, high-to-low change
148 //
149 ipic: interrupt-controller@c00 {
150 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <2>;
154 reg = <0xc00 0x100>;
155 };
156
157 rtc@a00 { // Real time clock
158 compatible = "fsl,mpc5121-rtc";
159 reg = <0xa00 0x100>;
160 interrupts = <79 0x8 80 0x8>;
161 interrupt-parent = < &ipic >;
162 };
163
164 reset@e00 { // Reset module
165 compatible = "fsl,mpc5121-reset";
166 reg = <0xe00 0x100>;
167 };
168
169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>;
172 };
173
174 pmc@1000{ //Power Management Controller
175 compatible = "fsl,mpc5121-pmc";
176 reg = <0x1000 0x100>;
177 interrupts = <83 0x2>;
178 interrupt-parent = < &ipic >;
179 };
180
181 gpio@1100 {
182 compatible = "fsl,mpc5121-gpio";
183 reg = <0x1100 0x100>;
184 interrupts = <78 0x8>;
185 interrupt-parent = < &ipic >;
186 };
187
188 can@1300 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <12 0x8>;
191 interrupt-parent = < &ipic >;
192 reg = <0x1300 0x80>;
193 };
194
195 can@1380 {
196 compatible = "fsl,mpc5121-mscan";
197 interrupts = <13 0x8>;
198 interrupt-parent = < &ipic >;
199 reg = <0x1380 0x80>;
200 };
201 87
202 i2c@1700 { 88 i2c@1700 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
206 reg = <0x1700 0x20>;
207 interrupts = <9 0x8>;
208 interrupt-parent = < &ipic >;
209 fsl,preserve-clocking; 89 fsl,preserve-clocking;
210 90
211 hwmon@4a { 91 hwmon@4a {
@@ -224,196 +104,75 @@
224 }; 104 };
225 }; 105 };
226 106
227 i2c@1720 { 107 eth0: ethernet@2800 {
228 #address-cells = <1>; 108 phy-handle = <&phy0>;
229 #size-cells = <0>;
230 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
231 reg = <0x1720 0x20>;
232 interrupts = <10 0x8>;
233 interrupt-parent = < &ipic >;
234 };
235
236 i2c@1740 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
240 reg = <0x1740 0x20>;
241 interrupts = <11 0x8>;
242 interrupt-parent = < &ipic >;
243 }; 109 };
244 110
245 i2ccontrol@1760 { 111 can@2300 {
246 compatible = "fsl,mpc5121-i2c-ctrl"; 112 status = "disabled";
247 reg = <0x1760 0x8>;
248 }; 113 };
249 114
250 axe@2000 { 115 can@2380 {
251 compatible = "fsl,mpc5121-axe"; 116 status = "disabled";
252 reg = <0x2000 0x100>;
253 interrupts = <42 0x8>;
254 interrupt-parent = < &ipic >;
255 }; 117 };
256 118
257 display@2100 { 119 viu@2400 {
258 compatible = "fsl,mpc5121-diu"; 120 status = "disabled";
259 reg = <0x2100 0x100>;
260 interrupts = <64 0x8>;
261 interrupt-parent = < &ipic >;
262 }; 121 };
263 122
264 mdio@2800 { 123 mdio@2800 {
265 compatible = "fsl,mpc5121-fec-mdio"; 124 phy0: ethernet-phy@0 {
266 reg = <0x2800 0x800>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 phy: ethernet-phy@0 {
270 reg = <1>; 125 reg = <1>;
271 device_type = "ethernet-phy";
272 }; 126 };
273 }; 127 };
274 128
275 ethernet@2800 { 129 /* mpc5121ads only uses USB0 */
276 device_type = "network"; 130 usb@3000 {
277 compatible = "fsl,mpc5121-fec"; 131 status = "disabled";
278 reg = <0x2800 0x800>;
279 local-mac-address = [ 00 00 00 00 00 00 ];
280 interrupts = <4 0x8>;
281 interrupt-parent = < &ipic >;
282 phy-handle = < &phy >;
283 fsl,align-tx-packets = <4>;
284 }; 132 };
285 133
286 // 5121e has two dr usb modules 134 /* USB0 using internal UTMI PHY */
287 // mpc5121_ads only uses USB0
288
289 // USB1 using external ULPI PHY
290 //usb@3000 {
291 // compatible = "fsl,mpc5121-usb2-dr";
292 // reg = <0x3000 0x1000>;
293 // #address-cells = <1>;
294 // #size-cells = <0>;
295 // interrupt-parent = < &ipic >;
296 // interrupts = <43 0x8>;
297 // dr_mode = "otg";
298 // phy_type = "ulpi";
299 //};
300
301 // USB0 using internal UTMI PHY
302 usb@4000 { 135 usb@4000 {
303 compatible = "fsl,mpc5121-usb2-dr"; 136 dr_mode = "host";
304 reg = <0x4000 0x1000>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 interrupt-parent = < &ipic >;
308 interrupts = <44 0x8>;
309 dr_mode = "otg";
310 phy_type = "utmi_wide";
311 fsl,invert-drvvbus; 137 fsl,invert-drvvbus;
312 fsl,invert-pwr-fault; 138 fsl,invert-pwr-fault;
313 }; 139 };
314 140
315 // IO control 141 /* PSC3 serial port A aka ttyPSC0 */
316 ioctl@a000 { 142 psc@11300 {
317 compatible = "fsl,mpc5121-ioctl";
318 reg = <0xA000 0x1000>;
319 };
320
321 pata@10200 {
322 compatible = "fsl,mpc5121-pata";
323 reg = <0x10200 0x100>;
324 interrupts = <5 0x8>;
325 interrupt-parent = < &ipic >;
326 };
327
328 // 512x PSCs are not 52xx PSC compatible
329 // PSC3 serial port A aka ttyPSC0
330 serial@11300 {
331 device_type = "serial";
332 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 143 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
333 // Logical port assignment needed until driver
334 // learns to use aliases
335 port-number = <0>;
336 cell-index = <3>;
337 reg = <0x11300 0x100>;
338 interrupts = <40 0x8>;
339 interrupt-parent = < &ipic >;
340 rx-fifo-size = <16>;
341 tx-fifo-size = <16>;
342 }; 144 };
343 145
344 // PSC4 serial port B aka ttyPSC1 146 /* PSC4 serial port B aka ttyPSC1 */
345 serial@11400 { 147 psc@11400 {
346 device_type = "serial";
347 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 148 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
348 // Logical port assignment needed until driver
349 // learns to use aliases
350 port-number = <1>;
351 cell-index = <4>;
352 reg = <0x11400 0x100>;
353 interrupts = <40 0x8>;
354 interrupt-parent = < &ipic >;
355 rx-fifo-size = <16>;
356 tx-fifo-size = <16>;
357 }; 149 };
358 150
359 // PSC5 in ac97 mode 151 /* PSC5 in ac97 mode */
360 ac97@11500 { 152 ac97: psc@11500 {
361 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; 153 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
362 cell-index = <5>;
363 reg = <0x11500 0x100>;
364 interrupts = <40 0x8>;
365 interrupt-parent = < &ipic >;
366 fsl,mode = "ac97-slave"; 154 fsl,mode = "ac97-slave";
367 rx-fifo-size = <384>; 155 fsl,rx-fifo-size = <384>;
368 tx-fifo-size = <384>; 156 fsl,tx-fifo-size = <384>;
369 };
370
371 pscfifo@11f00 {
372 compatible = "fsl,mpc5121-psc-fifo";
373 reg = <0x11f00 0x100>;
374 interrupts = <40 0x8>;
375 interrupt-parent = < &ipic >;
376 }; 157 };
377
378 dma@14000 {
379 compatible = "fsl,mpc5121-dma";
380 reg = <0x14000 0x1800>;
381 interrupts = <65 0x8>;
382 interrupt-parent = < &ipic >;
383 };
384
385 }; 158 };
386 159
387 pci: pci@80008500 { 160 pci: pci@80008500 {
388 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 161 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
389 interrupt-map = < 162 interrupt-map = <
390 // IDSEL 0x15 - Slot 1 PCI 163 /* IDSEL 0x15 - Slot 1 PCI */
391 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 164 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
392 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 165 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
393 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 166 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
394 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 167 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
395 168
396 // IDSEL 0x16 - Slot 2 MiniPCI 169 /* IDSEL 0x16 - Slot 2 MiniPCI */
397 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 170 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
398 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 171 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
399 172
400 // IDSEL 0x17 - Slot 3 MiniPCI 173 /* IDSEL 0x17 - Slot 3 MiniPCI */
401 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 174 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
402 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 175 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
403 >; 176 >;
404 interrupt-parent = < &ipic >;
405 interrupts = <1 0x8>;
406 bus-range = <0 0>;
407 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
408 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
409 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
410 clock-frequency = <0>;
411 #interrupt-cells = <1>;
412 #size-cells = <2>;
413 #address-cells = <3>;
414 reg = <0x80008500 0x100 /* internal registers */
415 0x80008300 0x8>; /* config space access registers */
416 compatible = "fsl,mpc5121-pci";
417 device_type = "pci";
418 }; 177 };
419}; 178};
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
index 39ed65a44c5f..969b2200b2f9 100644
--- a/arch/powerpc/boot/dts/mpc5200b.dtsi
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -64,50 +64,59 @@
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { // General Purpose Timer 67 gpt0: timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
69 reg = <0x600 0x10>; 70 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 71 interrupts = <1 9 0>;
72 // add 'fsl,has-wdt' to enable watchdog
71 }; 73 };
72 74
73 timer@610 { // General Purpose Timer 75 gpt1: timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
75 reg = <0x610 0x10>; 78 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 79 interrupts = <1 10 0>;
77 }; 80 };
78 81
79 timer@620 { // General Purpose Timer 82 gpt2: timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 83 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
84 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
81 reg = <0x620 0x10>; 85 reg = <0x620 0x10>;
82 interrupts = <1 11 0>; 86 interrupts = <1 11 0>;
83 }; 87 };
84 88
85 timer@630 { // General Purpose Timer 89 gpt3: timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
87 reg = <0x630 0x10>; 92 reg = <0x630 0x10>;
88 interrupts = <1 12 0>; 93 interrupts = <1 12 0>;
89 }; 94 };
90 95
91 timer@640 { // General Purpose Timer 96 gpt4: timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
93 reg = <0x640 0x10>; 99 reg = <0x640 0x10>;
94 interrupts = <1 13 0>; 100 interrupts = <1 13 0>;
95 }; 101 };
96 102
97 timer@650 { // General Purpose Timer 103 gpt5: timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
99 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
100 interrupts = <1 14 0>; 107 interrupts = <1 14 0>;
101 }; 108 };
102 109
103 timer@660 { // General Purpose Timer 110 gpt6: timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
105 reg = <0x660 0x10>; 113 reg = <0x660 0x10>;
106 interrupts = <1 15 0>; 114 interrupts = <1 15 0>;
107 }; 115 };
108 116
109 timer@670 { // General Purpose Timer 117 gpt7: timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 118 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
119 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
111 reg = <0x670 0x10>; 120 reg = <0x670 0x10>;
112 interrupts = <1 16 0>; 121 interrupts = <1 16 0>;
113 }; 122 };
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index 21d34720fcc9..d3a792bb5c1a 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -13,47 +13,23 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16/* Timer pins that need to be in GPIO mode */
17&gpt0 { gpio-controller; };
18&gpt1 { gpio-controller; };
19&gpt2 { gpio-controller; };
20&gpt3 { gpio-controller; };
21
22/* Disabled timers */
23&gpt4 { status = "disabled"; };
24&gpt5 { status = "disabled"; };
25&gpt6 { status = "disabled"; };
26&gpt7 { status = "disabled"; };
27
16/ { 28/ {
17 model = "manroland,mucmc52"; 29 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52"; 30 compatible = "manroland,mucmc52";
19 31
20 soc5200@f0000000 { 32 soc5200@f0000000 {
21 gpt0: timer@600 { // GPT 0 in GPIO mode
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
37 gpio-controller;
38 #gpio-cells = <2>;
39 };
40
41 timer@640 {
42 status = "disabled";
43 };
44
45 timer@650 {
46 status = "disabled";
47 };
48
49 timer@660 {
50 status = "disabled";
51 };
52
53 timer@670 {
54 status = "disabled";
55 };
56
57 rtc@800 { 33 rtc@800 {
58 status = "disabled"; 34 status = "disabled";
59 }; 35 };
diff --git a/arch/powerpc/boot/dts/o2d.dtsi b/arch/powerpc/boot/dts/o2d.dtsi
index 24f668039295..cf073e693f24 100644
--- a/arch/powerpc/boot/dts/o2d.dtsi
+++ b/arch/powerpc/boot/dts/o2d.dtsi
@@ -12,6 +12,13 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 {
16 gpio-controller;
17 fsl,has-wdt;
18 fsl,wdt-on-boot = <0>;
19};
20&gpt1 { gpio-controller; };
21
15/ { 22/ {
16 model = "ifm,o2d"; 23 model = "ifm,o2d";
17 compatible = "ifm,o2d"; 24 compatible = "ifm,o2d";
@@ -22,24 +29,6 @@
22 29
23 soc5200@f0000000 { 30 soc5200@f0000000 {
24 31
25 gpio_simple: gpio@b00 {
26 };
27
28 timer@600 { // General Purpose Timer
29 #gpio-cells = <2>;
30 gpio-controller;
31 fsl,has-wdt;
32 fsl,wdt-on-boot = <0>;
33 };
34
35 timer@610 {
36 #gpio-cells = <2>;
37 gpio-controller;
38 };
39
40 timer7: timer@670 {
41 };
42
43 rtc@800 { 32 rtc@800 {
44 status = "disabled"; 33 status = "disabled";
45 }; 34 };
@@ -118,7 +107,7 @@
118 csi@3,0 { 107 csi@3,0 {
119 compatible = "ifm,o2d-csi"; 108 compatible = "ifm,o2d-csi";
120 reg = <3 0 0x00100000>; 109 reg = <3 0 0x00100000>;
121 ifm,csi-clk-handle = <&timer7>; 110 ifm,csi-clk-handle = <&gpt7>;
122 gpios = <&gpio_simple 23 0 /* imag_capture */ 111 gpios = <&gpio_simple 23 0 /* imag_capture */
123 &gpio_simple 26 0 /* imag_reset */ 112 &gpio_simple 26 0 /* imag_reset */
124 &gpio_simple 29 0>; /* imag_master_en */ 113 &gpio_simple 29 0>; /* imag_master_en */
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 96512c058033..192e66af0001 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -14,51 +14,19 @@
14 14
15/include/ "mpc5200b.dtsi" 15/include/ "mpc5200b.dtsi"
16 16
17&gpt0 { fsl,has-wdt; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
17/ { 25/ {
18 model = "phytec,pcm030"; 26 model = "phytec,pcm030";
19 compatible = "phytec,pcm030"; 27 compatible = "phytec,pcm030";
20 28
21 soc5200@f0000000 { 29 soc5200@f0000000 {
22 timer@600 { // General Purpose Timer
23 fsl,has-wdt;
24 };
25
26 gpt2: timer@620 { // General Purpose Timer in GPIO mode
27 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
32 gpt3: timer@630 { // General Purpose Timer in GPIO mode
33 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
34 gpio-controller;
35 #gpio-cells = <2>;
36 };
37
38 gpt4: timer@640 { // General Purpose Timer in GPIO mode
39 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
40 gpio-controller;
41 #gpio-cells = <2>;
42 };
43
44 gpt5: timer@650 { // General Purpose Timer in GPIO mode
45 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
49
50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
51 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
52 gpio-controller;
53 #gpio-cells = <2>;
54 };
55
56 gpt7: timer@670 { // General Purpose Timer in GPIO mode
57 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
58 gpio-controller;
59 #gpio-cells = <2>;
60 };
61
62 audioplatform: psc@2000 { /* PSC1 in ac97 mode */ 30 audioplatform: psc@2000 { /* PSC1 in ac97 mode */
63 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 31 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
64 cell-index = <0>; 32 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 1dd478bfff96..96b139bf50e9 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -14,6 +14,14 @@
14 14
15/include/ "mpc5200b.dtsi" 15/include/ "mpc5200b.dtsi"
16 16
17&gpt0 { fsl,has-wdt; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
17/ { 25/ {
18 model = "phytec,pcm032"; 26 model = "phytec,pcm032";
19 compatible = "phytec,pcm032"; 27 compatible = "phytec,pcm032";
@@ -23,43 +31,6 @@
23 }; 31 };
24 32
25 soc5200@f0000000 { 33 soc5200@f0000000 {
26 timer@600 { // General Purpose Timer
27 fsl,has-wdt;
28 };
29
30 gpt2: timer@620 { // General Purpose Timer in GPIO mode
31 gpio-controller;
32 #gpio-cells = <2>;
33 };
34
35 gpt3: timer@630 { // General Purpose Timer in GPIO mode
36 gpio-controller;
37 #gpio-cells = <2>;
38 };
39
40 gpt4: timer@640 { // General Purpose Timer in GPIO mode
41 gpio-controller;
42 #gpio-cells = <2>;
43 };
44
45 gpt5: timer@650 { // General Purpose Timer in GPIO mode
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
49
50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
51 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
52 reg = <0x660 0x10>;
53 interrupts = <1 15 0>;
54 gpio-controller;
55 #gpio-cells = <2>;
56 };
57
58 gpt7: timer@670 { // General Purpose Timer in GPIO mode
59 gpio-controller;
60 #gpio-cells = <2>;
61 };
62
63 psc@2000 { /* PSC1 is ac97 */ 34 psc@2000 { /* PSC1 is ac97 */
64 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 35 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
65 cell-index = <0>; 36 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 94dfa5c9a7f9..0b069477838a 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
13 * option) any later version. 13 * option) any later version.
14 */ 14 */
15 15
16/dts-v1/; 16/include/ "mpc5121.dtsi"
17 17
18/ { 18/ {
19 model = "pdm360ng"; 19 model = "pdm360ng";
@@ -22,38 +22,12 @@
22 #size-cells = <1>; 22 #size-cells = <1>;
23 interrupt-parent = <&ipic>; 23 interrupt-parent = <&ipic>;
24 24
25 aliases {
26 ethernet0 = &eth0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,5121@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
41 bus-frequency = <198000000>; // 198 MHz csb bus
42 clock-frequency = <396000000>; // 396 MHz ppc core
43 };
44 };
45
46 memory { 25 memory {
47 device_type = "memory"; 26 device_type = "memory";
48 reg = <0x00000000 0x20000000>; // 512MB at 0 27 reg = <0x00000000 0x20000000>; // 512MB at 0
49 }; 28 };
50 29
51 nfc@40000000 { 30 nfc@40000000 {
52 compatible = "fsl,mpc5121-nfc";
53 reg = <0x40000000 0x100000>;
54 interrupts = <0x6 0x8>;
55 #address-cells = <0x1>;
56 #size-cells = <0x1>;
57 bank-width = <0x1>; 31 bank-width = <0x1>;
58 chips = <0x1>; 32 chips = <0x1>;
59 33
@@ -63,17 +37,7 @@
63 }; 37 };
64 }; 38 };
65 39
66 sram@50000000 {
67 compatible = "fsl,mpc5121-sram";
68 reg = <0x50000000 0x20000>; // 128K at 0x50000000
69 };
70
71 localbus@80000020 { 40 localbus@80000020 {
72 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 reg = <0x80000020 0x40>;
76
77 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */ 41 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
78 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */ 42 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
79 43
@@ -129,74 +93,8 @@
129 }; 93 };
130 94
131 soc@80000000 { 95 soc@80000000 {
132 compatible = "fsl,mpc5121-immr";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 #interrupt-cells = <2>;
136 ranges = <0x0 0x80000000 0x400000>;
137 reg = <0x80000000 0x400000>;
138 bus-frequency = <66000000>; // 66 MHz ips bus
139
140 // IPIC
141 // interrupts cell = <intr #, sense>
142 // sense values match linux IORESOURCE_IRQ_* defines:
143 // sense == 8: Level, low assertion
144 // sense == 2: Edge, high-to-low change
145 //
146 ipic: interrupt-controller@c00 {
147 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0xc00 0x100>;
152 };
153
154 rtc@a00 { // Real time clock
155 compatible = "fsl,mpc5121-rtc";
156 reg = <0xa00 0x100>;
157 interrupts = <79 0x8 80 0x8>;
158 };
159
160 reset@e00 { // Reset module
161 compatible = "fsl,mpc5121-reset";
162 reg = <0xe00 0x100>;
163 };
164
165 clock@f00 { // Clock control
166 compatible = "fsl,mpc5121-clock";
167 reg = <0xf00 0x100>;
168 };
169
170 pmc@1000{ //Power Management Controller
171 compatible = "fsl,mpc5121-pmc";
172 reg = <0x1000 0x100>;
173 interrupts = <83 0x2>;
174 };
175
176 gpio@1100 {
177 compatible = "fsl,mpc5121-gpio";
178 reg = <0x1100 0x100>;
179 interrupts = <78 0x8>;
180 };
181
182 can@1300 {
183 compatible = "fsl,mpc5121-mscan";
184 interrupts = <12 0x8>;
185 reg = <0x1300 0x80>;
186 };
187
188 can@1380 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <13 0x8>;
191 reg = <0x1380 0x80>;
192 };
193 96
194 i2c@1700 { 97 i2c@1700 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,mpc5121-i2c";
198 reg = <0x1700 0x20>;
199 interrupts = <0x9 0x8>;
200 fsl,preserve-clocking; 98 fsl,preserve-clocking;
201 99
202 eeprom@50 { 100 eeprom@50 {
@@ -210,201 +108,92 @@
210 }; 108 };
211 }; 109 };
212 110
213 i2c@1740 { 111 i2c@1720 {
214 #address-cells = <1>; 112 status = "disabled";
215 #size-cells = <0>;
216 compatible = "fsl,mpc5121-i2c";
217 reg = <0x1740 0x20>;
218 interrupts = <0xb 0x8>;
219 fsl,preserve-clocking;
220 };
221
222 i2ccontrol@1760 {
223 compatible = "fsl,mpc5121-i2c-ctrl";
224 reg = <0x1760 0x8>;
225 };
226
227 axe@2000 {
228 compatible = "fsl,mpc5121-axe";
229 reg = <0x2000 0x100>;
230 interrupts = <42 0x8>;
231 };
232
233 display@2100 {
234 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>;
237 }; 113 };
238 114
239 can@2300 { 115 i2c@1740 {
240 compatible = "fsl,mpc5121-mscan"; 116 fsl,preserve-clocking;
241 interrupts = <90 0x8>;
242 reg = <0x2300 0x80>;
243 };
244
245 can@2380 {
246 compatible = "fsl,mpc5121-mscan";
247 interrupts = <91 0x8>;
248 reg = <0x2380 0x80>;
249 }; 117 };
250 118
251 viu@2400 { 119 ethernet@2800 {
252 compatible = "fsl,mpc5121-viu"; 120 phy-handle = <&phy0>;
253 reg = <0x2400 0x400>;
254 interrupts = <67 0x8>;
255 }; 121 };
256 122
257 mdio@2800 { 123 mdio@2800 {
258 compatible = "fsl,mpc5121-fec-mdio"; 124 phy0: ethernet-phy@1f {
259 reg = <0x2800 0x200>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 phy: ethernet-phy@0 {
263 compatible = "smsc,lan8700"; 125 compatible = "smsc,lan8700";
264 reg = <0x1f>; 126 reg = <0x1f>;
265 }; 127 };
266 }; 128 };
267 129
268 eth0: ethernet@2800 { 130 /* USB1 using external ULPI PHY */
269 compatible = "fsl,mpc5121-fec";
270 reg = <0x2800 0x200>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <4 0x8>;
273 phy-handle = < &phy >;
274 };
275
276 // USB1 using external ULPI PHY
277 usb@3000 { 131 usb@3000 {
278 compatible = "fsl,mpc5121-usb2-dr";
279 reg = <0x3000 0x600>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <43 0x8>;
283 dr_mode = "host"; 132 dr_mode = "host";
284 phy_type = "ulpi";
285 }; 133 };
286 134
287 // USB0 using internal UTMI PHY 135 /* USB0 using internal UTMI PHY */
288 usb@4000 { 136 usb@4000 {
289 compatible = "fsl,mpc5121-usb2-dr";
290 reg = <0x4000 0x600>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 interrupts = <44 0x8>;
294 dr_mode = "otg";
295 phy_type = "utmi_wide";
296 fsl,invert-pwr-fault; 137 fsl,invert-pwr-fault;
297 }; 138 };
298 139
299 // IO control 140 psc@11000 {
300 ioctl@a000 {
301 compatible = "fsl,mpc5121-ioctl";
302 reg = <0xA000 0x1000>;
303 };
304
305 // 512x PSCs are not 52xx PSCs compatible
306 serial@11000 {
307 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 141 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
308 cell-index = <0>;
309 reg = <0x11000 0x100>;
310 interrupts = <40 0x8>;
311 fsl,rx-fifo-size = <16>;
312 fsl,tx-fifo-size = <16>;
313 }; 142 };
314 143
315 serial@11100 { 144 psc@11100 {
316 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 145 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
317 cell-index = <1>;
318 reg = <0x11100 0x100>;
319 interrupts = <40 0x8>;
320 fsl,rx-fifo-size = <16>;
321 fsl,tx-fifo-size = <16>;
322 }; 146 };
323 147
324 serial@11200 { 148 psc@11200 {
325 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 149 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
326 cell-index = <2>;
327 reg = <0x11200 0x100>;
328 interrupts = <40 0x8>;
329 fsl,rx-fifo-size = <16>;
330 fsl,tx-fifo-size = <16>;
331 }; 150 };
332 151
333 serial@11300 { 152 psc@11300 {
334 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 153 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335 cell-index = <3>;
336 reg = <0x11300 0x100>;
337 interrupts = <40 0x8>;
338 fsl,rx-fifo-size = <16>;
339 fsl,tx-fifo-size = <16>;
340 }; 154 };
341 155
342 serial@11400 { 156 psc@11400 {
343 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 157 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
344 cell-index = <4>;
345 reg = <0x11400 0x100>;
346 interrupts = <40 0x8>;
347 fsl,rx-fifo-size = <16>;
348 fsl,tx-fifo-size = <16>;
349 }; 158 };
350 159
351 serial@11600 { 160 psc@11500 {
352 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 161 status = "disabled";
353 cell-index = <6>;
354 reg = <0x11600 0x100>;
355 interrupts = <40 0x8>;
356 fsl,rx-fifo-size = <16>;
357 fsl,tx-fifo-size = <16>;
358 }; 162 };
359 163
360 serial@11800 { 164 psc@11600 {
361 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 165 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
362 cell-index = <8>;
363 reg = <0x11800 0x100>;
364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16>;
367 }; 166 };
368 167
369 serial@11B00 { 168 psc@11700 {
370 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 169 status = "disabled";
371 cell-index = <11>;
372 reg = <0x11B00 0x100>;
373 interrupts = <40 0x8>;
374 fsl,rx-fifo-size = <16>;
375 fsl,tx-fifo-size = <16>;
376 }; 170 };
377 171
378 pscfifo@11f00 { 172 psc@11800 {
379 compatible = "fsl,mpc5121-psc-fifo"; 173 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
380 reg = <0x11f00 0x100>;
381 interrupts = <40 0x8>;
382 }; 174 };
383 175
384 spi@11900 { 176 psc@11900 {
385 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; 177 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
386 cell-index = <9>;
387 #address-cells = <1>; 178 #address-cells = <1>;
388 #size-cells = <0>; 179 #size-cells = <0>;
389 reg = <0x11900 0x100>;
390 interrupts = <40 0x8>;
391 fsl,rx-fifo-size = <16>;
392 fsl,tx-fifo-size = <16>;
393 180
394 // 7845 touch screen controller 181 /* ADS7845 touch screen controller */
395 ts@0 { 182 ts@0 {
396 compatible = "ti,ads7846"; 183 compatible = "ti,ads7846";
397 reg = <0x0>; 184 reg = <0x0>;
398 spi-max-frequency = <3000000>; 185 spi-max-frequency = <3000000>;
399 // pen irq is GPIO25 186 /* pen irq is GPIO25 */
400 interrupts = <78 0x8>; 187 interrupts = <78 0x8>;
401 }; 188 };
402 }; 189 };
403 190
404 dma@14000 { 191 psc@11a00 {
405 compatible = "fsl,mpc5121-dma"; 192 status = "disabled";
406 reg = <0x14000 0x1800>; 193 };
407 interrupts = <65 0x8>; 194
195 psc@11b00 {
196 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
408 }; 197 };
409 }; 198 };
410}; 199};
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index ba83d5488ec6..5c462194ef06 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -13,54 +13,20 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { gpio-controller; };
17&gpt1 { gpio-controller; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
16/ { 25/ {
17 model = "manroland,uc101"; 26 model = "manroland,uc101";
18 compatible = "manroland,uc101"; 27 compatible = "manroland,uc101";
19 28
20 soc5200@f0000000 { 29 soc5200@f0000000 {
21 gpt0: timer@600 { // General Purpose Timer in GPIO mode
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
37 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
38 reg = <0x630 0x10>;
39 interrupts = <1 12 0>;
40 gpio-controller;
41 #gpio-cells = <2>;
42 };
43
44 gpt4: timer@640 { // General Purpose Timer in GPIO mode
45 gpio-controller;
46 #gpio-cells = <2>;
47 };
48
49 gpt5: timer@650 { // General Purpose Timer in GPIO mode
50 gpio-controller;
51 #gpio-cells = <2>;
52 };
53
54 gpt6: timer@660 { // General Purpose Timer in GPIO mode
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 gpt7: timer@670 { // General Purpose Timer in GPIO mode
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63
64 rtc@800 { 30 rtc@800 {
65 status = "disabled"; 31 status = "disabled";
66 }; 32 };
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8c0ab2ca689c..885c040d6194 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -53,4 +53,21 @@ struct mpc512x_ccm {
53 u32 m4ccr; /* MSCAN4 CCR */ 53 u32 m4ccr; /* MSCAN4 CCR */
54 u8 res[0x98]; /* Reserved */ 54 u8 res[0x98]; /* Reserved */
55}; 55};
56
57/*
58 * LPC Module
59 */
60struct mpc512x_lpc {
61 u32 cs_cfg[8]; /* CS config */
62 u32 cs_ctrl; /* CS Control Register */
63 u32 cs_status; /* CS Status Register */
64 u32 burst_ctrl; /* CS Burst Control Register */
65 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
66 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
67 u32 alt; /* Address Latch Timing Register */
68};
69
70int mpc512x_cs_config(unsigned int cs, u32 val);
71int __init mpc5121_clk_init(void);
72
56#endif /* __ASM_POWERPC_MPC5121_H__ */ 73#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 9f771e05457c..52d57d281724 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -26,6 +26,7 @@
26 26
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <asm/mpc5xxx.h> 28#include <asm/mpc5xxx.h>
29#include <asm/mpc5121.h>
29#include <asm/clk_interface.h> 30#include <asm/clk_interface.h>
30 31
31#undef CLK_DEBUG 32#undef CLK_DEBUG
@@ -122,7 +123,7 @@ struct mpc512x_clockctl {
122 u32 dccr; /* DIU Clk Cnfg Reg */ 123 u32 dccr; /* DIU Clk Cnfg Reg */
123}; 124};
124 125
125struct mpc512x_clockctl __iomem *clockctl; 126static struct mpc512x_clockctl __iomem *clockctl;
126 127
127static int mpc5121_clk_enable(struct clk *clk) 128static int mpc5121_clk_enable(struct clk *clk)
128{ 129{
@@ -184,7 +185,7 @@ static unsigned long spmf_mult(void)
184 36, 40, 44, 48, 185 36, 40, 44, 48,
185 52, 56, 60, 64 186 52, 56, 60, 64
186 }; 187 };
187 int spmf = (clockctl->spmr >> 24) & 0xf; 188 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
188 return spmf_to_mult[spmf]; 189 return spmf_to_mult[spmf];
189} 190}
190 191
@@ -206,7 +207,7 @@ static unsigned long sysdiv_div_x_2(void)
206 52, 56, 58, 62, 207 52, 56, 58, 62,
207 60, 64, 66, 208 60, 64, 66,
208 }; 209 };
209 int sysdiv = (clockctl->scfr2 >> 26) & 0x3f; 210 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
210 return sysdiv_to_div_x_2[sysdiv]; 211 return sysdiv_to_div_x_2[sysdiv];
211} 212}
212 213
@@ -230,7 +231,7 @@ static unsigned long sys_to_ref(unsigned long rate)
230 231
231static long ips_to_ref(unsigned long rate) 232static long ips_to_ref(unsigned long rate)
232{ 233{
233 int ips_div = (clockctl->scfr1 >> 23) & 0x7; 234 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
234 235
235 rate *= ips_div; /* csb_clk = ips_clk * ips_div */ 236 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
236 rate *= 2; /* sys_clk = csb_clk * 2 */ 237 rate *= 2; /* sys_clk = csb_clk * 2 */
@@ -284,7 +285,7 @@ static struct clk sys_clk = {
284 285
285static void diu_clk_calc(struct clk *clk) 286static void diu_clk_calc(struct clk *clk)
286{ 287{
287 int diudiv_x_2 = clockctl->scfr1 & 0xff; 288 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
288 unsigned long rate; 289 unsigned long rate;
289 290
290 rate = sys_clk.rate; 291 rate = sys_clk.rate;
@@ -311,7 +312,7 @@ static void half_clk_calc(struct clk *clk)
311 312
312static void generic_div_clk_calc(struct clk *clk) 313static void generic_div_clk_calc(struct clk *clk)
313{ 314{
314 int div = (clockctl->scfr1 >> clk->div_shift) & 0x7; 315 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
315 316
316 clk->rate = clk->parent->rate / div; 317 clk->rate = clk->parent->rate / div;
317} 318}
@@ -329,7 +330,7 @@ static struct clk csb_clk = {
329 330
330static void e300_clk_calc(struct clk *clk) 331static void e300_clk_calc(struct clk *clk)
331{ 332{
332 int spmf = (clockctl->spmr >> 16) & 0xf; 333 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
333 int ratex2 = clk->parent->rate * spmf; 334 int ratex2 = clk->parent->rate * spmf;
334 335
335 clk->rate = ratex2 / 2; 336 clk->rate = ratex2 / 2;
@@ -551,7 +552,7 @@ static struct clk ac97_clk = {
551 .calc = ac97_clk_calc, 552 .calc = ac97_clk_calc,
552}; 553};
553 554
554struct clk *rate_clks[] = { 555static struct clk *rate_clks[] = {
555 &ref_clk, 556 &ref_clk,
556 &sys_clk, 557 &sys_clk,
557 &diu_clk, 558 &diu_clk,
@@ -607,7 +608,7 @@ static void rate_clks_init(void)
607 * There are two clk enable registers with 32 enable bits each 608 * There are two clk enable registers with 32 enable bits each
608 * psc clocks and device clocks are all stored in dev_clks 609 * psc clocks and device clocks are all stored in dev_clks
609 */ 610 */
610struct clk dev_clks[2][32]; 611static struct clk dev_clks[2][32];
611 612
612/* 613/*
613 * Given a psc number return the dev_clk 614 * Given a psc number return the dev_clk
@@ -648,12 +649,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
648 out_be32(&clockctl->pccr[pscnum], 0x00020000); 649 out_be32(&clockctl->pccr[pscnum], 0x00020000);
649 out_be32(&clockctl->pccr[pscnum], 0x00030000); 650 out_be32(&clockctl->pccr[pscnum], 0x00030000);
650 651
651 if (clockctl->pccr[pscnum] & 0x80) { 652 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
652 clk->rate = spdif_rxclk.rate; 653 clk->rate = spdif_rxclk.rate;
653 return; 654 return;
654 } 655 }
655 656
656 switch ((clockctl->pccr[pscnum] >> 14) & 0x3) { 657 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
657 case 0: 658 case 0:
658 mclk_src = sys_clk.rate; 659 mclk_src = sys_clk.rate;
659 break; 660 break;
@@ -668,7 +669,7 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
668 break; 669 break;
669 } 670 }
670 671
671 mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1; 672 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
672 clk->rate = mclk_src / mclk_div; 673 clk->rate = mclk_src / mclk_div;
673} 674}
674 675
@@ -680,13 +681,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
680static void psc_clks_init(void) 681static void psc_clks_init(void)
681{ 682{
682 struct device_node *np; 683 struct device_node *np;
683 const u32 *cell_index;
684 struct platform_device *ofdev; 684 struct platform_device *ofdev;
685 u32 reg;
685 686
686 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") { 687 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
687 cell_index = of_get_property(np, "cell-index", NULL); 688 if (!of_property_read_u32(np, "reg", &reg)) {
688 if (cell_index) { 689 int pscnum = (reg & 0xf00) >> 8;
689 int pscnum = *cell_index;
690 struct clk *clk = psc_dev_clk(pscnum); 690 struct clk *clk = psc_dev_clk(pscnum);
691 691
692 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL; 692 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
@@ -696,7 +696,7 @@ static void psc_clks_init(void)
696 * AC97 is special rate clock does 696 * AC97 is special rate clock does
697 * not go through normal path 697 * not go through normal path
698 */ 698 */
699 if (strcmp("ac97", np->name) == 0) 699 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
700 clk->rate = ac97_clk.rate; 700 clk->rate = ac97_clk.rate;
701 else 701 else
702 psc_calc_rate(clk, pscnum, np); 702 psc_calc_rate(clk, pscnum, np);
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index c7f47cfa9c29..d30235b7e3f7 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -426,8 +426,38 @@ void __init mpc512x_psc_fifo_init(void)
426 426
427void __init mpc512x_init(void) 427void __init mpc512x_init(void)
428{ 428{
429 mpc512x_declare_of_platform_devices();
430 mpc5121_clk_init(); 429 mpc5121_clk_init();
430 mpc512x_declare_of_platform_devices();
431 mpc512x_restart_init(); 431 mpc512x_restart_init();
432 mpc512x_psc_fifo_init(); 432 mpc512x_psc_fifo_init();
433} 433}
434
435/**
436 * mpc512x_cs_config - Setup chip select configuration
437 * @cs: chip select number
438 * @val: chip select configuration value
439 *
440 * Perform chip select configuration for devices on LocalPlus Bus.
441 * Intended to dynamically reconfigure the chip select parameters
442 * for configurable devices on the bus.
443 */
444int mpc512x_cs_config(unsigned int cs, u32 val)
445{
446 static struct mpc512x_lpc __iomem *lpc;
447 struct device_node *np;
448
449 if (cs > 7)
450 return -EINVAL;
451
452 if (!lpc) {
453 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc");
454 lpc = of_iomap(np, 0);
455 of_node_put(np);
456 if (!lpc)
457 return -ENOMEM;
458 }
459
460 out_be32(&lpc->cs_cfg[cs], val);
461 return 0;
462}
463EXPORT_SYMBOL(mpc512x_cs_config);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
index f9f4537f546d..be7b1aa4d54c 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -20,9 +20,9 @@
20#include <asm/mpc52xx.h> 20#include <asm/mpc52xx.h>
21#include <asm/time.h> 21#include <asm/time.h>
22 22
23#include <sysdev/bestcomm/bestcomm.h> 23#include <linux/fsl/bestcomm/bestcomm.h>
24#include <sysdev/bestcomm/bestcomm_priv.h> 24#include <linux/fsl/bestcomm/bestcomm_priv.h>
25#include <sysdev/bestcomm/gen_bd.h> 25#include <linux/fsl/bestcomm/gen_bd.h>
26 26
27MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 27MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
28MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver"); 28MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 48a920d51489..52de8bccfb30 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -352,8 +352,6 @@ config OF_RTC
352 Uses information from the OF or flattened device tree to instantiate 352 Uses information from the OF or flattened device tree to instantiate
353 platform devices for direct mapped RTC chips like the DS1742 or DS1743. 353 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
354 354
355source "arch/powerpc/sysdev/bestcomm/Kconfig"
356
357config SIMPLE_GPIO 355config SIMPLE_GPIO
358 bool "Support for simple, memory-mapped GPIO controllers" 356 bool "Support for simple, memory-mapped GPIO controllers"
359 depends on PPC 357 depends on PPC
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index eca3d19304c7..b0a518e97599 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
26obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o 26obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
27obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 27obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
28obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 28obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
29obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
30mv64x60-$(CONFIG_PCI) += mv64x60_pci.o 29mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
31obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \ 30obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
32 mv64x60_udbg.o 31 mv64x60_udbg.o
diff --git a/arch/powerpc/sysdev/bestcomm/Kconfig b/arch/powerpc/sysdev/bestcomm/Kconfig
deleted file mode 100644
index 29e427085efb..000000000000
--- a/arch/powerpc/sysdev/bestcomm/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
1#
2# Kconfig options for Bestcomm
3#
4
5config PPC_BESTCOMM
6 tristate "Bestcomm DMA engine support"
7 depends on PPC_MPC52xx
8 default n
9 select PPC_LIB_RHEAP
10 help
11 BestComm is the name of the communication coprocessor found
12 on the Freescale MPC5200 family of processor. Its usage is
13 optional for some drivers (like ATA), but required for
14 others (like FEC).
15
16 If you want to use drivers that require DMA operations,
17 answer Y or M. Otherwise say N.
18
19config PPC_BESTCOMM_ATA
20 tristate
21 depends on PPC_BESTCOMM
22 help
23 This option enables the support for the ATA task.
24
25config PPC_BESTCOMM_FEC
26 tristate
27 depends on PPC_BESTCOMM
28 help
29 This option enables the support for the FEC tasks.
30
31config PPC_BESTCOMM_GEN_BD
32 tristate
33 depends on PPC_BESTCOMM
34 help
35 This option enables the support for the GenBD tasks.
36
diff --git a/arch/powerpc/sysdev/bestcomm/Makefile b/arch/powerpc/sysdev/bestcomm/Makefile
deleted file mode 100644
index aed2df2a6580..000000000000
--- a/arch/powerpc/sysdev/bestcomm/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
1#
2# Makefile for BestComm & co
3#
4
5bestcomm-core-objs := bestcomm.o sram.o
6bestcomm-ata-objs := ata.o bcom_ata_task.o
7bestcomm-fec-objs := fec.o bcom_fec_rx_task.o bcom_fec_tx_task.o
8bestcomm-gen-bd-objs := gen_bd.o bcom_gen_bd_rx_task.o bcom_gen_bd_tx_task.o
9
10obj-$(CONFIG_PPC_BESTCOMM) += bestcomm-core.o
11obj-$(CONFIG_PPC_BESTCOMM_ATA) += bestcomm-ata.o
12obj-$(CONFIG_PPC_BESTCOMM_FEC) += bestcomm-fec.o
13obj-$(CONFIG_PPC_BESTCOMM_GEN_BD) += bestcomm-gen-bd.o
14
diff --git a/arch/powerpc/sysdev/bestcomm/ata.c b/arch/powerpc/sysdev/bestcomm/ata.c
deleted file mode 100644
index 901c9f91e5dd..000000000000
--- a/arch/powerpc/sysdev/bestcomm/ata.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Bestcomm ATA task driver
3 *
4 *
5 * Patterned after bestcomm/fec.c by Dale Farnsworth <dfarnsworth@mvista.com>
6 * 2003-2004 (c) MontaVista, Software, Inc.
7 *
8 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
9 * Copyright (C) 2006 Freescale - John Rigby
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/types.h>
19#include <asm/io.h>
20
21#include "bestcomm.h"
22#include "bestcomm_priv.h"
23#include "ata.h"
24
25
26/* ======================================================================== */
27/* Task image/var/inc */
28/* ======================================================================== */
29
30/* ata task image */
31extern u32 bcom_ata_task[];
32
33/* ata task vars that need to be set before enabling the task */
34struct bcom_ata_var {
35 u32 enable; /* (u16*) address of task's control register */
36 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
37 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
38 u32 bd_start; /* (struct bcom_bd*) current bd */
39 u32 buffer_size; /* size of receive buffer */
40};
41
42/* ata task incs that need to be set before enabling the task */
43struct bcom_ata_inc {
44 u16 pad0;
45 s16 incr_bytes;
46 u16 pad1;
47 s16 incr_dst;
48 u16 pad2;
49 s16 incr_src;
50};
51
52
53/* ======================================================================== */
54/* Task support code */
55/* ======================================================================== */
56
57struct bcom_task *
58bcom_ata_init(int queue_len, int maxbufsize)
59{
60 struct bcom_task *tsk;
61 struct bcom_ata_var *var;
62 struct bcom_ata_inc *inc;
63
64 /* Prefetch breaks ATA DMA. Turn it off for ATA DMA */
65 bcom_disable_prefetch();
66
67 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_ata_bd), 0);
68 if (!tsk)
69 return NULL;
70
71 tsk->flags = BCOM_FLAGS_NONE;
72
73 bcom_ata_reset_bd(tsk);
74
75 var = (struct bcom_ata_var *) bcom_task_var(tsk->tasknum);
76 inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
77
78 if (bcom_load_image(tsk->tasknum, bcom_ata_task)) {
79 bcom_task_free(tsk);
80 return NULL;
81 }
82
83 var->enable = bcom_eng->regs_base +
84 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
85 var->bd_base = tsk->bd_pa;
86 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
87 var->bd_start = tsk->bd_pa;
88 var->buffer_size = maxbufsize;
89
90 /* Configure some stuff */
91 bcom_set_task_pragma(tsk->tasknum, BCOM_ATA_PRAGMA);
92 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
93
94 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ATA_RX], BCOM_IPR_ATA_RX);
95 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ATA_TX], BCOM_IPR_ATA_TX);
96
97 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
98
99 return tsk;
100}
101EXPORT_SYMBOL_GPL(bcom_ata_init);
102
103void bcom_ata_rx_prepare(struct bcom_task *tsk)
104{
105 struct bcom_ata_inc *inc;
106
107 inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
108
109 inc->incr_bytes = -(s16)sizeof(u32);
110 inc->incr_src = 0;
111 inc->incr_dst = sizeof(u32);
112
113 bcom_set_initiator(tsk->tasknum, BCOM_INITIATOR_ATA_RX);
114}
115EXPORT_SYMBOL_GPL(bcom_ata_rx_prepare);
116
117void bcom_ata_tx_prepare(struct bcom_task *tsk)
118{
119 struct bcom_ata_inc *inc;
120
121 inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum);
122
123 inc->incr_bytes = -(s16)sizeof(u32);
124 inc->incr_src = sizeof(u32);
125 inc->incr_dst = 0;
126
127 bcom_set_initiator(tsk->tasknum, BCOM_INITIATOR_ATA_TX);
128}
129EXPORT_SYMBOL_GPL(bcom_ata_tx_prepare);
130
131void bcom_ata_reset_bd(struct bcom_task *tsk)
132{
133 struct bcom_ata_var *var;
134
135 /* Reset all BD */
136 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
137
138 tsk->index = 0;
139 tsk->outdex = 0;
140
141 var = (struct bcom_ata_var *) bcom_task_var(tsk->tasknum);
142 var->bd_start = var->bd_base;
143}
144EXPORT_SYMBOL_GPL(bcom_ata_reset_bd);
145
146void bcom_ata_release(struct bcom_task *tsk)
147{
148 /* Nothing special for the ATA tasks */
149 bcom_task_free(tsk);
150}
151EXPORT_SYMBOL_GPL(bcom_ata_release);
152
153
154MODULE_DESCRIPTION("BestComm ATA task driver");
155MODULE_AUTHOR("John Rigby");
156MODULE_LICENSE("GPL v2");
157
diff --git a/arch/powerpc/sysdev/bestcomm/ata.h b/arch/powerpc/sysdev/bestcomm/ata.h
deleted file mode 100644
index 0b2371811334..000000000000
--- a/arch/powerpc/sysdev/bestcomm/ata.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Header for Bestcomm ATA task driver
3 *
4 *
5 * Copyright (C) 2006 Freescale - John Rigby
6 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __BESTCOMM_ATA_H__
14#define __BESTCOMM_ATA_H__
15
16
17struct bcom_ata_bd {
18 u32 status;
19 u32 src_pa;
20 u32 dst_pa;
21};
22
23extern struct bcom_task * bcom_ata_init(int queue_len, int maxbufsize);
24extern void bcom_ata_rx_prepare(struct bcom_task *tsk);
25extern void bcom_ata_tx_prepare(struct bcom_task *tsk);
26extern void bcom_ata_reset_bd(struct bcom_task *tsk);
27extern void bcom_ata_release(struct bcom_task *tsk);
28
29#endif /* __BESTCOMM_ATA_H__ */
30
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_ata_task.c b/arch/powerpc/sysdev/bestcomm/bcom_ata_task.c
deleted file mode 100644
index cc6049a4e469..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bcom_ata_task.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * Bestcomm ATA task microcode
3 *
4 * Copyright (c) 2004 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * Created based on bestcom/code_dma/image_rtos1/dma_image.hex
11 */
12
13#include <asm/types.h>
14
15/*
16 * The header consists of the following fields:
17 * u32 magic;
18 * u8 desc_size;
19 * u8 var_size;
20 * u8 inc_size;
21 * u8 first_var;
22 * u8 reserved[8];
23 *
24 * The size fields contain the number of 32-bit words.
25 */
26
27u32 bcom_ata_task[] = {
28 /* header */
29 0x4243544b,
30 0x0e060709,
31 0x00000000,
32 0x00000000,
33
34 /* Task descriptors */
35 0x8198009b, /* LCD: idx0 = var3; idx0 <= var2; idx0 += inc3 */
36 0x13e00c08, /* DRD1A: var3 = var1; FN=0 MORE init=31 WS=0 RS=0 */
37 0xb8000264, /* LCD: idx1 = *idx0, idx2 = var0; idx1 < var9; idx1 += inc4, idx2 += inc4 */
38 0x10000f00, /* DRD1A: var3 = idx0; FN=0 MORE init=0 WS=0 RS=0 */
39 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
40 0x0c8cfc8a, /* DRD2B1: *idx2 = EU3(); EU3(*idx2,var10) */
41 0xd8988240, /* LCDEXT: idx1 = idx1; idx1 > var9; idx1 += inc0 */
42 0xf845e011, /* LCDEXT: idx2 = *(idx0 + var00000015); ; idx2 += inc2 */
43 0xb845e00a, /* LCD: idx3 = *(idx0 + var00000019); ; idx3 += inc1 */
44 0x0bfecf90, /* DRD1A: *idx3 = *idx2; FN=0 TFD init=31 WS=3 RS=3 */
45 0x9898802d, /* LCD: idx1 = idx1; idx1 once var0; idx1 += inc5 */
46 0x64000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 INT EXT init=0 WS=0 RS=0 */
47 0x0c0cf849, /* DRD2B1: *idx0 = EU3(); EU3(idx1,var9) */
48 0x000001f8, /* NOP */
49
50 /* VAR[9]-VAR[14] */
51 0x40000000,
52 0x7fff7fff,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57
58 /* INC[0]-INC[6] */
59 0x40000000,
60 0xe0000000,
61 0xe0000000,
62 0xa000000c,
63 0x20000000,
64 0x00000000,
65 0x00000000,
66};
67
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c
deleted file mode 100644
index a1ad6a02fcef..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Bestcomm FEC RX task microcode
3 *
4 * Copyright (c) 2004 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
11 * on Tue Mar 22 11:19:38 2005 GMT
12 */
13
14#include <asm/types.h>
15
16/*
17 * The header consists of the following fields:
18 * u32 magic;
19 * u8 desc_size;
20 * u8 var_size;
21 * u8 inc_size;
22 * u8 first_var;
23 * u8 reserved[8];
24 *
25 * The size fields contain the number of 32-bit words.
26 */
27
28u32 bcom_fec_rx_task[] = {
29 /* header */
30 0x4243544b,
31 0x18060709,
32 0x00000000,
33 0x00000000,
34
35 /* Task descriptors */
36 0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
37 0x10601010, /* DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
38 0xb8800264, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc4, idx3 += inc4 */
39 0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
40 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
41 0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
42 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
43 0xb8c58029, /* LCD: idx3 = *(idx1 + var00000015); idx3 once var0; idx3 += inc5 */
44 0x60000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */
45 0x088cf8cc, /* DRD2B1: idx2 = EU3(); EU3(idx3,var12) */
46 0x991982f2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var11; idx2 += inc6, idx3 += inc2 */
47 0x006acf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=1 RS=1 */
48 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
49 0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
50 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
51 0x034cfc4e, /* DRD2B1: var13 = EU3(); EU3(*idx1,var14) */
52 0x00008868, /* DRD1A: idx2 = var13; FN=0 init=0 WS=0 RS=0 */
53 0x99198341, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var13; idx2 += inc0, idx3 += inc1 */
54 0x007ecf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=3 RS=3 */
55 0x99198272, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc6, idx3 += inc2 */
56 0x046acf80, /* DRD1A: *idx3 = *idx0; FN=0 INT init=3 WS=1 RS=1 */
57 0x9819002d, /* LCD: idx2 = idx0; idx2 once var0; idx2 += inc5 */
58 0x0060c790, /* DRD1A: *idx1 = *idx2; FN=0 init=3 WS=0 RS=0 */
59 0x000001f8, /* NOP */
60
61 /* VAR[9]-VAR[14] */
62 0x40000000,
63 0x7fff7fff,
64 0x00000000,
65 0x00000003,
66 0x40000008,
67 0x43ffffff,
68
69 /* INC[0]-INC[6] */
70 0x40000000,
71 0xe0000000,
72 0xe0000000,
73 0xa0000008,
74 0x20000000,
75 0x00000000,
76 0x4000ffff,
77};
78
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c
deleted file mode 100644
index b1c495c3a65a..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Bestcomm FEC TX task microcode
3 *
4 * Copyright (c) 2004 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
11 * on Tue Mar 22 11:19:29 2005 GMT
12 */
13
14#include <asm/types.h>
15
16/*
17 * The header consists of the following fields:
18 * u32 magic;
19 * u8 desc_size;
20 * u8 var_size;
21 * u8 inc_size;
22 * u8 first_var;
23 * u8 reserved[8];
24 *
25 * The size fields contain the number of 32-bit words.
26 */
27
28u32 bcom_fec_tx_task[] = {
29 /* header */
30 0x4243544b,
31 0x2407070d,
32 0x00000000,
33 0x00000000,
34
35 /* Task descriptors */
36 0x8018001b, /* LCD: idx0 = var0; idx0 <= var0; idx0 += inc3 */
37 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
38 0x01ccfc0d, /* DRD2B1: var7 = EU3(); EU3(*idx0,var13) */
39 0x8082a123, /* LCD: idx0 = var1, idx1 = var5; idx1 <= var4; idx0 += inc4, idx1 += inc3 */
40 0x10801418, /* DRD1A: var5 = var3; FN=0 MORE init=4 WS=0 RS=0 */
41 0xf88103a4, /* LCDEXT: idx2 = *idx1, idx3 = var2; idx2 < var14; idx2 += inc4, idx3 += inc4 */
42 0x801a6024, /* LCD: idx4 = var0; ; idx4 += inc4 */
43 0x10001708, /* DRD1A: var5 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
44 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
45 0x0cccfccf, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var15) */
46 0x991a002c, /* LCD: idx2 = idx2, idx3 = idx4; idx2 once var0; idx2 += inc5, idx3 += inc4 */
47 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
48 0x024cfc4d, /* DRD2B1: var9 = EU3(); EU3(*idx1,var13) */
49 0x60000003, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
50 0x0cccf247, /* DRD2B1: *idx3 = EU3(); EU3(var9,var7) */
51 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
52 0xb8c80029, /* LCD: idx3 = *(idx1 + var0000001a); idx3 once var0; idx3 += inc5 */
53 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
54 0x088cf8d1, /* DRD2B1: idx2 = EU3(); EU3(idx3,var17) */
55 0x00002f10, /* DRD1A: var11 = idx2; FN=0 init=0 WS=0 RS=0 */
56 0x99198432, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var16; idx2 += inc6, idx3 += inc2 */
57 0x008ac398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=1 RS=1 */
58 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
59 0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
60 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
61 0x048cfc53, /* DRD2B1: var18 = EU3(); EU3(*idx1,var19) */
62 0x60000008, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=8 EXT init=0 WS=0 RS=0 */
63 0x088cf48b, /* DRD2B1: idx2 = EU3(); EU3(var18,var11) */
64 0x99198481, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var18; idx2 += inc0, idx3 += inc1 */
65 0x009ec398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=3 RS=3 */
66 0x991983b2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var14; idx2 += inc6, idx3 += inc2 */
67 0x088ac398, /* DRD1A: *idx0 = *idx3; FN=0 TFD init=4 WS=1 RS=1 */
68 0x9919002d, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc5 */
69 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
70 0x0c4cf88e, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var14) */
71 0x000001f8, /* NOP */
72
73 /* VAR[13]-VAR[19] */
74 0x0c000000,
75 0x40000000,
76 0x7fff7fff,
77 0x00000000,
78 0x00000003,
79 0x40000004,
80 0x43ffffff,
81
82 /* INC[0]-INC[6] */
83 0x40000000,
84 0xe0000000,
85 0xe0000000,
86 0xa0000008,
87 0x20000000,
88 0x00000000,
89 0x4000ffff,
90};
91
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c
deleted file mode 100644
index efee022b0256..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Bestcomm GenBD RX task microcode
3 *
4 * Copyright (C) 2006 AppSpec Computer Technologies Corp.
5 * Jeff Gibbons <jeff.gibbons@appspec.com>
6 * Copyright (c) 2004 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 * Based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
13 * on Tue Mar 4 10:14:12 2006 GMT
14 *
15 */
16
17#include <asm/types.h>
18
19/*
20 * The header consists of the following fields:
21 * u32 magic;
22 * u8 desc_size;
23 * u8 var_size;
24 * u8 inc_size;
25 * u8 first_var;
26 * u8 reserved[8];
27 *
28 * The size fields contain the number of 32-bit words.
29 */
30
31u32 bcom_gen_bd_rx_task[] = {
32 /* header */
33 0x4243544b,
34 0x0d020409,
35 0x00000000,
36 0x00000000,
37
38 /* Task descriptors */
39 0x808220da, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc3, idx1 += inc2 */
40 0x13e01010, /* DRD1A: var4 = var2; FN=0 MORE init=31 WS=0 RS=0 */
41 0xb880025b, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc3, idx3 += inc3 */
42 0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
43 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
44 0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
45 0xd9190240, /* LCDEXT: idx2 = idx2; idx2 > var9; idx2 += inc0 */
46 0xb8c5e009, /* LCD: idx3 = *(idx1 + var00000015); ; idx3 += inc1 */
47 0x07fecf80, /* DRD1A: *idx3 = *idx0; FN=0 INT init=31 WS=3 RS=3 */
48 0x99190024, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc4 */
49 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
50 0x0c4cf889, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var9) */
51 0x000001f8, /* NOP */
52
53 /* VAR[9]-VAR[10] */
54 0x40000000,
55 0x7fff7fff,
56
57 /* INC[0]-INC[3] */
58 0x40000000,
59 0xe0000000,
60 0xa0000008,
61 0x20000000,
62};
63
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c
deleted file mode 100644
index c605aa42ecbb..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Bestcomm GenBD TX task microcode
3 *
4 * Copyright (C) 2006 AppSpec Computer Technologies Corp.
5 * Jeff Gibbons <jeff.gibbons@appspec.com>
6 * Copyright (c) 2004 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 * Based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
13 * on Tue Mar 4 10:14:12 2006 GMT
14 *
15 */
16
17#include <asm/types.h>
18
19/*
20 * The header consists of the following fields:
21 * u32 magic;
22 * u8 desc_size;
23 * u8 var_size;
24 * u8 inc_size;
25 * u8 first_var;
26 * u8 reserved[8];
27 *
28 * The size fields contain the number of 32-bit words.
29 */
30
31u32 bcom_gen_bd_tx_task[] = {
32 /* header */
33 0x4243544b,
34 0x0f040609,
35 0x00000000,
36 0x00000000,
37
38 /* Task descriptors */
39 0x800220e3, /* LCD: idx0 = var0, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
40 0x13e01010, /* DRD1A: var4 = var2; FN=0 MORE init=31 WS=0 RS=0 */
41 0xb8808264, /* LCD: idx2 = *idx1, idx3 = var1; idx2 < var9; idx2 += inc4, idx3 += inc4 */
42 0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
43 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
44 0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
45 0xd9190300, /* LCDEXT: idx2 = idx2; idx2 > var12; idx2 += inc0 */
46 0xb8c5e009, /* LCD: idx3 = *(idx1 + var00000015); ; idx3 += inc1 */
47 0x03fec398, /* DRD1A: *idx0 = *idx3; FN=0 init=31 WS=3 RS=3 */
48 0x9919826a, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc5, idx3 += inc2 */
49 0x0feac398, /* DRD1A: *idx0 = *idx3; FN=0 TFD INT init=31 WS=1 RS=1 */
50 0x99190036, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc6 */
51 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
52 0x0c4cf889, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var9) */
53 0x000001f8, /* NOP */
54
55 /* VAR[9]-VAR[12] */
56 0x40000000,
57 0x7fff7fff,
58 0x00000000,
59 0x40000004,
60
61 /* INC[0]-INC[5] */
62 0x40000000,
63 0xe0000000,
64 0xe0000000,
65 0xa0000008,
66 0x20000000,
67 0x4000ffff,
68};
69
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.c b/arch/powerpc/sysdev/bestcomm/bestcomm.c
deleted file mode 100644
index d9130630f7ef..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.c
+++ /dev/null
@@ -1,531 +0,0 @@
1/*
2 * Driver for MPC52xx processor BestComm peripheral controller
3 *
4 *
5 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2005 Varma Electronics Oy,
7 * ( by Andrey Volkov <avolkov@varma-el.com> )
8 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
9 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/of_platform.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include <asm/mpc52xx.h>
25
26#include "sram.h"
27#include "bestcomm_priv.h"
28#include "bestcomm.h"
29
30#define DRIVER_NAME "bestcomm-core"
31
32/* MPC5200 device tree match tables */
33static struct of_device_id mpc52xx_sram_ids[] = {
34 { .compatible = "fsl,mpc5200-sram", },
35 { .compatible = "mpc5200-sram", },
36 {}
37};
38
39
40struct bcom_engine *bcom_eng = NULL;
41EXPORT_SYMBOL_GPL(bcom_eng); /* needed for inline functions */
42
43/* ======================================================================== */
44/* Public and private API */
45/* ======================================================================== */
46
47/* Private API */
48
49struct bcom_task *
50bcom_task_alloc(int bd_count, int bd_size, int priv_size)
51{
52 int i, tasknum = -1;
53 struct bcom_task *tsk;
54
55 /* Don't try to do anything if bestcomm init failed */
56 if (!bcom_eng)
57 return NULL;
58
59 /* Get and reserve a task num */
60 spin_lock(&bcom_eng->lock);
61
62 for (i=0; i<BCOM_MAX_TASKS; i++)
63 if (!bcom_eng->tdt[i].stop) { /* we use stop as a marker */
64 bcom_eng->tdt[i].stop = 0xfffffffful; /* dummy addr */
65 tasknum = i;
66 break;
67 }
68
69 spin_unlock(&bcom_eng->lock);
70
71 if (tasknum < 0)
72 return NULL;
73
74 /* Allocate our structure */
75 tsk = kzalloc(sizeof(struct bcom_task) + priv_size, GFP_KERNEL);
76 if (!tsk)
77 goto error;
78
79 tsk->tasknum = tasknum;
80 if (priv_size)
81 tsk->priv = (void*)tsk + sizeof(struct bcom_task);
82
83 /* Get IRQ of that task */
84 tsk->irq = irq_of_parse_and_map(bcom_eng->ofnode, tsk->tasknum);
85 if (tsk->irq == NO_IRQ)
86 goto error;
87
88 /* Init the BDs, if needed */
89 if (bd_count) {
90 tsk->cookie = kmalloc(sizeof(void*) * bd_count, GFP_KERNEL);
91 if (!tsk->cookie)
92 goto error;
93
94 tsk->bd = bcom_sram_alloc(bd_count * bd_size, 4, &tsk->bd_pa);
95 if (!tsk->bd)
96 goto error;
97 memset(tsk->bd, 0x00, bd_count * bd_size);
98
99 tsk->num_bd = bd_count;
100 tsk->bd_size = bd_size;
101 }
102
103 return tsk;
104
105error:
106 if (tsk) {
107 if (tsk->irq != NO_IRQ)
108 irq_dispose_mapping(tsk->irq);
109 bcom_sram_free(tsk->bd);
110 kfree(tsk->cookie);
111 kfree(tsk);
112 }
113
114 bcom_eng->tdt[tasknum].stop = 0;
115
116 return NULL;
117}
118EXPORT_SYMBOL_GPL(bcom_task_alloc);
119
120void
121bcom_task_free(struct bcom_task *tsk)
122{
123 /* Stop the task */
124 bcom_disable_task(tsk->tasknum);
125
126 /* Clear TDT */
127 bcom_eng->tdt[tsk->tasknum].start = 0;
128 bcom_eng->tdt[tsk->tasknum].stop = 0;
129
130 /* Free everything */
131 irq_dispose_mapping(tsk->irq);
132 bcom_sram_free(tsk->bd);
133 kfree(tsk->cookie);
134 kfree(tsk);
135}
136EXPORT_SYMBOL_GPL(bcom_task_free);
137
138int
139bcom_load_image(int task, u32 *task_image)
140{
141 struct bcom_task_header *hdr = (struct bcom_task_header *)task_image;
142 struct bcom_tdt *tdt;
143 u32 *desc, *var, *inc;
144 u32 *desc_src, *var_src, *inc_src;
145
146 /* Safety checks */
147 if (hdr->magic != BCOM_TASK_MAGIC) {
148 printk(KERN_ERR DRIVER_NAME
149 ": Trying to load invalid microcode\n");
150 return -EINVAL;
151 }
152
153 if ((task < 0) || (task >= BCOM_MAX_TASKS)) {
154 printk(KERN_ERR DRIVER_NAME
155 ": Trying to load invalid task %d\n", task);
156 return -EINVAL;
157 }
158
159 /* Initial load or reload */
160 tdt = &bcom_eng->tdt[task];
161
162 if (tdt->start) {
163 desc = bcom_task_desc(task);
164 if (hdr->desc_size != bcom_task_num_descs(task)) {
165 printk(KERN_ERR DRIVER_NAME
166 ": Trying to reload wrong task image "
167 "(%d size %d/%d)!\n",
168 task,
169 hdr->desc_size,
170 bcom_task_num_descs(task));
171 return -EINVAL;
172 }
173 } else {
174 phys_addr_t start_pa;
175
176 desc = bcom_sram_alloc(hdr->desc_size * sizeof(u32), 4, &start_pa);
177 if (!desc)
178 return -ENOMEM;
179
180 tdt->start = start_pa;
181 tdt->stop = start_pa + ((hdr->desc_size-1) * sizeof(u32));
182 }
183
184 var = bcom_task_var(task);
185 inc = bcom_task_inc(task);
186
187 /* Clear & copy */
188 memset(var, 0x00, BCOM_VAR_SIZE);
189 memset(inc, 0x00, BCOM_INC_SIZE);
190
191 desc_src = (u32 *)(hdr + 1);
192 var_src = desc_src + hdr->desc_size;
193 inc_src = var_src + hdr->var_size;
194
195 memcpy(desc, desc_src, hdr->desc_size * sizeof(u32));
196 memcpy(var + hdr->first_var, var_src, hdr->var_size * sizeof(u32));
197 memcpy(inc, inc_src, hdr->inc_size * sizeof(u32));
198
199 return 0;
200}
201EXPORT_SYMBOL_GPL(bcom_load_image);
202
203void
204bcom_set_initiator(int task, int initiator)
205{
206 int i;
207 int num_descs;
208 u32 *desc;
209 int next_drd_has_initiator;
210
211 bcom_set_tcr_initiator(task, initiator);
212
213 /* Just setting tcr is apparently not enough due to some problem */
214 /* with it. So we just go thru all the microcode and replace in */
215 /* the DRD directly */
216
217 desc = bcom_task_desc(task);
218 next_drd_has_initiator = 1;
219 num_descs = bcom_task_num_descs(task);
220
221 for (i=0; i<num_descs; i++, desc++) {
222 if (!bcom_desc_is_drd(*desc))
223 continue;
224 if (next_drd_has_initiator)
225 if (bcom_desc_initiator(*desc) != BCOM_INITIATOR_ALWAYS)
226 bcom_set_desc_initiator(desc, initiator);
227 next_drd_has_initiator = !bcom_drd_is_extended(*desc);
228 }
229}
230EXPORT_SYMBOL_GPL(bcom_set_initiator);
231
232
233/* Public API */
234
235void
236bcom_enable(struct bcom_task *tsk)
237{
238 bcom_enable_task(tsk->tasknum);
239}
240EXPORT_SYMBOL_GPL(bcom_enable);
241
242void
243bcom_disable(struct bcom_task *tsk)
244{
245 bcom_disable_task(tsk->tasknum);
246}
247EXPORT_SYMBOL_GPL(bcom_disable);
248
249
250/* ======================================================================== */
251/* Engine init/cleanup */
252/* ======================================================================== */
253
254/* Function Descriptor table */
255/* this will need to be updated if Freescale changes their task code FDT */
256static u32 fdt_ops[] = {
257 0xa0045670, /* FDT[48] - load_acc() */
258 0x80045670, /* FDT[49] - unload_acc() */
259 0x21800000, /* FDT[50] - and() */
260 0x21e00000, /* FDT[51] - or() */
261 0x21500000, /* FDT[52] - xor() */
262 0x21400000, /* FDT[53] - andn() */
263 0x21500000, /* FDT[54] - not() */
264 0x20400000, /* FDT[55] - add() */
265 0x20500000, /* FDT[56] - sub() */
266 0x20800000, /* FDT[57] - lsh() */
267 0x20a00000, /* FDT[58] - rsh() */
268 0xc0170000, /* FDT[59] - crc8() */
269 0xc0145670, /* FDT[60] - crc16() */
270 0xc0345670, /* FDT[61] - crc32() */
271 0xa0076540, /* FDT[62] - endian32() */
272 0xa0000760, /* FDT[63] - endian16() */
273};
274
275
276static int bcom_engine_init(void)
277{
278 int task;
279 phys_addr_t tdt_pa, ctx_pa, var_pa, fdt_pa;
280 unsigned int tdt_size, ctx_size, var_size, fdt_size;
281
282 /* Allocate & clear SRAM zones for FDT, TDTs, contexts and vars/incs */
283 tdt_size = BCOM_MAX_TASKS * sizeof(struct bcom_tdt);
284 ctx_size = BCOM_MAX_TASKS * BCOM_CTX_SIZE;
285 var_size = BCOM_MAX_TASKS * (BCOM_VAR_SIZE + BCOM_INC_SIZE);
286 fdt_size = BCOM_FDT_SIZE;
287
288 bcom_eng->tdt = bcom_sram_alloc(tdt_size, sizeof(u32), &tdt_pa);
289 bcom_eng->ctx = bcom_sram_alloc(ctx_size, BCOM_CTX_ALIGN, &ctx_pa);
290 bcom_eng->var = bcom_sram_alloc(var_size, BCOM_VAR_ALIGN, &var_pa);
291 bcom_eng->fdt = bcom_sram_alloc(fdt_size, BCOM_FDT_ALIGN, &fdt_pa);
292
293 if (!bcom_eng->tdt || !bcom_eng->ctx || !bcom_eng->var || !bcom_eng->fdt) {
294 printk(KERN_ERR "DMA: SRAM alloc failed in engine init !\n");
295
296 bcom_sram_free(bcom_eng->tdt);
297 bcom_sram_free(bcom_eng->ctx);
298 bcom_sram_free(bcom_eng->var);
299 bcom_sram_free(bcom_eng->fdt);
300
301 return -ENOMEM;
302 }
303
304 memset(bcom_eng->tdt, 0x00, tdt_size);
305 memset(bcom_eng->ctx, 0x00, ctx_size);
306 memset(bcom_eng->var, 0x00, var_size);
307 memset(bcom_eng->fdt, 0x00, fdt_size);
308
309 /* Copy the FDT for the EU#3 */
310 memcpy(&bcom_eng->fdt[48], fdt_ops, sizeof(fdt_ops));
311
312 /* Initialize Task base structure */
313 for (task=0; task<BCOM_MAX_TASKS; task++)
314 {
315 out_be16(&bcom_eng->regs->tcr[task], 0);
316 out_8(&bcom_eng->regs->ipr[task], 0);
317
318 bcom_eng->tdt[task].context = ctx_pa;
319 bcom_eng->tdt[task].var = var_pa;
320 bcom_eng->tdt[task].fdt = fdt_pa;
321
322 var_pa += BCOM_VAR_SIZE + BCOM_INC_SIZE;
323 ctx_pa += BCOM_CTX_SIZE;
324 }
325
326 out_be32(&bcom_eng->regs->taskBar, tdt_pa);
327
328 /* Init 'always' initiator */
329 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ALWAYS], BCOM_IPR_ALWAYS);
330
331 /* Disable COMM Bus Prefetch on the original 5200; it's broken */
332 if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
333 bcom_disable_prefetch();
334
335 /* Init lock */
336 spin_lock_init(&bcom_eng->lock);
337
338 return 0;
339}
340
341static void
342bcom_engine_cleanup(void)
343{
344 int task;
345
346 /* Stop all tasks */
347 for (task=0; task<BCOM_MAX_TASKS; task++)
348 {
349 out_be16(&bcom_eng->regs->tcr[task], 0);
350 out_8(&bcom_eng->regs->ipr[task], 0);
351 }
352
353 out_be32(&bcom_eng->regs->taskBar, 0ul);
354
355 /* Release the SRAM zones */
356 bcom_sram_free(bcom_eng->tdt);
357 bcom_sram_free(bcom_eng->ctx);
358 bcom_sram_free(bcom_eng->var);
359 bcom_sram_free(bcom_eng->fdt);
360}
361
362
363/* ======================================================================== */
364/* OF platform driver */
365/* ======================================================================== */
366
367static int mpc52xx_bcom_probe(struct platform_device *op)
368{
369 struct device_node *ofn_sram;
370 struct resource res_bcom;
371
372 int rv;
373
374 /* Inform user we're ok so far */
375 printk(KERN_INFO "DMA: MPC52xx BestComm driver\n");
376
377 /* Get the bestcomm node */
378 of_node_get(op->dev.of_node);
379
380 /* Prepare SRAM */
381 ofn_sram = of_find_matching_node(NULL, mpc52xx_sram_ids);
382 if (!ofn_sram) {
383 printk(KERN_ERR DRIVER_NAME ": "
384 "No SRAM found in device tree\n");
385 rv = -ENODEV;
386 goto error_ofput;
387 }
388 rv = bcom_sram_init(ofn_sram, DRIVER_NAME);
389 of_node_put(ofn_sram);
390
391 if (rv) {
392 printk(KERN_ERR DRIVER_NAME ": "
393 "Error in SRAM init\n");
394 goto error_ofput;
395 }
396
397 /* Get a clean struct */
398 bcom_eng = kzalloc(sizeof(struct bcom_engine), GFP_KERNEL);
399 if (!bcom_eng) {
400 printk(KERN_ERR DRIVER_NAME ": "
401 "Can't allocate state structure\n");
402 rv = -ENOMEM;
403 goto error_sramclean;
404 }
405
406 /* Save the node */
407 bcom_eng->ofnode = op->dev.of_node;
408
409 /* Get, reserve & map io */
410 if (of_address_to_resource(op->dev.of_node, 0, &res_bcom)) {
411 printk(KERN_ERR DRIVER_NAME ": "
412 "Can't get resource\n");
413 rv = -EINVAL;
414 goto error_sramclean;
415 }
416
417 if (!request_mem_region(res_bcom.start, sizeof(struct mpc52xx_sdma),
418 DRIVER_NAME)) {
419 printk(KERN_ERR DRIVER_NAME ": "
420 "Can't request registers region\n");
421 rv = -EBUSY;
422 goto error_sramclean;
423 }
424
425 bcom_eng->regs_base = res_bcom.start;
426 bcom_eng->regs = ioremap(res_bcom.start, sizeof(struct mpc52xx_sdma));
427 if (!bcom_eng->regs) {
428 printk(KERN_ERR DRIVER_NAME ": "
429 "Can't map registers\n");
430 rv = -ENOMEM;
431 goto error_release;
432 }
433
434 /* Now, do the real init */
435 rv = bcom_engine_init();
436 if (rv)
437 goto error_unmap;
438
439 /* Done ! */
440 printk(KERN_INFO "DMA: MPC52xx BestComm engine @%08lx ok !\n",
441 (long)bcom_eng->regs_base);
442
443 return 0;
444
445 /* Error path */
446error_unmap:
447 iounmap(bcom_eng->regs);
448error_release:
449 release_mem_region(res_bcom.start, sizeof(struct mpc52xx_sdma));
450error_sramclean:
451 kfree(bcom_eng);
452 bcom_sram_cleanup();
453error_ofput:
454 of_node_put(op->dev.of_node);
455
456 printk(KERN_ERR "DMA: MPC52xx BestComm init failed !\n");
457
458 return rv;
459}
460
461
462static int mpc52xx_bcom_remove(struct platform_device *op)
463{
464 /* Clean up the engine */
465 bcom_engine_cleanup();
466
467 /* Cleanup SRAM */
468 bcom_sram_cleanup();
469
470 /* Release regs */
471 iounmap(bcom_eng->regs);
472 release_mem_region(bcom_eng->regs_base, sizeof(struct mpc52xx_sdma));
473
474 /* Release the node */
475 of_node_put(bcom_eng->ofnode);
476
477 /* Release memory */
478 kfree(bcom_eng);
479 bcom_eng = NULL;
480
481 return 0;
482}
483
484static struct of_device_id mpc52xx_bcom_of_match[] = {
485 { .compatible = "fsl,mpc5200-bestcomm", },
486 { .compatible = "mpc5200-bestcomm", },
487 {},
488};
489
490MODULE_DEVICE_TABLE(of, mpc52xx_bcom_of_match);
491
492
493static struct platform_driver mpc52xx_bcom_of_platform_driver = {
494 .probe = mpc52xx_bcom_probe,
495 .remove = mpc52xx_bcom_remove,
496 .driver = {
497 .name = DRIVER_NAME,
498 .owner = THIS_MODULE,
499 .of_match_table = mpc52xx_bcom_of_match,
500 },
501};
502
503
504/* ======================================================================== */
505/* Module */
506/* ======================================================================== */
507
508static int __init
509mpc52xx_bcom_init(void)
510{
511 return platform_driver_register(&mpc52xx_bcom_of_platform_driver);
512}
513
514static void __exit
515mpc52xx_bcom_exit(void)
516{
517 platform_driver_unregister(&mpc52xx_bcom_of_platform_driver);
518}
519
520/* If we're not a module, we must make sure everything is setup before */
521/* anyone tries to use us ... that's why we use subsys_initcall instead */
522/* of module_init. */
523subsys_initcall(mpc52xx_bcom_init);
524module_exit(mpc52xx_bcom_exit);
525
526MODULE_DESCRIPTION("Freescale MPC52xx BestComm DMA");
527MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
528MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
529MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
530MODULE_LICENSE("GPL v2");
531
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.h b/arch/powerpc/sysdev/bestcomm/bestcomm.h
deleted file mode 100644
index a0e2e6b19b57..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.h
+++ /dev/null
@@ -1,213 +0,0 @@
1/*
2 * Public header for the MPC52xx processor BestComm driver
3 *
4 *
5 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2005 Varma Electronics Oy,
7 * ( by Andrey Volkov <avolkov@varma-el.com> )
8 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
9 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#ifndef __BESTCOMM_H__
17#define __BESTCOMM_H__
18
19/**
20 * struct bcom_bd - Structure describing a generic BestComm buffer descriptor
21 * @status: The current status of this buffer. Exact meaning depends on the
22 * task type
23 * @data: An array of u32 extra data. Size of array is task dependent.
24 *
25 * Note: Don't dereference a bcom_bd pointer as an array. The size of the
26 * bcom_bd is variable. Use bcom_get_bd() instead.
27 */
28struct bcom_bd {
29 u32 status;
30 u32 data[0]; /* variable payload size */
31};
32
33/* ======================================================================== */
34/* Generic task management */
35/* ======================================================================== */
36
37/**
38 * struct bcom_task - Structure describing a loaded BestComm task
39 *
40 * This structure is never built by the driver it self. It's built and
41 * filled the intermediate layer of the BestComm API, the task dependent
42 * support code.
43 *
44 * Most likely you don't need to poke around inside this structure. The
45 * fields are exposed in the header just for the sake of inline functions
46 */
47struct bcom_task {
48 unsigned int tasknum;
49 unsigned int flags;
50 int irq;
51
52 struct bcom_bd *bd;
53 phys_addr_t bd_pa;
54 void **cookie;
55 unsigned short index;
56 unsigned short outdex;
57 unsigned int num_bd;
58 unsigned int bd_size;
59
60 void* priv;
61};
62
63#define BCOM_FLAGS_NONE 0x00000000ul
64#define BCOM_FLAGS_ENABLE_TASK (1ul << 0)
65
66/**
67 * bcom_enable - Enable a BestComm task
68 * @tsk: The BestComm task structure
69 *
70 * This function makes sure the given task is enabled and can be run
71 * by the BestComm engine as needed
72 */
73extern void bcom_enable(struct bcom_task *tsk);
74
75/**
76 * bcom_disable - Disable a BestComm task
77 * @tsk: The BestComm task structure
78 *
79 * This function disable a given task, making sure it's not executed
80 * by the BestComm engine.
81 */
82extern void bcom_disable(struct bcom_task *tsk);
83
84
85/**
86 * bcom_get_task_irq - Returns the irq number of a BestComm task
87 * @tsk: The BestComm task structure
88 */
89static inline int
90bcom_get_task_irq(struct bcom_task *tsk) {
91 return tsk->irq;
92}
93
94/* ======================================================================== */
95/* BD based tasks helpers */
96/* ======================================================================== */
97
98#define BCOM_BD_READY 0x40000000ul
99
100/** _bcom_next_index - Get next input index.
101 * @tsk: pointer to task structure
102 *
103 * Support function; Device drivers should not call this
104 */
105static inline int
106_bcom_next_index(struct bcom_task *tsk)
107{
108 return ((tsk->index + 1) == tsk->num_bd) ? 0 : tsk->index + 1;
109}
110
111/** _bcom_next_outdex - Get next output index.
112 * @tsk: pointer to task structure
113 *
114 * Support function; Device drivers should not call this
115 */
116static inline int
117_bcom_next_outdex(struct bcom_task *tsk)
118{
119 return ((tsk->outdex + 1) == tsk->num_bd) ? 0 : tsk->outdex + 1;
120}
121
122/**
123 * bcom_queue_empty - Checks if a BestComm task BD queue is empty
124 * @tsk: The BestComm task structure
125 */
126static inline int
127bcom_queue_empty(struct bcom_task *tsk)
128{
129 return tsk->index == tsk->outdex;
130}
131
132/**
133 * bcom_queue_full - Checks if a BestComm task BD queue is full
134 * @tsk: The BestComm task structure
135 */
136static inline int
137bcom_queue_full(struct bcom_task *tsk)
138{
139 return tsk->outdex == _bcom_next_index(tsk);
140}
141
142/**
143 * bcom_get_bd - Get a BD from the queue
144 * @tsk: The BestComm task structure
145 * index: Index of the BD to fetch
146 */
147static inline struct bcom_bd
148*bcom_get_bd(struct bcom_task *tsk, unsigned int index)
149{
150 /* A cast to (void*) so the address can be incremented by the
151 * real size instead of by sizeof(struct bcom_bd) */
152 return ((void *)tsk->bd) + (index * tsk->bd_size);
153}
154
155/**
156 * bcom_buffer_done - Checks if a BestComm
157 * @tsk: The BestComm task structure
158 */
159static inline int
160bcom_buffer_done(struct bcom_task *tsk)
161{
162 struct bcom_bd *bd;
163 if (bcom_queue_empty(tsk))
164 return 0;
165
166 bd = bcom_get_bd(tsk, tsk->outdex);
167 return !(bd->status & BCOM_BD_READY);
168}
169
170/**
171 * bcom_prepare_next_buffer - clear status of next available buffer.
172 * @tsk: The BestComm task structure
173 *
174 * Returns pointer to next buffer descriptor
175 */
176static inline struct bcom_bd *
177bcom_prepare_next_buffer(struct bcom_task *tsk)
178{
179 struct bcom_bd *bd;
180
181 bd = bcom_get_bd(tsk, tsk->index);
182 bd->status = 0; /* cleanup last status */
183 return bd;
184}
185
186static inline void
187bcom_submit_next_buffer(struct bcom_task *tsk, void *cookie)
188{
189 struct bcom_bd *bd = bcom_get_bd(tsk, tsk->index);
190
191 tsk->cookie[tsk->index] = cookie;
192 mb(); /* ensure the bd is really up-to-date */
193 bd->status |= BCOM_BD_READY;
194 tsk->index = _bcom_next_index(tsk);
195 if (tsk->flags & BCOM_FLAGS_ENABLE_TASK)
196 bcom_enable(tsk);
197}
198
199static inline void *
200bcom_retrieve_buffer(struct bcom_task *tsk, u32 *p_status, struct bcom_bd **p_bd)
201{
202 void *cookie = tsk->cookie[tsk->outdex];
203 struct bcom_bd *bd = bcom_get_bd(tsk, tsk->outdex);
204
205 if (p_status)
206 *p_status = bd->status;
207 if (p_bd)
208 *p_bd = bd;
209 tsk->outdex = _bcom_next_outdex(tsk);
210 return cookie;
211}
212
213#endif /* __BESTCOMM_H__ */
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h b/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
deleted file mode 100644
index 3b52f3ffbdf8..000000000000
--- a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
+++ /dev/null
@@ -1,350 +0,0 @@
1/*
2 * Private header for the MPC52xx processor BestComm driver
3 *
4 * By private, we mean that driver should not use it directly. It's meant
5 * to be used by the BestComm engine driver itself and by the intermediate
6 * layer between the core and the drivers.
7 *
8 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
9 * Copyright (C) 2005 Varma Electronics Oy,
10 * ( by Andrey Volkov <avolkov@varma-el.com> )
11 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
12 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
13 *
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
17 */
18
19#ifndef __BESTCOMM_PRIV_H__
20#define __BESTCOMM_PRIV_H__
21
22#include <linux/spinlock.h>
23#include <linux/of.h>
24#include <asm/io.h>
25#include <asm/mpc52xx.h>
26
27#include "sram.h"
28
29
30/* ======================================================================== */
31/* Engine related stuff */
32/* ======================================================================== */
33
34/* Zones sizes and needed alignments */
35#define BCOM_MAX_TASKS 16
36#define BCOM_MAX_VAR 24
37#define BCOM_MAX_INC 8
38#define BCOM_MAX_FDT 64
39#define BCOM_MAX_CTX 20
40#define BCOM_CTX_SIZE (BCOM_MAX_CTX * sizeof(u32))
41#define BCOM_CTX_ALIGN 0x100
42#define BCOM_VAR_SIZE (BCOM_MAX_VAR * sizeof(u32))
43#define BCOM_INC_SIZE (BCOM_MAX_INC * sizeof(u32))
44#define BCOM_VAR_ALIGN 0x80
45#define BCOM_FDT_SIZE (BCOM_MAX_FDT * sizeof(u32))
46#define BCOM_FDT_ALIGN 0x100
47
48/**
49 * struct bcom_tdt - Task Descriptor Table Entry
50 *
51 */
52struct bcom_tdt {
53 u32 start;
54 u32 stop;
55 u32 var;
56 u32 fdt;
57 u32 exec_status; /* used internally by BestComm engine */
58 u32 mvtp; /* used internally by BestComm engine */
59 u32 context;
60 u32 litbase;
61};
62
63/**
64 * struct bcom_engine
65 *
66 * This holds all info needed globaly to handle the engine
67 */
68struct bcom_engine {
69 struct device_node *ofnode;
70 struct mpc52xx_sdma __iomem *regs;
71 phys_addr_t regs_base;
72
73 struct bcom_tdt *tdt;
74 u32 *ctx;
75 u32 *var;
76 u32 *fdt;
77
78 spinlock_t lock;
79};
80
81extern struct bcom_engine *bcom_eng;
82
83
84/* ======================================================================== */
85/* Tasks related stuff */
86/* ======================================================================== */
87
88/* Tasks image header */
89#define BCOM_TASK_MAGIC 0x4243544B /* 'BCTK' */
90
91struct bcom_task_header {
92 u32 magic;
93 u8 desc_size; /* the size fields */
94 u8 var_size; /* are given in number */
95 u8 inc_size; /* of 32-bits words */
96 u8 first_var;
97 u8 reserved[8];
98};
99
100/* Descriptors structure & co */
101#define BCOM_DESC_NOP 0x000001f8
102#define BCOM_LCD_MASK 0x80000000
103#define BCOM_DRD_EXTENDED 0x40000000
104#define BCOM_DRD_INITIATOR_SHIFT 21
105
106/* Tasks pragma */
107#define BCOM_PRAGMA_BIT_RSV 7 /* reserved pragma bit */
108#define BCOM_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, */
109 /* 1=iter end */
110#define BCOM_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on */
111 /* task enable */
112#define BCOM_PRAGMA_BIT_PACK 4 /* pack data enable */
113#define BCOM_PRAGMA_BIT_INTEGER 3 /* data alignment */
114 /* 0=frac(msb), 1=int(lsb) */
115#define BCOM_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read */
116#define BCOM_PRAGMA_BIT_CW 1 /* write line buffer enable */
117#define BCOM_PRAGMA_BIT_RL 0 /* read line buffer enable */
118
119 /* Looks like XLB speculative read generates XLB errors when a buffer
120 * is at the end of the physical memory. i.e. when accessing the
121 * lasts words, the engine tries to prefetch the next but there is no
122 * next ...
123 */
124#define BCOM_STD_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \
125 (0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
126 (0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \
127 (0 << BCOM_PRAGMA_BIT_PACK) | \
128 (0 << BCOM_PRAGMA_BIT_INTEGER) | \
129 (0 << BCOM_PRAGMA_BIT_SPECREAD) | \
130 (1 << BCOM_PRAGMA_BIT_CW) | \
131 (1 << BCOM_PRAGMA_BIT_RL))
132
133#define BCOM_PCI_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \
134 (0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
135 (0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \
136 (0 << BCOM_PRAGMA_BIT_PACK) | \
137 (1 << BCOM_PRAGMA_BIT_INTEGER) | \
138 (0 << BCOM_PRAGMA_BIT_SPECREAD) | \
139 (1 << BCOM_PRAGMA_BIT_CW) | \
140 (1 << BCOM_PRAGMA_BIT_RL))
141
142#define BCOM_ATA_PRAGMA BCOM_STD_PRAGMA
143#define BCOM_CRC16_DP_0_PRAGMA BCOM_STD_PRAGMA
144#define BCOM_CRC16_DP_1_PRAGMA BCOM_STD_PRAGMA
145#define BCOM_FEC_RX_BD_PRAGMA BCOM_STD_PRAGMA
146#define BCOM_FEC_TX_BD_PRAGMA BCOM_STD_PRAGMA
147#define BCOM_GEN_DP_0_PRAGMA BCOM_STD_PRAGMA
148#define BCOM_GEN_DP_1_PRAGMA BCOM_STD_PRAGMA
149#define BCOM_GEN_DP_2_PRAGMA BCOM_STD_PRAGMA
150#define BCOM_GEN_DP_3_PRAGMA BCOM_STD_PRAGMA
151#define BCOM_GEN_DP_BD_0_PRAGMA BCOM_STD_PRAGMA
152#define BCOM_GEN_DP_BD_1_PRAGMA BCOM_STD_PRAGMA
153#define BCOM_GEN_RX_BD_PRAGMA BCOM_STD_PRAGMA
154#define BCOM_GEN_TX_BD_PRAGMA BCOM_STD_PRAGMA
155#define BCOM_GEN_LPC_PRAGMA BCOM_STD_PRAGMA
156#define BCOM_PCI_RX_PRAGMA BCOM_PCI_PRAGMA
157#define BCOM_PCI_TX_PRAGMA BCOM_PCI_PRAGMA
158
159/* Initiators number */
160#define BCOM_INITIATOR_ALWAYS 0
161#define BCOM_INITIATOR_SCTMR_0 1
162#define BCOM_INITIATOR_SCTMR_1 2
163#define BCOM_INITIATOR_FEC_RX 3
164#define BCOM_INITIATOR_FEC_TX 4
165#define BCOM_INITIATOR_ATA_RX 5
166#define BCOM_INITIATOR_ATA_TX 6
167#define BCOM_INITIATOR_SCPCI_RX 7
168#define BCOM_INITIATOR_SCPCI_TX 8
169#define BCOM_INITIATOR_PSC3_RX 9
170#define BCOM_INITIATOR_PSC3_TX 10
171#define BCOM_INITIATOR_PSC2_RX 11
172#define BCOM_INITIATOR_PSC2_TX 12
173#define BCOM_INITIATOR_PSC1_RX 13
174#define BCOM_INITIATOR_PSC1_TX 14
175#define BCOM_INITIATOR_SCTMR_2 15
176#define BCOM_INITIATOR_SCLPC 16
177#define BCOM_INITIATOR_PSC5_RX 17
178#define BCOM_INITIATOR_PSC5_TX 18
179#define BCOM_INITIATOR_PSC4_RX 19
180#define BCOM_INITIATOR_PSC4_TX 20
181#define BCOM_INITIATOR_I2C2_RX 21
182#define BCOM_INITIATOR_I2C2_TX 22
183#define BCOM_INITIATOR_I2C1_RX 23
184#define BCOM_INITIATOR_I2C1_TX 24
185#define BCOM_INITIATOR_PSC6_RX 25
186#define BCOM_INITIATOR_PSC6_TX 26
187#define BCOM_INITIATOR_IRDA_RX 25
188#define BCOM_INITIATOR_IRDA_TX 26
189#define BCOM_INITIATOR_SCTMR_3 27
190#define BCOM_INITIATOR_SCTMR_4 28
191#define BCOM_INITIATOR_SCTMR_5 29
192#define BCOM_INITIATOR_SCTMR_6 30
193#define BCOM_INITIATOR_SCTMR_7 31
194
195/* Initiators priorities */
196#define BCOM_IPR_ALWAYS 7
197#define BCOM_IPR_SCTMR_0 2
198#define BCOM_IPR_SCTMR_1 2
199#define BCOM_IPR_FEC_RX 6
200#define BCOM_IPR_FEC_TX 5
201#define BCOM_IPR_ATA_RX 7
202#define BCOM_IPR_ATA_TX 7
203#define BCOM_IPR_SCPCI_RX 2
204#define BCOM_IPR_SCPCI_TX 2
205#define BCOM_IPR_PSC3_RX 2
206#define BCOM_IPR_PSC3_TX 2
207#define BCOM_IPR_PSC2_RX 2
208#define BCOM_IPR_PSC2_TX 2
209#define BCOM_IPR_PSC1_RX 2
210#define BCOM_IPR_PSC1_TX 2
211#define BCOM_IPR_SCTMR_2 2
212#define BCOM_IPR_SCLPC 2
213#define BCOM_IPR_PSC5_RX 2
214#define BCOM_IPR_PSC5_TX 2
215#define BCOM_IPR_PSC4_RX 2
216#define BCOM_IPR_PSC4_TX 2
217#define BCOM_IPR_I2C2_RX 2
218#define BCOM_IPR_I2C2_TX 2
219#define BCOM_IPR_I2C1_RX 2
220#define BCOM_IPR_I2C1_TX 2
221#define BCOM_IPR_PSC6_RX 2
222#define BCOM_IPR_PSC6_TX 2
223#define BCOM_IPR_IRDA_RX 2
224#define BCOM_IPR_IRDA_TX 2
225#define BCOM_IPR_SCTMR_3 2
226#define BCOM_IPR_SCTMR_4 2
227#define BCOM_IPR_SCTMR_5 2
228#define BCOM_IPR_SCTMR_6 2
229#define BCOM_IPR_SCTMR_7 2
230
231
232/* ======================================================================== */
233/* API */
234/* ======================================================================== */
235
236extern struct bcom_task *bcom_task_alloc(int bd_count, int bd_size, int priv_size);
237extern void bcom_task_free(struct bcom_task *tsk);
238extern int bcom_load_image(int task, u32 *task_image);
239extern void bcom_set_initiator(int task, int initiator);
240
241
242#define TASK_ENABLE 0x8000
243
244/**
245 * bcom_disable_prefetch - Hook to disable bus prefetching
246 *
247 * ATA DMA and the original MPC5200 need this due to silicon bugs. At the
248 * moment disabling prefetch is a one-way street. There is no mechanism
249 * in place to turn prefetch back on after it has been disabled. There is
250 * no reason it couldn't be done, it would just be more complex to implement.
251 */
252static inline void bcom_disable_prefetch(void)
253{
254 u16 regval;
255
256 regval = in_be16(&bcom_eng->regs->PtdCntrl);
257 out_be16(&bcom_eng->regs->PtdCntrl, regval | 1);
258};
259
260static inline void
261bcom_enable_task(int task)
262{
263 u16 reg;
264 reg = in_be16(&bcom_eng->regs->tcr[task]);
265 out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE);
266}
267
268static inline void
269bcom_disable_task(int task)
270{
271 u16 reg = in_be16(&bcom_eng->regs->tcr[task]);
272 out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE);
273}
274
275
276static inline u32 *
277bcom_task_desc(int task)
278{
279 return bcom_sram_pa2va(bcom_eng->tdt[task].start);
280}
281
282static inline int
283bcom_task_num_descs(int task)
284{
285 return (bcom_eng->tdt[task].stop - bcom_eng->tdt[task].start)/sizeof(u32) + 1;
286}
287
288static inline u32 *
289bcom_task_var(int task)
290{
291 return bcom_sram_pa2va(bcom_eng->tdt[task].var);
292}
293
294static inline u32 *
295bcom_task_inc(int task)
296{
297 return &bcom_task_var(task)[BCOM_MAX_VAR];
298}
299
300
301static inline int
302bcom_drd_is_extended(u32 desc)
303{
304 return (desc) & BCOM_DRD_EXTENDED;
305}
306
307static inline int
308bcom_desc_is_drd(u32 desc)
309{
310 return !(desc & BCOM_LCD_MASK) && desc != BCOM_DESC_NOP;
311}
312
313static inline int
314bcom_desc_initiator(u32 desc)
315{
316 return (desc >> BCOM_DRD_INITIATOR_SHIFT) & 0x1f;
317}
318
319static inline void
320bcom_set_desc_initiator(u32 *desc, int initiator)
321{
322 *desc = (*desc & ~(0x1f << BCOM_DRD_INITIATOR_SHIFT)) |
323 ((initiator & 0x1f) << BCOM_DRD_INITIATOR_SHIFT);
324}
325
326
327static inline void
328bcom_set_task_pragma(int task, int pragma)
329{
330 u32 *fdt = &bcom_eng->tdt[task].fdt;
331 *fdt = (*fdt & ~0xff) | pragma;
332}
333
334static inline void
335bcom_set_task_auto_start(int task, int next_task)
336{
337 u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
338 out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task);
339}
340
341static inline void
342bcom_set_tcr_initiator(int task, int initiator)
343{
344 u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
345 out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8));
346}
347
348
349#endif /* __BESTCOMM_PRIV_H__ */
350
diff --git a/arch/powerpc/sysdev/bestcomm/fec.c b/arch/powerpc/sysdev/bestcomm/fec.c
deleted file mode 100644
index 957a988d23ea..000000000000
--- a/arch/powerpc/sysdev/bestcomm/fec.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/*
2 * Bestcomm FEC tasks driver
3 *
4 *
5 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
7 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <asm/io.h>
18
19#include "bestcomm.h"
20#include "bestcomm_priv.h"
21#include "fec.h"
22
23
24/* ======================================================================== */
25/* Task image/var/inc */
26/* ======================================================================== */
27
28/* fec tasks images */
29extern u32 bcom_fec_rx_task[];
30extern u32 bcom_fec_tx_task[];
31
32/* rx task vars that need to be set before enabling the task */
33struct bcom_fec_rx_var {
34 u32 enable; /* (u16*) address of task's control register */
35 u32 fifo; /* (u32*) address of fec's fifo */
36 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
37 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
38 u32 bd_start; /* (struct bcom_bd*) current bd */
39 u32 buffer_size; /* size of receive buffer */
40};
41
42/* rx task incs that need to be set before enabling the task */
43struct bcom_fec_rx_inc {
44 u16 pad0;
45 s16 incr_bytes;
46 u16 pad1;
47 s16 incr_dst;
48 u16 pad2;
49 s16 incr_dst_ma;
50};
51
52/* tx task vars that need to be set before enabling the task */
53struct bcom_fec_tx_var {
54 u32 DRD; /* (u32*) address of self-modified DRD */
55 u32 fifo; /* (u32*) address of fec's fifo */
56 u32 enable; /* (u16*) address of task's control register */
57 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
58 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
59 u32 bd_start; /* (struct bcom_bd*) current bd */
60 u32 buffer_size; /* set by uCode for each packet */
61};
62
63/* tx task incs that need to be set before enabling the task */
64struct bcom_fec_tx_inc {
65 u16 pad0;
66 s16 incr_bytes;
67 u16 pad1;
68 s16 incr_src;
69 u16 pad2;
70 s16 incr_src_ma;
71};
72
73/* private structure in the task */
74struct bcom_fec_priv {
75 phys_addr_t fifo;
76 int maxbufsize;
77};
78
79
80/* ======================================================================== */
81/* Task support code */
82/* ======================================================================== */
83
84struct bcom_task *
85bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize)
86{
87 struct bcom_task *tsk;
88 struct bcom_fec_priv *priv;
89
90 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
91 sizeof(struct bcom_fec_priv));
92 if (!tsk)
93 return NULL;
94
95 tsk->flags = BCOM_FLAGS_NONE;
96
97 priv = tsk->priv;
98 priv->fifo = fifo;
99 priv->maxbufsize = maxbufsize;
100
101 if (bcom_fec_rx_reset(tsk)) {
102 bcom_task_free(tsk);
103 return NULL;
104 }
105
106 return tsk;
107}
108EXPORT_SYMBOL_GPL(bcom_fec_rx_init);
109
110int
111bcom_fec_rx_reset(struct bcom_task *tsk)
112{
113 struct bcom_fec_priv *priv = tsk->priv;
114 struct bcom_fec_rx_var *var;
115 struct bcom_fec_rx_inc *inc;
116
117 /* Shutdown the task */
118 bcom_disable_task(tsk->tasknum);
119
120 /* Reset the microcode */
121 var = (struct bcom_fec_rx_var *) bcom_task_var(tsk->tasknum);
122 inc = (struct bcom_fec_rx_inc *) bcom_task_inc(tsk->tasknum);
123
124 if (bcom_load_image(tsk->tasknum, bcom_fec_rx_task))
125 return -1;
126
127 var->enable = bcom_eng->regs_base +
128 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
129 var->fifo = (u32) priv->fifo;
130 var->bd_base = tsk->bd_pa;
131 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
132 var->bd_start = tsk->bd_pa;
133 var->buffer_size = priv->maxbufsize;
134
135 inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
136 inc->incr_dst = sizeof(u32); /* task image, but we stick */
137 inc->incr_dst_ma= sizeof(u8); /* to the official ones */
138
139 /* Reset the BDs */
140 tsk->index = 0;
141 tsk->outdex = 0;
142
143 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
144
145 /* Configure some stuff */
146 bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_RX_BD_PRAGMA);
147 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
148
149 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_RX], BCOM_IPR_FEC_RX);
150
151 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
152
153 return 0;
154}
155EXPORT_SYMBOL_GPL(bcom_fec_rx_reset);
156
157void
158bcom_fec_rx_release(struct bcom_task *tsk)
159{
160 /* Nothing special for the FEC tasks */
161 bcom_task_free(tsk);
162}
163EXPORT_SYMBOL_GPL(bcom_fec_rx_release);
164
165
166
167 /* Return 2nd to last DRD */
168 /* This is an ugly hack, but at least it's only done
169 once at initialization */
170static u32 *self_modified_drd(int tasknum)
171{
172 u32 *desc;
173 int num_descs;
174 int drd_count;
175 int i;
176
177 num_descs = bcom_task_num_descs(tasknum);
178 desc = bcom_task_desc(tasknum) + num_descs - 1;
179 drd_count = 0;
180 for (i=0; i<num_descs; i++, desc--)
181 if (bcom_desc_is_drd(*desc) && ++drd_count == 3)
182 break;
183 return desc;
184}
185
186struct bcom_task *
187bcom_fec_tx_init(int queue_len, phys_addr_t fifo)
188{
189 struct bcom_task *tsk;
190 struct bcom_fec_priv *priv;
191
192 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
193 sizeof(struct bcom_fec_priv));
194 if (!tsk)
195 return NULL;
196
197 tsk->flags = BCOM_FLAGS_ENABLE_TASK;
198
199 priv = tsk->priv;
200 priv->fifo = fifo;
201
202 if (bcom_fec_tx_reset(tsk)) {
203 bcom_task_free(tsk);
204 return NULL;
205 }
206
207 return tsk;
208}
209EXPORT_SYMBOL_GPL(bcom_fec_tx_init);
210
211int
212bcom_fec_tx_reset(struct bcom_task *tsk)
213{
214 struct bcom_fec_priv *priv = tsk->priv;
215 struct bcom_fec_tx_var *var;
216 struct bcom_fec_tx_inc *inc;
217
218 /* Shutdown the task */
219 bcom_disable_task(tsk->tasknum);
220
221 /* Reset the microcode */
222 var = (struct bcom_fec_tx_var *) bcom_task_var(tsk->tasknum);
223 inc = (struct bcom_fec_tx_inc *) bcom_task_inc(tsk->tasknum);
224
225 if (bcom_load_image(tsk->tasknum, bcom_fec_tx_task))
226 return -1;
227
228 var->enable = bcom_eng->regs_base +
229 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
230 var->fifo = (u32) priv->fifo;
231 var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum));
232 var->bd_base = tsk->bd_pa;
233 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
234 var->bd_start = tsk->bd_pa;
235
236 inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
237 inc->incr_src = sizeof(u32); /* task image, but we stick */
238 inc->incr_src_ma= sizeof(u8); /* to the official ones */
239
240 /* Reset the BDs */
241 tsk->index = 0;
242 tsk->outdex = 0;
243
244 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
245
246 /* Configure some stuff */
247 bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_TX_BD_PRAGMA);
248 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
249
250 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_TX], BCOM_IPR_FEC_TX);
251
252 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
253
254 return 0;
255}
256EXPORT_SYMBOL_GPL(bcom_fec_tx_reset);
257
258void
259bcom_fec_tx_release(struct bcom_task *tsk)
260{
261 /* Nothing special for the FEC tasks */
262 bcom_task_free(tsk);
263}
264EXPORT_SYMBOL_GPL(bcom_fec_tx_release);
265
266
267MODULE_DESCRIPTION("BestComm FEC tasks driver");
268MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
269MODULE_LICENSE("GPL v2");
270
diff --git a/arch/powerpc/sysdev/bestcomm/fec.h b/arch/powerpc/sysdev/bestcomm/fec.h
deleted file mode 100644
index ee565d94d503..000000000000
--- a/arch/powerpc/sysdev/bestcomm/fec.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Header for Bestcomm FEC tasks driver
3 *
4 *
5 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
7 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#ifndef __BESTCOMM_FEC_H__
15#define __BESTCOMM_FEC_H__
16
17
18struct bcom_fec_bd {
19 u32 status;
20 u32 skb_pa;
21};
22
23#define BCOM_FEC_TX_BD_TFD 0x08000000ul /* transmit frame done */
24#define BCOM_FEC_TX_BD_TC 0x04000000ul /* transmit CRC */
25#define BCOM_FEC_TX_BD_ABC 0x02000000ul /* append bad CRC */
26
27#define BCOM_FEC_RX_BD_L 0x08000000ul /* buffer is last in frame */
28#define BCOM_FEC_RX_BD_BC 0x00800000ul /* DA is broadcast */
29#define BCOM_FEC_RX_BD_MC 0x00400000ul /* DA is multicast and not broadcast */
30#define BCOM_FEC_RX_BD_LG 0x00200000ul /* Rx frame length violation */
31#define BCOM_FEC_RX_BD_NO 0x00100000ul /* Rx non-octet aligned frame */
32#define BCOM_FEC_RX_BD_CR 0x00040000ul /* Rx CRC error */
33#define BCOM_FEC_RX_BD_OV 0x00020000ul /* overrun */
34#define BCOM_FEC_RX_BD_TR 0x00010000ul /* Rx frame truncated */
35#define BCOM_FEC_RX_BD_LEN_MASK 0x000007fful /* mask for length of received frame */
36#define BCOM_FEC_RX_BD_ERRORS (BCOM_FEC_RX_BD_LG | BCOM_FEC_RX_BD_NO | \
37 BCOM_FEC_RX_BD_CR | BCOM_FEC_RX_BD_OV | BCOM_FEC_RX_BD_TR)
38
39
40extern struct bcom_task *
41bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize);
42
43extern int
44bcom_fec_rx_reset(struct bcom_task *tsk);
45
46extern void
47bcom_fec_rx_release(struct bcom_task *tsk);
48
49
50extern struct bcom_task *
51bcom_fec_tx_init(int queue_len, phys_addr_t fifo);
52
53extern int
54bcom_fec_tx_reset(struct bcom_task *tsk);
55
56extern void
57bcom_fec_tx_release(struct bcom_task *tsk);
58
59
60#endif /* __BESTCOMM_FEC_H__ */
61
diff --git a/arch/powerpc/sysdev/bestcomm/gen_bd.c b/arch/powerpc/sysdev/bestcomm/gen_bd.c
deleted file mode 100644
index e0a53e3147b2..000000000000
--- a/arch/powerpc/sysdev/bestcomm/gen_bd.c
+++ /dev/null
@@ -1,354 +0,0 @@
1/*
2 * Driver for MPC52xx processor BestComm General Buffer Descriptor
3 *
4 * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
5 * Copyright (C) 2006 AppSpec Computer Technologies Corp.
6 * Jeff Gibbons <jeff.gibbons@appspec.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/types.h>
18#include <asm/errno.h>
19#include <asm/io.h>
20
21#include <asm/mpc52xx.h>
22#include <asm/mpc52xx_psc.h>
23
24#include "bestcomm.h"
25#include "bestcomm_priv.h"
26#include "gen_bd.h"
27
28
29/* ======================================================================== */
30/* Task image/var/inc */
31/* ======================================================================== */
32
33/* gen_bd tasks images */
34extern u32 bcom_gen_bd_rx_task[];
35extern u32 bcom_gen_bd_tx_task[];
36
37/* rx task vars that need to be set before enabling the task */
38struct bcom_gen_bd_rx_var {
39 u32 enable; /* (u16*) address of task's control register */
40 u32 fifo; /* (u32*) address of gen_bd's fifo */
41 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
42 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
43 u32 bd_start; /* (struct bcom_bd*) current bd */
44 u32 buffer_size; /* size of receive buffer */
45};
46
47/* rx task incs that need to be set before enabling the task */
48struct bcom_gen_bd_rx_inc {
49 u16 pad0;
50 s16 incr_bytes;
51 u16 pad1;
52 s16 incr_dst;
53};
54
55/* tx task vars that need to be set before enabling the task */
56struct bcom_gen_bd_tx_var {
57 u32 fifo; /* (u32*) address of gen_bd's fifo */
58 u32 enable; /* (u16*) address of task's control register */
59 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
60 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
61 u32 bd_start; /* (struct bcom_bd*) current bd */
62 u32 buffer_size; /* set by uCode for each packet */
63};
64
65/* tx task incs that need to be set before enabling the task */
66struct bcom_gen_bd_tx_inc {
67 u16 pad0;
68 s16 incr_bytes;
69 u16 pad1;
70 s16 incr_src;
71 u16 pad2;
72 s16 incr_src_ma;
73};
74
75/* private structure */
76struct bcom_gen_bd_priv {
77 phys_addr_t fifo;
78 int initiator;
79 int ipr;
80 int maxbufsize;
81};
82
83
84/* ======================================================================== */
85/* Task support code */
86/* ======================================================================== */
87
88struct bcom_task *
89bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo,
90 int initiator, int ipr, int maxbufsize)
91{
92 struct bcom_task *tsk;
93 struct bcom_gen_bd_priv *priv;
94
95 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
96 sizeof(struct bcom_gen_bd_priv));
97 if (!tsk)
98 return NULL;
99
100 tsk->flags = BCOM_FLAGS_NONE;
101
102 priv = tsk->priv;
103 priv->fifo = fifo;
104 priv->initiator = initiator;
105 priv->ipr = ipr;
106 priv->maxbufsize = maxbufsize;
107
108 if (bcom_gen_bd_rx_reset(tsk)) {
109 bcom_task_free(tsk);
110 return NULL;
111 }
112
113 return tsk;
114}
115EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_init);
116
117int
118bcom_gen_bd_rx_reset(struct bcom_task *tsk)
119{
120 struct bcom_gen_bd_priv *priv = tsk->priv;
121 struct bcom_gen_bd_rx_var *var;
122 struct bcom_gen_bd_rx_inc *inc;
123
124 /* Shutdown the task */
125 bcom_disable_task(tsk->tasknum);
126
127 /* Reset the microcode */
128 var = (struct bcom_gen_bd_rx_var *) bcom_task_var(tsk->tasknum);
129 inc = (struct bcom_gen_bd_rx_inc *) bcom_task_inc(tsk->tasknum);
130
131 if (bcom_load_image(tsk->tasknum, bcom_gen_bd_rx_task))
132 return -1;
133
134 var->enable = bcom_eng->regs_base +
135 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
136 var->fifo = (u32) priv->fifo;
137 var->bd_base = tsk->bd_pa;
138 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
139 var->bd_start = tsk->bd_pa;
140 var->buffer_size = priv->maxbufsize;
141
142 inc->incr_bytes = -(s16)sizeof(u32);
143 inc->incr_dst = sizeof(u32);
144
145 /* Reset the BDs */
146 tsk->index = 0;
147 tsk->outdex = 0;
148
149 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
150
151 /* Configure some stuff */
152 bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_RX_BD_PRAGMA);
153 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
154
155 out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
156 bcom_set_initiator(tsk->tasknum, priv->initiator);
157
158 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
159
160 return 0;
161}
162EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_reset);
163
164void
165bcom_gen_bd_rx_release(struct bcom_task *tsk)
166{
167 /* Nothing special for the GenBD tasks */
168 bcom_task_free(tsk);
169}
170EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_release);
171
172
173extern struct bcom_task *
174bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo,
175 int initiator, int ipr)
176{
177 struct bcom_task *tsk;
178 struct bcom_gen_bd_priv *priv;
179
180 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
181 sizeof(struct bcom_gen_bd_priv));
182 if (!tsk)
183 return NULL;
184
185 tsk->flags = BCOM_FLAGS_NONE;
186
187 priv = tsk->priv;
188 priv->fifo = fifo;
189 priv->initiator = initiator;
190 priv->ipr = ipr;
191
192 if (bcom_gen_bd_tx_reset(tsk)) {
193 bcom_task_free(tsk);
194 return NULL;
195 }
196
197 return tsk;
198}
199EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_init);
200
201int
202bcom_gen_bd_tx_reset(struct bcom_task *tsk)
203{
204 struct bcom_gen_bd_priv *priv = tsk->priv;
205 struct bcom_gen_bd_tx_var *var;
206 struct bcom_gen_bd_tx_inc *inc;
207
208 /* Shutdown the task */
209 bcom_disable_task(tsk->tasknum);
210
211 /* Reset the microcode */
212 var = (struct bcom_gen_bd_tx_var *) bcom_task_var(tsk->tasknum);
213 inc = (struct bcom_gen_bd_tx_inc *) bcom_task_inc(tsk->tasknum);
214
215 if (bcom_load_image(tsk->tasknum, bcom_gen_bd_tx_task))
216 return -1;
217
218 var->enable = bcom_eng->regs_base +
219 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
220 var->fifo = (u32) priv->fifo;
221 var->bd_base = tsk->bd_pa;
222 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
223 var->bd_start = tsk->bd_pa;
224
225 inc->incr_bytes = -(s16)sizeof(u32);
226 inc->incr_src = sizeof(u32);
227 inc->incr_src_ma = sizeof(u8);
228
229 /* Reset the BDs */
230 tsk->index = 0;
231 tsk->outdex = 0;
232
233 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
234
235 /* Configure some stuff */
236 bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_TX_BD_PRAGMA);
237 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
238
239 out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
240 bcom_set_initiator(tsk->tasknum, priv->initiator);
241
242 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
243
244 return 0;
245}
246EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_reset);
247
248void
249bcom_gen_bd_tx_release(struct bcom_task *tsk)
250{
251 /* Nothing special for the GenBD tasks */
252 bcom_task_free(tsk);
253}
254EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_release);
255
256/* ---------------------------------------------------------------------
257 * PSC support code
258 */
259
260/**
261 * bcom_psc_parameters - Bestcomm initialization value table for PSC devices
262 *
263 * This structure is only used internally. It is a lookup table for PSC
264 * specific parameters to bestcomm tasks.
265 */
266static struct bcom_psc_params {
267 int rx_initiator;
268 int rx_ipr;
269 int tx_initiator;
270 int tx_ipr;
271} bcom_psc_params[] = {
272 [0] = {
273 .rx_initiator = BCOM_INITIATOR_PSC1_RX,
274 .rx_ipr = BCOM_IPR_PSC1_RX,
275 .tx_initiator = BCOM_INITIATOR_PSC1_TX,
276 .tx_ipr = BCOM_IPR_PSC1_TX,
277 },
278 [1] = {
279 .rx_initiator = BCOM_INITIATOR_PSC2_RX,
280 .rx_ipr = BCOM_IPR_PSC2_RX,
281 .tx_initiator = BCOM_INITIATOR_PSC2_TX,
282 .tx_ipr = BCOM_IPR_PSC2_TX,
283 },
284 [2] = {
285 .rx_initiator = BCOM_INITIATOR_PSC3_RX,
286 .rx_ipr = BCOM_IPR_PSC3_RX,
287 .tx_initiator = BCOM_INITIATOR_PSC3_TX,
288 .tx_ipr = BCOM_IPR_PSC3_TX,
289 },
290 [3] = {
291 .rx_initiator = BCOM_INITIATOR_PSC4_RX,
292 .rx_ipr = BCOM_IPR_PSC4_RX,
293 .tx_initiator = BCOM_INITIATOR_PSC4_TX,
294 .tx_ipr = BCOM_IPR_PSC4_TX,
295 },
296 [4] = {
297 .rx_initiator = BCOM_INITIATOR_PSC5_RX,
298 .rx_ipr = BCOM_IPR_PSC5_RX,
299 .tx_initiator = BCOM_INITIATOR_PSC5_TX,
300 .tx_ipr = BCOM_IPR_PSC5_TX,
301 },
302 [5] = {
303 .rx_initiator = BCOM_INITIATOR_PSC6_RX,
304 .rx_ipr = BCOM_IPR_PSC6_RX,
305 .tx_initiator = BCOM_INITIATOR_PSC6_TX,
306 .tx_ipr = BCOM_IPR_PSC6_TX,
307 },
308};
309
310/**
311 * bcom_psc_gen_bd_rx_init - Allocate a receive bcom_task for a PSC port
312 * @psc_num: Number of the PSC to allocate a task for
313 * @queue_len: number of buffer descriptors to allocate for the task
314 * @fifo: physical address of FIFO register
315 * @maxbufsize: Maximum receive data size in bytes.
316 *
317 * Allocate a bestcomm task structure for receiving data from a PSC.
318 */
319struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len,
320 phys_addr_t fifo, int maxbufsize)
321{
322 if (psc_num >= MPC52xx_PSC_MAXNUM)
323 return NULL;
324
325 return bcom_gen_bd_rx_init(queue_len, fifo,
326 bcom_psc_params[psc_num].rx_initiator,
327 bcom_psc_params[psc_num].rx_ipr,
328 maxbufsize);
329}
330EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_rx_init);
331
332/**
333 * bcom_psc_gen_bd_tx_init - Allocate a transmit bcom_task for a PSC port
334 * @psc_num: Number of the PSC to allocate a task for
335 * @queue_len: number of buffer descriptors to allocate for the task
336 * @fifo: physical address of FIFO register
337 *
338 * Allocate a bestcomm task structure for transmitting data to a PSC.
339 */
340struct bcom_task *
341bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len, phys_addr_t fifo)
342{
343 struct psc;
344 return bcom_gen_bd_tx_init(queue_len, fifo,
345 bcom_psc_params[psc_num].tx_initiator,
346 bcom_psc_params[psc_num].tx_ipr);
347}
348EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_tx_init);
349
350
351MODULE_DESCRIPTION("BestComm General Buffer Descriptor tasks driver");
352MODULE_AUTHOR("Jeff Gibbons <jeff.gibbons@appspec.com>");
353MODULE_LICENSE("GPL v2");
354
diff --git a/arch/powerpc/sysdev/bestcomm/gen_bd.h b/arch/powerpc/sysdev/bestcomm/gen_bd.h
deleted file mode 100644
index de47260e69da..000000000000
--- a/arch/powerpc/sysdev/bestcomm/gen_bd.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Header for Bestcomm General Buffer Descriptor tasks driver
3 *
4 *
5 * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2006 AppSpec Computer Technologies Corp.
7 * Jeff Gibbons <jeff.gibbons@appspec.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 *
14 */
15
16#ifndef __BESTCOMM_GEN_BD_H__
17#define __BESTCOMM_GEN_BD_H__
18
19struct bcom_gen_bd {
20 u32 status;
21 u32 buf_pa;
22};
23
24
25extern struct bcom_task *
26bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo,
27 int initiator, int ipr, int maxbufsize);
28
29extern int
30bcom_gen_bd_rx_reset(struct bcom_task *tsk);
31
32extern void
33bcom_gen_bd_rx_release(struct bcom_task *tsk);
34
35
36extern struct bcom_task *
37bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo,
38 int initiator, int ipr);
39
40extern int
41bcom_gen_bd_tx_reset(struct bcom_task *tsk);
42
43extern void
44bcom_gen_bd_tx_release(struct bcom_task *tsk);
45
46
47/* PSC support utility wrappers */
48struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len,
49 phys_addr_t fifo, int maxbufsize);
50struct bcom_task * bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len,
51 phys_addr_t fifo);
52#endif /* __BESTCOMM_GEN_BD_H__ */
53
diff --git a/arch/powerpc/sysdev/bestcomm/sram.c b/arch/powerpc/sysdev/bestcomm/sram.c
deleted file mode 100644
index b6db23e085fb..000000000000
--- a/arch/powerpc/sysdev/bestcomm/sram.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Simple memory allocator for on-board SRAM
3 *
4 *
5 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
6 *
7 * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/kernel.h>
16#include <linux/export.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19#include <linux/string.h>
20#include <linux/ioport.h>
21#include <linux/of.h>
22
23#include <asm/io.h>
24#include <asm/mmu.h>
25
26#include "sram.h"
27
28
29/* Struct keeping our 'state' */
30struct bcom_sram *bcom_sram = NULL;
31EXPORT_SYMBOL_GPL(bcom_sram); /* needed for inline functions */
32
33
34/* ======================================================================== */
35/* Public API */
36/* ======================================================================== */
37/* DO NOT USE in interrupts, if needed in irq handler, we should use the
38 _irqsave version of the spin_locks */
39
40int bcom_sram_init(struct device_node *sram_node, char *owner)
41{
42 int rv;
43 const u32 *regaddr_p;
44 u64 regaddr64, size64;
45 unsigned int psize;
46
47 /* Create our state struct */
48 if (bcom_sram) {
49 printk(KERN_ERR "%s: bcom_sram_init: "
50 "Already initialized !\n", owner);
51 return -EBUSY;
52 }
53
54 bcom_sram = kmalloc(sizeof(struct bcom_sram), GFP_KERNEL);
55 if (!bcom_sram) {
56 printk(KERN_ERR "%s: bcom_sram_init: "
57 "Couldn't allocate internal state !\n", owner);
58 return -ENOMEM;
59 }
60
61 /* Get address and size of the sram */
62 regaddr_p = of_get_address(sram_node, 0, &size64, NULL);
63 if (!regaddr_p) {
64 printk(KERN_ERR "%s: bcom_sram_init: "
65 "Invalid device node !\n", owner);
66 rv = -EINVAL;
67 goto error_free;
68 }
69
70 regaddr64 = of_translate_address(sram_node, regaddr_p);
71
72 bcom_sram->base_phys = (phys_addr_t) regaddr64;
73 bcom_sram->size = (unsigned int) size64;
74
75 /* Request region */
76 if (!request_mem_region(bcom_sram->base_phys, bcom_sram->size, owner)) {
77 printk(KERN_ERR "%s: bcom_sram_init: "
78 "Couldn't request region !\n", owner);
79 rv = -EBUSY;
80 goto error_free;
81 }
82
83 /* Map SRAM */
84 /* sram is not really __iomem */
85 bcom_sram->base_virt = (void*) ioremap(bcom_sram->base_phys, bcom_sram->size);
86
87 if (!bcom_sram->base_virt) {
88 printk(KERN_ERR "%s: bcom_sram_init: "
89 "Map error SRAM zone 0x%08lx (0x%0x)!\n",
90 owner, (long)bcom_sram->base_phys, bcom_sram->size );
91 rv = -ENOMEM;
92 goto error_release;
93 }
94
95 /* Create an rheap (defaults to 32 bits word alignment) */
96 bcom_sram->rh = rh_create(4);
97
98 /* Attach the free zones */
99#if 0
100 /* Currently disabled ... for future use only */
101 reg_addr_p = of_get_property(sram_node, "available", &psize);
102#else
103 regaddr_p = NULL;
104 psize = 0;
105#endif
106
107 if (!regaddr_p || !psize) {
108 /* Attach the whole zone */
109 rh_attach_region(bcom_sram->rh, 0, bcom_sram->size);
110 } else {
111 /* Attach each zone independently */
112 while (psize >= 2 * sizeof(u32)) {
113 phys_addr_t zbase = of_translate_address(sram_node, regaddr_p);
114 rh_attach_region(bcom_sram->rh, zbase - bcom_sram->base_phys, regaddr_p[1]);
115 regaddr_p += 2;
116 psize -= 2 * sizeof(u32);
117 }
118 }
119
120 /* Init our spinlock */
121 spin_lock_init(&bcom_sram->lock);
122
123 return 0;
124
125error_release:
126 release_mem_region(bcom_sram->base_phys, bcom_sram->size);
127error_free:
128 kfree(bcom_sram);
129 bcom_sram = NULL;
130
131 return rv;
132}
133EXPORT_SYMBOL_GPL(bcom_sram_init);
134
135void bcom_sram_cleanup(void)
136{
137 /* Free resources */
138 if (bcom_sram) {
139 rh_destroy(bcom_sram->rh);
140 iounmap((void __iomem *)bcom_sram->base_virt);
141 release_mem_region(bcom_sram->base_phys, bcom_sram->size);
142 kfree(bcom_sram);
143 bcom_sram = NULL;
144 }
145}
146EXPORT_SYMBOL_GPL(bcom_sram_cleanup);
147
148void* bcom_sram_alloc(int size, int align, phys_addr_t *phys)
149{
150 unsigned long offset;
151
152 spin_lock(&bcom_sram->lock);
153 offset = rh_alloc_align(bcom_sram->rh, size, align, NULL);
154 spin_unlock(&bcom_sram->lock);
155
156 if (IS_ERR_VALUE(offset))
157 return NULL;
158
159 *phys = bcom_sram->base_phys + offset;
160 return bcom_sram->base_virt + offset;
161}
162EXPORT_SYMBOL_GPL(bcom_sram_alloc);
163
164void bcom_sram_free(void *ptr)
165{
166 unsigned long offset;
167
168 if (!ptr)
169 return;
170
171 offset = ptr - bcom_sram->base_virt;
172
173 spin_lock(&bcom_sram->lock);
174 rh_free(bcom_sram->rh, offset);
175 spin_unlock(&bcom_sram->lock);
176}
177EXPORT_SYMBOL_GPL(bcom_sram_free);
178
diff --git a/arch/powerpc/sysdev/bestcomm/sram.h b/arch/powerpc/sysdev/bestcomm/sram.h
deleted file mode 100644
index b6d668963cce..000000000000
--- a/arch/powerpc/sysdev/bestcomm/sram.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Handling of a sram zone for bestcomm
3 *
4 *
5 * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifndef __BESTCOMM_SRAM_H__
13#define __BESTCOMM_SRAM_H__
14
15#include <asm/rheap.h>
16#include <asm/mmu.h>
17#include <linux/spinlock.h>
18
19
20/* Structure used internally */
21 /* The internals are here for the inline functions
22 * sake, certainly not for the user to mess with !
23 */
24struct bcom_sram {
25 phys_addr_t base_phys;
26 void *base_virt;
27 unsigned int size;
28 rh_info_t *rh;
29 spinlock_t lock;
30};
31
32extern struct bcom_sram *bcom_sram;
33
34
35/* Public API */
36extern int bcom_sram_init(struct device_node *sram_node, char *owner);
37extern void bcom_sram_cleanup(void);
38
39extern void* bcom_sram_alloc(int size, int align, phys_addr_t *phys);
40extern void bcom_sram_free(void *ptr);
41
42static inline phys_addr_t bcom_sram_va2pa(void *va) {
43 return bcom_sram->base_phys +
44 (unsigned long)(va - bcom_sram->base_virt);
45}
46
47static inline void *bcom_sram_pa2va(phys_addr_t pa) {
48 return bcom_sram->base_virt +
49 (unsigned long)(pa - bcom_sram->base_phys);
50}
51
52
53#endif /* __BESTCOMM_SRAM_H__ */
54
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c
index 96f815a55dfd..5492dc5f56f4 100644
--- a/arch/powerpc/sysdev/mpc5xxx_clocks.c
+++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c
@@ -9,9 +9,9 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11#include <linux/export.h> 11#include <linux/export.h>
12#include <asm/mpc5xxx.h>
12 13
13unsigned int 14unsigned long mpc5xxx_get_bus_frequency(struct device_node *node)
14mpc5xxx_get_bus_frequency(struct device_node *node)
15{ 15{
16 struct device_node *np; 16 struct device_node *np;
17 const unsigned int *p_bus_freq = NULL; 17 const unsigned int *p_bus_freq = NULL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 19:40:15 -0500