8 files changed, 48 insertions, 8 deletions

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 8831c48c2bc9..693a3275606f 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -169,6 +169,12 @@
                         #clock-cells = <1>;
                 };
 
+                cmu_dmc: clock-controller@105C0000 {
+                        compatible = "samsung,exynos3250-cmu-dmc";
+                        reg = <0x105C0000 0x2000>;
+                        #clock-cells = <1>;
+                };
+
                 rtc: rtc@10070000 {
                         compatible = "samsung,exynos3250-rtc";
                         reg = <0x10070000 0x100>;
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index a70546945985..80fc5d7e9ef9 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -1,5 +1,6 @@
 /* The pxa3xx skeleton simply augments the 2xx version */
-/include/ "pxa2xx.dtsi"
+#include "pxa2xx.dtsi"
+#include "dt-bindings/clock/pxa2xx-clock.h"
 
 / {
         model = "Marvell PXA27x familiy SoC";
@@ -35,4 +36,21 @@
                         #pwm-cells = <1>;
                 };
         };
+
+        clocks {
+               /*
+                * The muxing of external clocks/internal dividers for osc* clock
+                * sources has been hidden under the carpet by now.
+                */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                pxa2xx_clks: pxa2xx_clks@41300004 {
+                        compatible = "marvell,pxa-clocks";
+                        #clock-cells = <1>;
+                        status = "okay";
+                };
+        };
+
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index d73a2287b37a..531272c0e526 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -287,7 +287,7 @@
 
                 mbus_clk: clk@01c2015c {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        compatible = "allwinner,sun5i-a13-mbus-clk";
                         reg = <0x01c2015c 0x4>;
                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                         clock-output-names = "mbus";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index c4b5d7825b9f..b131068f4f35 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -285,7 +285,7 @@
 
                 mbus_clk: clk@01c2015c {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        compatible = "allwinner,sun5i-a13-mbus-clk";
                         reg = <0x01c2015c 0x4>;
                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                         clock-output-names = "mbus";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index a96b99465069..82097c905c48 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -382,7 +382,7 @@
 
                 mbus_clk: clk@01c2015c {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        compatible = "allwinner,sun5i-a13-mbus-clk";
                         reg = <0x01c2015c 0x4>;
                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
                         clock-output-names = "mbus";
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b8ad045bcb8d..03cbb16898a3 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -723,8 +723,16 @@ int __init omap_clk_init(void)
         ti_clk_init_features();
 
         ret = of_prcm_init();
-        if (!ret)
-                ret = omap_clk_soc_init();
+        if (ret)
+                return ret;
+
+        of_clk_init(NULL);
+
+        ti_dt_clk_init_retry_clks();
+
+        ti_dt_clockdomains_setup();
+
+        ret = omap_clk_soc_init();
 
         return ret;
 }
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 74054b813600..ee2b5222eac0 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -525,8 +525,6 @@ int __init of_prcm_init(void)
                 memmap_index++;
         }
 
-        ti_dt_clockdomains_setup();
-
         return 0;
 }
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index ee6ced1cea7f..f1dd62946b36 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -143,6 +143,16 @@
 #define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
 #define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
 
+#define CCCR_CPDIS_BIT  (31)
+#define CCCR_PPDIS_BIT  (30)
+#define CCCR_LCD_26_BIT (27)
+#define CCCR_A_BIT      (25)
+
+#define CCSR_N2_MASK    CCCR_N_MASK
+#define CCSR_M_MASK     CCCR_M_MASK
+#define CCSR_L_MASK     CCCR_L_MASK
+#define CCSR_N2_SHIFT   7
+
 #define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
 #define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
 #define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */