aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig.debug7
-rw-r--r--arch/powerpc/boot/Makefile2
-rw-r--r--arch/powerpc/configs/cell_defconfig3
-rw-r--r--arch/powerpc/configs/celleb_defconfig152
-rw-r--r--arch/powerpc/configs/ppc64_defconfig3
-rw-r--r--arch/powerpc/include/asm/firmware.h10
-rw-r--r--arch/powerpc/include/asm/smp.h1
-rw-r--r--arch/powerpc/kernel/udbg.c2
-rw-r--r--arch/powerpc/platforms/Kconfig5
-rw-r--r--arch/powerpc/platforms/cell/Kconfig11
-rw-r--r--arch/powerpc/platforms/cell/Makefile15
-rw-r--r--arch/powerpc/platforms/cell/beat.c264
-rw-r--r--arch/powerpc/platforms/cell/beat.h39
-rw-r--r--arch/powerpc/platforms/cell/beat_htab.c445
-rw-r--r--arch/powerpc/platforms/cell/beat_hvCall.S285
-rw-r--r--arch/powerpc/platforms/cell/beat_interrupt.c253
-rw-r--r--arch/powerpc/platforms/cell/beat_interrupt.h30
-rw-r--r--arch/powerpc/platforms/cell/beat_iommu.c115
-rw-r--r--arch/powerpc/platforms/cell/beat_spu_priv1.c205
-rw-r--r--arch/powerpc/platforms/cell/beat_syscall.h164
-rw-r--r--arch/powerpc/platforms/cell/beat_udbg.c98
-rw-r--r--arch/powerpc/platforms/cell/beat_wrapper.h290
-rw-r--r--arch/powerpc/platforms/cell/celleb_pci.c499
-rw-r--r--arch/powerpc/platforms/cell/celleb_pci.h46
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc.h232
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_epci.c428
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_pciex.c538
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_sio.c99
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_uhc.c95
-rw-r--r--arch/powerpc/platforms/cell/celleb_setup.c243
-rw-r--r--arch/powerpc/platforms/cell/iommu.c2
31 files changed, 1 insertions, 4580 deletions
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index bfd823abff93..0efa8f90a8f1 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -193,13 +193,6 @@ config PPC_EARLY_DEBUG_PAS_REALMODE
193 Select this to enable early debugging for PA Semi. 193 Select this to enable early debugging for PA Semi.
194 Output will be on UART0. 194 Output will be on UART0.
195 195
196config PPC_EARLY_DEBUG_BEAT
197 bool "Beat HV Console"
198 depends on PPC_CELLEB
199 select PPC_UDBG_BEAT
200 help
201 Select this to enable early debugging for Celleb with Beat.
202
203config PPC_EARLY_DEBUG_44x 196config PPC_EARLY_DEBUG_44x
204 bool "Early serial debugging for IBM/AMCC 44x CPUs" 197 bool "Early serial debugging for IBM/AMCC 44x CPUs"
205 depends on 44x 198 depends on 44x
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 73a19fac4850..73eddda53b8e 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -110,7 +110,6 @@ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
110src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S 110src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
111src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S 111src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
112src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S 112src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
113src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
114src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S 113src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
115 114
116src-wlib := $(sort $(src-wlib-y)) 115src-wlib := $(sort $(src-wlib-y))
@@ -215,7 +214,6 @@ image-$(CONFIG_PPC_POWERNV) += zImage.pseries
215image-$(CONFIG_PPC_MAPLE) += zImage.maple 214image-$(CONFIG_PPC_MAPLE) += zImage.maple
216image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries 215image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
217image-$(CONFIG_PPC_PS3) += dtbImage.ps3 216image-$(CONFIG_PPC_PS3) += dtbImage.ps3
218image-$(CONFIG_PPC_CELLEB) += zImage.pseries
219image-$(CONFIG_PPC_CELL_QPACE) += zImage.pseries 217image-$(CONFIG_PPC_CELL_QPACE) += zImage.pseries
220image-$(CONFIG_PPC_CHRP) += zImage.chrp 218image-$(CONFIG_PPC_CHRP) += zImage.chrp
221image-$(CONFIG_PPC_EFIKA) += zImage.chrp 219image-$(CONFIG_PPC_EFIKA) += zImage.chrp
diff --git a/arch/powerpc/configs/cell_defconfig b/arch/powerpc/configs/cell_defconfig
index 9788b3c2d563..9227b517560a 100644
--- a/arch/powerpc/configs/cell_defconfig
+++ b/arch/powerpc/configs/cell_defconfig
@@ -28,7 +28,6 @@ CONFIG_PS3_ROM=m
28CONFIG_PS3_FLASH=m 28CONFIG_PS3_FLASH=m
29CONFIG_PS3_LPM=m 29CONFIG_PS3_LPM=m
30CONFIG_PPC_IBM_CELL_BLADE=y 30CONFIG_PPC_IBM_CELL_BLADE=y
31CONFIG_PPC_CELLEB=y
32CONFIG_RTAS_FLASH=y 31CONFIG_RTAS_FLASH=y
33CONFIG_CPU_FREQ=y 32CONFIG_CPU_FREQ=y
34CONFIG_CPU_FREQ_GOV_POWERSAVE=y 33CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@@ -113,7 +112,6 @@ CONFIG_IDE=y
113CONFIG_BLK_DEV_GENERIC=y 112CONFIG_BLK_DEV_GENERIC=y
114CONFIG_BLK_DEV_AEC62XX=y 113CONFIG_BLK_DEV_AEC62XX=y
115CONFIG_BLK_DEV_SIIMAGE=y 114CONFIG_BLK_DEV_SIIMAGE=y
116CONFIG_BLK_DEV_CELLEB=y
117CONFIG_BLK_DEV_SD=y 115CONFIG_BLK_DEV_SD=y
118CONFIG_BLK_DEV_SR=m 116CONFIG_BLK_DEV_SR=m
119CONFIG_CHR_DEV_SG=y 117CONFIG_CHR_DEV_SG=y
@@ -156,7 +154,6 @@ CONFIG_SERIAL_TXX9_NR_UARTS=2
156CONFIG_SERIAL_TXX9_CONSOLE=y 154CONFIG_SERIAL_TXX9_CONSOLE=y
157CONFIG_SERIAL_OF_PLATFORM=y 155CONFIG_SERIAL_OF_PLATFORM=y
158CONFIG_HVC_RTAS=y 156CONFIG_HVC_RTAS=y
159CONFIG_HVC_BEAT=y
160CONFIG_IPMI_HANDLER=m 157CONFIG_IPMI_HANDLER=m
161CONFIG_IPMI_DEVICE_INTERFACE=m 158CONFIG_IPMI_DEVICE_INTERFACE=m
162CONFIG_IPMI_SI=m 159CONFIG_IPMI_SI=m
diff --git a/arch/powerpc/configs/celleb_defconfig b/arch/powerpc/configs/celleb_defconfig
deleted file mode 100644
index ff454dcd2dd3..000000000000
--- a/arch/powerpc/configs/celleb_defconfig
+++ /dev/null
@@ -1,152 +0,0 @@
1CONFIG_PPC64=y
2CONFIG_TUNE_CELL=y
3CONFIG_ALTIVEC=y
4CONFIG_SMP=y
5CONFIG_NR_CPUS=4
6CONFIG_SYSVIPC=y
7CONFIG_FHANDLE=y
8CONFIG_NO_HZ=y
9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=15
13CONFIG_BLK_DEV_INITRD=y
14# CONFIG_COMPAT_BRK is not set
15CONFIG_MODULES=y
16CONFIG_MODULE_UNLOAD=y
17CONFIG_MODVERSIONS=y
18CONFIG_MODULE_SRCVERSION_ALL=y
19CONFIG_PARTITION_ADVANCED=y
20# CONFIG_PPC_POWERNV is not set
21# CONFIG_PPC_PSERIES is not set
22# CONFIG_PPC_PMAC is not set
23CONFIG_PPC_CELLEB=y
24CONFIG_SPU_FS=y
25# CONFIG_CBE_THERM is not set
26CONFIG_UDBG_RTAS_CONSOLE=y
27# CONFIG_RTAS_PROC is not set
28CONFIG_BINFMT_MISC=m
29CONFIG_KEXEC=y
30CONFIG_NUMA=y
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_INET=y
35CONFIG_IP_MULTICAST=y
36CONFIG_SYN_COOKIES=y
37CONFIG_IPV6=y
38CONFIG_INET6_AH=m
39CONFIG_INET6_ESP=m
40CONFIG_INET6_IPCOMP=m
41CONFIG_IPV6_TUNNEL=m
42CONFIG_NETFILTER=y
43CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
44CONFIG_BLK_DEV_LOOP=y
45CONFIG_BLK_DEV_RAM=y
46CONFIG_BLK_DEV_RAM_SIZE=131072
47CONFIG_IDE=y
48CONFIG_BLK_DEV_IDECD=m
49CONFIG_BLK_DEV_GENERIC=y
50CONFIG_BLK_DEV_CELLEB=y
51CONFIG_SCSI=m
52# CONFIG_SCSI_PROC_FS is not set
53CONFIG_BLK_DEV_SD=m
54CONFIG_BLK_DEV_SR=m
55CONFIG_CHR_DEV_SG=m
56CONFIG_MD=y
57CONFIG_BLK_DEV_MD=m
58CONFIG_MD_LINEAR=m
59CONFIG_MD_RAID0=m
60CONFIG_MD_RAID1=m
61CONFIG_BLK_DEV_DM=m
62CONFIG_DM_CRYPT=m
63CONFIG_DM_SNAPSHOT=m
64CONFIG_DM_MIRROR=m
65CONFIG_DM_ZERO=m
66CONFIG_DM_MULTIPATH=m
67CONFIG_NETDEVICES=y
68CONFIG_SPIDER_NET=y
69# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
70# CONFIG_INPUT_KEYBOARD is not set
71# CONFIG_INPUT_MOUSE is not set
72# CONFIG_SERIO_I8042 is not set
73# CONFIG_LEGACY_PTYS is not set
74CONFIG_SERIAL_NONSTANDARD=y
75CONFIG_SERIAL_TXX9_NR_UARTS=3
76CONFIG_SERIAL_TXX9_CONSOLE=y
77CONFIG_HVC_RTAS=y
78CONFIG_HVC_BEAT=y
79# CONFIG_HW_RANDOM is not set
80CONFIG_GEN_RTC=y
81CONFIG_I2C=y
82# CONFIG_HWMON is not set
83CONFIG_WATCHDOG=y
84# CONFIG_VGA_CONSOLE is not set
85CONFIG_USB_HIDDEV=y
86CONFIG_USB=y
87CONFIG_USB_MON=y
88CONFIG_USB_EHCI_HCD=m
89# CONFIG_USB_EHCI_HCD_PPC_OF is not set
90CONFIG_USB_OHCI_HCD=m
91CONFIG_USB_STORAGE=m
92CONFIG_EXT2_FS=y
93CONFIG_EXT2_FS_XATTR=y
94CONFIG_EXT2_FS_POSIX_ACL=y
95CONFIG_EXT2_FS_SECURITY=y
96CONFIG_EXT2_FS_XIP=y
97CONFIG_EXT3_FS=y
98CONFIG_EXT3_FS_POSIX_ACL=y
99CONFIG_EXT3_FS_SECURITY=y
100CONFIG_ISO9660_FS=m
101CONFIG_JOLIET=y
102CONFIG_UDF_FS=m
103CONFIG_MSDOS_FS=m
104CONFIG_VFAT_FS=m
105CONFIG_PROC_KCORE=y
106CONFIG_TMPFS=y
107CONFIG_HUGETLBFS=y
108CONFIG_NFS_FS=m
109CONFIG_NFS_V3_ACL=y
110CONFIG_NFSD=m
111CONFIG_NFSD_V3=y
112CONFIG_NFSD_V3_ACL=y
113CONFIG_NLS_ISO8859_1=m
114CONFIG_NLS_ISO8859_2=m
115CONFIG_NLS_ISO8859_3=m
116CONFIG_NLS_ISO8859_4=m
117CONFIG_NLS_ISO8859_5=m
118CONFIG_NLS_ISO8859_6=m
119CONFIG_NLS_ISO8859_7=m
120CONFIG_NLS_ISO8859_9=m
121CONFIG_NLS_ISO8859_13=m
122CONFIG_NLS_ISO8859_14=m
123CONFIG_NLS_ISO8859_15=m
124CONFIG_LIBCRC32C=m
125CONFIG_DEBUG_FS=y
126CONFIG_MAGIC_SYSRQ=y
127CONFIG_DEBUG_KERNEL=y
128CONFIG_DEBUG_MUTEXES=y
129CONFIG_XMON=y
130CONFIG_XMON_DEFAULT=y
131CONFIG_CRYPTO_NULL=m
132CONFIG_CRYPTO_TEST=m
133CONFIG_CRYPTO_ECB=m
134CONFIG_CRYPTO_PCBC=m
135CONFIG_CRYPTO_HMAC=y
136CONFIG_CRYPTO_MD4=m
137CONFIG_CRYPTO_MD5=y
138CONFIG_CRYPTO_MICHAEL_MIC=m
139CONFIG_CRYPTO_SHA256=m
140CONFIG_CRYPTO_SHA512=m
141CONFIG_CRYPTO_TGR192=m
142CONFIG_CRYPTO_WP512=m
143CONFIG_CRYPTO_ANUBIS=m
144CONFIG_CRYPTO_ARC4=m
145CONFIG_CRYPTO_BLOWFISH=m
146CONFIG_CRYPTO_CAST5=m
147CONFIG_CRYPTO_CAST6=m
148CONFIG_CRYPTO_KHAZAD=m
149CONFIG_CRYPTO_SERPENT=m
150CONFIG_CRYPTO_TEA=m
151CONFIG_CRYPTO_TWOFISH=m
152# CONFIG_CRYPTO_HW is not set
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 3315c9f0828a..aad501ae3834 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -36,7 +36,6 @@ CONFIG_PS3_ROM=m
36CONFIG_PS3_FLASH=m 36CONFIG_PS3_FLASH=m
37CONFIG_PS3_LPM=m 37CONFIG_PS3_LPM=m
38CONFIG_PPC_IBM_CELL_BLADE=y 38CONFIG_PPC_IBM_CELL_BLADE=y
39CONFIG_PPC_CELLEB=y
40CONFIG_PPC_CELL_QPACE=y 39CONFIG_PPC_CELL_QPACE=y
41CONFIG_RTAS_FLASH=m 40CONFIG_RTAS_FLASH=m
42CONFIG_IBMEBUS=y 41CONFIG_IBMEBUS=y
@@ -89,7 +88,6 @@ CONFIG_IDE=y
89CONFIG_BLK_DEV_IDECD=y 88CONFIG_BLK_DEV_IDECD=y
90CONFIG_BLK_DEV_GENERIC=y 89CONFIG_BLK_DEV_GENERIC=y
91CONFIG_BLK_DEV_AMD74XX=y 90CONFIG_BLK_DEV_AMD74XX=y
92CONFIG_BLK_DEV_CELLEB=y
93CONFIG_BLK_DEV_IDE_PMAC=y 91CONFIG_BLK_DEV_IDE_PMAC=y
94CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 92CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
95CONFIG_BLK_DEV_SD=y 93CONFIG_BLK_DEV_SD=y
@@ -196,7 +194,6 @@ CONFIG_SERIAL_TXX9_CONSOLE=y
196CONFIG_SERIAL_JSM=m 194CONFIG_SERIAL_JSM=m
197CONFIG_HVC_CONSOLE=y 195CONFIG_HVC_CONSOLE=y
198CONFIG_HVC_RTAS=y 196CONFIG_HVC_RTAS=y
199CONFIG_HVC_BEAT=y
200CONFIG_HVCS=m 197CONFIG_HVCS=m
201CONFIG_VIRTIO_CONSOLE=m 198CONFIG_VIRTIO_CONSOLE=m
202CONFIG_IBM_BSR=m 199CONFIG_IBM_BSR=m
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 681bc0314b6b..e05808a328db 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -42,7 +42,7 @@
42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000) 42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
43#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000) 43#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
44#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000) 44#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
45#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000) 45/* Free ASM_CONST(0x0000000001000000) */
46#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) 46#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
47#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000) 47#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
48#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000) 48#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
@@ -75,8 +75,6 @@ enum {
75 FW_FEATURE_POWERNV_ALWAYS = 0, 75 FW_FEATURE_POWERNV_ALWAYS = 0,
76 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 76 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
77 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 77 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
78 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
79 FW_FEATURE_CELLEB_ALWAYS = 0,
80 FW_FEATURE_NATIVE_POSSIBLE = 0, 78 FW_FEATURE_NATIVE_POSSIBLE = 0,
81 FW_FEATURE_NATIVE_ALWAYS = 0, 79 FW_FEATURE_NATIVE_ALWAYS = 0,
82 FW_FEATURE_POSSIBLE = 80 FW_FEATURE_POSSIBLE =
@@ -89,9 +87,6 @@ enum {
89#ifdef CONFIG_PPC_PS3 87#ifdef CONFIG_PPC_PS3
90 FW_FEATURE_PS3_POSSIBLE | 88 FW_FEATURE_PS3_POSSIBLE |
91#endif 89#endif
92#ifdef CONFIG_PPC_CELLEB
93 FW_FEATURE_CELLEB_POSSIBLE |
94#endif
95#ifdef CONFIG_PPC_NATIVE 90#ifdef CONFIG_PPC_NATIVE
96 FW_FEATURE_NATIVE_ALWAYS | 91 FW_FEATURE_NATIVE_ALWAYS |
97#endif 92#endif
@@ -106,9 +101,6 @@ enum {
106#ifdef CONFIG_PPC_PS3 101#ifdef CONFIG_PPC_PS3
107 FW_FEATURE_PS3_ALWAYS & 102 FW_FEATURE_PS3_ALWAYS &
108#endif 103#endif
109#ifdef CONFIG_PPC_CELLEB
110 FW_FEATURE_CELLEB_ALWAYS &
111#endif
112#ifdef CONFIG_PPC_NATIVE 104#ifdef CONFIG_PPC_NATIVE
113 FW_FEATURE_NATIVE_ALWAYS & 105 FW_FEATURE_NATIVE_ALWAYS &
114#endif 106#endif
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index d607df5081a7..7c19959cd705 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -125,7 +125,6 @@ extern irqreturn_t smp_ipi_demux(void);
125 125
126void smp_init_pSeries(void); 126void smp_init_pSeries(void);
127void smp_init_cell(void); 127void smp_init_cell(void);
128void smp_init_celleb(void);
129void smp_setup_cpu_maps(void); 128void smp_setup_cpu_maps(void);
130 129
131extern int __cpu_disable(void); 130extern int __cpu_disable(void);
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index b7aa07279a63..7cc38b5b58bc 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -46,8 +46,6 @@ void __init udbg_early_init(void)
46#elif defined(CONFIG_PPC_EARLY_DEBUG_MAPLE) 46#elif defined(CONFIG_PPC_EARLY_DEBUG_MAPLE)
47 /* Maple real mode debug */ 47 /* Maple real mode debug */
48 udbg_init_maple_realmode(); 48 udbg_init_maple_realmode();
49#elif defined(CONFIG_PPC_EARLY_DEBUG_BEAT)
50 udbg_init_debug_beat();
51#elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE) 49#elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE)
52 udbg_init_pas_realmode(); 50 udbg_init_pas_realmode();
53#elif defined(CONFIG_PPC_EARLY_DEBUG_BOOTX) 51#elif defined(CONFIG_PPC_EARLY_DEBUG_BOOTX)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 391b3f6b54a3..b7f9c408bf24 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -72,11 +72,6 @@ config PPC_SMP_MUXED_IPI
72 cpu. This will enable the generic code to multiplex the 4 72 cpu. This will enable the generic code to multiplex the 4
73 messages on to one ipi. 73 messages on to one ipi.
74 74
75config PPC_UDBG_BEAT
76 bool "BEAT based debug console"
77 depends on PPC_CELLEB
78 default n
79
80config IPIC 75config IPIC
81 bool 76 bool
82 default n 77 default n
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 870b6dbd4d18..2f23133ab3d1 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -33,17 +33,6 @@ config PPC_IBM_CELL_BLADE
33 select PPC_UDBG_16550 33 select PPC_UDBG_16550
34 select UDBG_RTAS_CONSOLE 34 select UDBG_RTAS_CONSOLE
35 35
36config PPC_CELLEB
37 bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
38 depends on PPC64 && PPC_BOOK3S
39 select PPC_CELL_NATIVE
40 select PPC_OF_PLATFORM_PCI
41 select PCI
42 select HAS_TXX9_SERIAL
43 select PPC_UDBG_BEAT
44 select USB_OHCI_BIG_ENDIAN_MMIO
45 select USB_EHCI_BIG_ENDIAN_MMIO
46
47config PPC_CELL_QPACE 36config PPC_CELL_QPACE
48 bool "IBM Cell - QPACE" 37 bool "IBM Cell - QPACE"
49 depends on PPC64 && PPC_BOOK3S 38 depends on PPC64 && PPC_BOOK3S
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index 2d16884f67b9..34699bddfddd 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -29,18 +29,3 @@ obj-$(CONFIG_AXON_MSI) += axon_msi.o
29 29
30# qpace setup 30# qpace setup
31obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o 31obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o
32
33# celleb stuff
34ifeq ($(CONFIG_PPC_CELLEB),y)
35obj-y += celleb_setup.o \
36 celleb_pci.o celleb_scc_epci.o \
37 celleb_scc_pciex.o \
38 celleb_scc_uhc.o \
39 spider-pci.o beat.o beat_htab.o \
40 beat_hvCall.o beat_interrupt.o \
41 beat_iommu.o
42
43obj-$(CONFIG_PPC_UDBG_BEAT) += beat_udbg.o
44obj-$(CONFIG_SERIAL_TXX9) += celleb_scc_sio.o
45obj-$(CONFIG_SPU_BASE) += beat_spu_priv1.o
46endif
diff --git a/arch/powerpc/platforms/cell/beat.c b/arch/powerpc/platforms/cell/beat.c
deleted file mode 100644
index affcf566d460..000000000000
--- a/arch/powerpc/platforms/cell/beat.c
+++ /dev/null
@@ -1,264 +0,0 @@
1/*
2 * Simple routines for Celleb/Beat
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/export.h>
22#include <linux/init.h>
23#include <linux/err.h>
24#include <linux/rtc.h>
25#include <linux/interrupt.h>
26#include <linux/irqreturn.h>
27#include <linux/reboot.h>
28
29#include <asm/hvconsole.h>
30#include <asm/time.h>
31#include <asm/machdep.h>
32#include <asm/firmware.h>
33
34#include "beat_wrapper.h"
35#include "beat.h"
36#include "beat_interrupt.h"
37
38static int beat_pm_poweroff_flag;
39
40void beat_restart(char *cmd)
41{
42 beat_shutdown_logical_partition(!beat_pm_poweroff_flag);
43}
44
45void beat_power_off(void)
46{
47 beat_shutdown_logical_partition(0);
48}
49
50u64 beat_halt_code = 0x1000000000000000UL;
51EXPORT_SYMBOL(beat_halt_code);
52
53void beat_halt(void)
54{
55 beat_shutdown_logical_partition(beat_halt_code);
56}
57
58int beat_set_rtc_time(struct rtc_time *rtc_time)
59{
60 u64 tim;
61 tim = mktime(rtc_time->tm_year+1900,
62 rtc_time->tm_mon+1, rtc_time->tm_mday,
63 rtc_time->tm_hour, rtc_time->tm_min, rtc_time->tm_sec);
64 if (beat_rtc_write(tim))
65 return -1;
66 return 0;
67}
68
69void beat_get_rtc_time(struct rtc_time *rtc_time)
70{
71 u64 tim;
72
73 if (beat_rtc_read(&tim))
74 tim = 0;
75 to_tm(tim, rtc_time);
76 rtc_time->tm_year -= 1900;
77 rtc_time->tm_mon -= 1;
78}
79
80#define BEAT_NVRAM_SIZE 4096
81
82ssize_t beat_nvram_read(char *buf, size_t count, loff_t *index)
83{
84 unsigned int i;
85 unsigned long len;
86 char *p = buf;
87
88 if (*index >= BEAT_NVRAM_SIZE)
89 return -ENODEV;
90 i = *index;
91 if (i + count > BEAT_NVRAM_SIZE)
92 count = BEAT_NVRAM_SIZE - i;
93
94 for (; count != 0; count -= len) {
95 len = count;
96 if (len > BEAT_NVRW_CNT)
97 len = BEAT_NVRW_CNT;
98 if (beat_eeprom_read(i, len, p))
99 return -EIO;
100
101 p += len;
102 i += len;
103 }
104 *index = i;
105 return p - buf;
106}
107
108ssize_t beat_nvram_write(char *buf, size_t count, loff_t *index)
109{
110 unsigned int i;
111 unsigned long len;
112 char *p = buf;
113
114 if (*index >= BEAT_NVRAM_SIZE)
115 return -ENODEV;
116 i = *index;
117 if (i + count > BEAT_NVRAM_SIZE)
118 count = BEAT_NVRAM_SIZE - i;
119
120 for (; count != 0; count -= len) {
121 len = count;
122 if (len > BEAT_NVRW_CNT)
123 len = BEAT_NVRW_CNT;
124 if (beat_eeprom_write(i, len, p))
125 return -EIO;
126
127 p += len;
128 i += len;
129 }
130 *index = i;
131 return p - buf;
132}
133
134ssize_t beat_nvram_get_size(void)
135{
136 return BEAT_NVRAM_SIZE;
137}
138
139int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
140{
141 if (beat_set_dabr(dabr, dabrx))
142 return -1;
143 return 0;
144}
145
146int64_t beat_get_term_char(u64 vterm, u64 *len, u64 *t1, u64 *t2)
147{
148 u64 db[2];
149 s64 ret;
150
151 ret = beat_get_characters_from_console(vterm, len, (u8 *)db);
152 if (ret == 0) {
153 *t1 = db[0];
154 *t2 = db[1];
155 }
156 return ret;
157}
158EXPORT_SYMBOL(beat_get_term_char);
159
160int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
161{
162 u64 db[2];
163
164 db[0] = t1;
165 db[1] = t2;
166 return beat_put_characters_to_console(vterm, len, (u8 *)db);
167}
168EXPORT_SYMBOL(beat_put_term_char);
169
170void beat_power_save(void)
171{
172 beat_pause(0);
173}
174
175#ifdef CONFIG_KEXEC
176void beat_kexec_cpu_down(int crash, int secondary)
177{
178 beatic_deinit_IRQ();
179}
180#endif
181
182static irqreturn_t beat_power_event(int virq, void *arg)
183{
184 printk(KERN_DEBUG "Beat: power button pressed\n");
185 beat_pm_poweroff_flag = 1;
186 ctrl_alt_del();
187 return IRQ_HANDLED;
188}
189
190static irqreturn_t beat_reset_event(int virq, void *arg)
191{
192 printk(KERN_DEBUG "Beat: reset button pressed\n");
193 beat_pm_poweroff_flag = 0;
194 ctrl_alt_del();
195 return IRQ_HANDLED;
196}
197
198static struct beat_event_list {
199 const char *typecode;
200 irq_handler_t handler;
201 unsigned int virq;
202} beat_event_list[] = {
203 { "power", beat_power_event, 0 },
204 { "reset", beat_reset_event, 0 },
205};
206
207static int __init beat_register_event(void)
208{
209 u64 path[4], data[2];
210 int rc, i;
211 unsigned int virq;
212
213 for (i = 0; i < ARRAY_SIZE(beat_event_list); i++) {
214 struct beat_event_list *ev = &beat_event_list[i];
215
216 if (beat_construct_event_receive_port(data) != 0) {
217 printk(KERN_ERR "Beat: "
218 "cannot construct event receive port for %s\n",
219 ev->typecode);
220 return -EINVAL;
221 }
222
223 virq = irq_create_mapping(NULL, data[0]);
224 if (virq == NO_IRQ) {
225 printk(KERN_ERR "Beat: failed to get virtual IRQ"
226 " for event receive port for %s\n",
227 ev->typecode);
228 beat_destruct_event_receive_port(data[0]);
229 return -EIO;
230 }
231 ev->virq = virq;
232
233 rc = request_irq(virq, ev->handler, 0,
234 ev->typecode, NULL);
235 if (rc != 0) {
236 printk(KERN_ERR "Beat: failed to request virtual IRQ"
237 " for event receive port for %s\n",
238 ev->typecode);
239 beat_destruct_event_receive_port(data[0]);
240 return rc;
241 }
242
243 path[0] = 0x1000000065780000ul; /* 1,ex */
244 path[1] = 0x627574746f6e0000ul; /* button */
245 path[2] = 0;
246 strncpy((char *)&path[2], ev->typecode, 8);
247 path[3] = 0;
248 data[1] = 0;
249
250 beat_create_repository_node(path, data);
251 }
252 return 0;
253}
254
255static int __init beat_event_init(void)
256{
257 if (!firmware_has_feature(FW_FEATURE_BEAT))
258 return -EINVAL;
259
260 beat_pm_poweroff_flag = 0;
261 return beat_register_event();
262}
263
264device_initcall(beat_event_init);
diff --git a/arch/powerpc/platforms/cell/beat.h b/arch/powerpc/platforms/cell/beat.h
deleted file mode 100644
index bfcb8e351ae5..000000000000
--- a/arch/powerpc/platforms/cell/beat.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Guest OS Interfaces.
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_BEAT_H
22#define _CELLEB_BEAT_H
23
24int64_t beat_get_term_char(uint64_t, uint64_t *, uint64_t *, uint64_t *);
25int64_t beat_put_term_char(uint64_t, uint64_t, uint64_t, uint64_t);
26int64_t beat_repository_encode(int, const char *, uint64_t[4]);
27void beat_restart(char *);
28void beat_power_off(void);
29void beat_halt(void);
30int beat_set_rtc_time(struct rtc_time *);
31void beat_get_rtc_time(struct rtc_time *);
32ssize_t beat_nvram_get_size(void);
33ssize_t beat_nvram_read(char *, size_t, loff_t *);
34ssize_t beat_nvram_write(char *, size_t, loff_t *);
35int beat_set_xdabr(unsigned long, unsigned long);
36void beat_power_save(void);
37void beat_kexec_cpu_down(int, int);
38
39#endif /* _CELLEB_BEAT_H */
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
deleted file mode 100644
index bee9232fe619..000000000000
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ /dev/null
@@ -1,445 +0,0 @@
1/*
2 * "Cell Reference Set" HTAB support.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/lpar.c:
7 * Copyright (C) 2001 Todd Inglett, IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 */
23
24#undef DEBUG_LOW
25
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
28
29#include <asm/mmu.h>
30#include <asm/page.h>
31#include <asm/pgtable.h>
32#include <asm/machdep.h>
33#include <asm/udbg.h>
34
35#include "beat_wrapper.h"
36
37#ifdef DEBUG_LOW
38#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while (0)
39#else
40#define DBG_LOW(fmt...) do { } while (0)
41#endif
42
43static DEFINE_RAW_SPINLOCK(beat_htab_lock);
44
45static inline unsigned int beat_read_mask(unsigned hpte_group)
46{
47 unsigned long rmask = 0;
48 u64 hpte_v[5];
49
50 beat_read_htab_entries(0, hpte_group + 0, hpte_v);
51 if (!(hpte_v[0] & HPTE_V_BOLTED))
52 rmask |= 0x8000;
53 if (!(hpte_v[1] & HPTE_V_BOLTED))
54 rmask |= 0x4000;
55 if (!(hpte_v[2] & HPTE_V_BOLTED))
56 rmask |= 0x2000;
57 if (!(hpte_v[3] & HPTE_V_BOLTED))
58 rmask |= 0x1000;
59 beat_read_htab_entries(0, hpte_group + 4, hpte_v);
60 if (!(hpte_v[0] & HPTE_V_BOLTED))
61 rmask |= 0x0800;
62 if (!(hpte_v[1] & HPTE_V_BOLTED))
63 rmask |= 0x0400;
64 if (!(hpte_v[2] & HPTE_V_BOLTED))
65 rmask |= 0x0200;
66 if (!(hpte_v[3] & HPTE_V_BOLTED))
67 rmask |= 0x0100;
68 hpte_group = ~hpte_group & (htab_hash_mask * HPTES_PER_GROUP);
69 beat_read_htab_entries(0, hpte_group + 0, hpte_v);
70 if (!(hpte_v[0] & HPTE_V_BOLTED))
71 rmask |= 0x80;
72 if (!(hpte_v[1] & HPTE_V_BOLTED))
73 rmask |= 0x40;
74 if (!(hpte_v[2] & HPTE_V_BOLTED))
75 rmask |= 0x20;
76 if (!(hpte_v[3] & HPTE_V_BOLTED))
77 rmask |= 0x10;
78 beat_read_htab_entries(0, hpte_group + 4, hpte_v);
79 if (!(hpte_v[0] & HPTE_V_BOLTED))
80 rmask |= 0x08;
81 if (!(hpte_v[1] & HPTE_V_BOLTED))
82 rmask |= 0x04;
83 if (!(hpte_v[2] & HPTE_V_BOLTED))
84 rmask |= 0x02;
85 if (!(hpte_v[3] & HPTE_V_BOLTED))
86 rmask |= 0x01;
87 return rmask;
88}
89
90static long beat_lpar_hpte_insert(unsigned long hpte_group,
91 unsigned long vpn, unsigned long pa,
92 unsigned long rflags, unsigned long vflags,
93 int psize, int apsize, int ssize)
94{
95 unsigned long lpar_rc;
96 u64 hpte_v, hpte_r, slot;
97
98 if (vflags & HPTE_V_SECONDARY)
99 return -1;
100
101 if (!(vflags & HPTE_V_BOLTED))
102 DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
103 "rflags=%lx, vflags=%lx, psize=%d)\n",
104 hpte_group, va, pa, rflags, vflags, psize);
105
106 hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
107 vflags | HPTE_V_VALID;
108 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
109
110 if (!(vflags & HPTE_V_BOLTED))
111 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
112
113 if (rflags & _PAGE_NO_CACHE)
114 hpte_r &= ~HPTE_R_M;
115
116 raw_spin_lock(&beat_htab_lock);
117 lpar_rc = beat_read_mask(hpte_group);
118 if (lpar_rc == 0) {
119 if (!(vflags & HPTE_V_BOLTED))
120 DBG_LOW(" full\n");
121 raw_spin_unlock(&beat_htab_lock);
122 return -1;
123 }
124
125 lpar_rc = beat_insert_htab_entry(0, hpte_group, lpar_rc << 48,
126 hpte_v, hpte_r, &slot);
127 raw_spin_unlock(&beat_htab_lock);
128
129 /*
130 * Since we try and ioremap PHBs we don't own, the pte insert
131 * will fail. However we must catch the failure in hash_page
132 * or we will loop forever, so return -2 in this case.
133 */
134 if (unlikely(lpar_rc != 0)) {
135 if (!(vflags & HPTE_V_BOLTED))
136 DBG_LOW(" lpar err %lx\n", lpar_rc);
137 return -2;
138 }
139 if (!(vflags & HPTE_V_BOLTED))
140 DBG_LOW(" -> slot: %lx\n", slot);
141
142 /* We have to pass down the secondary bucket bit here as well */
143 return (slot ^ hpte_group) & 15;
144}
145
146static long beat_lpar_hpte_remove(unsigned long hpte_group)
147{
148 DBG_LOW("hpte_remove(group=%lx)\n", hpte_group);
149 return -1;
150}
151
152static unsigned long beat_lpar_hpte_getword0(unsigned long slot)
153{
154 unsigned long dword0;
155 unsigned long lpar_rc;
156 u64 dword[5];
157
158 lpar_rc = beat_read_htab_entries(0, slot & ~3UL, dword);
159
160 dword0 = dword[slot&3];
161
162 BUG_ON(lpar_rc != 0);
163
164 return dword0;
165}
166
167static void beat_lpar_hptab_clear(void)
168{
169 unsigned long size_bytes = 1UL << ppc64_pft_size;
170 unsigned long hpte_count = size_bytes >> 4;
171 int i;
172 u64 dummy0, dummy1;
173
174 /* TODO: Use bulk call */
175 for (i = 0; i < hpte_count; i++)
176 beat_write_htab_entry(0, i, 0, 0, -1UL, -1UL, &dummy0, &dummy1);
177}
178
179/*
180 * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
181 * the low 3 bits of flags happen to line up. So no transform is needed.
182 * We can probably optimize here and assume the high bits of newpp are
183 * already zero. For now I am paranoid.
184 */
185static long beat_lpar_hpte_updatepp(unsigned long slot,
186 unsigned long newpp,
187 unsigned long vpn,
188 int psize, int apsize,
189 int ssize, unsigned long flags)
190{
191 unsigned long lpar_rc;
192 u64 dummy0, dummy1;
193 unsigned long want_v;
194
195 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
196
197 DBG_LOW(" update: "
198 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
199 want_v & HPTE_V_AVPN, slot, psize, newpp);
200
201 raw_spin_lock(&beat_htab_lock);
202 dummy0 = beat_lpar_hpte_getword0(slot);
203 if ((dummy0 & ~0x7FUL) != (want_v & ~0x7FUL)) {
204 DBG_LOW("not found !\n");
205 raw_spin_unlock(&beat_htab_lock);
206 return -1;
207 }
208
209 lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7, &dummy0,
210 &dummy1);
211 raw_spin_unlock(&beat_htab_lock);
212 if (lpar_rc != 0 || dummy0 == 0) {
213 DBG_LOW("not found !\n");
214 return -1;
215 }
216
217 DBG_LOW("ok %lx %lx\n", dummy0, dummy1);
218
219 BUG_ON(lpar_rc != 0);
220
221 return 0;
222}
223
224static long beat_lpar_hpte_find(unsigned long vpn, int psize)
225{
226 unsigned long hash;
227 unsigned long i, j;
228 long slot;
229 unsigned long want_v, hpte_v;
230
231 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
232 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
233
234 for (j = 0; j < 2; j++) {
235 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
236 for (i = 0; i < HPTES_PER_GROUP; i++) {
237 hpte_v = beat_lpar_hpte_getword0(slot);
238
239 if (HPTE_V_COMPARE(hpte_v, want_v)
240 && (hpte_v & HPTE_V_VALID)
241 && (!!(hpte_v & HPTE_V_SECONDARY) == j)) {
242 /* HPTE matches */
243 if (j)
244 slot = -slot;
245 return slot;
246 }
247 ++slot;
248 }
249 hash = ~hash;
250 }
251
252 return -1;
253}
254
255static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
256 unsigned long ea,
257 int psize, int ssize)
258{
259 unsigned long vpn;
260 unsigned long lpar_rc, slot, vsid;
261 u64 dummy0, dummy1;
262
263 vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
264 vpn = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
265
266 raw_spin_lock(&beat_htab_lock);
267 slot = beat_lpar_hpte_find(vpn, psize);
268 BUG_ON(slot == -1);
269
270 lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
271 &dummy0, &dummy1);
272 raw_spin_unlock(&beat_htab_lock);
273
274 BUG_ON(lpar_rc != 0);
275}
276
277static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
278 int psize, int apsize,
279 int ssize, int local)
280{
281 unsigned long want_v;
282 unsigned long lpar_rc;
283 u64 dummy1, dummy2;
284 unsigned long flags;
285
286 DBG_LOW(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
287 slot, va, psize, local);
288 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
289
290 raw_spin_lock_irqsave(&beat_htab_lock, flags);
291 dummy1 = beat_lpar_hpte_getword0(slot);
292
293 if ((dummy1 & ~0x7FUL) != (want_v & ~0x7FUL)) {
294 DBG_LOW("not found !\n");
295 raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
296 return;
297 }
298
299 lpar_rc = beat_write_htab_entry(0, slot, 0, 0, HPTE_V_VALID, 0,
300 &dummy1, &dummy2);
301 raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
302
303 BUG_ON(lpar_rc != 0);
304}
305
306void __init hpte_init_beat(void)
307{
308 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate;
309 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp;
310 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
311 ppc_md.hpte_insert = beat_lpar_hpte_insert;
312 ppc_md.hpte_remove = beat_lpar_hpte_remove;
313 ppc_md.hpte_clear_all = beat_lpar_hptab_clear;
314}
315
316static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
317 unsigned long vpn, unsigned long pa,
318 unsigned long rflags, unsigned long vflags,
319 int psize, int apsize, int ssize)
320{
321 unsigned long lpar_rc;
322 u64 hpte_v, hpte_r, slot;
323
324 if (vflags & HPTE_V_SECONDARY)
325 return -1;
326
327 if (!(vflags & HPTE_V_BOLTED))
328 DBG_LOW("hpte_insert(group=%lx, vpn=%016lx, pa=%016lx, "
329 "rflags=%lx, vflags=%lx, psize=%d)\n",
330 hpte_group, vpn, pa, rflags, vflags, psize);
331
332 hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
333 vflags | HPTE_V_VALID;
334 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
335
336 if (!(vflags & HPTE_V_BOLTED))
337 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
338
339 if (rflags & _PAGE_NO_CACHE)
340 hpte_r &= ~HPTE_R_M;
341
342 /* insert into not-volted entry */
343 lpar_rc = beat_insert_htab_entry3(0, hpte_group, hpte_v, hpte_r,
344 HPTE_V_BOLTED, 0, &slot);
345 /*
346 * Since we try and ioremap PHBs we don't own, the pte insert
347 * will fail. However we must catch the failure in hash_page
348 * or we will loop forever, so return -2 in this case.
349 */
350 if (unlikely(lpar_rc != 0)) {
351 if (!(vflags & HPTE_V_BOLTED))
352 DBG_LOW(" lpar err %lx\n", lpar_rc);
353 return -2;
354 }
355 if (!(vflags & HPTE_V_BOLTED))
356 DBG_LOW(" -> slot: %lx\n", slot);
357
358 /* We have to pass down the secondary bucket bit here as well */
359 return (slot ^ hpte_group) & 15;
360}
361
362/*
363 * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
364 * the low 3 bits of flags happen to line up. So no transform is needed.
365 * We can probably optimize here and assume the high bits of newpp are
366 * already zero. For now I am paranoid.
367 */
368static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
369 unsigned long newpp,
370 unsigned long vpn,
371 int psize, int apsize,
372 int ssize, unsigned long flags)
373{
374 unsigned long lpar_rc;
375 unsigned long want_v;
376 unsigned long pss;
377
378 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
379 pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
380
381 DBG_LOW(" update: "
382 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
383 want_v & HPTE_V_AVPN, slot, psize, newpp);
384
385 lpar_rc = beat_update_htab_permission3(0, slot, want_v, pss, 7, newpp);
386
387 if (lpar_rc == 0xfffffff7) {
388 DBG_LOW("not found !\n");
389 return -1;
390 }
391
392 DBG_LOW("ok\n");
393
394 BUG_ON(lpar_rc != 0);
395
396 return 0;
397}
398
399static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
400 int psize, int apsize,
401 int ssize, int local)
402{
403 unsigned long want_v;
404 unsigned long lpar_rc;
405 unsigned long pss;
406
407 DBG_LOW(" inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
408 slot, vpn, psize, local);
409 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
410 pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
411
412 lpar_rc = beat_invalidate_htab_entry3(0, slot, want_v, pss);
413
414 /* E_busy can be valid output: page may be already replaced */
415 BUG_ON(lpar_rc != 0 && lpar_rc != 0xfffffff7);
416}
417
418static int64_t _beat_lpar_hptab_clear_v3(void)
419{
420 return beat_clear_htab3(0);
421}
422
423static void beat_lpar_hptab_clear_v3(void)
424{
425 _beat_lpar_hptab_clear_v3();
426}
427
428void __init hpte_init_beat_v3(void)
429{
430 if (_beat_lpar_hptab_clear_v3() == 0) {
431 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate_v3;
432 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp_v3;
433 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
434 ppc_md.hpte_insert = beat_lpar_hpte_insert_v3;
435 ppc_md.hpte_remove = beat_lpar_hpte_remove;
436 ppc_md.hpte_clear_all = beat_lpar_hptab_clear_v3;
437 } else {
438 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate;
439 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp;
440 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
441 ppc_md.hpte_insert = beat_lpar_hpte_insert;
442 ppc_md.hpte_remove = beat_lpar_hpte_remove;
443 ppc_md.hpte_clear_all = beat_lpar_hptab_clear;
444 }
445}
diff --git a/arch/powerpc/platforms/cell/beat_hvCall.S b/arch/powerpc/platforms/cell/beat_hvCall.S
deleted file mode 100644
index 96c801907126..000000000000
--- a/arch/powerpc/platforms/cell/beat_hvCall.S
+++ /dev/null
@@ -1,285 +0,0 @@
1/*
2 * Beat hypervisor call I/F
3 *
4 * (C) Copyright 2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/hvCall.S.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <asm/ppc_asm.h>
24
25/* Not implemented on Beat, now */
26#define HCALL_INST_PRECALL
27#define HCALL_INST_POSTCALL
28
29 .text
30
31#define HVSC .long 0x44000022
32
33/* Note: takes only 7 input parameters at maximum */
34_GLOBAL(beat_hcall_norets)
35 HMT_MEDIUM
36
37 mfcr r0
38 stw r0,8(r1)
39
40 HCALL_INST_PRECALL
41
42 mr r11,r3
43 mr r3,r4
44 mr r4,r5
45 mr r5,r6
46 mr r6,r7
47 mr r7,r8
48 mr r8,r9
49
50 HVSC /* invoke the hypervisor */
51
52 HCALL_INST_POSTCALL
53
54 lwz r0,8(r1)
55 mtcrf 0xff,r0
56
57 blr /* return r3 = status */
58
59/* Note: takes 8 input parameters at maximum */
60_GLOBAL(beat_hcall_norets8)
61 HMT_MEDIUM
62
63 mfcr r0
64 stw r0,8(r1)
65
66 HCALL_INST_PRECALL
67
68 mr r11,r3
69 mr r3,r4
70 mr r4,r5
71 mr r5,r6
72 mr r6,r7
73 mr r7,r8
74 mr r8,r9
75 ld r10,STK_PARAM(R10)(r1)
76
77 HVSC /* invoke the hypervisor */
78
79 HCALL_INST_POSTCALL
80
81 lwz r0,8(r1)
82 mtcrf 0xff,r0
83
84 blr /* return r3 = status */
85
86/* Note: takes only 6 input parameters, 1 output parameters at maximum */
87_GLOBAL(beat_hcall1)
88 HMT_MEDIUM
89
90 mfcr r0
91 stw r0,8(r1)
92
93 HCALL_INST_PRECALL
94
95 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
96
97 mr r11,r3
98 mr r3,r5
99 mr r4,r6
100 mr r5,r7
101 mr r6,r8
102 mr r7,r9
103 mr r8,r10
104
105 HVSC /* invoke the hypervisor */
106
107 HCALL_INST_POSTCALL
108
109 ld r12,STK_PARAM(R4)(r1)
110 std r4, 0(r12)
111
112 lwz r0,8(r1)
113 mtcrf 0xff,r0
114
115 blr /* return r3 = status */
116
117/* Note: takes only 6 input parameters, 2 output parameters at maximum */
118_GLOBAL(beat_hcall2)
119 HMT_MEDIUM
120
121 mfcr r0
122 stw r0,8(r1)
123
124 HCALL_INST_PRECALL
125
126 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
127
128 mr r11,r3
129 mr r3,r5
130 mr r4,r6
131 mr r5,r7
132 mr r6,r8
133 mr r7,r9
134 mr r8,r10
135
136 HVSC /* invoke the hypervisor */
137
138 HCALL_INST_POSTCALL
139
140 ld r12,STK_PARAM(R4)(r1)
141 std r4, 0(r12)
142 std r5, 8(r12)
143
144 lwz r0,8(r1)
145 mtcrf 0xff,r0
146
147 blr /* return r3 = status */
148
149/* Note: takes only 6 input parameters, 3 output parameters at maximum */
150_GLOBAL(beat_hcall3)
151 HMT_MEDIUM
152
153 mfcr r0
154 stw r0,8(r1)
155
156 HCALL_INST_PRECALL
157
158 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
159
160 mr r11,r3
161 mr r3,r5
162 mr r4,r6
163 mr r5,r7
164 mr r6,r8
165 mr r7,r9
166 mr r8,r10
167
168 HVSC /* invoke the hypervisor */
169
170 HCALL_INST_POSTCALL
171
172 ld r12,STK_PARAM(R4)(r1)
173 std r4, 0(r12)
174 std r5, 8(r12)
175 std r6, 16(r12)
176
177 lwz r0,8(r1)
178 mtcrf 0xff,r0
179
180 blr /* return r3 = status */
181
182/* Note: takes only 6 input parameters, 4 output parameters at maximum */
183_GLOBAL(beat_hcall4)
184 HMT_MEDIUM
185
186 mfcr r0
187 stw r0,8(r1)
188
189 HCALL_INST_PRECALL
190
191 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
192
193 mr r11,r3
194 mr r3,r5
195 mr r4,r6
196 mr r5,r7
197 mr r6,r8
198 mr r7,r9
199 mr r8,r10
200
201 HVSC /* invoke the hypervisor */
202
203 HCALL_INST_POSTCALL
204
205 ld r12,STK_PARAM(R4)(r1)
206 std r4, 0(r12)
207 std r5, 8(r12)
208 std r6, 16(r12)
209 std r7, 24(r12)
210
211 lwz r0,8(r1)
212 mtcrf 0xff,r0
213
214 blr /* return r3 = status */
215
216/* Note: takes only 6 input parameters, 5 output parameters at maximum */
217_GLOBAL(beat_hcall5)
218 HMT_MEDIUM
219
220 mfcr r0
221 stw r0,8(r1)
222
223 HCALL_INST_PRECALL
224
225 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
226
227 mr r11,r3
228 mr r3,r5
229 mr r4,r6
230 mr r5,r7
231 mr r6,r8
232 mr r7,r9
233 mr r8,r10
234
235 HVSC /* invoke the hypervisor */
236
237 HCALL_INST_POSTCALL
238
239 ld r12,STK_PARAM(R4)(r1)
240 std r4, 0(r12)
241 std r5, 8(r12)
242 std r6, 16(r12)
243 std r7, 24(r12)
244 std r8, 32(r12)
245
246 lwz r0,8(r1)
247 mtcrf 0xff,r0
248
249 blr /* return r3 = status */
250
251/* Note: takes only 6 input parameters, 6 output parameters at maximum */
252_GLOBAL(beat_hcall6)
253 HMT_MEDIUM
254
255 mfcr r0
256 stw r0,8(r1)
257
258 HCALL_INST_PRECALL
259
260 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
261
262 mr r11,r3
263 mr r3,r5
264 mr r4,r6
265 mr r5,r7
266 mr r6,r8
267 mr r7,r9
268 mr r8,r10
269
270 HVSC /* invoke the hypervisor */
271
272 HCALL_INST_POSTCALL
273
274 ld r12,STK_PARAM(R4)(r1)
275 std r4, 0(r12)
276 std r5, 8(r12)
277 std r6, 16(r12)
278 std r7, 24(r12)
279 std r8, 32(r12)
280 std r9, 40(r12)
281
282 lwz r0,8(r1)
283 mtcrf 0xff,r0
284
285 blr /* return r3 = status */
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
deleted file mode 100644
index 9e5dfbcc00af..000000000000
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Celleb/Beat Interrupt controller
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/percpu.h>
25#include <linux/types.h>
26
27#include <asm/machdep.h>
28
29#include "beat_interrupt.h"
30#include "beat_wrapper.h"
31
32#define MAX_IRQS NR_IRQS
33static DEFINE_RAW_SPINLOCK(beatic_irq_mask_lock);
34static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
35static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
36
37static struct irq_domain *beatic_host;
38
39/*
40 * In this implementation, "virq" == "IRQ plug number",
41 * "(irq_hw_number_t)hwirq" == "IRQ outlet number".
42 */
43
44/* assumption: locked */
45static inline void beatic_update_irq_mask(unsigned int irq_plug)
46{
47 int off;
48 unsigned long masks[4];
49
50 off = (irq_plug / 256) * 4;
51 masks[0] = beatic_irq_mask_enable[off + 0]
52 & beatic_irq_mask_ack[off + 0];
53 masks[1] = beatic_irq_mask_enable[off + 1]
54 & beatic_irq_mask_ack[off + 1];
55 masks[2] = beatic_irq_mask_enable[off + 2]
56 & beatic_irq_mask_ack[off + 2];
57 masks[3] = beatic_irq_mask_enable[off + 3]
58 & beatic_irq_mask_ack[off + 3];
59 if (beat_set_interrupt_mask(irq_plug&~255UL,
60 masks[0], masks[1], masks[2], masks[3]) != 0)
61 panic("Failed to set mask IRQ!");
62}
63
64static void beatic_mask_irq(struct irq_data *d)
65{
66 unsigned long flags;
67
68 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
69 beatic_irq_mask_enable[d->irq/64] &= ~(1UL << (63 - (d->irq%64)));
70 beatic_update_irq_mask(d->irq);
71 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
72}
73
74static void beatic_unmask_irq(struct irq_data *d)
75{
76 unsigned long flags;
77
78 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
79 beatic_irq_mask_enable[d->irq/64] |= 1UL << (63 - (d->irq%64));
80 beatic_update_irq_mask(d->irq);
81 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
82}
83
84static void beatic_ack_irq(struct irq_data *d)
85{
86 unsigned long flags;
87
88 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
89 beatic_irq_mask_ack[d->irq/64] &= ~(1UL << (63 - (d->irq%64)));
90 beatic_update_irq_mask(d->irq);
91 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
92}
93
94static void beatic_end_irq(struct irq_data *d)
95{
96 s64 err;
97 unsigned long flags;
98
99 err = beat_downcount_of_interrupt(d->irq);
100 if (err != 0) {
101 if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */
102 panic("Failed to downcount IRQ! Error = %16llx", err);
103
104 printk(KERN_ERR "IRQ over-downcounted, plug %d\n", d->irq);
105 }
106 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
107 beatic_irq_mask_ack[d->irq/64] |= 1UL << (63 - (d->irq%64));
108 beatic_update_irq_mask(d->irq);
109 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
110}
111
112static struct irq_chip beatic_pic = {
113 .name = "CELL-BEAT",
114 .irq_unmask = beatic_unmask_irq,
115 .irq_mask = beatic_mask_irq,
116 .irq_eoi = beatic_end_irq,
117};
118
119/*
120 * Dispose binding hardware IRQ number (hw) and Virtuql IRQ number (virq),
121 * update flags.
122 *
123 * Note that the number (virq) is already assigned at upper layer.
124 */
125static void beatic_pic_host_unmap(struct irq_domain *h, unsigned int virq)
126{
127 beat_destruct_irq_plug(virq);
128}
129
130/*
131 * Create or update binding hardware IRQ number (hw) and Virtuql
132 * IRQ number (virq). This is called only once for a given mapping.
133 *
134 * Note that the number (virq) is already assigned at upper layer.
135 */
136static int beatic_pic_host_map(struct irq_domain *h, unsigned int virq,
137 irq_hw_number_t hw)
138{
139 int64_t err;
140
141 err = beat_construct_and_connect_irq_plug(virq, hw);
142 if (err < 0)
143 return -EIO;
144
145 irq_set_status_flags(virq, IRQ_LEVEL);
146 irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
147 return 0;
148}
149
150/*
151 * Translate device-tree interrupt spec to irq_hw_number_t style (ulong),
152 * to pass away to irq_create_mapping().
153 *
154 * Called from irq_create_of_mapping() only.
155 * Note: We have only 1 entry to translate.
156 */
157static int beatic_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
158 const u32 *intspec, unsigned int intsize,
159 irq_hw_number_t *out_hwirq,
160 unsigned int *out_flags)
161{
162 const u64 *intspec2 = (const u64 *)intspec;
163
164 *out_hwirq = *intspec2;
165 *out_flags |= IRQ_TYPE_LEVEL_LOW;
166 return 0;
167}
168
169static int beatic_pic_host_match(struct irq_domain *h, struct device_node *np)
170{
171 /* Match all */
172 return 1;
173}
174
175static const struct irq_domain_ops beatic_pic_host_ops = {
176 .map = beatic_pic_host_map,
177 .unmap = beatic_pic_host_unmap,
178 .xlate = beatic_pic_host_xlate,
179 .match = beatic_pic_host_match,
180};
181
182/*
183 * Get an IRQ number
184 * Note: returns VIRQ
185 */
186static inline unsigned int beatic_get_irq_plug(void)
187{
188 int i;
189 uint64_t pending[4], ub;
190
191 for (i = 0; i < MAX_IRQS; i += 256) {
192 beat_detect_pending_interrupts(i, pending);
193 __asm__ ("cntlzd %0,%1":"=r"(ub):
194 "r"(pending[0] & beatic_irq_mask_enable[i/64+0]
195 & beatic_irq_mask_ack[i/64+0]));
196 if (ub != 64)
197 return i + ub + 0;
198 __asm__ ("cntlzd %0,%1":"=r"(ub):
199 "r"(pending[1] & beatic_irq_mask_enable[i/64+1]
200 & beatic_irq_mask_ack[i/64+1]));
201 if (ub != 64)
202 return i + ub + 64;
203 __asm__ ("cntlzd %0,%1":"=r"(ub):
204 "r"(pending[2] & beatic_irq_mask_enable[i/64+2]
205 & beatic_irq_mask_ack[i/64+2]));
206 if (ub != 64)
207 return i + ub + 128;
208 __asm__ ("cntlzd %0,%1":"=r"(ub):
209 "r"(pending[3] & beatic_irq_mask_enable[i/64+3]
210 & beatic_irq_mask_ack[i/64+3]));
211 if (ub != 64)
212 return i + ub + 192;
213 }
214
215 return NO_IRQ;
216}
217unsigned int beatic_get_irq(void)
218{
219 unsigned int ret;
220
221 ret = beatic_get_irq_plug();
222 if (ret != NO_IRQ)
223 beatic_ack_irq(irq_get_irq_data(ret));
224 return ret;
225}
226
227/*
228 */
229void __init beatic_init_IRQ(void)
230{
231 int i;
232
233 memset(beatic_irq_mask_enable, 0, sizeof(beatic_irq_mask_enable));
234 memset(beatic_irq_mask_ack, 255, sizeof(beatic_irq_mask_ack));
235 for (i = 0; i < MAX_IRQS; i += 256)
236 beat_set_interrupt_mask(i, 0L, 0L, 0L, 0L);
237
238 /* Set out get_irq function */
239 ppc_md.get_irq = beatic_get_irq;
240
241 /* Allocate an irq host */
242 beatic_host = irq_domain_add_nomap(NULL, ~0, &beatic_pic_host_ops, NULL);
243 BUG_ON(beatic_host == NULL);
244 irq_set_default_host(beatic_host);
245}
246
247void beatic_deinit_IRQ(void)
248{
249 int i;
250
251 for (i = 1; i < nr_irqs; i++)
252 beat_destruct_irq_plug(i);
253}
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.h b/arch/powerpc/platforms/cell/beat_interrupt.h
deleted file mode 100644
index a7e52f91a078..000000000000
--- a/arch/powerpc/platforms/cell/beat_interrupt.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Celleb/Beat Interrupt controller
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef ASM_BEAT_PIC_H
22#define ASM_BEAT_PIC_H
23#ifdef __KERNEL__
24
25extern void beatic_init_IRQ(void);
26extern unsigned int beatic_get_irq(void);
27extern void beatic_deinit_IRQ(void);
28
29#endif
30#endif /* ASM_BEAT_PIC_H */
diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c
deleted file mode 100644
index 3ce685568935..000000000000
--- a/arch/powerpc/platforms/cell/beat_iommu.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Support for IOMMU on Celleb platform.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/dma-mapping.h>
24#include <linux/pci.h>
25#include <linux/of_platform.h>
26
27#include <asm/machdep.h>
28
29#include "beat_wrapper.h"
30
31#define DMA_FLAGS 0xf800000000000000UL /* r/w permitted, coherency required,
32 strongest order */
33
34static int __init find_dma_window(u64 *io_space_id, u64 *ioid,
35 u64 *base, u64 *size, u64 *io_page_size)
36{
37 struct device_node *dn;
38 const unsigned long *dma_window;
39
40 for_each_node_by_type(dn, "ioif") {
41 dma_window = of_get_property(dn, "toshiba,dma-window", NULL);
42 if (dma_window) {
43 *io_space_id = (dma_window[0] >> 32) & 0xffffffffUL;
44 *ioid = dma_window[0] & 0x7ffUL;
45 *base = dma_window[1];
46 *size = dma_window[2];
47 *io_page_size = 1 << dma_window[3];
48 of_node_put(dn);
49 return 1;
50 }
51 }
52 return 0;
53}
54
55static unsigned long celleb_dma_direct_offset;
56
57static void __init celleb_init_direct_mapping(void)
58{
59 u64 lpar_addr, io_addr;
60 u64 io_space_id, ioid, dma_base, dma_size, io_page_size;
61
62 if (!find_dma_window(&io_space_id, &ioid, &dma_base, &dma_size,
63 &io_page_size)) {
64 pr_info("No dma window found !\n");
65 return;
66 }
67
68 for (lpar_addr = 0; lpar_addr < dma_size; lpar_addr += io_page_size) {
69 io_addr = lpar_addr + dma_base;
70 (void)beat_put_iopte(io_space_id, io_addr, lpar_addr,
71 ioid, DMA_FLAGS);
72 }
73
74 celleb_dma_direct_offset = dma_base;
75}
76
77static void celleb_dma_dev_setup(struct device *dev)
78{
79 set_dma_ops(dev, &dma_direct_ops);
80 set_dma_offset(dev, celleb_dma_direct_offset);
81}
82
83static void celleb_pci_dma_dev_setup(struct pci_dev *pdev)
84{
85 celleb_dma_dev_setup(&pdev->dev);
86}
87
88static int celleb_of_bus_notify(struct notifier_block *nb,
89 unsigned long action, void *data)
90{
91 struct device *dev = data;
92
93 /* We are only intereted in device addition */
94 if (action != BUS_NOTIFY_ADD_DEVICE)
95 return 0;
96
97 celleb_dma_dev_setup(dev);
98
99 return 0;
100}
101
102static struct notifier_block celleb_of_bus_notifier = {
103 .notifier_call = celleb_of_bus_notify
104};
105
106static int __init celleb_init_iommu(void)
107{
108 celleb_init_direct_mapping();
109 ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
110 bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier);
111
112 return 0;
113}
114
115machine_arch_initcall(celleb_beat, celleb_init_iommu);
diff --git a/arch/powerpc/platforms/cell/beat_spu_priv1.c b/arch/powerpc/platforms/cell/beat_spu_priv1.c
deleted file mode 100644
index 13f52589d3a9..000000000000
--- a/arch/powerpc/platforms/cell/beat_spu_priv1.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * spu hypervisor abstraction for Beat
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <asm/types.h>
22#include <asm/spu.h>
23#include <asm/spu_priv1.h>
24
25#include "beat_wrapper.h"
26
27static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
28{
29 spu->shadow_int_mask_RW[class] = mask;
30 beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
31}
32
33static inline u64 _int_mask_get(struct spu *spu, int class)
34{
35 return spu->shadow_int_mask_RW[class];
36}
37
38static void int_mask_set(struct spu *spu, int class, u64 mask)
39{
40 _int_mask_set(spu, class, mask);
41}
42
43static u64 int_mask_get(struct spu *spu, int class)
44{
45 return _int_mask_get(spu, class);
46}
47
48static void int_mask_and(struct spu *spu, int class, u64 mask)
49{
50 u64 old_mask;
51 old_mask = _int_mask_get(spu, class);
52 _int_mask_set(spu, class, old_mask & mask);
53}
54
55static void int_mask_or(struct spu *spu, int class, u64 mask)
56{
57 u64 old_mask;
58 old_mask = _int_mask_get(spu, class);
59 _int_mask_set(spu, class, old_mask | mask);
60}
61
62static void int_stat_clear(struct spu *spu, int class, u64 stat)
63{
64 beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
65}
66
67static u64 int_stat_get(struct spu *spu, int class)
68{
69 u64 int_stat;
70 beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
71 return int_stat;
72}
73
74static void cpu_affinity_set(struct spu *spu, int cpu)
75{
76 return;
77}
78
79static u64 mfc_dar_get(struct spu *spu)
80{
81 u64 dar;
82 beat_get_spe_privileged_state_1_registers(
83 spu->spe_id,
84 offsetof(struct spu_priv1, mfc_dar_RW), &dar);
85 return dar;
86}
87
88static u64 mfc_dsisr_get(struct spu *spu)
89{
90 u64 dsisr;
91 beat_get_spe_privileged_state_1_registers(
92 spu->spe_id,
93 offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
94 return dsisr;
95}
96
97static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
98{
99 beat_set_spe_privileged_state_1_registers(
100 spu->spe_id,
101 offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
102}
103
104static void mfc_sdr_setup(struct spu *spu)
105{
106 return;
107}
108
109static void mfc_sr1_set(struct spu *spu, u64 sr1)
110{
111 beat_set_spe_privileged_state_1_registers(
112 spu->spe_id,
113 offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
114}
115
116static u64 mfc_sr1_get(struct spu *spu)
117{
118 u64 sr1;
119 beat_get_spe_privileged_state_1_registers(
120 spu->spe_id,
121 offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
122 return sr1;
123}
124
125static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
126{
127 beat_set_spe_privileged_state_1_registers(
128 spu->spe_id,
129 offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
130}
131
132static u64 mfc_tclass_id_get(struct spu *spu)
133{
134 u64 tclass_id;
135 beat_get_spe_privileged_state_1_registers(
136 spu->spe_id,
137 offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
138 return tclass_id;
139}
140
141static void tlb_invalidate(struct spu *spu)
142{
143 beat_set_spe_privileged_state_1_registers(
144 spu->spe_id,
145 offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
146}
147
148static void resource_allocation_groupID_set(struct spu *spu, u64 id)
149{
150 beat_set_spe_privileged_state_1_registers(
151 spu->spe_id,
152 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
153 id);
154}
155
156static u64 resource_allocation_groupID_get(struct spu *spu)
157{
158 u64 id;
159 beat_get_spe_privileged_state_1_registers(
160 spu->spe_id,
161 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
162 &id);
163 return id;
164}
165
166static void resource_allocation_enable_set(struct spu *spu, u64 enable)
167{
168 beat_set_spe_privileged_state_1_registers(
169 spu->spe_id,
170 offsetof(struct spu_priv1, resource_allocation_enable_RW),
171 enable);
172}
173
174static u64 resource_allocation_enable_get(struct spu *spu)
175{
176 u64 enable;
177 beat_get_spe_privileged_state_1_registers(
178 spu->spe_id,
179 offsetof(struct spu_priv1, resource_allocation_enable_RW),
180 &enable);
181 return enable;
182}
183
184const struct spu_priv1_ops spu_priv1_beat_ops = {
185 .int_mask_and = int_mask_and,
186 .int_mask_or = int_mask_or,
187 .int_mask_set = int_mask_set,
188 .int_mask_get = int_mask_get,
189 .int_stat_clear = int_stat_clear,
190 .int_stat_get = int_stat_get,
191 .cpu_affinity_set = cpu_affinity_set,
192 .mfc_dar_get = mfc_dar_get,
193 .mfc_dsisr_get = mfc_dsisr_get,
194 .mfc_dsisr_set = mfc_dsisr_set,
195 .mfc_sdr_setup = mfc_sdr_setup,
196 .mfc_sr1_set = mfc_sr1_set,
197 .mfc_sr1_get = mfc_sr1_get,
198 .mfc_tclass_id_set = mfc_tclass_id_set,
199 .mfc_tclass_id_get = mfc_tclass_id_get,
200 .tlb_invalidate = tlb_invalidate,
201 .resource_allocation_groupID_set = resource_allocation_groupID_set,
202 .resource_allocation_groupID_get = resource_allocation_groupID_get,
203 .resource_allocation_enable_set = resource_allocation_enable_set,
204 .resource_allocation_enable_get = resource_allocation_enable_get,
205};
diff --git a/arch/powerpc/platforms/cell/beat_syscall.h b/arch/powerpc/platforms/cell/beat_syscall.h
deleted file mode 100644
index 8580dc7e1798..000000000000
--- a/arch/powerpc/platforms/cell/beat_syscall.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Beat hypervisor call numbers
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef BEAT_BEAT_syscall_H
22#define BEAT_BEAT_syscall_H
23
24#ifdef __ASSEMBLY__
25#define __BEAT_ADD_VENDOR_ID(__x, __v) ((__v)<<60|(__x))
26#else
27#define __BEAT_ADD_VENDOR_ID(__x, __v) ((u64)(__v)<<60|(__x))
28#endif
29#define HV_allocate_memory __BEAT_ADD_VENDOR_ID(0, 0)
30#define HV_construct_virtual_address_space __BEAT_ADD_VENDOR_ID(2, 0)
31#define HV_destruct_virtual_address_space __BEAT_ADD_VENDOR_ID(10, 0)
32#define HV_get_virtual_address_space_id_of_ppe __BEAT_ADD_VENDOR_ID(4, 0)
33#define HV_query_logical_partition_address_region_info \
34 __BEAT_ADD_VENDOR_ID(6, 0)
35#define HV_release_memory __BEAT_ADD_VENDOR_ID(13, 0)
36#define HV_select_virtual_address_space __BEAT_ADD_VENDOR_ID(7, 0)
37#define HV_load_range_registers __BEAT_ADD_VENDOR_ID(68, 0)
38#define HV_set_ppe_l2cache_rmt_entry __BEAT_ADD_VENDOR_ID(70, 0)
39#define HV_set_ppe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(71, 0)
40#define HV_set_spe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(72, 0)
41#define HV_get_io_address_translation_fault_info __BEAT_ADD_VENDOR_ID(14, 0)
42#define HV_get_iopte __BEAT_ADD_VENDOR_ID(16, 0)
43#define HV_preload_iopt_cache __BEAT_ADD_VENDOR_ID(17, 0)
44#define HV_put_iopte __BEAT_ADD_VENDOR_ID(15, 0)
45#define HV_connect_event_ports __BEAT_ADD_VENDOR_ID(21, 0)
46#define HV_construct_event_receive_port __BEAT_ADD_VENDOR_ID(18, 0)
47#define HV_destruct_event_receive_port __BEAT_ADD_VENDOR_ID(19, 0)
48#define HV_destruct_event_send_port __BEAT_ADD_VENDOR_ID(22, 0)
49#define HV_get_state_of_event_send_port __BEAT_ADD_VENDOR_ID(25, 0)
50#define HV_request_to_connect_event_ports __BEAT_ADD_VENDOR_ID(20, 0)
51#define HV_send_event_externally __BEAT_ADD_VENDOR_ID(23, 0)
52#define HV_send_event_locally __BEAT_ADD_VENDOR_ID(24, 0)
53#define HV_construct_and_connect_irq_plug __BEAT_ADD_VENDOR_ID(28, 0)
54#define HV_destruct_irq_plug __BEAT_ADD_VENDOR_ID(29, 0)
55#define HV_detect_pending_interrupts __BEAT_ADD_VENDOR_ID(26, 0)
56#define HV_end_of_interrupt __BEAT_ADD_VENDOR_ID(27, 0)
57#define HV_assign_control_signal_notification_port __BEAT_ADD_VENDOR_ID(45, 0)
58#define HV_end_of_control_signal_processing __BEAT_ADD_VENDOR_ID(48, 0)
59#define HV_get_control_signal __BEAT_ADD_VENDOR_ID(46, 0)
60#define HV_set_irq_mask_for_spe __BEAT_ADD_VENDOR_ID(61, 0)
61#define HV_shutdown_logical_partition __BEAT_ADD_VENDOR_ID(44, 0)
62#define HV_connect_message_ports __BEAT_ADD_VENDOR_ID(35, 0)
63#define HV_destruct_message_port __BEAT_ADD_VENDOR_ID(36, 0)
64#define HV_receive_message __BEAT_ADD_VENDOR_ID(37, 0)
65#define HV_get_message_port_info __BEAT_ADD_VENDOR_ID(34, 0)
66#define HV_request_to_connect_message_ports __BEAT_ADD_VENDOR_ID(33, 0)
67#define HV_send_message __BEAT_ADD_VENDOR_ID(32, 0)
68#define HV_get_logical_ppe_id __BEAT_ADD_VENDOR_ID(69, 0)
69#define HV_pause __BEAT_ADD_VENDOR_ID(9, 0)
70#define HV_destruct_shared_memory_handle __BEAT_ADD_VENDOR_ID(51, 0)
71#define HV_get_shared_memory_info __BEAT_ADD_VENDOR_ID(52, 0)
72#define HV_permit_sharing_memory __BEAT_ADD_VENDOR_ID(50, 0)
73#define HV_request_to_attach_shared_memory __BEAT_ADD_VENDOR_ID(49, 0)
74#define HV_enable_logical_spe_execution __BEAT_ADD_VENDOR_ID(55, 0)
75#define HV_construct_logical_spe __BEAT_ADD_VENDOR_ID(53, 0)
76#define HV_disable_logical_spe_execution __BEAT_ADD_VENDOR_ID(56, 0)
77#define HV_destruct_logical_spe __BEAT_ADD_VENDOR_ID(54, 0)
78#define HV_sense_spe_execution_status __BEAT_ADD_VENDOR_ID(58, 0)
79#define HV_insert_htab_entry __BEAT_ADD_VENDOR_ID(101, 0)
80#define HV_read_htab_entries __BEAT_ADD_VENDOR_ID(95, 0)
81#define HV_write_htab_entry __BEAT_ADD_VENDOR_ID(94, 0)
82#define HV_assign_io_address_translation_fault_port \
83 __BEAT_ADD_VENDOR_ID(100, 0)
84#define HV_set_interrupt_mask __BEAT_ADD_VENDOR_ID(73, 0)
85#define HV_get_logical_partition_id __BEAT_ADD_VENDOR_ID(74, 0)
86#define HV_create_repository_node2 __BEAT_ADD_VENDOR_ID(90, 0)
87#define HV_create_repository_node __BEAT_ADD_VENDOR_ID(90, 0) /* alias */
88#define HV_get_repository_node_value2 __BEAT_ADD_VENDOR_ID(91, 0)
89#define HV_get_repository_node_value __BEAT_ADD_VENDOR_ID(91, 0) /* alias */
90#define HV_modify_repository_node_value2 __BEAT_ADD_VENDOR_ID(92, 0)
91#define HV_modify_repository_node_value __BEAT_ADD_VENDOR_ID(92, 0) /* alias */
92#define HV_remove_repository_node2 __BEAT_ADD_VENDOR_ID(93, 0)
93#define HV_remove_repository_node __BEAT_ADD_VENDOR_ID(93, 0) /* alias */
94#define HV_cancel_shared_memory __BEAT_ADD_VENDOR_ID(104, 0)
95#define HV_clear_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(206, 0)
96#define HV_construct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(80, 0)
97#define HV_destruct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(81, 0)
98#define HV_disconnect_ipspc_service __BEAT_ADD_VENDOR_ID(88, 0)
99#define HV_execute_ipspc_command __BEAT_ADD_VENDOR_ID(86, 0)
100#define HV_get_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(205, 0)
101#define HV_get_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(208, 0)
102#define HV_permit_use_of_ipspc_service __BEAT_ADD_VENDOR_ID(85, 0)
103#define HV_reinitialize_logical_spe __BEAT_ADD_VENDOR_ID(82, 0)
104#define HV_request_ipspc_service __BEAT_ADD_VENDOR_ID(84, 0)
105#define HV_stop_ipspc_command __BEAT_ADD_VENDOR_ID(87, 0)
106#define HV_set_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(204, 0)
107#define HV_get_status_of_ipspc_service __BEAT_ADD_VENDOR_ID(203, 0)
108#define HV_put_characters_to_console __BEAT_ADD_VENDOR_ID(0x101, 1)
109#define HV_get_characters_from_console __BEAT_ADD_VENDOR_ID(0x102, 1)
110#define HV_get_base_clock __BEAT_ADD_VENDOR_ID(0x111, 1)
111#define HV_set_base_clock __BEAT_ADD_VENDOR_ID(0x112, 1)
112#define HV_get_frame_cycle __BEAT_ADD_VENDOR_ID(0x114, 1)
113#define HV_disable_console __BEAT_ADD_VENDOR_ID(0x115, 1)
114#define HV_disable_all_console __BEAT_ADD_VENDOR_ID(0x116, 1)
115#define HV_oneshot_timer __BEAT_ADD_VENDOR_ID(0x117, 1)
116#define HV_set_dabr __BEAT_ADD_VENDOR_ID(0x118, 1)
117#define HV_get_dabr __BEAT_ADD_VENDOR_ID(0x119, 1)
118#define HV_start_hv_stats __BEAT_ADD_VENDOR_ID(0x21c, 1)
119#define HV_stop_hv_stats __BEAT_ADD_VENDOR_ID(0x21d, 1)
120#define HV_get_hv_stats __BEAT_ADD_VENDOR_ID(0x21e, 1)
121#define HV_get_hv_error_stats __BEAT_ADD_VENDOR_ID(0x221, 1)
122#define HV_get_stats __BEAT_ADD_VENDOR_ID(0x224, 1)
123#define HV_get_heap_stats __BEAT_ADD_VENDOR_ID(0x225, 1)
124#define HV_get_memory_stats __BEAT_ADD_VENDOR_ID(0x227, 1)
125#define HV_get_memory_detail __BEAT_ADD_VENDOR_ID(0x228, 1)
126#define HV_set_priority_of_irq_outlet __BEAT_ADD_VENDOR_ID(0x122, 1)
127#define HV_get_physical_spe_by_reservation_id __BEAT_ADD_VENDOR_ID(0x128, 1)
128#define HV_get_spe_context __BEAT_ADD_VENDOR_ID(0x129, 1)
129#define HV_set_spe_context __BEAT_ADD_VENDOR_ID(0x12a, 1)
130#define HV_downcount_of_interrupt __BEAT_ADD_VENDOR_ID(0x12e, 1)
131#define HV_peek_spe_context __BEAT_ADD_VENDOR_ID(0x12f, 1)
132#define HV_read_bpa_register __BEAT_ADD_VENDOR_ID(0x131, 1)
133#define HV_write_bpa_register __BEAT_ADD_VENDOR_ID(0x132, 1)
134#define HV_map_context_table_of_spe __BEAT_ADD_VENDOR_ID(0x137, 1)
135#define HV_get_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x138, 1)
136#define HV_set_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x139, 1)
137#define HV_init_pm __BEAT_ADD_VENDOR_ID(0x150, 1)
138#define HV_set_pm_signal __BEAT_ADD_VENDOR_ID(0x151, 1)
139#define HV_get_pm_signal __BEAT_ADD_VENDOR_ID(0x152, 1)
140#define HV_set_pm_config __BEAT_ADD_VENDOR_ID(0x153, 1)
141#define HV_get_pm_config __BEAT_ADD_VENDOR_ID(0x154, 1)
142#define HV_get_inner_trace_data __BEAT_ADD_VENDOR_ID(0x155, 1)
143#define HV_set_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x156, 1)
144#define HV_get_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x157, 1)
145#define HV_set_pm_interrupt __BEAT_ADD_VENDOR_ID(0x158, 1)
146#define HV_get_pm_interrupt __BEAT_ADD_VENDOR_ID(0x159, 1)
147#define HV_kick_pm __BEAT_ADD_VENDOR_ID(0x160, 1)
148#define HV_construct_pm_context __BEAT_ADD_VENDOR_ID(0x164, 1)
149#define HV_destruct_pm_context __BEAT_ADD_VENDOR_ID(0x165, 1)
150#define HV_be_slow __BEAT_ADD_VENDOR_ID(0x170, 1)
151#define HV_assign_ipspc_server_connection_status_notification_port \
152 __BEAT_ADD_VENDOR_ID(0x173, 1)
153#define HV_get_raid_of_physical_spe __BEAT_ADD_VENDOR_ID(0x174, 1)
154#define HV_set_physical_spe_to_rag __BEAT_ADD_VENDOR_ID(0x175, 1)
155#define HV_release_physical_spe_from_rag __BEAT_ADD_VENDOR_ID(0x176, 1)
156#define HV_rtc_read __BEAT_ADD_VENDOR_ID(0x190, 1)
157#define HV_rtc_write __BEAT_ADD_VENDOR_ID(0x191, 1)
158#define HV_eeprom_read __BEAT_ADD_VENDOR_ID(0x192, 1)
159#define HV_eeprom_write __BEAT_ADD_VENDOR_ID(0x193, 1)
160#define HV_insert_htab_entry3 __BEAT_ADD_VENDOR_ID(0x104, 1)
161#define HV_invalidate_htab_entry3 __BEAT_ADD_VENDOR_ID(0x105, 1)
162#define HV_update_htab_permission3 __BEAT_ADD_VENDOR_ID(0x106, 1)
163#define HV_clear_htab3 __BEAT_ADD_VENDOR_ID(0x107, 1)
164#endif
diff --git a/arch/powerpc/platforms/cell/beat_udbg.c b/arch/powerpc/platforms/cell/beat_udbg.c
deleted file mode 100644
index 350735bc8888..000000000000
--- a/arch/powerpc/platforms/cell/beat_udbg.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * udbg function for Beat
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/console.h>
23
24#include <asm/machdep.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27
28#include "beat.h"
29
30#define celleb_vtermno 0
31
32static void udbg_putc_beat(char c)
33{
34 unsigned long rc;
35
36 if (c == '\n')
37 udbg_putc_beat('\r');
38
39 rc = beat_put_term_char(celleb_vtermno, 1, (uint64_t)c << 56, 0);
40}
41
42/* Buffered chars getc */
43static u64 inbuflen;
44static u64 inbuf[2]; /* must be 2 u64s */
45
46static int udbg_getc_poll_beat(void)
47{
48 /* The interface is tricky because it may return up to 16 chars.
49 * We save them statically for future calls to udbg_getc().
50 */
51 char ch, *buf = (char *)inbuf;
52 int i;
53 long rc;
54 if (inbuflen == 0) {
55 /* get some more chars. */
56 inbuflen = 0;
57 rc = beat_get_term_char(celleb_vtermno, &inbuflen,
58 inbuf+0, inbuf+1);
59 if (rc != 0)
60 inbuflen = 0; /* otherwise inbuflen is garbage */
61 }
62 if (inbuflen <= 0 || inbuflen > 16) {
63 /* Catch error case as well as other oddities (corruption) */
64 inbuflen = 0;
65 return -1;
66 }
67 ch = buf[0];
68 for (i = 1; i < inbuflen; i++) /* shuffle them down. */
69 buf[i-1] = buf[i];
70 inbuflen--;
71 return ch;
72}
73
74static int udbg_getc_beat(void)
75{
76 int ch;
77 for (;;) {
78 ch = udbg_getc_poll_beat();
79 if (ch == -1) {
80 /* This shouldn't be needed...but... */
81 volatile unsigned long delay;
82 for (delay = 0; delay < 2000000; delay++)
83 ;
84 } else {
85 return ch;
86 }
87 }
88}
89
90/* call this from early_init() for a working debug console on
91 * vterm capable LPAR machines
92 */
93void __init udbg_init_debug_beat(void)
94{
95 udbg_putc = udbg_putc_beat;
96 udbg_getc = udbg_getc_beat;
97 udbg_getc_poll = udbg_getc_poll_beat;
98}
diff --git a/arch/powerpc/platforms/cell/beat_wrapper.h b/arch/powerpc/platforms/cell/beat_wrapper.h
deleted file mode 100644
index c1109969f242..000000000000
--- a/arch/powerpc/platforms/cell/beat_wrapper.h
+++ /dev/null
@@ -1,290 +0,0 @@
1/*
2 * Beat hypervisor call I/F
3 *
4 * (C) Copyright 2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/plpar_wrapper.h.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22#ifndef BEAT_HCALL
23#include <linux/string.h>
24#include "beat_syscall.h"
25
26/* defined in hvCall.S */
27extern s64 beat_hcall_norets(u64 opcode, ...);
28extern s64 beat_hcall_norets8(u64 opcode, u64 arg1, u64 arg2, u64 arg3,
29 u64 arg4, u64 arg5, u64 arg6, u64 arg7, u64 arg8);
30extern s64 beat_hcall1(u64 opcode, u64 retbuf[1], ...);
31extern s64 beat_hcall2(u64 opcode, u64 retbuf[2], ...);
32extern s64 beat_hcall3(u64 opcode, u64 retbuf[3], ...);
33extern s64 beat_hcall4(u64 opcode, u64 retbuf[4], ...);
34extern s64 beat_hcall5(u64 opcode, u64 retbuf[5], ...);
35extern s64 beat_hcall6(u64 opcode, u64 retbuf[6], ...);
36
37static inline s64 beat_downcount_of_interrupt(u64 plug_id)
38{
39 return beat_hcall_norets(HV_downcount_of_interrupt, plug_id);
40}
41
42static inline s64 beat_set_interrupt_mask(u64 index,
43 u64 val0, u64 val1, u64 val2, u64 val3)
44{
45 return beat_hcall_norets(HV_set_interrupt_mask, index,
46 val0, val1, val2, val3);
47}
48
49static inline s64 beat_destruct_irq_plug(u64 plug_id)
50{
51 return beat_hcall_norets(HV_destruct_irq_plug, plug_id);
52}
53
54static inline s64 beat_construct_and_connect_irq_plug(u64 plug_id,
55 u64 outlet_id)
56{
57 return beat_hcall_norets(HV_construct_and_connect_irq_plug, plug_id,
58 outlet_id);
59}
60
61static inline s64 beat_detect_pending_interrupts(u64 index, u64 *retbuf)
62{
63 return beat_hcall4(HV_detect_pending_interrupts, retbuf, index);
64}
65
66static inline s64 beat_pause(u64 style)
67{
68 return beat_hcall_norets(HV_pause, style);
69}
70
71static inline s64 beat_read_htab_entries(u64 htab_id, u64 index, u64 *retbuf)
72{
73 return beat_hcall5(HV_read_htab_entries, retbuf, htab_id, index);
74}
75
76static inline s64 beat_insert_htab_entry(u64 htab_id, u64 group,
77 u64 bitmask, u64 hpte_v, u64 hpte_r, u64 *slot)
78{
79 u64 dummy[3];
80 s64 ret;
81
82 ret = beat_hcall3(HV_insert_htab_entry, dummy, htab_id, group,
83 bitmask, hpte_v, hpte_r);
84 *slot = dummy[0];
85 return ret;
86}
87
88static inline s64 beat_write_htab_entry(u64 htab_id, u64 slot,
89 u64 hpte_v, u64 hpte_r, u64 mask_v, u64 mask_r,
90 u64 *ret_v, u64 *ret_r)
91{
92 u64 dummy[2];
93 s64 ret;
94
95 ret = beat_hcall2(HV_write_htab_entry, dummy, htab_id, slot,
96 hpte_v, hpte_r, mask_v, mask_r);
97 *ret_v = dummy[0];
98 *ret_r = dummy[1];
99 return ret;
100}
101
102static inline s64 beat_insert_htab_entry3(u64 htab_id, u64 group,
103 u64 hpte_v, u64 hpte_r, u64 mask_v, u64 value_v, u64 *slot)
104{
105 u64 dummy[1];
106 s64 ret;
107
108 ret = beat_hcall1(HV_insert_htab_entry3, dummy, htab_id, group,
109 hpte_v, hpte_r, mask_v, value_v);
110 *slot = dummy[0];
111 return ret;
112}
113
114static inline s64 beat_invalidate_htab_entry3(u64 htab_id, u64 group,
115 u64 va, u64 pss)
116{
117 return beat_hcall_norets(HV_invalidate_htab_entry3,
118 htab_id, group, va, pss);
119}
120
121static inline s64 beat_update_htab_permission3(u64 htab_id, u64 group,
122 u64 va, u64 pss, u64 ptel_mask, u64 ptel_value)
123{
124 return beat_hcall_norets(HV_update_htab_permission3,
125 htab_id, group, va, pss, ptel_mask, ptel_value);
126}
127
128static inline s64 beat_clear_htab3(u64 htab_id)
129{
130 return beat_hcall_norets(HV_clear_htab3, htab_id);
131}
132
133static inline void beat_shutdown_logical_partition(u64 code)
134{
135 (void)beat_hcall_norets(HV_shutdown_logical_partition, code);
136}
137
138static inline s64 beat_rtc_write(u64 time_from_epoch)
139{
140 return beat_hcall_norets(HV_rtc_write, time_from_epoch);
141}
142
143static inline s64 beat_rtc_read(u64 *time_from_epoch)
144{
145 u64 dummy[1];
146 s64 ret;
147
148 ret = beat_hcall1(HV_rtc_read, dummy);
149 *time_from_epoch = dummy[0];
150 return ret;
151}
152
153#define BEAT_NVRW_CNT (sizeof(u64) * 6)
154
155static inline s64 beat_eeprom_write(u64 index, u64 length, u8 *buffer)
156{
157 u64 b[6];
158
159 if (length > BEAT_NVRW_CNT)
160 return -1;
161 memcpy(b, buffer, sizeof(b));
162 return beat_hcall_norets8(HV_eeprom_write, index, length,
163 b[0], b[1], b[2], b[3], b[4], b[5]);
164}
165
166static inline s64 beat_eeprom_read(u64 index, u64 length, u8 *buffer)
167{
168 u64 b[6];
169 s64 ret;
170
171 if (length > BEAT_NVRW_CNT)
172 return -1;
173 ret = beat_hcall6(HV_eeprom_read, b, index, length);
174 memcpy(buffer, b, length);
175 return ret;
176}
177
178static inline s64 beat_set_dabr(u64 value, u64 style)
179{
180 return beat_hcall_norets(HV_set_dabr, value, style);
181}
182
183static inline s64 beat_get_characters_from_console(u64 termno, u64 *len,
184 u8 *buffer)
185{
186 u64 dummy[3];
187 s64 ret;
188
189 ret = beat_hcall3(HV_get_characters_from_console, dummy, termno, len);
190 *len = dummy[0];
191 memcpy(buffer, dummy + 1, *len);
192 return ret;
193}
194
195static inline s64 beat_put_characters_to_console(u64 termno, u64 len,
196 u8 *buffer)
197{
198 u64 b[2];
199
200 memcpy(b, buffer, len);
201 return beat_hcall_norets(HV_put_characters_to_console, termno, len,
202 b[0], b[1]);
203}
204
205static inline s64 beat_get_spe_privileged_state_1_registers(
206 u64 id, u64 offsetof, u64 *value)
207{
208 u64 dummy[1];
209 s64 ret;
210
211 ret = beat_hcall1(HV_get_spe_privileged_state_1_registers, dummy, id,
212 offsetof);
213 *value = dummy[0];
214 return ret;
215}
216
217static inline s64 beat_set_irq_mask_for_spe(u64 id, u64 class, u64 mask)
218{
219 return beat_hcall_norets(HV_set_irq_mask_for_spe, id, class, mask);
220}
221
222static inline s64 beat_clear_interrupt_status_of_spe(u64 id, u64 class,
223 u64 mask)
224{
225 return beat_hcall_norets(HV_clear_interrupt_status_of_spe,
226 id, class, mask);
227}
228
229static inline s64 beat_set_spe_privileged_state_1_registers(
230 u64 id, u64 offsetof, u64 value)
231{
232 return beat_hcall_norets(HV_set_spe_privileged_state_1_registers,
233 id, offsetof, value);
234}
235
236static inline s64 beat_get_interrupt_status_of_spe(u64 id, u64 class, u64 *val)
237{
238 u64 dummy[1];
239 s64 ret;
240
241 ret = beat_hcall1(HV_get_interrupt_status_of_spe, dummy, id, class);
242 *val = dummy[0];
243 return ret;
244}
245
246static inline s64 beat_put_iopte(u64 ioas_id, u64 io_addr, u64 real_addr,
247 u64 ioid, u64 flags)
248{
249 return beat_hcall_norets(HV_put_iopte, ioas_id, io_addr, real_addr,
250 ioid, flags);
251}
252
253static inline s64 beat_construct_event_receive_port(u64 *port)
254{
255 u64 dummy[1];
256 s64 ret;
257
258 ret = beat_hcall1(HV_construct_event_receive_port, dummy);
259 *port = dummy[0];
260 return ret;
261}
262
263static inline s64 beat_destruct_event_receive_port(u64 port)
264{
265 s64 ret;
266
267 ret = beat_hcall_norets(HV_destruct_event_receive_port, port);
268 return ret;
269}
270
271static inline s64 beat_create_repository_node(u64 path[4], u64 data[2])
272{
273 s64 ret;
274
275 ret = beat_hcall_norets(HV_create_repository_node2,
276 path[0], path[1], path[2], path[3], data[0], data[1]);
277 return ret;
278}
279
280static inline s64 beat_get_repository_node_value(u64 lpid, u64 path[4],
281 u64 data[2])
282{
283 s64 ret;
284
285 ret = beat_hcall2(HV_get_repository_node_value2, data,
286 lpid, path[0], path[1], path[2], path[3]);
287 return ret;
288}
289
290#endif
diff --git a/arch/powerpc/platforms/cell/celleb_pci.c b/arch/powerpc/platforms/cell/celleb_pci.c
deleted file mode 100644
index 9b11b5dd8b7c..000000000000
--- a/arch/powerpc/platforms/cell/celleb_pci.c
+++ /dev/null
@@ -1,499 +0,0 @@
1/*
2 * Support for PCI on Celleb platform.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/kernel/rtas_pci.c:
7 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#undef DEBUG
26
27#include <linux/kernel.h>
28#include <linux/threads.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31#include <linux/init.h>
32#include <linux/memblock.h>
33#include <linux/pci_regs.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/slab.h>
37
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/prom.h>
41#include <asm/pci-bridge.h>
42#include <asm/ppc-pci.h>
43
44#include "celleb_pci.h"
45
46#define MAX_PCI_DEVICES 32
47#define MAX_PCI_FUNCTIONS 8
48#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
49
50/* definition for fake pci configuration area for GbE, .... ,and etc. */
51
52struct celleb_pci_resource {
53 struct resource r[MAX_PCI_BASE_ADDRS];
54};
55
56struct celleb_pci_private {
57 unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
58 struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
59};
60
61static inline u8 celleb_fake_config_readb(void *addr)
62{
63 u8 *p = addr;
64 return *p;
65}
66
67static inline u16 celleb_fake_config_readw(void *addr)
68{
69 __le16 *p = addr;
70 return le16_to_cpu(*p);
71}
72
73static inline u32 celleb_fake_config_readl(void *addr)
74{
75 __le32 *p = addr;
76 return le32_to_cpu(*p);
77}
78
79static inline void celleb_fake_config_writeb(u32 val, void *addr)
80{
81 u8 *p = addr;
82 *p = val;
83}
84
85static inline void celleb_fake_config_writew(u32 val, void *addr)
86{
87 __le16 val16;
88 __le16 *p = addr;
89 val16 = cpu_to_le16(val);
90 *p = val16;
91}
92
93static inline void celleb_fake_config_writel(u32 val, void *addr)
94{
95 __le32 val32;
96 __le32 *p = addr;
97 val32 = cpu_to_le32(val);
98 *p = val32;
99}
100
101static unsigned char *get_fake_config_start(struct pci_controller *hose,
102 int devno, int fn)
103{
104 struct celleb_pci_private *private = hose->private_data;
105
106 if (private == NULL)
107 return NULL;
108
109 return private->fake_config[devno][fn];
110}
111
112static struct celleb_pci_resource *get_resource_start(
113 struct pci_controller *hose,
114 int devno, int fn)
115{
116 struct celleb_pci_private *private = hose->private_data;
117
118 if (private == NULL)
119 return NULL;
120
121 return private->res[devno][fn];
122}
123
124
125static void celleb_config_read_fake(unsigned char *config, int where,
126 int size, u32 *val)
127{
128 char *p = config + where;
129
130 switch (size) {
131 case 1:
132 *val = celleb_fake_config_readb(p);
133 break;
134 case 2:
135 *val = celleb_fake_config_readw(p);
136 break;
137 case 4:
138 *val = celleb_fake_config_readl(p);
139 break;
140 }
141}
142
143static void celleb_config_write_fake(unsigned char *config, int where,
144 int size, u32 val)
145{
146 char *p = config + where;
147
148 switch (size) {
149 case 1:
150 celleb_fake_config_writeb(val, p);
151 break;
152 case 2:
153 celleb_fake_config_writew(val, p);
154 break;
155 case 4:
156 celleb_fake_config_writel(val, p);
157 break;
158 }
159}
160
161static int celleb_fake_pci_read_config(struct pci_bus *bus,
162 unsigned int devfn, int where, int size, u32 *val)
163{
164 char *config;
165 struct pci_controller *hose = pci_bus_to_host(bus);
166 unsigned int devno = devfn >> 3;
167 unsigned int fn = devfn & 0x7;
168
169 /* allignment check */
170 BUG_ON(where % size);
171
172 pr_debug(" fake read: bus=0x%x, ", bus->number);
173 config = get_fake_config_start(hose, devno, fn);
174
175 pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
176 if (!config) {
177 pr_debug("failed\n");
178 return PCIBIOS_DEVICE_NOT_FOUND;
179 }
180
181 celleb_config_read_fake(config, where, size, val);
182 pr_debug("val=0x%x\n", *val);
183
184 return PCIBIOS_SUCCESSFUL;
185}
186
187
188static int celleb_fake_pci_write_config(struct pci_bus *bus,
189 unsigned int devfn, int where, int size, u32 val)
190{
191 char *config;
192 struct pci_controller *hose = pci_bus_to_host(bus);
193 struct celleb_pci_resource *res;
194 unsigned int devno = devfn >> 3;
195 unsigned int fn = devfn & 0x7;
196
197 /* allignment check */
198 BUG_ON(where % size);
199
200 config = get_fake_config_start(hose, devno, fn);
201
202 if (!config)
203 return PCIBIOS_DEVICE_NOT_FOUND;
204
205 if (val == ~0) {
206 int i = (where - PCI_BASE_ADDRESS_0) >> 3;
207
208 switch (where) {
209 case PCI_BASE_ADDRESS_0:
210 case PCI_BASE_ADDRESS_2:
211 if (size != 4)
212 return PCIBIOS_DEVICE_NOT_FOUND;
213 res = get_resource_start(hose, devno, fn);
214 if (!res)
215 return PCIBIOS_DEVICE_NOT_FOUND;
216 celleb_config_write_fake(config, where, size,
217 (res->r[i].end - res->r[i].start));
218 return PCIBIOS_SUCCESSFUL;
219 case PCI_BASE_ADDRESS_1:
220 case PCI_BASE_ADDRESS_3:
221 case PCI_BASE_ADDRESS_4:
222 case PCI_BASE_ADDRESS_5:
223 break;
224 default:
225 break;
226 }
227 }
228
229 celleb_config_write_fake(config, where, size, val);
230 pr_debug(" fake write: where=%x, size=%d, val=%x\n",
231 where, size, val);
232
233 return PCIBIOS_SUCCESSFUL;
234}
235
236static struct pci_ops celleb_fake_pci_ops = {
237 .read = celleb_fake_pci_read_config,
238 .write = celleb_fake_pci_write_config,
239};
240
241static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
242 unsigned int devno, unsigned int fn,
243 unsigned int num_base_addr)
244{
245 u32 val;
246 unsigned char *config;
247 struct celleb_pci_resource *res;
248
249 config = get_fake_config_start(hose, devno, fn);
250 res = get_resource_start(hose, devno, fn);
251
252 if (!config || !res)
253 return;
254
255 switch (num_base_addr) {
256 case 3:
257 val = (res->r[2].start & 0xfffffff0)
258 | PCI_BASE_ADDRESS_MEM_TYPE_64;
259 celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
260 val = res->r[2].start >> 32;
261 celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
262 /* FALLTHROUGH */
263 case 2:
264 val = (res->r[1].start & 0xfffffff0)
265 | PCI_BASE_ADDRESS_MEM_TYPE_64;
266 celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
267 val = res->r[1].start >> 32;
268 celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
269 /* FALLTHROUGH */
270 case 1:
271 val = (res->r[0].start & 0xfffffff0)
272 | PCI_BASE_ADDRESS_MEM_TYPE_64;
273 celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
274 val = res->r[0].start >> 32;
275 celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
276 break;
277 }
278
279 val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
280 celleb_config_write_fake(config, PCI_COMMAND, 2, val);
281}
282
283static int __init celleb_setup_fake_pci_device(struct device_node *node,
284 struct pci_controller *hose)
285{
286 unsigned int rlen;
287 int num_base_addr = 0;
288 u32 val;
289 const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
290 unsigned int devno, fn;
291 struct celleb_pci_private *private = hose->private_data;
292 unsigned char **config = NULL;
293 struct celleb_pci_resource **res = NULL;
294 const char *name;
295 const unsigned long *li;
296 int size, result;
297
298 if (private == NULL) {
299 printk(KERN_ERR "PCI: "
300 "memory space for pci controller is not assigned\n");
301 goto error;
302 }
303
304 name = of_get_property(node, "model", &rlen);
305 if (!name) {
306 printk(KERN_ERR "PCI: model property not found.\n");
307 goto error;
308 }
309
310 wi4 = of_get_property(node, "reg", &rlen);
311 if (wi4 == NULL)
312 goto error;
313
314 devno = ((wi4[0] >> 8) & 0xff) >> 3;
315 fn = (wi4[0] >> 8) & 0x7;
316
317 pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
318 devno, fn);
319
320 size = 256;
321 config = &private->fake_config[devno][fn];
322 *config = zalloc_maybe_bootmem(size, GFP_KERNEL);
323 if (*config == NULL) {
324 printk(KERN_ERR "PCI: "
325 "not enough memory for fake configuration space\n");
326 goto error;
327 }
328 pr_debug("PCI: fake config area assigned 0x%016lx\n",
329 (unsigned long)*config);
330
331 size = sizeof(struct celleb_pci_resource);
332 res = &private->res[devno][fn];
333 *res = zalloc_maybe_bootmem(size, GFP_KERNEL);
334 if (*res == NULL) {
335 printk(KERN_ERR
336 "PCI: not enough memory for resource data space\n");
337 goto error;
338 }
339 pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
340
341 wi0 = of_get_property(node, "device-id", NULL);
342 wi1 = of_get_property(node, "vendor-id", NULL);
343 wi2 = of_get_property(node, "class-code", NULL);
344 wi3 = of_get_property(node, "revision-id", NULL);
345 if (!wi0 || !wi1 || !wi2 || !wi3) {
346 printk(KERN_ERR "PCI: Missing device tree properties.\n");
347 goto error;
348 }
349
350 celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
351 celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
352 pr_debug("class-code = 0x%08x\n", wi2[0]);
353
354 celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
355 celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
356 (wi2[0] >> 8) & 0xffff);
357 celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
358
359 while (num_base_addr < MAX_PCI_BASE_ADDRS) {
360 result = of_address_to_resource(node,
361 num_base_addr, &(*res)->r[num_base_addr]);
362 if (result)
363 break;
364 num_base_addr++;
365 }
366
367 celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
368
369 li = of_get_property(node, "interrupts", &rlen);
370 if (!li) {
371 printk(KERN_ERR "PCI: interrupts not found.\n");
372 goto error;
373 }
374 val = li[0];
375 celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
376 celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
377
378#ifdef DEBUG
379 pr_debug("PCI: %s irq=%ld\n", name, li[0]);
380 for (i = 0; i < 6; i++) {
381 celleb_config_read_fake(*config,
382 PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
383 &val);
384 pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
385 name, fn, i, val);
386 }
387#endif
388
389 celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
390 PCI_HEADER_TYPE_NORMAL);
391
392 return 0;
393
394error:
395 if (mem_init_done) {
396 if (config)
397 kfree(*config);
398 if (res)
399 kfree(*res);
400 } else {
401 if (config && *config) {
402 size = 256;
403 memblock_free(__pa(*config), size);
404 }
405 if (res && *res) {
406 size = sizeof(struct celleb_pci_resource);
407 memblock_free(__pa(*res), size);
408 }
409 }
410
411 return 1;
412}
413
414static int __init phb_set_bus_ranges(struct device_node *dev,
415 struct pci_controller *phb)
416{
417 const int *bus_range;
418 unsigned int len;
419
420 bus_range = of_get_property(dev, "bus-range", &len);
421 if (bus_range == NULL || len < 2 * sizeof(int))
422 return 1;
423
424 phb->first_busno = bus_range[0];
425 phb->last_busno = bus_range[1];
426
427 return 0;
428}
429
430static void __init celleb_alloc_private_mem(struct pci_controller *hose)
431{
432 hose->private_data =
433 zalloc_maybe_bootmem(sizeof(struct celleb_pci_private),
434 GFP_KERNEL);
435}
436
437static int __init celleb_setup_fake_pci(struct device_node *dev,
438 struct pci_controller *phb)
439{
440 struct device_node *node;
441
442 phb->ops = &celleb_fake_pci_ops;
443 celleb_alloc_private_mem(phb);
444
445 for (node = of_get_next_child(dev, NULL);
446 node != NULL; node = of_get_next_child(dev, node))
447 celleb_setup_fake_pci_device(node, phb);
448
449 return 0;
450}
451
452static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
453 .setup = celleb_setup_fake_pci,
454};
455
456static const struct of_device_id celleb_phb_match[] __initconst = {
457 {
458 .name = "pci-pseudo",
459 .data = &celleb_fake_pci_spec,
460 }, {
461 .name = "epci",
462 .data = &celleb_epci_spec,
463 }, {
464 .name = "pcie",
465 .data = &celleb_pciex_spec,
466 }, {
467 },
468};
469
470int __init celleb_setup_phb(struct pci_controller *phb)
471{
472 struct device_node *dev = phb->dn;
473 const struct of_device_id *match;
474 const struct celleb_phb_spec *phb_spec;
475 int rc;
476
477 match = of_match_node(celleb_phb_match, dev);
478 if (!match)
479 return 1;
480
481 phb_set_bus_ranges(dev, phb);
482 phb->buid = 1;
483
484 phb_spec = match->data;
485 rc = (*phb_spec->setup)(dev, phb);
486 if (rc)
487 return 1;
488
489 if (phb_spec->ops)
490 iowa_register_bus(phb, phb_spec->ops,
491 phb_spec->iowa_init,
492 phb_spec->iowa_data);
493 return 0;
494}
495
496int celleb_pci_probe_mode(struct pci_bus *bus)
497{
498 return PCI_PROBE_DEVTREE;
499}
diff --git a/arch/powerpc/platforms/cell/celleb_pci.h b/arch/powerpc/platforms/cell/celleb_pci.h
deleted file mode 100644
index a801fcc5f389..000000000000
--- a/arch/powerpc/platforms/cell/celleb_pci.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * pci prototypes for Celleb platform
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_PCI_H
22#define _CELLEB_PCI_H
23
24#include <linux/pci.h>
25
26#include <asm/pci-bridge.h>
27#include <asm/prom.h>
28#include <asm/ppc-pci.h>
29#include <asm/io-workarounds.h>
30
31struct iowa_bus;
32
33struct celleb_phb_spec {
34 int (*setup)(struct device_node *, struct pci_controller *);
35 struct ppc_pci_io *ops;
36 int (*iowa_init)(struct iowa_bus *, void *);
37 void *iowa_data;
38};
39
40extern int celleb_setup_phb(struct pci_controller *);
41extern int celleb_pci_probe_mode(struct pci_bus *);
42
43extern struct celleb_phb_spec celleb_epci_spec;
44extern struct celleb_phb_spec celleb_pciex_spec;
45
46#endif /* _CELLEB_PCI_H */
diff --git a/arch/powerpc/platforms/cell/celleb_scc.h b/arch/powerpc/platforms/cell/celleb_scc.h
deleted file mode 100644
index b596a711c348..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc.h
+++ /dev/null
@@ -1,232 +0,0 @@
1/*
2 * SCC (Super Companion Chip) definitions
3 *
4 * (C) Copyright 2004-2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_SCC_H
22#define _CELLEB_SCC_H
23
24#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
25#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
26#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
27#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
28#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
29#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
30#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
31#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
33
34#define SCC_EPCI_REG 0x0000d000
35
36/* EPCI registers */
37#define SCC_EPCI_CNF10_REG 0x010
38#define SCC_EPCI_CNF14_REG 0x014
39#define SCC_EPCI_CNF18_REG 0x018
40#define SCC_EPCI_PVBAT 0x100
41#define SCC_EPCI_VPMBAT 0x104
42#define SCC_EPCI_VPIBAT 0x108
43#define SCC_EPCI_VCSR 0x110
44#define SCC_EPCI_VIENAB 0x114
45#define SCC_EPCI_VISTAT 0x118
46#define SCC_EPCI_VRDCOUNT 0x124
47#define SCC_EPCI_BAM0 0x12c
48#define SCC_EPCI_BAM1 0x134
49#define SCC_EPCI_BAM2 0x13c
50#define SCC_EPCI_IADR 0x164
51#define SCC_EPCI_CLKRST 0x800
52#define SCC_EPCI_INTSET 0x804
53#define SCC_EPCI_STATUS 0x808
54#define SCC_EPCI_ABTSET 0x80c
55#define SCC_EPCI_WATRP 0x810
56#define SCC_EPCI_DUMYRADR 0x814
57#define SCC_EPCI_SWRESP 0x818
58#define SCC_EPCI_CNTOPT 0x81c
59#define SCC_EPCI_ECMODE 0xf00
60#define SCC_EPCI_IOM_AC_NUM 5
61#define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4)
62#define SCC_EPCI_IOT_AC_NUM 4
63#define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4)
64#define SCC_EPCI_MAEA 0xf50
65#define SCC_EPCI_MAEC 0xf54
66#define SCC_EPCI_CKCTRL 0xff0
67
68/* bits for SCC_EPCI_VCSR */
69#define SCC_EPCI_VCSR_FRE 0x00020000
70#define SCC_EPCI_VCSR_FWE 0x00010000
71#define SCC_EPCI_VCSR_DR 0x00000400
72#define SCC_EPCI_VCSR_SR 0x00000008
73#define SCC_EPCI_VCSR_AT 0x00000004
74
75/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */
76#define SCC_EPCI_VISTAT_PMPE 0x00000008
77#define SCC_EPCI_VISTAT_PMFE 0x00000004
78#define SCC_EPCI_VISTAT_PRA 0x00000002
79#define SCC_EPCI_VISTAT_PRD 0x00000001
80#define SCC_EPCI_VISTAT_ALL 0x0000000f
81
82#define SCC_EPCI_VIENAB_PMPEE 0x00000008
83#define SCC_EPCI_VIENAB_PMFEE 0x00000004
84#define SCC_EPCI_VIENAB_PRA 0x00000002
85#define SCC_EPCI_VIENAB_PRD 0x00000001
86#define SCC_EPCI_VIENAB_ALL 0x0000000f
87
88/* bits for SCC_EPCI_CLKRST */
89#define SCC_EPCI_CLKRST_CKS_MASK 0x00030000
90#define SCC_EPCI_CLKRST_CKS_2 0x00000000
91#define SCC_EPCI_CLKRST_CKS_4 0x00010000
92#define SCC_EPCI_CLKRST_CKS_8 0x00020000
93#define SCC_EPCI_CLKRST_PCICRST 0x00000400
94#define SCC_EPCI_CLKRST_BC 0x00000200
95#define SCC_EPCI_CLKRST_PCIRST 0x00000100
96#define SCC_EPCI_CLKRST_PCKEN 0x00000001
97
98/* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */
99#define SCC_EPCI_INT_2M 0x01000000
100#define SCC_EPCI_INT_RERR 0x00200000
101#define SCC_EPCI_INT_SERR 0x00100000
102#define SCC_EPCI_INT_PRTER 0x00080000
103#define SCC_EPCI_INT_SER 0x00040000
104#define SCC_EPCI_INT_PER 0x00020000
105#define SCC_EPCI_INT_PAI 0x00010000
106#define SCC_EPCI_INT_1M 0x00000100
107#define SCC_EPCI_INT_PME 0x00000010
108#define SCC_EPCI_INT_INTD 0x00000008
109#define SCC_EPCI_INT_INTC 0x00000004
110#define SCC_EPCI_INT_INTB 0x00000002
111#define SCC_EPCI_INT_INTA 0x00000001
112#define SCC_EPCI_INT_DEVINT 0x0000000f
113#define SCC_EPCI_INT_ALL 0x003f001f
114#define SCC_EPCI_INT_ALLERR 0x003f0000
115
116/* bits for SCC_EPCI_CKCTRL */
117#define SCC_EPCI_CKCTRL_CRST0 0x00010000
118#define SCC_EPCI_CKCTRL_CRST1 0x00020000
119#define SCC_EPCI_CKCTRL_OCLKEN 0x00000100
120#define SCC_EPCI_CKCTRL_LCLKEN 0x00000001
121
122#define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10)
123#define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32)
124
125/* bits for SCC_EPCI_CNTOPT */
126#define SCC_EPCI_CNTOPT_O2PMB 0x00000002
127
128/* SCC PCIEXC SMMIO registers */
129#define PEXCADRS 0x000
130#define PEXCWDATA 0x004
131#define PEXCRDATA 0x008
132#define PEXDADRS 0x010
133#define PEXDCMND 0x014
134#define PEXDWDATA 0x018
135#define PEXDRDATA 0x01c
136#define PEXREQID 0x020
137#define PEXTIDMAP 0x024
138#define PEXINTMASK 0x028
139#define PEXINTSTS 0x02c
140#define PEXAERRMASK 0x030
141#define PEXAERRSTS 0x034
142#define PEXPRERRMASK 0x040
143#define PEXPRERRSTS 0x044
144#define PEXPRERRID01 0x048
145#define PEXPRERRID23 0x04c
146#define PEXVDMASK 0x050
147#define PEXVDSTS 0x054
148#define PEXRCVCPLIDA 0x060
149#define PEXLENERRIDA 0x068
150#define PEXPHYPLLST 0x070
151#define PEXDMRDEN0 0x100
152#define PEXDMRDADR0 0x104
153#define PEXDMRDENX 0x110
154#define PEXDMRDADRX 0x114
155#define PEXECMODE 0xf00
156#define PEXMAEA(n) (0xf50 + (8 * n))
157#define PEXMAEC(n) (0xf54 + (8 * n))
158#define PEXCCRCTRL 0xff0
159
160/* SCC PCIEXC bits and shifts for PEXCADRS */
161#define PEXCADRS_BYTE_EN_SHIFT 20
162#define PEXCADRS_CMD_SHIFT 16
163#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT)
164#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT)
165
166/* SCC PCIEXC shifts for PEXDADRS */
167#define PEXDADRS_BUSNO_SHIFT 20
168#define PEXDADRS_DEVNO_SHIFT 15
169#define PEXDADRS_FUNCNO_SHIFT 12
170
171/* SCC PCIEXC bits and shifts for PEXDCMND */
172#define PEXDCMND_BYTE_EN_SHIFT 4
173#define PEXDCMND_IO_READ 0x2
174#define PEXDCMND_IO_WRITE 0x3
175#define PEXDCMND_CONFIG_READ 0xa
176#define PEXDCMND_CONFIG_WRITE 0xb
177
178/* SCC PCIEXC bits for PEXPHYPLLST */
179#define PEXPHYPLLST_PEXPHYAPLLST 0x00000001
180
181/* SCC PCIEXC bits for PEXECMODE */
182#define PEXECMODE_ALL_THROUGH 0x00000000
183#define PEXECMODE_ALL_8BIT 0x00550155
184#define PEXECMODE_ALL_16BIT 0x00aa02aa
185
186/* SCC PCIEXC bits for PEXCCRCTRL */
187#define PEXCCRCTRL_PEXIPCOREEN 0x00040000
188#define PEXCCRCTRL_PEXIPCONTEN 0x00020000
189#define PEXCCRCTRL_PEXPHYPLLEN 0x00010000
190#define PEXCCRCTRL_PCIEXCAOCKEN 0x00000100
191
192/* SCC PCIEXC port configuration registers */
193#define PEXTCERRCHK 0x21c
194#define PEXTAMAPB0 0x220
195#define PEXTAMAPL0 0x224
196#define PEXTAMAPB(n) (PEXTAMAPB0 + 8 * (n))
197#define PEXTAMAPL(n) (PEXTAMAPL0 + 8 * (n))
198#define PEXCHVC0P 0x500
199#define PEXCHVC0NP 0x504
200#define PEXCHVC0C 0x508
201#define PEXCDVC0P 0x50c
202#define PEXCDVC0NP 0x510
203#define PEXCDVC0C 0x514
204#define PEXCHVCXP 0x518
205#define PEXCHVCXNP 0x51c
206#define PEXCHVCXC 0x520
207#define PEXCDVCXP 0x524
208#define PEXCDVCXNP 0x528
209#define PEXCDVCXC 0x52c
210#define PEXCTTRG 0x530
211#define PEXTSCTRL 0x700
212#define PEXTSSTS 0x704
213#define PEXSKPCTRL 0x708
214
215/* UHC registers */
216#define SCC_UHC_CKRCTRL 0xff0
217#define SCC_UHC_ECMODE 0xf00
218
219/* bits for SCC_UHC_CKRCTRL */
220#define SCC_UHC_F48MCKLEN 0x00000001
221#define SCC_UHC_P_SUSPEND 0x00000002
222#define SCC_UHC_PHY_SUSPEND_SEL 0x00000004
223#define SCC_UHC_HCLKEN 0x00000100
224#define SCC_UHC_USBEN 0x00010000
225#define SCC_UHC_USBCEN 0x00020000
226#define SCC_UHC_PHYEN 0x00040000
227
228/* bits for SCC_UHC_ECMODE */
229#define SCC_UHC_ECMODE_BY_BYTE 0x00000555
230#define SCC_UHC_ECMODE_BY_WORD 0x00000aaa
231
232#endif /* _CELLEB_SCC_H */
diff --git a/arch/powerpc/platforms/cell/celleb_scc_epci.c b/arch/powerpc/platforms/cell/celleb_scc_epci.c
deleted file mode 100644
index 9438bbed402f..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_epci.c
+++ /dev/null
@@ -1,428 +0,0 @@
1/*
2 * Support for SCC external PCI
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/threads.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/pci_regs.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34
35#include "celleb_scc.h"
36#include "celleb_pci.h"
37
38#define MAX_PCI_DEVICES 32
39#define MAX_PCI_FUNCTIONS 8
40
41#define iob() __asm__ __volatile__("eieio; sync":::"memory")
42
43static inline PCI_IO_ADDR celleb_epci_get_epci_base(
44 struct pci_controller *hose)
45{
46 /*
47 * Note:
48 * Celleb epci uses cfg_addr as a base address for
49 * epci control registers.
50 */
51
52 return hose->cfg_addr;
53}
54
55static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
56 struct pci_controller *hose)
57{
58 /*
59 * Note:
60 * Celleb epci uses cfg_data as a base address for
61 * configuration area for epci devices.
62 */
63
64 return hose->cfg_data;
65}
66
67static inline void clear_and_disable_master_abort_interrupt(
68 struct pci_controller *hose)
69{
70 PCI_IO_ADDR epci_base;
71 PCI_IO_ADDR reg;
72 epci_base = celleb_epci_get_epci_base(hose);
73 reg = epci_base + PCI_COMMAND;
74 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
75}
76
77static int celleb_epci_check_abort(struct pci_controller *hose,
78 PCI_IO_ADDR addr)
79{
80 PCI_IO_ADDR reg;
81 PCI_IO_ADDR epci_base;
82 u32 val;
83
84 iob();
85 epci_base = celleb_epci_get_epci_base(hose);
86
87 reg = epci_base + PCI_COMMAND;
88 val = in_be32(reg);
89
90 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
91 out_be32(reg,
92 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
93
94 /* clear PCI Controller error, FRE, PMFE */
95 reg = epci_base + SCC_EPCI_STATUS;
96 out_be32(reg, SCC_EPCI_INT_PAI);
97
98 reg = epci_base + SCC_EPCI_VCSR;
99 val = in_be32(reg) & 0xffff;
100 val |= SCC_EPCI_VCSR_FRE;
101 out_be32(reg, val);
102
103 reg = epci_base + SCC_EPCI_VISTAT;
104 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
105 return PCIBIOS_DEVICE_NOT_FOUND;
106 }
107
108 return PCIBIOS_SUCCESSFUL;
109}
110
111static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
112 struct pci_controller *hose, unsigned int devfn, int where)
113{
114 PCI_IO_ADDR addr;
115
116 if (bus != hose->bus)
117 addr = celleb_epci_get_epci_cfg(hose) +
118 (((bus->number & 0xff) << 16)
119 | ((devfn & 0xff) << 8)
120 | (where & 0xff)
121 | 0x01000000);
122 else
123 addr = celleb_epci_get_epci_cfg(hose) +
124 (((devfn & 0xff) << 8) | (where & 0xff));
125
126 pr_debug("EPCI: config_addr = 0x%p\n", addr);
127
128 return addr;
129}
130
131static int celleb_epci_read_config(struct pci_bus *bus,
132 unsigned int devfn, int where, int size, u32 *val)
133{
134 PCI_IO_ADDR epci_base;
135 PCI_IO_ADDR addr;
136 struct pci_controller *hose = pci_bus_to_host(bus);
137
138 /* allignment check */
139 BUG_ON(where % size);
140
141 if (!celleb_epci_get_epci_cfg(hose))
142 return PCIBIOS_DEVICE_NOT_FOUND;
143
144 if (bus->number == hose->first_busno && devfn == 0) {
145 /* EPCI controller self */
146
147 epci_base = celleb_epci_get_epci_base(hose);
148 addr = epci_base + where;
149
150 switch (size) {
151 case 1:
152 *val = in_8(addr);
153 break;
154 case 2:
155 *val = in_be16(addr);
156 break;
157 case 4:
158 *val = in_be32(addr);
159 break;
160 default:
161 return PCIBIOS_DEVICE_NOT_FOUND;
162 }
163
164 } else {
165
166 clear_and_disable_master_abort_interrupt(hose);
167 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
168
169 switch (size) {
170 case 1:
171 *val = in_8(addr);
172 break;
173 case 2:
174 *val = in_le16(addr);
175 break;
176 case 4:
177 *val = in_le32(addr);
178 break;
179 default:
180 return PCIBIOS_DEVICE_NOT_FOUND;
181 }
182 }
183
184 pr_debug("EPCI: "
185 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
186 addr, devfn, where, size, *val);
187
188 return celleb_epci_check_abort(hose, NULL);
189}
190
191static int celleb_epci_write_config(struct pci_bus *bus,
192 unsigned int devfn, int where, int size, u32 val)
193{
194 PCI_IO_ADDR epci_base;
195 PCI_IO_ADDR addr;
196 struct pci_controller *hose = pci_bus_to_host(bus);
197
198 /* allignment check */
199 BUG_ON(where % size);
200
201 if (!celleb_epci_get_epci_cfg(hose))
202 return PCIBIOS_DEVICE_NOT_FOUND;
203
204 if (bus->number == hose->first_busno && devfn == 0) {
205 /* EPCI controller self */
206
207 epci_base = celleb_epci_get_epci_base(hose);
208 addr = epci_base + where;
209
210 switch (size) {
211 case 1:
212 out_8(addr, val);
213 break;
214 case 2:
215 out_be16(addr, val);
216 break;
217 case 4:
218 out_be32(addr, val);
219 break;
220 default:
221 return PCIBIOS_DEVICE_NOT_FOUND;
222 }
223
224 } else {
225
226 clear_and_disable_master_abort_interrupt(hose);
227 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
228
229 switch (size) {
230 case 1:
231 out_8(addr, val);
232 break;
233 case 2:
234 out_le16(addr, val);
235 break;
236 case 4:
237 out_le32(addr, val);
238 break;
239 default:
240 return PCIBIOS_DEVICE_NOT_FOUND;
241 }
242 }
243
244 return celleb_epci_check_abort(hose, addr);
245}
246
247struct pci_ops celleb_epci_ops = {
248 .read = celleb_epci_read_config,
249 .write = celleb_epci_write_config,
250};
251
252/* to be moved in FW */
253static int __init celleb_epci_init(struct pci_controller *hose)
254{
255 u32 val;
256 PCI_IO_ADDR reg;
257 PCI_IO_ADDR epci_base;
258 int hwres = 0;
259
260 epci_base = celleb_epci_get_epci_base(hose);
261
262 /* PCI core reset(Internal bus and PCI clock) */
263 reg = epci_base + SCC_EPCI_CKCTRL;
264 val = in_be32(reg);
265 if (val == 0x00030101)
266 hwres = 1;
267 else {
268 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
269 out_be32(reg, val);
270
271 /* set PCI core clock */
272 val = in_be32(reg);
273 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
274 out_be32(reg, val);
275
276 /* release PCI core reset (internal bus) */
277 val = in_be32(reg);
278 val |= SCC_EPCI_CKCTRL_CRST0;
279 out_be32(reg, val);
280
281 /* set PCI clock select */
282 reg = epci_base + SCC_EPCI_CLKRST;
283 val = in_be32(reg);
284 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
285 val |= SCC_EPCI_CLKRST_CKS_2;
286 out_be32(reg, val);
287
288 /* set arbiter */
289 reg = epci_base + SCC_EPCI_ABTSET;
290 out_be32(reg, 0x0f1f001f); /* temporary value */
291
292 /* buffer on */
293 reg = epci_base + SCC_EPCI_CLKRST;
294 val = in_be32(reg);
295 val |= SCC_EPCI_CLKRST_BC;
296 out_be32(reg, val);
297
298 /* PCI clock enable */
299 val = in_be32(reg);
300 val |= SCC_EPCI_CLKRST_PCKEN;
301 out_be32(reg, val);
302
303 /* release PCI core reset (all) */
304 reg = epci_base + SCC_EPCI_CKCTRL;
305 val = in_be32(reg);
306 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
307 out_be32(reg, val);
308
309 /* set base translation registers. (already set by Beat) */
310
311 /* set base address masks. (already set by Beat) */
312 }
313
314 /* release interrupt masks and clear all interrupts */
315 reg = epci_base + SCC_EPCI_INTSET;
316 out_be32(reg, 0x013f011f); /* all interrupts enable */
317 reg = epci_base + SCC_EPCI_VIENAB;
318 val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
319 out_be32(reg, val);
320 reg = epci_base + SCC_EPCI_STATUS;
321 out_be32(reg, 0xffffffff);
322 reg = epci_base + SCC_EPCI_VISTAT;
323 out_be32(reg, 0xffffffff);
324
325 /* disable PCI->IB address translation */
326 reg = epci_base + SCC_EPCI_VCSR;
327 val = in_be32(reg);
328 val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
329 out_be32(reg, val);
330
331 /* set base addresses. (no need to set?) */
332
333 /* memory space, bus master enable */
334 reg = epci_base + PCI_COMMAND;
335 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
336 out_be32(reg, val);
337
338 /* endian mode setup */
339 reg = epci_base + SCC_EPCI_ECMODE;
340 val = 0x00550155;
341 out_be32(reg, val);
342
343 /* set control option */
344 reg = epci_base + SCC_EPCI_CNTOPT;
345 val = in_be32(reg);
346 val |= SCC_EPCI_CNTOPT_O2PMB;
347 out_be32(reg, val);
348
349 /* XXX: temporay: set registers for address conversion setup */
350 reg = epci_base + SCC_EPCI_CNF10_REG;
351 out_be32(reg, 0x80000008);
352 reg = epci_base + SCC_EPCI_CNF14_REG;
353 out_be32(reg, 0x40000008);
354
355 reg = epci_base + SCC_EPCI_BAM0;
356 out_be32(reg, 0x80000000);
357 reg = epci_base + SCC_EPCI_BAM1;
358 out_be32(reg, 0xe0000000);
359
360 reg = epci_base + SCC_EPCI_PVBAT;
361 out_be32(reg, 0x80000000);
362
363 if (!hwres) {
364 /* release external PCI reset */
365 reg = epci_base + SCC_EPCI_CLKRST;
366 val = in_be32(reg);
367 val |= SCC_EPCI_CLKRST_PCIRST;
368 out_be32(reg, val);
369 }
370
371 return 0;
372}
373
374static int __init celleb_setup_epci(struct device_node *node,
375 struct pci_controller *hose)
376{
377 struct resource r;
378
379 pr_debug("PCI: celleb_setup_epci()\n");
380
381 /*
382 * Note:
383 * Celleb epci uses cfg_addr and cfg_data member of
384 * pci_controller structure in irregular way.
385 *
386 * cfg_addr is used to map for control registers of
387 * celleb epci.
388 *
389 * cfg_data is used for configuration area of devices
390 * on Celleb epci buses.
391 */
392
393 if (of_address_to_resource(node, 0, &r))
394 goto error;
395 hose->cfg_addr = ioremap(r.start, resource_size(&r));
396 if (!hose->cfg_addr)
397 goto error;
398 pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
399 r.start, (unsigned long)hose->cfg_addr, resource_size(&r));
400
401 if (of_address_to_resource(node, 2, &r))
402 goto error;
403 hose->cfg_data = ioremap(r.start, resource_size(&r));
404 if (!hose->cfg_data)
405 goto error;
406 pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
407 r.start, (unsigned long)hose->cfg_data, resource_size(&r));
408
409 hose->ops = &celleb_epci_ops;
410 celleb_epci_init(hose);
411
412 return 0;
413
414error:
415 if (hose->cfg_addr)
416 iounmap(hose->cfg_addr);
417
418 if (hose->cfg_data)
419 iounmap(hose->cfg_data);
420 return 1;
421}
422
423struct celleb_phb_spec celleb_epci_spec __initdata = {
424 .setup = celleb_setup_epci,
425 .ops = &spiderpci_ops,
426 .iowa_init = &spiderpci_iowa_init,
427 .iowa_data = (void *)0,
428};
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
deleted file mode 100644
index 94170e4f2ce7..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ /dev/null
@@ -1,538 +0,0 @@
1/*
2 * Support for Celleb PCI-Express.
3 *
4 * (C) Copyright 2007-2008 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/pci.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/iommu.h>
34#include <asm/byteorder.h>
35
36#include "celleb_scc.h"
37#include "celleb_pci.h"
38
39#define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off))
40#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
41
42static void scc_pciex_io_flush(struct iowa_bus *bus)
43{
44 (void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
45}
46
47/*
48 * Memory space access to device on PCIEX
49 */
50#define PCIEX_MMIO_READ(name, ret) \
51static ret scc_pciex_##name(const PCI_IO_ADDR addr) \
52{ \
53 ret val = __do_##name(addr); \
54 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
55 return val; \
56}
57
58#define PCIEX_MMIO_READ_STR(name) \
59static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf, \
60 unsigned long count) \
61{ \
62 __do_##name(addr, buf, count); \
63 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
64}
65
66PCIEX_MMIO_READ(readb, u8)
67PCIEX_MMIO_READ(readw, u16)
68PCIEX_MMIO_READ(readl, u32)
69PCIEX_MMIO_READ(readq, u64)
70PCIEX_MMIO_READ(readw_be, u16)
71PCIEX_MMIO_READ(readl_be, u32)
72PCIEX_MMIO_READ(readq_be, u64)
73PCIEX_MMIO_READ_STR(readsb)
74PCIEX_MMIO_READ_STR(readsw)
75PCIEX_MMIO_READ_STR(readsl)
76
77static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
78 unsigned long n)
79{
80 __do_memcpy_fromio(dest, src, n);
81 scc_pciex_io_flush(iowa_mem_find_bus(src));
82}
83
84/*
85 * I/O port access to devices on PCIEX.
86 */
87
88static inline unsigned long get_bus_address(struct pci_controller *phb,
89 unsigned long port)
90{
91 return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
92}
93
94static u32 scc_pciex_read_port(struct pci_controller *phb,
95 unsigned long port, int size)
96{
97 unsigned int byte_enable;
98 unsigned int cmd, shift;
99 unsigned long addr;
100 u32 data, ret;
101
102 BUG_ON(((port & 0x3ul) + size) > 4);
103
104 addr = get_bus_address(phb, port);
105 shift = addr & 0x3ul;
106 byte_enable = ((1 << size) - 1) << shift;
107 cmd = PEXDCMND_IO_READ | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
108 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
109 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
110 data = PEX_IN(phb->cfg_addr, PEXDRDATA);
111 ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));
112
113 pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
114 " cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
115 cmd, data, ret);
116
117 return ret;
118}
119
120static void scc_pciex_write_port(struct pci_controller *phb,
121 unsigned long port, int size, u32 val)
122{
123 unsigned int byte_enable;
124 unsigned int cmd, shift;
125 unsigned long addr;
126 u32 data;
127
128 BUG_ON(((port & 0x3ul) + size) > 4);
129
130 addr = get_bus_address(phb, port);
131 shift = addr & 0x3ul;
132 byte_enable = ((1 << size) - 1) << shift;
133 cmd = PEXDCMND_IO_WRITE | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
134 data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
135 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
136 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
137 PEX_OUT(phb->cfg_addr, PEXDWDATA, data);
138
139 pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
140 " be=%x, cmd=%x, data=%x\n", port, addr, size, val,
141 byte_enable, cmd, data);
142}
143
144static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
145{
146 return (u8)scc_pciex_read_port(phb, port, 1);
147}
148
149static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
150{
151 u32 data;
152 if ((port & 0x3ul) < 3)
153 data = scc_pciex_read_port(phb, port, 2);
154 else {
155 u32 d1 = scc_pciex_read_port(phb, port, 1);
156 u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
157 data = d1 | (d2 << 8);
158 }
159 return (u16)data;
160}
161
162static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
163{
164 unsigned int mod = port & 0x3ul;
165 u32 data;
166 if (mod == 0)
167 data = scc_pciex_read_port(phb, port, 4);
168 else {
169 u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
170 u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
171 data = d1 | (d2 << (mod * 8));
172 }
173 return data;
174}
175
176static void __scc_pciex_outb(struct pci_controller *phb,
177 u8 val, unsigned long port)
178{
179 scc_pciex_write_port(phb, port, 1, (u32)val);
180}
181
182static void __scc_pciex_outw(struct pci_controller *phb,
183 u16 val, unsigned long port)
184{
185 if ((port & 0x3ul) < 3)
186 scc_pciex_write_port(phb, port, 2, (u32)val);
187 else {
188 u32 d1 = val & 0x000000FF;
189 u32 d2 = (val & 0x0000FF00) >> 8;
190 scc_pciex_write_port(phb, port, 1, d1);
191 scc_pciex_write_port(phb, port + 1, 1, d2);
192 }
193}
194
195static void __scc_pciex_outl(struct pci_controller *phb,
196 u32 val, unsigned long port)
197{
198 unsigned int mod = port & 0x3ul;
199 if (mod == 0)
200 scc_pciex_write_port(phb, port, 4, val);
201 else {
202 u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
203 u32 d2 = val >> ((4 - mod) * 8);
204 scc_pciex_write_port(phb, port, 4 - mod, d1);
205 scc_pciex_write_port(phb, port + 1, mod, d2);
206 }
207}
208
209#define PCIEX_PIO_FUNC(size, name) \
210static u##size scc_pciex_in##name(unsigned long port) \
211{ \
212 struct iowa_bus *bus = iowa_pio_find_bus(port); \
213 u##size data = __scc_pciex_in##name(bus->phb, port); \
214 scc_pciex_io_flush(bus); \
215 return data; \
216} \
217static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
218{ \
219 struct iowa_bus *bus = iowa_pio_find_bus(p); \
220 __le##size *dst = b; \
221 for (; c != 0; c--, dst++) \
222 *dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
223 scc_pciex_io_flush(bus); \
224} \
225static void scc_pciex_out##name(u##size val, unsigned long port) \
226{ \
227 struct iowa_bus *bus = iowa_pio_find_bus(port); \
228 __scc_pciex_out##name(bus->phb, val, port); \
229} \
230static void scc_pciex_outs##name(unsigned long p, const void *b, \
231 unsigned long c) \
232{ \
233 struct iowa_bus *bus = iowa_pio_find_bus(p); \
234 const __le##size *src = b; \
235 for (; c != 0; c--, src++) \
236 __scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
237}
238#define __le8 u8
239#define cpu_to_le8(x) (x)
240#define le8_to_cpu(x) (x)
241PCIEX_PIO_FUNC(8, b)
242PCIEX_PIO_FUNC(16, w)
243PCIEX_PIO_FUNC(32, l)
244
245static struct ppc_pci_io scc_pciex_ops = {
246 .readb = scc_pciex_readb,
247 .readw = scc_pciex_readw,
248 .readl = scc_pciex_readl,
249 .readq = scc_pciex_readq,
250 .readw_be = scc_pciex_readw_be,
251 .readl_be = scc_pciex_readl_be,
252 .readq_be = scc_pciex_readq_be,
253 .readsb = scc_pciex_readsb,
254 .readsw = scc_pciex_readsw,
255 .readsl = scc_pciex_readsl,
256 .memcpy_fromio = scc_pciex_memcpy_fromio,
257 .inb = scc_pciex_inb,
258 .inw = scc_pciex_inw,
259 .inl = scc_pciex_inl,
260 .outb = scc_pciex_outb,
261 .outw = scc_pciex_outw,
262 .outl = scc_pciex_outl,
263 .insb = scc_pciex_insb,
264 .insw = scc_pciex_insw,
265 .insl = scc_pciex_insl,
266 .outsb = scc_pciex_outsb,
267 .outsw = scc_pciex_outsw,
268 .outsl = scc_pciex_outsl,
269};
270
271static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
272{
273 dma_addr_t dummy_page_da;
274 void *dummy_page_va;
275
276 dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
277 if (!dummy_page_va) {
278 pr_err("PCIEX:Alloc dummy_page_va failed\n");
279 return -1;
280 }
281
282 dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
283 PAGE_SIZE, DMA_FROM_DEVICE);
284 if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
285 pr_err("PCIEX:Map dummy page failed.\n");
286 kfree(dummy_page_va);
287 return -1;
288 }
289
290 PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);
291
292 return 0;
293}
294
295/*
296 * config space access
297 */
298#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
299 ((uint32_t)(((addr) & ~0x3UL) | \
300 ((bus_no) << PEXDADRS_BUSNO_SHIFT) | \
301 ((dev_no) << PEXDADRS_DEVNO_SHIFT) | \
302 ((func_no) << PEXDADRS_FUNCNO_SHIFT)))
303
304#define MK_PEXDCMND_BYTE_EN(addr, size) \
305 ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
306#define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))
307
308static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
309 uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
310 uint64_t off, uint64_t size)
311{
312 uint32_t ret;
313 uint32_t addr, cmd;
314
315 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
316 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
317 PEX_OUT(base, PEXDADRS, addr);
318 PEX_OUT(base, PEXDCMND, cmd);
319 ret = (PEX_IN(base, PEXDRDATA)
320 >> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
321 return ret;
322}
323
324static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
325 uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
326 uint32_t data)
327{
328 uint32_t addr, cmd;
329
330 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
331 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
332 PEX_OUT(base, PEXDADRS, addr);
333 PEX_OUT(base, PEXDCMND, cmd);
334 PEX_OUT(base, PEXDWDATA,
335 (data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
336}
337
338#define MK_PEXCADRS_BYTE_EN(off, len) \
339 ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
340#define MK_PEXCADRS(cmd, addr, size) \
341 ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
342static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
343 uint32_t where, uint32_t size)
344{
345 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
346 return (PEX_IN(base, PEXCRDATA)
347 >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
348}
349
350static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
351 uint32_t size, uint32_t val)
352{
353 uint32_t data;
354
355 data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
356 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
357 PEX_OUT(base, PEXCWDATA, data);
358}
359
360/* Interfaces */
361/* Note: Work-around
362 * On SCC PCIEXC, one device is seen on all 32 dev_no.
363 * As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
364 * (dev_no = 1)
365 */
366static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
367 int where, int size, unsigned int *val)
368{
369 struct pci_controller *phb = pci_bus_to_host(bus);
370
371 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
372 *val = ~0;
373 return PCIBIOS_DEVICE_NOT_FOUND;
374 }
375
376 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
377 *val = config_read_pciex_rc(phb->cfg_addr, where, size);
378 else
379 *val = config_read_pciex_dev(phb->cfg_addr, bus->number,
380 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
381
382 return PCIBIOS_SUCCESSFUL;
383}
384
385static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
386 int where, int size, unsigned int val)
387{
388 struct pci_controller *phb = pci_bus_to_host(bus);
389
390 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
391 return PCIBIOS_DEVICE_NOT_FOUND;
392
393 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
394 config_write_pciex_rc(phb->cfg_addr, where, size, val);
395 else
396 config_write_pciex_dev(phb->cfg_addr, bus->number,
397 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
398 return PCIBIOS_SUCCESSFUL;
399}
400
401static struct pci_ops scc_pciex_pci_ops = {
402 .read = scc_pciex_read_config,
403 .write = scc_pciex_write_config,
404};
405
406static void pciex_clear_intr_all(unsigned int __iomem *base)
407{
408 PEX_OUT(base, PEXAERRSTS, 0xffffffff);
409 PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
410 PEX_OUT(base, PEXINTSTS, 0xffffffff);
411}
412
413#if 0
414static void pciex_disable_intr_all(unsigned int *base)
415{
416 PEX_OUT(base, PEXINTMASK, 0x0);
417 PEX_OUT(base, PEXAERRMASK, 0x0);
418 PEX_OUT(base, PEXPRERRMASK, 0x0);
419 PEX_OUT(base, PEXVDMASK, 0x0);
420}
421#endif
422
423static void pciex_enable_intr_all(unsigned int __iomem *base)
424{
425 PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
426 PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
427 PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
428 PEX_OUT(base, PEXVDMASK, 0x00000001);
429}
430
431static void pciex_check_status(unsigned int __iomem *base)
432{
433 uint32_t err = 0;
434 uint32_t intsts, aerr, prerr, rcvcp, lenerr;
435 uint32_t maea, maec;
436
437 intsts = PEX_IN(base, PEXINTSTS);
438 aerr = PEX_IN(base, PEXAERRSTS);
439 prerr = PEX_IN(base, PEXPRERRSTS);
440 rcvcp = PEX_IN(base, PEXRCVCPLIDA);
441 lenerr = PEX_IN(base, PEXLENERRIDA);
442
443 if (intsts || aerr || prerr || rcvcp || lenerr)
444 err = 1;
445
446 pr_info("PCEXC interrupt!!\n");
447 pr_info("PEXINTSTS :0x%08x\n", intsts);
448 pr_info("PEXAERRSTS :0x%08x\n", aerr);
449 pr_info("PEXPRERRSTS :0x%08x\n", prerr);
450 pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
451 pr_info("PEXLENERRIDA :0x%08x\n", lenerr);
452
453 /* print detail of Protection Error */
454 if (intsts & 0x00004000) {
455 uint32_t i, n;
456 for (i = 0; i < 4; i++) {
457 n = 1 << i;
458 if (prerr & n) {
459 maea = PEX_IN(base, PEXMAEA(i));
460 maec = PEX_IN(base, PEXMAEC(i));
461 pr_info("PEXMAEC%d :0x%08x\n", i, maec);
462 pr_info("PEXMAEA%d :0x%08x\n", i, maea);
463 }
464 }
465 }
466
467 if (err)
468 pciex_clear_intr_all(base);
469}
470
471static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
472{
473 struct pci_controller *phb = dev_id;
474
475 pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);
476
477 BUG_ON(phb->cfg_addr == NULL);
478
479 pciex_check_status(phb->cfg_addr);
480
481 return IRQ_HANDLED;
482}
483
484static __init int celleb_setup_pciex(struct device_node *node,
485 struct pci_controller *phb)
486{
487 struct resource r;
488 int virq;
489
490 /* SMMIO registers; used inside this file */
491 if (of_address_to_resource(node, 0, &r)) {
492 pr_err("PCIEXC:Failed to get config resource.\n");
493 return 1;
494 }
495 phb->cfg_addr = ioremap(r.start, resource_size(&r));
496 if (!phb->cfg_addr) {
497 pr_err("PCIEXC:Failed to remap SMMIO region.\n");
498 return 1;
499 }
500
501 /* Not use cfg_data, cmd and data regs are near address reg */
502 phb->cfg_data = NULL;
503
504 /* set pci_ops */
505 phb->ops = &scc_pciex_pci_ops;
506
507 /* internal interrupt handler */
508 virq = irq_of_parse_and_map(node, 1);
509 if (!virq) {
510 pr_err("PCIEXC:Failed to map irq\n");
511 goto error;
512 }
513 if (request_irq(virq, pciex_handle_internal_irq,
514 0, "pciex", (void *)phb)) {
515 pr_err("PCIEXC:Failed to request irq\n");
516 goto error;
517 }
518
519 /* enable all interrupts */
520 pciex_clear_intr_all(phb->cfg_addr);
521 pciex_enable_intr_all(phb->cfg_addr);
522 /* MSI: TBD */
523
524 return 0;
525
526error:
527 phb->cfg_data = NULL;
528 if (phb->cfg_addr)
529 iounmap(phb->cfg_addr);
530 phb->cfg_addr = NULL;
531 return 1;
532}
533
534struct celleb_phb_spec celleb_pciex_spec __initdata = {
535 .setup = celleb_setup_pciex,
536 .ops = &scc_pciex_ops,
537 .iowa_init = &scc_pciex_iowa_init,
538};
diff --git a/arch/powerpc/platforms/cell/celleb_scc_sio.c b/arch/powerpc/platforms/cell/celleb_scc_sio.c
deleted file mode 100644
index c8eb57193826..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_sio.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * setup serial port in SCC
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/tty.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/console.h>
25
26#include <asm/io.h>
27#include <asm/prom.h>
28
29/* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
30 mmio=0xfff000-0x1000,0xff2000-0x1000 */
31static int txx9_serial_bitmap __initdata;
32
33static struct {
34 uint32_t offset;
35 uint32_t index;
36} txx9_scc_tab[3] __initdata = {
37 { 0x300, 0 }, /* 0xFFF300 */
38 { 0x400, 0 }, /* 0xFFF400 */
39 { 0x800, 1 } /* 0xFF2800 */
40};
41
42static int __init txx9_serial_init(void)
43{
44 extern int early_serial_txx9_setup(struct uart_port *port);
45 struct device_node *node;
46 int i;
47 struct uart_port req;
48 struct of_phandle_args irq;
49 struct resource res;
50
51 for_each_compatible_node(node, "serial", "toshiba,sio-scc") {
52 for (i = 0; i < ARRAY_SIZE(txx9_scc_tab); i++) {
53 if (!(txx9_serial_bitmap & (1<<i)))
54 continue;
55
56 if (of_irq_parse_one(node, i, &irq))
57 continue;
58 if (of_address_to_resource(node,
59 txx9_scc_tab[i].index, &res))
60 continue;
61
62 memset(&req, 0, sizeof(req));
63 req.line = i;
64 req.iotype = UPIO_MEM;
65 req.mapbase = res.start + txx9_scc_tab[i].offset;
66#ifdef CONFIG_SERIAL_TXX9_CONSOLE
67 req.membase = ioremap(req.mapbase, 0x24);
68#endif
69 req.irq = irq_create_of_mapping(&irq);
70 req.flags |= UPF_IOREMAP | UPF_BUGGY_UART
71 /*HAVE_CTS_LINE*/;
72 req.uartclk = 83300000;
73 early_serial_txx9_setup(&req);
74 }
75 }
76
77 return 0;
78}
79
80static int __init txx9_serial_config(char *ptr)
81{
82 int i;
83
84 for (;;) {
85 switch (get_option(&ptr, &i)) {
86 default:
87 return 0;
88 case 2:
89 txx9_serial_bitmap |= 1 << i;
90 break;
91 case 1:
92 txx9_serial_bitmap |= 1 << i;
93 return 0;
94 }
95 }
96}
97__setup("txx9_serial=", txx9_serial_config);
98
99console_initcall(txx9_serial_init);
diff --git a/arch/powerpc/platforms/cell/celleb_scc_uhc.c b/arch/powerpc/platforms/cell/celleb_scc_uhc.c
deleted file mode 100644
index d63b720bfe3a..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_uhc.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * SCC (Super Companion Chip) UHC setup
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23
24#include <asm/delay.h>
25#include <asm/io.h>
26#include <asm/machdep.h>
27
28#include "celleb_scc.h"
29
30#define UHC_RESET_WAIT_MAX 10000
31
32static inline int uhc_clkctrl_ready(u32 val)
33{
34 const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
35 return((val & mask) == mask);
36}
37
38/*
39 * UHC(usb host controller) enable function.
40 * affect to both of OHCI and EHCI core module.
41 */
42static void enable_scc_uhc(struct pci_dev *dev)
43{
44 void __iomem *uhc_base;
45 u32 __iomem *uhc_clkctrl;
46 u32 __iomem *uhc_ecmode;
47 u32 val = 0;
48 int i;
49
50 if (!machine_is(celleb_beat) &&
51 !machine_is(celleb_native))
52 return;
53
54 uhc_base = ioremap(pci_resource_start(dev, 0),
55 pci_resource_len(dev, 0));
56 if (!uhc_base) {
57 printk(KERN_ERR "failed to map UHC register base.\n");
58 return;
59 }
60 uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
61 uhc_ecmode = uhc_base + SCC_UHC_ECMODE;
62
63 /* setup for normal mode */
64 val |= SCC_UHC_F48MCKLEN;
65 out_be32(uhc_clkctrl, val);
66 val |= SCC_UHC_PHY_SUSPEND_SEL;
67 out_be32(uhc_clkctrl, val);
68 udelay(10);
69 val |= SCC_UHC_PHYEN;
70 out_be32(uhc_clkctrl, val);
71 udelay(50);
72
73 /* disable reset */
74 val |= SCC_UHC_HCLKEN;
75 out_be32(uhc_clkctrl, val);
76 val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
77 out_be32(uhc_clkctrl, val);
78 i = 0;
79 while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
80 udelay(10);
81 if (i++ > UHC_RESET_WAIT_MAX) {
82 printk(KERN_ERR "Failed to disable UHC reset %x\n",
83 in_be32(uhc_clkctrl));
84 break;
85 }
86 }
87
88 /* Endian Conversion Mode for Master ALL area */
89 out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
90
91 iounmap(uhc_base);
92}
93
94DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
95 PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);
diff --git a/arch/powerpc/platforms/cell/celleb_setup.c b/arch/powerpc/platforms/cell/celleb_setup.c
deleted file mode 100644
index 90be8ec51686..000000000000
--- a/arch/powerpc/platforms/cell/celleb_setup.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/*
2 * Celleb setup code
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/cell/setup.c:
7 * Copyright (C) 1995 Linus Torvalds
8 * Adapted from 'alpha' version by Gary Thomas
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * Modified by PPC64 Team, IBM Corp
11 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 */
27
28#undef DEBUG
29
30#include <linux/cpu.h>
31#include <linux/sched.h>
32#include <linux/kernel.h>
33#include <linux/export.h>
34#include <linux/mm.h>
35#include <linux/stddef.h>
36#include <linux/unistd.h>
37#include <linux/reboot.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/irq.h>
41#include <linux/seq_file.h>
42#include <linux/root_dev.h>
43#include <linux/console.h>
44#include <linux/of_platform.h>
45
46#include <asm/mmu.h>
47#include <asm/processor.h>
48#include <asm/io.h>
49#include <asm/prom.h>
50#include <asm/machdep.h>
51#include <asm/cputable.h>
52#include <asm/irq.h>
53#include <asm/time.h>
54#include <asm/spu_priv1.h>
55#include <asm/firmware.h>
56#include <asm/rtas.h>
57#include <asm/cell-regs.h>
58
59#include "beat_interrupt.h"
60#include "beat_wrapper.h"
61#include "beat.h"
62#include "celleb_pci.h"
63#include "interrupt.h"
64#include "pervasive.h"
65#include "ras.h"
66
67static char celleb_machine_type[128] = "Celleb";
68
69static void celleb_show_cpuinfo(struct seq_file *m)
70{
71 struct device_node *root;
72 const char *model = "";
73
74 root = of_find_node_by_path("/");
75 if (root)
76 model = of_get_property(root, "model", NULL);
77 /* using "CHRP" is to trick anaconda into installing FCx into Celleb */
78 seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
79 of_node_put(root);
80}
81
82static int __init celleb_machine_type_hack(char *ptr)
83{
84 strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
85 return 0;
86}
87
88__setup("celleb_machine_type_hack=", celleb_machine_type_hack);
89
90static void celleb_progress(char *s, unsigned short hex)
91{
92 printk("*** %04x : %s\n", hex, s ? s : "");
93}
94
95static void __init celleb_setup_arch_common(void)
96{
97 /* init to some ~sane value until calibrate_delay() runs */
98 loops_per_jiffy = 50000000;
99
100#ifdef CONFIG_DUMMY_CONSOLE
101 conswitchp = &dummy_con;
102#endif
103}
104
105static const struct of_device_id celleb_bus_ids[] __initconst = {
106 { .type = "scc", },
107 { .type = "ioif", }, /* old style */
108 {},
109};
110
111static int __init celleb_publish_devices(void)
112{
113 /* Publish OF platform devices for southbridge IOs */
114 of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
115
116 return 0;
117}
118machine_device_initcall(celleb_beat, celleb_publish_devices);
119machine_device_initcall(celleb_native, celleb_publish_devices);
120
121
122/*
123 * functions for Celleb-Beat
124 */
125static void __init celleb_setup_arch_beat(void)
126{
127#ifdef CONFIG_SPU_BASE
128 spu_priv1_ops = &spu_priv1_beat_ops;
129 spu_management_ops = &spu_management_of_ops;
130#endif
131
132 celleb_setup_arch_common();
133}
134
135static int __init celleb_probe_beat(void)
136{
137 unsigned long root = of_get_flat_dt_root();
138
139 if (!of_flat_dt_is_compatible(root, "Beat"))
140 return 0;
141
142 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
143 | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
144 hpte_init_beat_v3();
145 pm_power_off = beat_power_off;
146
147 return 1;
148}
149
150
151/*
152 * functions for Celleb-native
153 */
154static void __init celleb_init_IRQ_native(void)
155{
156 iic_init_IRQ();
157 spider_init_IRQ();
158}
159
160static void __init celleb_setup_arch_native(void)
161{
162#ifdef CONFIG_SPU_BASE
163 spu_priv1_ops = &spu_priv1_mmio_ops;
164 spu_management_ops = &spu_management_of_ops;
165#endif
166
167 cbe_regs_init();
168
169#ifdef CONFIG_CBE_RAS
170 cbe_ras_init();
171#endif
172
173#ifdef CONFIG_SMP
174 smp_init_cell();
175#endif
176
177 cbe_pervasive_init();
178
179 /* XXX: nvram initialization should be added */
180
181 celleb_setup_arch_common();
182}
183
184static int __init celleb_probe_native(void)
185{
186 unsigned long root = of_get_flat_dt_root();
187
188 if (of_flat_dt_is_compatible(root, "Beat") ||
189 !of_flat_dt_is_compatible(root, "TOSHIBA,Celleb"))
190 return 0;
191
192 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
193 hpte_init_native();
194 pm_power_off = rtas_power_off;
195
196 return 1;
197}
198
199
200/*
201 * machine definitions
202 */
203define_machine(celleb_beat) {
204 .name = "Cell Reference Set (Beat)",
205 .probe = celleb_probe_beat,
206 .setup_arch = celleb_setup_arch_beat,
207 .show_cpuinfo = celleb_show_cpuinfo,
208 .restart = beat_restart,
209 .halt = beat_halt,
210 .get_rtc_time = beat_get_rtc_time,
211 .set_rtc_time = beat_set_rtc_time,
212 .calibrate_decr = generic_calibrate_decr,
213 .progress = celleb_progress,
214 .power_save = beat_power_save,
215 .nvram_size = beat_nvram_get_size,
216 .nvram_read = beat_nvram_read,
217 .nvram_write = beat_nvram_write,
218 .set_dabr = beat_set_xdabr,
219 .init_IRQ = beatic_init_IRQ,
220 .get_irq = beatic_get_irq,
221 .pci_probe_mode = celleb_pci_probe_mode,
222 .pci_setup_phb = celleb_setup_phb,
223#ifdef CONFIG_KEXEC
224 .kexec_cpu_down = beat_kexec_cpu_down,
225#endif
226};
227
228define_machine(celleb_native) {
229 .name = "Cell Reference Set (native)",
230 .probe = celleb_probe_native,
231 .setup_arch = celleb_setup_arch_native,
232 .show_cpuinfo = celleb_show_cpuinfo,
233 .restart = rtas_restart,
234 .halt = rtas_halt,
235 .get_boot_time = rtas_get_boot_time,
236 .get_rtc_time = rtas_get_rtc_time,
237 .set_rtc_time = rtas_set_rtc_time,
238 .calibrate_decr = generic_calibrate_decr,
239 .progress = celleb_progress,
240 .pci_probe_mode = celleb_pci_probe_mode,
241 .pci_setup_phb = celleb_setup_phb,
242 .init_IRQ = celleb_init_IRQ_native,
243};
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index c7c8720aa39f..31b1a67daccf 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -1234,5 +1234,3 @@ static int __init cell_iommu_init(void)
1234 return 0; 1234 return 0;
1235} 1235}
1236machine_arch_initcall(cell, cell_iommu_init); 1236machine_arch_initcall(cell, cell_iommu_init);
1237machine_arch_initcall(celleb_native, cell_iommu_init);
1238
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 18:55:52 -0500