3 files changed, 51 insertions, 0 deletions

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 0bb1335313b2..aede2c347bde 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -189,6 +189,11 @@
 #define X86_FEATURE_DTHERM      ( 7*32+ 7) /* Digital Thermal Sensor */
 #define X86_FEATURE_HW_PSTATE   ( 7*32+ 8) /* AMD HW-PState */
 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
+#define X86_FEATURE_HWP         ( 7*32+ 10) /* "hwp" Intel HWP */
+#define X86_FEATURE_HWP_NOITFY  ( 7*32+ 11) /* Intel HWP_NOTIFY */
+#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */
+#define X86_FEATURE_HWP_EPP     ( 7*32+13) /* Intel HWP_EPP */
+#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index e21331ce368f..62838e54947d 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -152,6 +152,45 @@
 #define MSR_CC6_DEMOTION_POLICY_CONFIG  0x00000668
 #define MSR_MC6_DEMOTION_POLICY_CONFIG  0x00000669
 
+/* Hardware P state interface */
+#define MSR_PPERF                       0x0000064e
+#define MSR_PERF_LIMIT_REASONS          0x0000064f
+#define MSR_PM_ENABLE                   0x00000770
+#define MSR_HWP_CAPABILITIES            0x00000771
+#define MSR_HWP_REQUEST_PKG             0x00000772
+#define MSR_HWP_INTERRUPT               0x00000773
+#define MSR_HWP_REQUEST                 0x00000774
+#define MSR_HWP_STATUS                  0x00000777
+
+/* CPUID.6.EAX */
+#define HWP_BASE_BIT                    (1<<7)
+#define HWP_NOTIFICATIONS_BIT           (1<<8)
+#define HWP_ACTIVITY_WINDOW_BIT         (1<<9)
+#define HWP_ENERGY_PERF_PREFERENCE_BIT  (1<<10)
+#define HWP_PACKAGE_LEVEL_REQUEST_BIT   (1<<11)
+
+/* IA32_HWP_CAPABILITIES */
+#define HWP_HIGHEST_PERF(x)             (x & 0xff)
+#define HWP_GUARANTEED_PERF(x)          ((x & (0xff << 8)) >>8)
+#define HWP_MOSTEFFICIENT_PERF(x)       ((x & (0xff << 16)) >>16)
+#define HWP_LOWEST_PERF(x)              ((x & (0xff << 24)) >>24)
+
+/* IA32_HWP_REQUEST */
+#define HWP_MIN_PERF(x)                 (x & 0xff)
+#define HWP_MAX_PERF(x)                 ((x & 0xff) << 8)
+#define HWP_DESIRED_PERF(x)             ((x & 0xff) << 16)
+#define HWP_ENERGY_PERF_PREFERENCE(x)   ((x & 0xff) << 24)
+#define HWP_ACTIVITY_WINDOW(x)          ((x & 0xff3) << 32)
+#define HWP_PACKAGE_CONTROL(x)          ((x & 0x1) << 42)
+
+/* IA32_HWP_STATUS */
+#define HWP_GUARANTEED_CHANGE(x)        (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM(x)     (x & 0x4)
+
+/* IA32_HWP_INTERRUPT */
+#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
+
 #define MSR_AMD64_MC0_MASK              0xc0010044
 
 #define MSR_IA32_MCx_CTL(x)             (MSR_IA32_MC0_CTL + 4*(x))
@@ -345,6 +384,8 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
 
+#define MSR_MISC_PWR_MGMT               0x000001aa
+
 #define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
 #define ENERGY_PERF_BIAS_PERFORMANCE    0
 #define ENERGY_PERF_BIAS_NORMAL         6
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 4a8013d55947..60639093d536 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -36,6 +36,11 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                 { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
                 { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
                 { X86_FEATURE_PTS,              CR_EAX, 6, 0x00000006, 0 },
+                { X86_FEATURE_HWP,              CR_EAX, 7, 0x00000006, 0 },
+                { X86_FEATURE_HWP_NOITFY,       CR_EAX, 8, 0x00000006, 0 },
+                { X86_FEATURE_HWP_ACT_WINDOW,   CR_EAX, 9, 0x00000006, 0 },
+                { X86_FEATURE_HWP_EPP,          CR_EAX,10, 0x00000006, 0 },
+                { X86_FEATURE_HWP_PKG_REQ,      CR_EAX,11, 0x00000006, 0 },
                 { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                 { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
                 { X86_FEATURE_HW_PSTATE,        CR_EDX, 7, 0x80000007, 0 },