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-rw-r--r--arch/powerpc/boot/dts/b4860emu.dts7
-rw-r--r--arch/powerpc/boot/dts/bsc9132qds.dts35
-rw-r--r--arch/powerpc/boot/dts/bsc9132qds.dtsi101
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi185
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi430
-rw-r--r--arch/powerpc/boot/dts/fsl/t1042si-post.dtsi37
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi104
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi12
-rw-r--r--arch/powerpc/boot/dts/kmcoge4.dts152
-rw-r--r--arch/powerpc/boot/dts/oca4080.dts118
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts219
-rw-r--r--arch/powerpc/boot/dts/t1040qds.dts46
-rw-r--r--arch/powerpc/boot/dts/t1042qds.dts46
-rw-r--r--arch/powerpc/boot/dts/t104xqds.dtsi166
-rw-r--r--arch/powerpc/boot/dts/t4240emu.dts15
-rw-r--r--arch/powerpc/configs/85xx/kmp204x_defconfig225
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/kernel/epapr_paravirt.c19
-rw-r--r--arch/powerpc/mm/tlb_nohash.c7
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig19
-rw-r--r--arch/powerpc/platforms/85xx/Makefile3
-rw-r--r--arch/powerpc/platforms/85xx/bsc913x_qds.c74
-rw-r--r--arch/powerpc/platforms/85xx/corenet_generic.c9
-rw-r--r--arch/powerpc/platforms/85xx/p1023_rdb.c (renamed from arch/powerpc/platforms/85xx/p1023_rds.c)36
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c3
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c10
-rw-r--r--arch/powerpc/sysdev/fsl_rmu.c6
-rw-r--r--arch/powerpc/sysdev/mpic.c8
47 files changed, 1929 insertions, 289 deletions
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021f2dfc..85646b4f96e1 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -61,21 +61,25 @@
61 device_type = "cpu"; 61 device_type = "cpu";
62 reg = <0 1>; 62 reg = <0 1>;
63 next-level-cache = <&L2>; 63 next-level-cache = <&L2>;
64 fsl,portid-mapping = <0x80000000>;
64 }; 65 };
65 cpu1: PowerPC,e6500@2 { 66 cpu1: PowerPC,e6500@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 reg = <2 3>; 68 reg = <2 3>;
68 next-level-cache = <&L2>; 69 next-level-cache = <&L2>;
70 fsl,portid-mapping = <0x80000000>;
69 }; 71 };
70 cpu2: PowerPC,e6500@4 { 72 cpu2: PowerPC,e6500@4 {
71 device_type = "cpu"; 73 device_type = "cpu";
72 reg = <4 5>; 74 reg = <4 5>;
73 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
74 }; 77 };
75 cpu3: PowerPC,e6500@6 { 78 cpu3: PowerPC,e6500@6 {
76 device_type = "cpu"; 79 device_type = "cpu";
77 reg = <6 7>; 80 reg = <6 7>;
78 next-level-cache = <&L2>; 81 next-level-cache = <&L2>;
82 fsl,portid-mapping = <0x80000000>;
79 }; 83 };
80 }; 84 };
81}; 85};
@@ -157,7 +161,7 @@
157 }; 161 };
158 162
159 corenet-cf@18000 { 163 corenet-cf@18000 {
160 compatible = "fsl,b4-corenet-cf"; 164 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
161 reg = <0x18000 0x1000>; 165 reg = <0x18000 0x1000>;
162 interrupts = <16 2 1 0>; 166 interrupts = <16 2 1 0>;
163 fsl,ccf-num-csdids = <32>; 167 fsl,ccf-num-csdids = <32>;
@@ -167,6 +171,7 @@
167 iommu@20000 { 171 iommu@20000 {
168 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 172 compatible = "fsl,pamu-v1.0", "fsl,pamu";
169 reg = <0x20000 0x4000>; 173 reg = <0x20000 0x4000>;
174 fsl,portid-mapping = <0x8000>;
170 #address-cells = <1>; 175 #address-cells = <1>;
171 #size-cells = <1>; 176 #size-cells = <1>;
172 interrupts = < 177 interrupts = <
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dts b/arch/powerpc/boot/dts/bsc9132qds.dts
new file mode 100644
index 000000000000..6cab1062bc74
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dts
@@ -0,0 +1,35 @@
1/*
2 * BSC9132 QDS Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/bsc9132si-pre.dtsi"
13
14/ {
15 model = "fsl,bsc9132qds";
16 compatible = "fsl,bsc9132qds";
17
18 memory {
19 device_type = "memory";
20 };
21
22 ifc: ifc@ff71e000 {
23 /* NOR, NAND Flash on board */
24 ranges = <0x0 0x0 0x0 0x88000000 0x08000000
25 0x1 0x0 0x0 0xff800000 0x00010000>;
26 reg = <0x0 0xff71e000 0x0 0x2000>;
27 };
28
29 soc: soc@ff700000 {
30 ranges = <0x0 0x0 0xff700000 0x100000>;
31 };
32};
33
34/include/ "bsc9132qds.dtsi"
35/include/ "fsl/bsc9132si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dtsi b/arch/powerpc/boot/dts/bsc9132qds.dtsi
new file mode 100644
index 000000000000..af8e88830221
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dtsi
@@ -0,0 +1,101 @@
1/*
2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43 };
44
45 nand@1,0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,ifc-nand";
49 reg = <0x1 0x0 0x4000>;
50 };
51};
52
53&soc {
54 spi@7000 {
55 flash@0 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "spansion,s25sl12801";
59 reg = <0>;
60 spi-max-frequency = <30000000>;
61 };
62 };
63
64 i2c@3000 {
65 fpga: fpga@66 {
66 compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
67 reg = <0x66>;
68 };
69 };
70
71 usb@22000 {
72 phy_type = "ulpi";
73 };
74
75 mdio@24000 {
76 phy0: ethernet-phy@0 {
77 reg = <0x0>;
78 };
79
80 phy1: ethernet-phy@1 {
81 reg = <0x1>;
82 };
83
84 tbi0: tbi-phy@11 {
85 reg = <0x1f>;
86 device_type = "tbi-phy";
87 };
88 };
89
90 enet0: ethernet@b0000 {
91 phy-handle = <&phy0>;
92 tbi-handle = <&tbi0>;
93 phy-connection-type = "sgmii";
94 };
95
96 enet1: ethernet@b1000 {
97 phy-handle = <&phy1>;
98 tbi-handle = <&tbi0>;
99 phy-connection-type = "sgmii";
100 };
101};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f9927be..d67894459ac8 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
76 compatible = "fsl,b4420-l3-cache-controller", "cache"; 76 compatible = "fsl,b4420-l3-cache-controller", "cache";
77 }; 77 };
78 78
79 corenet-cf@18000 {
80 compatible = "fsl,b4420-corenet-cf";
81 };
82
83 guts: global-utilities@e0000 { 79 guts: global-utilities@e0000 {
84 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; 80 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85 }; 81 };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 2419731c2c54..338af7e39dd9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -66,12 +66,14 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 }; 78 };
77}; 79};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b05117..582381dba1d7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
120 compatible = "fsl,b4860-l3-cache-controller", "cache"; 120 compatible = "fsl,b4860-l3-cache-controller", "cache";
121 }; 121 };
122 122
123 corenet-cf@18000 {
124 compatible = "fsl,b4860-corenet-cf";
125 };
126
127 guts: global-utilities@e0000 { 123 guts: global-utilities@e0000 {
128 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; 124 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
129 }; 125 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 142ac862cacf..1948f73fd26b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -66,24 +66,28 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 cpu2: PowerPC,e6500@4 { 78 cpu2: PowerPC,e6500@4 {
77 device_type = "cpu"; 79 device_type = "cpu";
78 reg = <4 5>; 80 reg = <4 5>;
79 clocks = <&mux0>; 81 clocks = <&mux0>;
80 next-level-cache = <&L2>; 82 next-level-cache = <&L2>;
83 fsl,portid-mapping = <0x80000000>;
81 }; 84 };
82 cpu3: PowerPC,e6500@6 { 85 cpu3: PowerPC,e6500@6 {
83 device_type = "cpu"; 86 device_type = "cpu";
84 reg = <6 7>; 87 reg = <6 7>;
85 clocks = <&mux0>; 88 clocks = <&mux0>;
86 next-level-cache = <&L2>; 89 next-level-cache = <&L2>;
90 fsl,portid-mapping = <0x80000000>;
87 }; 91 };
88 }; 92 };
89}; 93};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e48277c46..1a54ba71f685 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
158 }; 158 };
159 159
160 corenet-cf@18000 { 160 corenet-cf@18000 {
161 compatible = "fsl,b4-corenet-cf"; 161 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
162 reg = <0x18000 0x1000>; 162 reg = <0x18000 0x1000>;
163 interrupts = <16 2 1 0>; 163 interrupts = <16 2 1 0>;
164 fsl,ccf-num-csdids = <32>; 164 fsl,ccf-num-csdids = <32>;
@@ -168,6 +168,7 @@
168 iommu@20000 { 168 iommu@20000 {
169 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 169 compatible = "fsl,pamu-v1.0", "fsl,pamu";
170 reg = <0x20000 0x4000>; 170 reg = <0x20000 0x4000>;
171 fsl,portid-mapping = <0x8000>;
171 #address-cells = <1>; 172 #address-cells = <1>;
172 #size-cells = <1>; 173 #size-cells = <1>;
173 interrupts = < 174 interrupts = <
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
new file mode 100644
index 000000000000..c72307198140
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
@@ -0,0 +1,185 @@
1/*
2 * BSC9132 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 /* FIXME: Test whether interrupts are split */
40 interrupts = <16 2 0 0 20 2 0 0>;
41};
42
43&soc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "soc";
47 compatible = "fsl,bsc9132-immr", "simple-bus";
48 bus-frequency = <0>; // Filled out by uboot.
49
50 ecm-law@0 {
51 compatible = "fsl,ecm-law";
52 reg = <0x0 0x1000>;
53 fsl,num-laws = <12>;
54 };
55
56 ecm@1000 {
57 compatible = "fsl,bsc9132-ecm", "fsl,ecm";
58 reg = <0x1000 0x1000>;
59 interrupts = <16 2 0 0>;
60 };
61
62 memory-controller@2000 {
63 compatible = "fsl,bsc9132-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupts = <16 2 1 8>;
66 };
67
68/include/ "pq3-i2c-0.dtsi"
69 i2c@3000 {
70 interrupts = <17 2 0 0>;
71 };
72
73/include/ "pq3-i2c-1.dtsi"
74 i2c@3100 {
75 interrupts = <17 2 0 0>;
76 };
77
78/include/ "pq3-duart-0.dtsi"
79 serial0: serial@4500 {
80 interrupts = <18 2 0 0>;
81 };
82
83 serial1: serial@4600 {
84 interrupts = <18 2 0 0 >;
85 };
86/include/ "pq3-espi-0.dtsi"
87 spi0: spi@7000 {
88 fsl,espi-num-chipselects = <1>;
89 interrupts = <22 0x2 0 0>;
90 };
91
92/include/ "pq3-gpio-0.dtsi"
93 gpio-controller@f000 {
94 interrupts = <19 0x2 0 0>;
95 };
96
97 L2: l2-cache-controller@20000 {
98 compatible = "fsl,bsc9132-l2-cache-controller";
99 reg = <0x20000 0x1000>;
100 cache-line-size = <32>; // 32 bytes
101 cache-size = <0x40000>; // L2,256K
102 interrupts = <16 2 1 0>;
103 };
104
105/include/ "pq3-dma-0.dtsi"
106
107dma@21300 {
108
109 dma-channel@0 {
110 interrupts = <62 2 0 0>;
111 };
112
113 dma-channel@80 {
114 interrupts = <63 2 0 0>;
115 };
116
117 dma-channel@100 {
118 interrupts = <64 2 0 0>;
119 };
120
121 dma-channel@180 {
122 interrupts = <65 2 0 0>;
123 };
124};
125
126/include/ "pq3-usb2-dr-0.dtsi"
127usb@22000 {
128 compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
129 interrupts = <40 0x2 0 0>;
130};
131
132/include/ "pq3-esdhc-0.dtsi"
133 sdhc@2e000 {
134 fsl,sdhci-auto-cmd12;
135 interrupts = <41 0x2 0 0>;
136 };
137
138/include/ "pq3-sec4.4-0.dtsi"
139crypto@30000 {
140 interrupts = <57 2 0 0>;
141
142 sec_jr0: jr@1000 {
143 interrupts = <58 2 0 0>;
144 };
145
146 sec_jr1: jr@2000 {
147 interrupts = <59 2 0 0>;
148 };
149
150 sec_jr2: jr@3000 {
151 interrupts = <60 2 0 0>;
152 };
153
154 sec_jr3: jr@4000 {
155 interrupts = <61 2 0 0>;
156 };
157};
158
159/include/ "pq3-mpic.dtsi"
160/include/ "pq3-mpic-timer-B.dtsi"
161
162/include/ "pq3-etsec2-0.dtsi"
163enet0: ethernet@b0000 {
164 queue-group@b0000 {
165 fsl,rx-bit-map = <0xff>;
166 fsl,tx-bit-map = <0xff>;
167 interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
168 };
169};
170
171/include/ "pq3-etsec2-1.dtsi"
172enet1: ethernet@b1000 {
173 queue-group@b1000 {
174 fsl,rx-bit-map = <0xff>;
175 fsl,tx-bit-map = <0xff>;
176 interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
177 };
178};
179
180global-utilities@e0000 {
181 compatible = "fsl,bsc9132-guts";
182 reg = <0xe0000 0x1000>;
183 fsl,has-rstcr;
184 };
185};
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
new file mode 100644
index 000000000000..301a9dba5790
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
@@ -0,0 +1,66 @@
1/*
2 * BSC9132 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
39/ {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 serial0 = &serial0;
46 ethernet0 = &enet0;
47 ethernet1 = &enet1;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: PowerPC,e500v2@0 {
55 device_type = "cpu";
56 reg = <0x0>;
57 next-level-cache = <&L2>;
58 };
59
60 cpu1: PowerPC,e500v2@1 {
61 device_type = "cpu";
62 reg = <0x1>;
63 next-level-cache = <&L2>;
64 };
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a33083c..5290df83ff30 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -246,7 +246,7 @@
246 }; 246 };
247 247
248 corenet-cf@18000 { 248 corenet-cf@18000 {
249 compatible = "fsl,corenet-cf"; 249 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
250 reg = <0x18000 0x1000>; 250 reg = <0x18000 0x1000>;
251 interrupts = <16 2 1 31>; 251 interrupts = <16 2 1 31>;
252 fsl,ccf-num-csdids = <32>; 252 fsl,ccf-num-csdids = <32>;
@@ -262,6 +262,7 @@
262 interrupts = < 262 interrupts = <
263 24 2 0 0 263 24 2 0 0
264 16 2 1 30>; 264 16 2 1 30>;
265 fsl,portid-mapping = <0x0f000000>;
265 266
266 pamu0: pamu@0 { 267 pamu0: pamu@0 {
267 reg = <0 0x1000>; 268 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 22f3b14517de..b1ea147f2995 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 7af6d45fd998..cd63cb1b1042 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -273,7 +273,7 @@
273 }; 273 };
274 274
275 corenet-cf@18000 { 275 corenet-cf@18000 {
276 compatible = "fsl,corenet-cf"; 276 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
277 reg = <0x18000 0x1000>; 277 reg = <0x18000 0x1000>;
278 interrupts = <16 2 1 31>; 278 interrupts = <16 2 1 31>;
279 fsl,ccf-num-csdids = <32>; 279 fsl,ccf-num-csdids = <32>;
@@ -289,6 +289,7 @@
289 interrupts = < 289 interrupts = <
290 24 2 0 0 290 24 2 0 0
291 16 2 1 30>; 291 16 2 1 30>;
292 fsl,portid-mapping = <0x0f000000>;
292 293
293 pamu0: pamu@0 { 294 pamu0: pamu@0 {
294 reg = <0 0x1000>; 295 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 468e8be8ac6f..dc5f4b362c24 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -84,6 +84,7 @@
84 reg = <0>; 84 reg = <0>;
85 clocks = <&mux0>; 85 clocks = <&mux0>;
86 next-level-cache = <&L2_0>; 86 next-level-cache = <&L2_0>;
87 fsl,portid-mapping = <0x80000000>;
87 L2_0: l2-cache { 88 L2_0: l2-cache {
88 next-level-cache = <&cpc>; 89 next-level-cache = <&cpc>;
89 }; 90 };
@@ -93,6 +94,7 @@
93 reg = <1>; 94 reg = <1>;
94 clocks = <&mux1>; 95 clocks = <&mux1>;
95 next-level-cache = <&L2_1>; 96 next-level-cache = <&L2_1>;
97 fsl,portid-mapping = <0x40000000>;
96 L2_1: l2-cache { 98 L2_1: l2-cache {
97 next-level-cache = <&cpc>; 99 next-level-cache = <&cpc>;
98 }; 100 };
@@ -102,6 +104,7 @@
102 reg = <2>; 104 reg = <2>;
103 clocks = <&mux2>; 105 clocks = <&mux2>;
104 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x20000000>;
105 L2_2: l2-cache { 108 L2_2: l2-cache {
106 next-level-cache = <&cpc>; 109 next-level-cache = <&cpc>;
107 }; 110 };
@@ -111,6 +114,7 @@
111 reg = <3>; 114 reg = <3>;
112 clocks = <&mux3>; 115 clocks = <&mux3>;
113 next-level-cache = <&L2_3>; 116 next-level-cache = <&L2_3>;
117 fsl,portid-mapping = <0x10000000>;
114 L2_3: l2-cache { 118 L2_3: l2-cache {
115 next-level-cache = <&cpc>; 119 next-level-cache = <&cpc>;
116 }; 120 };
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 2415e1f1d3fa..12947ccddf25 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -281,7 +281,7 @@
281 }; 281 };
282 282
283 corenet-cf@18000 { 283 corenet-cf@18000 {
284 compatible = "fsl,corenet-cf"; 284 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
285 reg = <0x18000 0x1000>; 285 reg = <0x18000 0x1000>;
286 interrupts = <16 2 1 31>; 286 interrupts = <16 2 1 31>;
287 fsl,ccf-num-csdids = <32>; 287 fsl,ccf-num-csdids = <32>;
@@ -297,6 +297,7 @@
297 interrupts = < 297 interrupts = <
298 24 2 0 0 298 24 2 0 0
299 16 2 1 30>; 299 16 2 1 30>;
300 fsl,portid-mapping = <0x00f80000>;
300 301
301 pamu0: pamu@0 { 302 pamu0: pamu@0 {
302 reg = <0 0x1000>; 303 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 0040b5a5379e..38bde0958672 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
@@ -119,6 +123,7 @@
119 reg = <4>; 123 reg = <4>;
120 clocks = <&mux4>; 124 clocks = <&mux4>;
121 next-level-cache = <&L2_4>; 125 next-level-cache = <&L2_4>;
126 fsl,portid-mapping = <0x08000000>;
122 L2_4: l2-cache { 127 L2_4: l2-cache {
123 next-level-cache = <&cpc>; 128 next-level-cache = <&cpc>;
124 }; 129 };
@@ -128,6 +133,7 @@
128 reg = <5>; 133 reg = <5>;
129 clocks = <&mux5>; 134 clocks = <&mux5>;
130 next-level-cache = <&L2_5>; 135 next-level-cache = <&L2_5>;
136 fsl,portid-mapping = <0x04000000>;
131 L2_5: l2-cache { 137 L2_5: l2-cache {
132 next-level-cache = <&cpc>; 138 next-level-cache = <&cpc>;
133 }; 139 };
@@ -137,6 +143,7 @@
137 reg = <6>; 143 reg = <6>;
138 clocks = <&mux6>; 144 clocks = <&mux6>;
139 next-level-cache = <&L2_6>; 145 next-level-cache = <&L2_6>;
146 fsl,portid-mapping = <0x02000000>;
140 L2_6: l2-cache { 147 L2_6: l2-cache {
141 next-level-cache = <&cpc>; 148 next-level-cache = <&cpc>;
142 }; 149 };
@@ -146,6 +153,7 @@
146 reg = <7>; 153 reg = <7>;
147 clocks = <&mux7>; 154 clocks = <&mux7>;
148 next-level-cache = <&L2_7>; 155 next-level-cache = <&L2_7>;
156 fsl,portid-mapping = <0x01000000>;
149 L2_7: l2-cache { 157 L2_7: l2-cache {
150 next-level-cache = <&cpc>; 158 next-level-cache = <&cpc>;
151 }; 159 };
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 2985de4ad6be..4c4a2b0436b2 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -278,7 +278,7 @@
278 }; 278 };
279 279
280 corenet-cf@18000 { 280 corenet-cf@18000 {
281 compatible = "fsl,corenet-cf"; 281 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
282 reg = <0x18000 0x1000>; 282 reg = <0x18000 0x1000>;
283 interrupts = <16 2 1 31>; 283 interrupts = <16 2 1 31>;
284 fsl,ccf-num-csdids = <32>; 284 fsl,ccf-num-csdids = <32>;
@@ -294,6 +294,7 @@
294 interrupts = < 294 interrupts = <
295 24 2 0 0 295 24 2 0 0
296 16 2 1 30>; 296 16 2 1 30>;
297 fsl,portid-mapping = <0x3c000000>;
297 298
298 pamu0: pamu@0 { 299 pamu0: pamu@0 {
299 reg = <0 0x1000>; 300 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index fe1a2e6613b4..1cc61e126e4c 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -90,6 +90,7 @@
90 reg = <0>; 90 reg = <0>;
91 clocks = <&mux0>; 91 clocks = <&mux0>;
92 next-level-cache = <&L2_0>; 92 next-level-cache = <&L2_0>;
93 fsl,portid-mapping = <0x80000000>;
93 L2_0: l2-cache { 94 L2_0: l2-cache {
94 next-level-cache = <&cpc>; 95 next-level-cache = <&cpc>;
95 }; 96 };
@@ -99,6 +100,7 @@
99 reg = <1>; 100 reg = <1>;
100 clocks = <&mux1>; 101 clocks = <&mux1>;
101 next-level-cache = <&L2_1>; 102 next-level-cache = <&L2_1>;
103 fsl,portid-mapping = <0x40000000>;
102 L2_1: l2-cache { 104 L2_1: l2-cache {
103 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
104 }; 106 };
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 546a899efe20..67296fdd9698 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -233,7 +233,7 @@
233 }; 233 };
234 234
235 corenet-cf@18000 { 235 corenet-cf@18000 {
236 compatible = "fsl,corenet-cf"; 236 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
237 reg = <0x18000 0x1000>; 237 reg = <0x18000 0x1000>;
238 interrupts = <16 2 1 31>; 238 interrupts = <16 2 1 31>;
239 fsl,ccf-num-csdids = <32>; 239 fsl,ccf-num-csdids = <32>;
@@ -248,6 +248,7 @@
248 #size-cells = <1>; 248 #size-cells = <1>;
249 interrupts = <24 2 0 0 249 interrupts = <24 2 0 0
250 16 2 1 30>; 250 16 2 1 30>;
251 fsl,portid-mapping = <0x0f800000>;
251 252
252 pamu0: pamu@0 { 253 pamu0: pamu@0 {
253 reg = <0 0x1000>; 254 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 3674686687cb..b048a2be05a8 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000000000000..12e597eea3c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,430 @@
1/*
2 * T1040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42&pci0 {
43 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
44 device_type = "pci";
45 #size-cells = <2>;
46 #address-cells = <3>;
47 bus-range = <0x0 0xff>;
48 interrupts = <20 2 0 0>;
49 fsl,iommu-parent = <&pamu0>;
50 pcie@0 {
51 reg = <0 0 0 0 0>;
52 #interrupt-cells = <1>;
53 #size-cells = <2>;
54 #address-cells = <3>;
55 device_type = "pci";
56 interrupts = <20 2 0 0>;
57 interrupt-map-mask = <0xf800 0 0 7>;
58 interrupt-map = <
59 /* IDSEL 0x0 */
60 0000 0 0 1 &mpic 40 1 0 0
61 0000 0 0 2 &mpic 1 1 0 0
62 0000 0 0 3 &mpic 2 1 0 0
63 0000 0 0 4 &mpic 3 1 0 0
64 >;
65 };
66};
67
68&pci1 {
69 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
70 device_type = "pci";
71 #size-cells = <2>;
72 #address-cells = <3>;
73 bus-range = <0 0xff>;
74 interrupts = <21 2 0 0>;
75 fsl,iommu-parent = <&pamu0>;
76 pcie@0 {
77 reg = <0 0 0 0 0>;
78 #interrupt-cells = <1>;
79 #size-cells = <2>;
80 #address-cells = <3>;
81 device_type = "pci";
82 interrupts = <21 2 0 0>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <
85 /* IDSEL 0x0 */
86 0000 0 0 1 &mpic 41 1 0 0
87 0000 0 0 2 &mpic 5 1 0 0
88 0000 0 0 3 &mpic 6 1 0 0
89 0000 0 0 4 &mpic 7 1 0 0
90 >;
91 };
92};
93
94&pci2 {
95 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
96 device_type = "pci";
97 #size-cells = <2>;
98 #address-cells = <3>;
99 bus-range = <0x0 0xff>;
100 interrupts = <22 2 0 0>;
101 fsl,iommu-parent = <&pamu0>;
102 pcie@0 {
103 reg = <0 0 0 0 0>;
104 #interrupt-cells = <1>;
105 #size-cells = <2>;
106 #address-cells = <3>;
107 device_type = "pci";
108 interrupts = <22 2 0 0>;
109 interrupt-map-mask = <0xf800 0 0 7>;
110 interrupt-map = <
111 /* IDSEL 0x0 */
112 0000 0 0 1 &mpic 42 1 0 0
113 0000 0 0 2 &mpic 9 1 0 0
114 0000 0 0 3 &mpic 10 1 0 0
115 0000 0 0 4 &mpic 11 1 0 0
116 >;
117 };
118};
119
120&pci3 {
121 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
122 device_type = "pci";
123 #size-cells = <2>;
124 #address-cells = <3>;
125 bus-range = <0x0 0xff>;
126 interrupts = <23 2 0 0>;
127 fsl,iommu-parent = <&pamu0>;
128 pcie@0 {
129 reg = <0 0 0 0 0>;
130 #interrupt-cells = <1>;
131 #size-cells = <2>;
132 #address-cells = <3>;
133 device_type = "pci";
134 interrupts = <23 2 0 0>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map = <
137 /* IDSEL 0x0 */
138 0000 0 0 1 &mpic 43 1 0 0
139 0000 0 0 2 &mpic 0 1 0 0
140 0000 0 0 3 &mpic 4 1 0 0
141 0000 0 0 4 &mpic 8 1 0 0
142 >;
143 };
144};
145
146&dcsr {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,dcsr", "simple-bus";
150
151 dcsr-epu@0 {
152 compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
153 interrupts = <52 2 0 0
154 84 2 0 0
155 85 2 0 0>;
156 reg = <0x0 0x1000>;
157 };
158 dcsr-npc {
159 compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
160 reg = <0x1000 0x1000 0x1002000 0x10000>;
161 };
162 dcsr-nxc@2000 {
163 compatible = "fsl,dcsr-nxc";
164 reg = <0x2000 0x1000>;
165 };
166 dcsr-corenet {
167 compatible = "fsl,dcsr-corenet";
168 reg = <0x8000 0x1000 0x1A000 0x1000>;
169 };
170 dcsr-dpaa@9000 {
171 compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
172 reg = <0x9000 0x1000>;
173 };
174 dcsr-ocn@11000 {
175 compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
176 reg = <0x11000 0x1000>;
177 };
178 dcsr-ddr@12000 {
179 compatible = "fsl,dcsr-ddr";
180 dev-handle = <&ddr1>;
181 reg = <0x12000 0x1000>;
182 };
183 dcsr-nal@18000 {
184 compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
185 reg = <0x18000 0x1000>;
186 };
187 dcsr-rcpm@22000 {
188 compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
189 reg = <0x22000 0x1000>;
190 };
191 dcsr-snpc@30000 {
192 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
193 reg = <0x30000 0x1000 0x1022000 0x10000>;
194 };
195 dcsr-snpc@31000 {
196 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
197 reg = <0x31000 0x1000 0x1042000 0x10000>;
198 };
199 dcsr-cpu-sb-proxy@100000 {
200 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
201 cpu-handle = <&cpu0>;
202 reg = <0x100000 0x1000 0x101000 0x1000>;
203 };
204 dcsr-cpu-sb-proxy@108000 {
205 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
206 cpu-handle = <&cpu1>;
207 reg = <0x108000 0x1000 0x109000 0x1000>;
208 };
209 dcsr-cpu-sb-proxy@110000 {
210 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
211 cpu-handle = <&cpu2>;
212 reg = <0x110000 0x1000 0x111000 0x1000>;
213 };
214 dcsr-cpu-sb-proxy@118000 {
215 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
216 cpu-handle = <&cpu3>;
217 reg = <0x118000 0x1000 0x119000 0x1000>;
218 };
219};
220
221&soc {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 device_type = "soc";
225 compatible = "simple-bus";
226
227 soc-sram-error {
228 compatible = "fsl,soc-sram-error";
229 interrupts = <16 2 1 29>;
230 };
231
232 corenet-law@0 {
233 compatible = "fsl,corenet-law";
234 reg = <0x0 0x1000>;
235 fsl,num-laws = <16>;
236 };
237
238 ddr1: memory-controller@8000 {
239 compatible = "fsl,qoriq-memory-controller-v5.0",
240 "fsl,qoriq-memory-controller";
241 reg = <0x8000 0x1000>;
242 interrupts = <16 2 1 23>;
243 };
244
245 cpc: l3-cache-controller@10000 {
246 compatible = "fsl,t1040-l3-cache-controller", "cache";
247 reg = <0x10000 0x1000>;
248 interrupts = <16 2 1 27>;
249 };
250
251 corenet-cf@18000 {
252 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
253 reg = <0x18000 0x1000>;
254 interrupts = <16 2 1 31>;
255 fsl,ccf-num-csdids = <32>;
256 fsl,ccf-num-snoopids = <32>;
257 };
258
259 iommu@20000 {
260 compatible = "fsl,pamu-v1.0", "fsl,pamu";
261 reg = <0x20000 0x1000>;
262 ranges = <0 0x20000 0x1000>;
263 #address-cells = <1>;
264 #size-cells = <1>;
265 interrupts = <
266 24 2 0 0
267 16 2 1 30>;
268 pamu0: pamu@0 {
269 reg = <0 0x1000>;
270 fsl,primary-cache-geometry = <128 1>;
271 fsl,secondary-cache-geometry = <16 2>;
272 };
273 };
274
275/include/ "qoriq-mpic.dtsi"
276
277 guts: global-utilities@e0000 {
278 compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
279 reg = <0xe0000 0xe00>;
280 fsl,has-rstcr;
281 fsl,liodn-bits = <12>;
282 };
283
284 clockgen: global-utilities@e1000 {
285 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
286 ranges = <0x0 0xe1000 0x1000>;
287 reg = <0xe1000 0x1000>;
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 sysclk: sysclk {
292 #clock-cells = <0>;
293 compatible = "fsl,qoriq-sysclk-2.0";
294 clock-output-names = "sysclk", "fixed-clock";
295 };
296
297
298 pll0: pll0@800 {
299 #clock-cells = <1>;
300 reg = <0x800 4>;
301 compatible = "fsl,qoriq-core-pll-2.0";
302 clocks = <&sysclk>;
303 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
304 };
305
306 pll1: pll1@820 {
307 #clock-cells = <1>;
308 reg = <0x820 4>;
309 compatible = "fsl,qoriq-core-pll-2.0";
310 clocks = <&sysclk>;
311 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
312 };
313
314 mux0: mux0@0 {
315 #clock-cells = <0>;
316 reg = <0x0 4>;
317 compatible = "fsl,qoriq-core-mux-2.0";
318 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
319 <&pll1 0>, <&pll1 1>, <&pll1 2>;
320 clock-names = "pll0", "pll0-div2", "pll1-div4",
321 "pll1", "pll1-div2", "pll1-div4";
322 clock-output-names = "cmux0";
323 };
324
325 mux1: mux1@20 {
326 #clock-cells = <0>;
327 reg = <0x20 4>;
328 compatible = "fsl,qoriq-core-mux-2.0";
329 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
330 <&pll1 0>, <&pll1 1>, <&pll1 2>;
331 clock-names = "pll0", "pll0-div2", "pll1-div4",
332 "pll1", "pll1-div2", "pll1-div4";
333 clock-output-names = "cmux1";
334 };
335
336 mux2: mux2@40 {
337 #clock-cells = <0>;
338 reg = <0x40 4>;
339 compatible = "fsl,qoriq-core-mux-2.0";
340 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
341 <&pll1 0>, <&pll1 1>, <&pll1 2>;
342 clock-names = "pll0", "pll0-div2", "pll1-div4",
343 "pll1", "pll1-div2", "pll1-div4";
344 clock-output-names = "cmux2";
345 };
346
347 mux3: mux3@60 {
348 #clock-cells = <0>;
349 reg = <0x60 4>;
350 compatible = "fsl,qoriq-core-mux-2.0";
351 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
352 <&pll1 0>, <&pll1 1>, <&pll1 2>;
353 clock-names = "pll0_0", "pll0_1", "pll0_2",
354 "pll1_0", "pll1_1", "pll1_2";
355 clock-output-names = "cmux3";
356 };
357 };
358
359 rcpm: global-utilities@e2000 {
360 compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0";
361 reg = <0xe2000 0x1000>;
362 };
363
364 sfp: sfp@e8000 {
365 compatible = "fsl,t1040-sfp";
366 reg = <0xe8000 0x1000>;
367 };
368
369 serdes: serdes@ea000 {
370 compatible = "fsl,t1040-serdes";
371 reg = <0xea000 0x4000>;
372 };
373
374/include/ "elo3-dma-0.dtsi"
375/include/ "elo3-dma-1.dtsi"
376/include/ "qoriq-espi-0.dtsi"
377 spi@110000 {
378 fsl,espi-num-chipselects = <4>;
379 };
380
381/include/ "qoriq-esdhc-0.dtsi"
382 sdhc@114000 {
383 compatible = "fsl,t1040-esdhc", "fsl,esdhc";
384 fsl,iommu-parent = <&pamu0>;
385 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
386 sdhci,auto-cmd12;
387 };
388/include/ "qoriq-i2c-0.dtsi"
389/include/ "qoriq-i2c-1.dtsi"
390/include/ "qoriq-duart-0.dtsi"
391/include/ "qoriq-duart-1.dtsi"
392/include/ "qoriq-gpio-0.dtsi"
393/include/ "qoriq-gpio-1.dtsi"
394/include/ "qoriq-gpio-2.dtsi"
395/include/ "qoriq-gpio-3.dtsi"
396/include/ "qoriq-usb2-mph-0.dtsi"
397 usb0: usb@210000 {
398 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
399 fsl,iommu-parent = <&pamu0>;
400 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
401 phy_type = "utmi";
402 port0;
403 };
404/include/ "qoriq-usb2-dr-0.dtsi"
405 usb1: usb@211000 {
406 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
407 fsl,iommu-parent = <&pamu0>;
408 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
409 dr_mode = "host";
410 phy_type = "utmi";
411 };
412
413 display@180000 {
414 compatible = "fsl,t1040-diu", "fsl,diu";
415 reg = <0x180000 1000>;
416 interrupts = <74 2 0 0>;
417 };
418
419/include/ "qoriq-sata2-0.dtsi"
420 sata@220000 {
421 fsl,iommu-parent = <&pamu0>;
422 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
423 };
424/include/ "qoriq-sata2-1.dtsi"
425 sata@221000 {
426 fsl,iommu-parent = <&pamu0>;
427 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
428 };
429/include/ "qoriq-sec5.0-0.dtsi"
430};
diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
new file mode 100644
index 000000000000..319b74f29724
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -0,0 +1,37 @@
1/*
2 * T1042 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "t1040si-post.dtsi"
36
37/* Place holder for ethernet related device tree nodes */
diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
new file mode 100644
index 000000000000..bbb7025ca9c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -0,0 +1,104 @@
1/*
2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e5500_power_isa.dtsi"
38
39/ {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46 dcsr = &dcsr;
47
48 serial0 = &serial0;
49 serial1 = &serial1;
50 serial2 = &serial2;
51 serial3 = &serial3;
52 pci0 = &pci0;
53 pci1 = &pci1;
54 pci2 = &pci2;
55 pci3 = &pci3;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 sdhc = &sdhc;
59
60 crypto = &crypto;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,e5500@0 {
68 device_type = "cpu";
69 reg = <0>;
70 clocks = <&mux0>;
71 next-level-cache = <&L2_1>;
72 L2_1: l2-cache {
73 next-level-cache = <&cpc>;
74 };
75 };
76 cpu1: PowerPC,e5500@1 {
77 device_type = "cpu";
78 reg = <1>;
79 clocks = <&mux1>;
80 next-level-cache = <&L2_2>;
81 L2_2: l2-cache {
82 next-level-cache = <&cpc>;
83 };
84 };
85 cpu2: PowerPC,e5500@2 {
86 device_type = "cpu";
87 reg = <2>;
88 clocks = <&mux2>;
89 next-level-cache = <&L2_3>;
90 L2_3: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu3: PowerPC,e5500@3 {
95 device_type = "cpu";
96 reg = <3>;
97 clocks = <&mux3>;
98 next-level-cache = <&L2_4>;
99 L2_4: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 };
104};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74ff11b4..793669baa13e 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
343 }; 343 };
344 344
345 corenet-cf@18000 { 345 corenet-cf@18000 {
346 compatible = "fsl,corenet-cf"; 346 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
347 reg = <0x18000 0x1000>; 347 reg = <0x18000 0x1000>;
348 interrupts = <16 2 1 31>; 348 interrupts = <16 2 1 31>;
349 fsl,ccf-num-csdids = <32>; 349 fsl,ccf-num-csdids = <32>;
@@ -353,6 +353,7 @@
353 iommu@20000 { 353 iommu@20000 {
354 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 354 compatible = "fsl,pamu-v1.0", "fsl,pamu";
355 reg = <0x20000 0x6000>; 355 reg = <0x20000 0x6000>;
356 fsl,portid-mapping = <0x8000>;
356 interrupts = < 357 interrupts = <
357 24 2 0 0 358 24 2 0 0
358 16 2 1 30>; 359 16 2 1 30>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 0b8ccc5b4a46..d2f157edbe81 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,72 +69,84 @@
69 reg = <0 1>; 69 reg = <0 1>;
70 clocks = <&mux0>; 70 clocks = <&mux0>;
71 next-level-cache = <&L2_1>; 71 next-level-cache = <&L2_1>;
72 fsl,portid-mapping = <0x80000000>;
72 }; 73 };
73 cpu1: PowerPC,e6500@2 { 74 cpu1: PowerPC,e6500@2 {
74 device_type = "cpu"; 75 device_type = "cpu";
75 reg = <2 3>; 76 reg = <2 3>;
76 clocks = <&mux0>; 77 clocks = <&mux0>;
77 next-level-cache = <&L2_1>; 78 next-level-cache = <&L2_1>;
79 fsl,portid-mapping = <0x80000000>;
78 }; 80 };
79 cpu2: PowerPC,e6500@4 { 81 cpu2: PowerPC,e6500@4 {
80 device_type = "cpu"; 82 device_type = "cpu";
81 reg = <4 5>; 83 reg = <4 5>;
82 clocks = <&mux0>; 84 clocks = <&mux0>;
83 next-level-cache = <&L2_1>; 85 next-level-cache = <&L2_1>;
86 fsl,portid-mapping = <0x80000000>;
84 }; 87 };
85 cpu3: PowerPC,e6500@6 { 88 cpu3: PowerPC,e6500@6 {
86 device_type = "cpu"; 89 device_type = "cpu";
87 reg = <6 7>; 90 reg = <6 7>;
88 clocks = <&mux0>; 91 clocks = <&mux0>;
89 next-level-cache = <&L2_1>; 92 next-level-cache = <&L2_1>;
93 fsl,portid-mapping = <0x80000000>;
90 }; 94 };
91 cpu4: PowerPC,e6500@8 { 95 cpu4: PowerPC,e6500@8 {
92 device_type = "cpu"; 96 device_type = "cpu";
93 reg = <8 9>; 97 reg = <8 9>;
94 clocks = <&mux1>; 98 clocks = <&mux1>;
95 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
96 }; 101 };
97 cpu5: PowerPC,e6500@10 { 102 cpu5: PowerPC,e6500@10 {
98 device_type = "cpu"; 103 device_type = "cpu";
99 reg = <10 11>; 104 reg = <10 11>;
100 clocks = <&mux1>; 105 clocks = <&mux1>;
101 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x40000000>;
102 }; 108 };
103 cpu6: PowerPC,e6500@12 { 109 cpu6: PowerPC,e6500@12 {
104 device_type = "cpu"; 110 device_type = "cpu";
105 reg = <12 13>; 111 reg = <12 13>;
106 clocks = <&mux1>; 112 clocks = <&mux1>;
107 next-level-cache = <&L2_2>; 113 next-level-cache = <&L2_2>;
114 fsl,portid-mapping = <0x40000000>;
108 }; 115 };
109 cpu7: PowerPC,e6500@14 { 116 cpu7: PowerPC,e6500@14 {
110 device_type = "cpu"; 117 device_type = "cpu";
111 reg = <14 15>; 118 reg = <14 15>;
112 clocks = <&mux1>; 119 clocks = <&mux1>;
113 next-level-cache = <&L2_2>; 120 next-level-cache = <&L2_2>;
121 fsl,portid-mapping = <0x40000000>;
114 }; 122 };
115 cpu8: PowerPC,e6500@16 { 123 cpu8: PowerPC,e6500@16 {
116 device_type = "cpu"; 124 device_type = "cpu";
117 reg = <16 17>; 125 reg = <16 17>;
118 clocks = <&mux2>; 126 clocks = <&mux2>;
119 next-level-cache = <&L2_3>; 127 next-level-cache = <&L2_3>;
128 fsl,portid-mapping = <0x20000000>;
120 }; 129 };
121 cpu9: PowerPC,e6500@18 { 130 cpu9: PowerPC,e6500@18 {
122 device_type = "cpu"; 131 device_type = "cpu";
123 reg = <18 19>; 132 reg = <18 19>;
124 clocks = <&mux2>; 133 clocks = <&mux2>;
125 next-level-cache = <&L2_3>; 134 next-level-cache = <&L2_3>;
135 fsl,portid-mapping = <0x20000000>;
126 }; 136 };
127 cpu10: PowerPC,e6500@20 { 137 cpu10: PowerPC,e6500@20 {
128 device_type = "cpu"; 138 device_type = "cpu";
129 reg = <20 21>; 139 reg = <20 21>;
130 clocks = <&mux2>; 140 clocks = <&mux2>;
131 next-level-cache = <&L2_3>; 141 next-level-cache = <&L2_3>;
142 fsl,portid-mapping = <0x20000000>;
132 }; 143 };
133 cpu11: PowerPC,e6500@22 { 144 cpu11: PowerPC,e6500@22 {
134 device_type = "cpu"; 145 device_type = "cpu";
135 reg = <22 23>; 146 reg = <22 23>;
136 clocks = <&mux2>; 147 clocks = <&mux2>;
137 next-level-cache = <&L2_3>; 148 next-level-cache = <&L2_3>;
149 fsl,portid-mapping = <0x20000000>;
138 }; 150 };
139 }; 151 };
140}; 152};
diff --git a/arch/powerpc/boot/dts/kmcoge4.dts b/arch/powerpc/boot/dts/kmcoge4.dts
new file mode 100644
index 000000000000..89b4119f3b19
--- /dev/null
+++ b/arch/powerpc/boot/dts/kmcoge4.dts
@@ -0,0 +1,152 @@
1/*
2 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
3 *
4 * (C) Copyright 2014
5 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
6 *
7 * Copyright 2011 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/include/ "fsl/p2041si-pre.dtsi"
16
17/ {
18 model = "keymile,kmcoge4";
19 compatible = "keymile,kmcoge4", "keymile,kmp204x";
20 #address-cells = <2>;
21 #size-cells = <2>;
22 interrupt-parent = <&mpic>;
23
24 memory {
25 device_type = "memory";
26 };
27
28 dcsr: dcsr@f00000000 {
29 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
30 };
31
32 soc: soc@ffe000000 {
33 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
34 reg = <0xf 0xfe000000 0 0x00001000>;
35 spi@110000 {
36 flash@0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "spansion,s25fl256s1";
40 reg = <0>;
41 spi-max-frequency = <20000000>; /* input clock */
42 };
43
44 network_clock@1 {
45 compatible = "zarlink,zl30343";
46 reg = <1>;
47 spi-max-frequency = <8000000>;
48 };
49
50 flash@2 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "micron,m25p32";
54 reg = <2>;
55 spi-max-frequency = <15000000>;
56 };
57 };
58
59 i2c@119000 {
60 status = "disabled";
61 };
62
63 i2c@119100 {
64 status = "disabled";
65 };
66
67 usb0: usb@210000 {
68 status = "disabled";
69 };
70
71 usb1: usb@211000 {
72 status = "disabled";
73 };
74
75 sata@220000 {
76 status = "disabled";
77 };
78
79 sata@221000 {
80 status = "disabled";
81 };
82 };
83
84 rio: rapidio@ffe0c0000 {
85 status = "disabled";
86 };
87
88 lbc: localbus@ffe124000 {
89 reg = <0xf 0xfe124000 0 0x1000>;
90 ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
91 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
92 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
93 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
94
95 nand@0,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "fsl,elbc-fcm-nand";
99 reg = <0 0 0x40000>;
100 };
101
102 board-control@1,0 {
103 compatible = "keymile,qriox";
104 reg = <1 0 0x80>;
105 };
106
107 chassis-mgmt@3,0 {
108 compatible = "keymile,bfticu";
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 reg = <3 0 0x100>;
112 interrupt-parent = <&mpic>;
113 interrupts = <6 1 0 0>;
114 };
115 };
116
117 pci0: pcie@ffe200000 {
118 reg = <0xf 0xfe200000 0 0x1000>;
119 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
120 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
121 pcie@0 {
122 ranges = <0x02000000 0 0xe0000000
123 0x02000000 0 0xe0000000
124 0 0x20000000
125
126 0x01000000 0 0x00000000
127 0x01000000 0 0x00000000
128 0 0x00010000>;
129 };
130 };
131
132 pci1: pcie@ffe201000 {
133 status = "disabled";
134 };
135
136 pci2: pcie@ffe202000 {
137 reg = <0xf 0xfe202000 0 0x1000>;
138 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
139 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
140 pcie@0 {
141 ranges = <0x02000000 0 0xe0000000
142 0x02000000 0 0xe0000000
143 0 0x20000000
144
145 0x01000000 0 0x00000000
146 0x01000000 0 0x00000000
147 0 0x00010000>;
148 };
149 };
150};
151
152/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/oca4080.dts b/arch/powerpc/boot/dts/oca4080.dts
new file mode 100644
index 000000000000..3d4c751d1608
--- /dev/null
+++ b/arch/powerpc/boot/dts/oca4080.dts
@@ -0,0 +1,118 @@
1/*
2 * OCA4080 Device Tree Source
3 *
4 * Copyright 2014 Prodrive Technologies B.V.
5 *
6 * Based on:
7 * P4080DS Device Tree Source
8 * Copyright 2009-2011 Freescale Semiconductor Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * * Neither the name of Freescale Semiconductor nor the
18 * names of its contributors may be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") as published by the Free Software
24 * Foundation, either version 2 of that License or (at your option) any
25 * later version.
26 *
27 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
28 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
31 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/include/ "fsl/p4080si-pre.dtsi"
40
41/ {
42 model = "fsl,OCA4080";
43 compatible = "fsl,OCA4080";
44 #address-cells = <2>;
45 #size-cells = <2>;
46 interrupt-parent = <&mpic>;
47
48 memory {
49 device_type = "memory";
50 };
51
52 dcsr: dcsr@f00000000 {
53 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
54 };
55
56 soc: soc@ffe000000 {
57 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
58 reg = <0xf 0xfe000000 0 0x00001000>;
59
60 i2c@118000 {
61 status = "disabled";
62 };
63
64 i2c@118100 {
65 status = "disabled";
66 };
67
68 i2c@119000 {
69 status = "disabled";
70 };
71
72 i2c@119100 {
73 status = "disabled";
74 };
75
76 usb0: usb@210000 {
77 status = "disabled";
78 };
79
80 usb1: usb@211000 {
81 status = "disabled";
82 };
83 };
84
85 rio: rapidio@ffe0c0000 {
86 reg = <0xf 0xfe0c0000 0 0x11000>;
87
88 port1 {
89 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
90 };
91 };
92
93 lbc: localbus@ffe124000 {
94 reg = <0xf 0xfe124000 0 0x1000>;
95 ranges = <0 0 0xf 0xef800000 0x800000>;
96
97 flash@0,0 {
98 compatible = "cfi-flash";
99 reg = <0 0 0x00800000>;
100 bank-width = <2>;
101 device-width = <2>;
102 };
103 };
104
105 pci0: pcie@ffe200000 {
106 status = "disabled";
107 };
108
109 pci1: pcie@ffe201000 {
110 status = "disabled";
111 };
112
113 pci2: pcie@ffe202000 {
114 status = "disabled";
115 };
116};
117
118/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
deleted file mode 100644
index beb6cb12e59d..000000000000
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * P1023 RDS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Author: Roy Zang <tie-fei.zang@freescale.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of Freescale Semiconductor nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation, either version 2 of that License or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
26 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/include/ "fsl/p1023si-pre.dtsi"
38
39/ {
40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>;
43 #size-cells = <2>;
44 interrupt-parent = <&mpic>;
45
46 memory {
47 device_type = "memory";
48 };
49
50 soc: soc@ff600000 {
51 ranges = <0x0 0x0 0xff600000 0x200000>;
52
53 i2c@3000 {
54 rtc@68 {
55 compatible = "dallas,ds1374";
56 reg = <0x68>;
57 };
58 };
59
60 spi@7000 {
61 fsl_dataflash@0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "atmel,at45db081d";
65 reg = <0>;
66 spi-max-frequency = <40000000>; /* input clock */
67 partition@u-boot {
68 /* 512KB for u-boot Bootloader Image */
69 label = "u-boot-spi";
70 reg = <0x00000000 0x00080000>;
71 read-only;
72 };
73 partition@dtb {
74 /* 512KB for DTB Image */
75 label = "dtb-spi";
76 reg = <0x00080000 0x00080000>;
77 read-only;
78 };
79 };
80 };
81
82 usb@22000 {
83 dr_mode = "host";
84 phy_type = "ulpi";
85 };
86 };
87
88 lbc: localbus@ff605000 {
89 reg = <0 0xff605000 0 0x1000>;
90
91 /* NOR Flash, BCSR */
92 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
93 0x1 0x0 0x0 0xe0000000 0x00008000>;
94
95 nor@0,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "cfi-flash";
99 reg = <0x0 0x0 0x02000000>;
100 bank-width = <2>;
101 device-width = <1>;
102 partition@0 {
103 label = "ramdisk";
104 reg = <0x00000000 0x01c00000>;
105 };
106 partition@1c00000 {
107 label = "kernel";
108 reg = <0x01c00000 0x002e0000>;
109 };
110 partiton@1ee0000 {
111 label = "dtb";
112 reg = <0x01ee0000 0x00020000>;
113 };
114 partition@1f00000 {
115 label = "firmware";
116 reg = <0x01f00000 0x00080000>;
117 read-only;
118 };
119 partition@1f80000 {
120 label = "u-boot";
121 reg = <0x01f80000 0x00080000>;
122 read-only;
123 };
124 };
125
126 fpga@1,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "fsl,p1023rds-fpga";
130 reg = <1 0 0x8000>;
131 ranges = <0 1 0 0x8000>;
132
133 bcsr@20 {
134 compatible = "fsl,p1023rds-bcsr";
135 reg = <0x20 0x20>;
136 };
137 };
138 };
139
140 pci0: pcie@ff60a000 {
141 reg = <0 0xff60a000 0 0x1000>;
142 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
143 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
144 pcie@0 {
145 /* IRQ[0:3] are pulled up on board, set to active-low */
146 interrupt-map-mask = <0xf800 0 0 7>;
147 interrupt-map = <
148 /* IDSEL 0x0 */
149 0000 0 0 1 &mpic 0 1 0 0
150 0000 0 0 2 &mpic 1 1 0 0
151 0000 0 0 3 &mpic 2 1 0 0
152 0000 0 0 4 &mpic 3 1 0 0
153 >;
154 ranges = <0x2000000 0x0 0xc0000000
155 0x2000000 0x0 0xc0000000
156 0x0 0x20000000
157
158 0x1000000 0x0 0x0
159 0x1000000 0x0 0x0
160 0x0 0x100000>;
161 };
162 };
163
164 board_pci1: pci1: pcie@ff609000 {
165 reg = <0 0xff609000 0 0x1000>;
166 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
167 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
168 pcie@0 {
169 /*
170 * IRQ[4:6] only for PCIe, set to active-high,
171 * IRQ[7] is pulled up on board, set to active-low
172 */
173 interrupt-map-mask = <0xf800 0 0 7>;
174 interrupt-map = <
175 /* IDSEL 0x0 */
176 0000 0 0 1 &mpic 4 2 0 0
177 0000 0 0 2 &mpic 5 2 0 0
178 0000 0 0 3 &mpic 6 2 0 0
179 0000 0 0 4 &mpic 7 1 0 0
180 >;
181 ranges = <0x2000000 0x0 0xa0000000
182 0x2000000 0x0 0xa0000000
183 0x0 0x20000000
184
185 0x1000000 0x0 0x0
186 0x1000000 0x0 0x0
187 0x0 0x100000>;
188 };
189 };
190
191 pci2: pcie@ff60b000 {
192 reg = <0 0xff60b000 0 0x1000>;
193 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
194 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
195 pcie@0 {
196 /*
197 * IRQ[8:10] are pulled up on board, set to active-low
198 * IRQ[11] only for PCIe, set to active-high,
199 */
200 interrupt-map-mask = <0xf800 0 0 7>;
201 interrupt-map = <
202 /* IDSEL 0x0 */
203 0000 0 0 1 &mpic 8 1 0 0
204 0000 0 0 2 &mpic 9 1 0 0
205 0000 0 0 3 &mpic 10 1 0 0
206 0000 0 0 4 &mpic 11 2 0 0
207 >;
208 ranges = <0x2000000 0x0 0x80000000
209 0x2000000 0x0 0x80000000
210 0x0 0x20000000
211
212 0x1000000 0x0 0x0
213 0x1000000 0x0 0x0
214 0x0 0x100000>;
215 };
216 };
217};
218
219/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1040qds.dts b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000000000000..973c29c2f56e
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
1/*
2 * T1040QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xqds.dtsi"
37
38/ {
39 model = "fsl,T1040QDS";
40 compatible = "fsl,T1040QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44};
45
46/include/ "fsl/t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1042qds.dts b/arch/powerpc/boot/dts/t1042qds.dts
new file mode 100644
index 000000000000..45bd03752154
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1042qds.dts
@@ -0,0 +1,46 @@
1/*
2 * T1042QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xqds.dtsi"
37
38/ {
39 model = "fsl,T1042QDS";
40 compatible = "fsl,T1042QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44};
45
46/include/ "fsl/t1042si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t104xqds.dtsi b/arch/powerpc/boot/dts/t104xqds.dtsi
new file mode 100644
index 000000000000..234f4b596c5b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t104xqds.dtsi
@@ -0,0 +1,166 @@
1/*
2 * T104xQDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 model = "fsl,T1040QDS";
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
40
41 ifc: localbus@ffe124000 {
42 reg = <0xf 0xfe124000 0 0x2000>;
43 ranges = <0 0 0xf 0xe8000000 0x08000000
44 2 0 0xf 0xff800000 0x00010000
45 3 0 0xf 0xffdf0000 0x00008000>;
46
47 nor@0,0 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "cfi-flash";
51 reg = <0x0 0x0 0x8000000>;
52
53 bank-width = <2>;
54 device-width = <1>;
55 };
56
57 nand@2,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "fsl,ifc-nand";
61 reg = <0x2 0x0 0x10000>;
62 };
63
64 board-control@3,0 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "fsl,fpga-qixis";
68 reg = <3 0 0x300>;
69 };
70 };
71
72 memory {
73 device_type = "memory";
74 };
75
76 dcsr: dcsr@f00000000 {
77 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
78 };
79
80 soc: soc@ffe000000 {
81 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
82 reg = <0xf 0xfe000000 0 0x00001000>;
83
84 spi@110000 {
85 flash@0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "micron,n25q128a11";
89 reg = <0>;
90 spi-max-frequency = <10000000>; /* input clock */
91 };
92 };
93
94 i2c@118000 {
95 pca9547@77 {
96 compatible = "philips,pca9547";
97 reg = <0x77>;
98 };
99 rtc@68 {
100 compatible = "dallas,ds3232";
101 reg = <0x68>;
102 interrupts = <0x1 0x1 0 0>;
103 };
104 };
105 };
106
107 pci0: pcie@ffe240000 {
108 reg = <0xf 0xfe240000 0 0x10000>;
109 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
110 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
111 pcie@0 {
112 ranges = <0x02000000 0 0xe0000000
113 0x02000000 0 0xe0000000
114 0 0x10000000
115
116 0x01000000 0 0x00000000
117 0x01000000 0 0x00000000
118 0 0x00010000>;
119 };
120 };
121
122 pci1: pcie@ffe250000 {
123 reg = <0xf 0xfe250000 0 0x10000>;
124 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
125 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
126 pcie@0 {
127 ranges = <0x02000000 0 0xe0000000
128 0x02000000 0 0xe0000000
129 0 0x10000000
130
131 0x01000000 0 0x00000000
132 0x01000000 0 0x00000000
133 0 0x00010000>;
134 };
135 };
136
137 pci2: pcie@ffe260000 {
138 reg = <0xf 0xfe260000 0 0x10000>;
139 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
140 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
141 pcie@0 {
142 ranges = <0x02000000 0 0xe0000000
143 0x02000000 0 0xe0000000
144 0 0x10000000
145
146 0x01000000 0 0x00000000
147 0x01000000 0 0x00000000
148 0 0x00010000>;
149 };
150 };
151
152 pci3: pcie@ffe270000 {
153 reg = <0xf 0xfe270000 0 0x10000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
155 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x10000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166};
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab335598..bc12127a03fb 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -60,63 +60,75 @@
60 device_type = "cpu"; 60 device_type = "cpu";
61 reg = <0 1>; 61 reg = <0 1>;
62 next-level-cache = <&L2_1>; 62 next-level-cache = <&L2_1>;
63 fsl,portid-mapping = <0x80000000>;
63 }; 64 };
64 cpu1: PowerPC,e6500@2 { 65 cpu1: PowerPC,e6500@2 {
65 device_type = "cpu"; 66 device_type = "cpu";
66 reg = <2 3>; 67 reg = <2 3>;
67 next-level-cache = <&L2_1>; 68 next-level-cache = <&L2_1>;
69 fsl,portid-mapping = <0x80000000>;
68 }; 70 };
69 cpu2: PowerPC,e6500@4 { 71 cpu2: PowerPC,e6500@4 {
70 device_type = "cpu"; 72 device_type = "cpu";
71 reg = <4 5>; 73 reg = <4 5>;
72 next-level-cache = <&L2_1>; 74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>;
73 }; 76 };
74 cpu3: PowerPC,e6500@6 { 77 cpu3: PowerPC,e6500@6 {
75 device_type = "cpu"; 78 device_type = "cpu";
76 reg = <6 7>; 79 reg = <6 7>;
77 next-level-cache = <&L2_1>; 80 next-level-cache = <&L2_1>;
81 fsl,portid-mapping = <0x80000000>;
78 }; 82 };
79 83
80 cpu4: PowerPC,e6500@8 { 84 cpu4: PowerPC,e6500@8 {
81 device_type = "cpu"; 85 device_type = "cpu";
82 reg = <8 9>; 86 reg = <8 9>;
83 next-level-cache = <&L2_2>; 87 next-level-cache = <&L2_2>;
88 fsl,portid-mapping = <0x40000000>;
84 }; 89 };
85 cpu5: PowerPC,e6500@10 { 90 cpu5: PowerPC,e6500@10 {
86 device_type = "cpu"; 91 device_type = "cpu";
87 reg = <10 11>; 92 reg = <10 11>;
88 next-level-cache = <&L2_2>; 93 next-level-cache = <&L2_2>;
94 fsl,portid-mapping = <0x40000000>;
89 }; 95 };
90 cpu6: PowerPC,e6500@12 { 96 cpu6: PowerPC,e6500@12 {
91 device_type = "cpu"; 97 device_type = "cpu";
92 reg = <12 13>; 98 reg = <12 13>;
93 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
94 }; 101 };
95 cpu7: PowerPC,e6500@14 { 102 cpu7: PowerPC,e6500@14 {
96 device_type = "cpu"; 103 device_type = "cpu";
97 reg = <14 15>; 104 reg = <14 15>;
98 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x40000000>;
99 }; 107 };
100 108
101 cpu8: PowerPC,e6500@16 { 109 cpu8: PowerPC,e6500@16 {
102 device_type = "cpu"; 110 device_type = "cpu";
103 reg = <16 17>; 111 reg = <16 17>;
104 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
113 fsl,portid-mapping = <0x20000000>;
105 }; 114 };
106 cpu9: PowerPC,e6500@18 { 115 cpu9: PowerPC,e6500@18 {
107 device_type = "cpu"; 116 device_type = "cpu";
108 reg = <18 19>; 117 reg = <18 19>;
109 next-level-cache = <&L2_3>; 118 next-level-cache = <&L2_3>;
119 fsl,portid-mapping = <0x20000000>;
110 }; 120 };
111 cpu10: PowerPC,e6500@20 { 121 cpu10: PowerPC,e6500@20 {
112 device_type = "cpu"; 122 device_type = "cpu";
113 reg = <20 21>; 123 reg = <20 21>;
114 next-level-cache = <&L2_3>; 124 next-level-cache = <&L2_3>;
125 fsl,portid-mapping = <0x20000000>;
115 }; 126 };
116 cpu11: PowerPC,e6500@22 { 127 cpu11: PowerPC,e6500@22 {
117 device_type = "cpu"; 128 device_type = "cpu";
118 reg = <22 23>; 129 reg = <22 23>;
119 next-level-cache = <&L2_3>; 130 next-level-cache = <&L2_3>;
131 fsl,portid-mapping = <0x20000000>;
120 }; 132 };
121 }; 133 };
122}; 134};
@@ -213,7 +225,7 @@
213 }; 225 };
214 226
215 corenet-cf@18000 { 227 corenet-cf@18000 {
216 compatible = "fsl,corenet-cf"; 228 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
217 reg = <0x18000 0x1000>; 229 reg = <0x18000 0x1000>;
218 interrupts = <16 2 1 31>; 230 interrupts = <16 2 1 31>;
219 fsl,ccf-num-csdids = <32>; 231 fsl,ccf-num-csdids = <32>;
@@ -223,6 +235,7 @@
223 iommu@20000 { 235 iommu@20000 {
224 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 236 compatible = "fsl,pamu-v1.0", "fsl,pamu";
225 reg = <0x20000 0x6000>; 237 reg = <0x20000 0x6000>;
238 fsl,portid-mapping = <0x8000>;
226 interrupts = < 239 interrupts = <
227 24 2 0 0 240 24 2 0 0
228 16 2 1 30>; 241 16 2 1 30>;
diff --git a/arch/powerpc/configs/85xx/kmp204x_defconfig b/arch/powerpc/configs/85xx/kmp204x_defconfig
new file mode 100644
index 000000000000..e9a81e5ba273
--- /dev/null
+++ b/arch/powerpc/configs/85xx/kmp204x_defconfig
@@ -0,0 +1,225 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=8
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_AUDIT=y
7CONFIG_NO_HZ=y
8CONFIG_HIGH_RES_TIMERS=y
9CONFIG_BSD_PROCESS_ACCT=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=14
13CONFIG_CGROUPS=y
14CONFIG_CGROUP_SCHED=y
15CONFIG_RELAY=y
16CONFIG_BLK_DEV_INITRD=y
17CONFIG_KALLSYMS_ALL=y
18CONFIG_EMBEDDED=y
19CONFIG_PERF_EVENTS=y
20CONFIG_SLAB=y
21CONFIG_MODULES=y
22CONFIG_MODULE_UNLOAD=y
23CONFIG_MODULE_FORCE_UNLOAD=y
24CONFIG_MODVERSIONS=y
25# CONFIG_BLK_DEV_BSG is not set
26CONFIG_PARTITION_ADVANCED=y
27CONFIG_MAC_PARTITION=y
28CONFIG_CORENET_GENERIC=y
29CONFIG_MPIC_MSGR=y
30CONFIG_HIGHMEM=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32CONFIG_BINFMT_MISC=m
33CONFIG_KEXEC=y
34CONFIG_FORCE_MAX_ZONEORDER=13
35CONFIG_PCI=y
36CONFIG_PCIEPORTBUS=y
37# CONFIG_PCIEASPM is not set
38CONFIG_PCI_MSI=y
39CONFIG_ADVANCED_OPTIONS=y
40CONFIG_LOWMEM_SIZE_BOOL=y
41CONFIG_LOWMEM_SIZE=0x20000000
42CONFIG_NET=y
43CONFIG_PACKET=y
44CONFIG_UNIX=y
45CONFIG_XFRM_USER=y
46CONFIG_XFRM_SUB_POLICY=y
47CONFIG_XFRM_STATISTICS=y
48CONFIG_NET_KEY=y
49CONFIG_NET_KEY_MIGRATE=y
50CONFIG_INET=y
51CONFIG_IP_MULTICAST=y
52CONFIG_IP_ADVANCED_ROUTER=y
53CONFIG_IP_MULTIPLE_TABLES=y
54CONFIG_IP_ROUTE_MULTIPATH=y
55CONFIG_IP_ROUTE_VERBOSE=y
56CONFIG_IP_PNP=y
57CONFIG_IP_PNP_DHCP=y
58CONFIG_IP_PNP_BOOTP=y
59CONFIG_IP_PNP_RARP=y
60CONFIG_NET_IPIP=y
61CONFIG_IP_MROUTE=y
62CONFIG_IP_PIMSM_V1=y
63CONFIG_IP_PIMSM_V2=y
64CONFIG_INET_AH=y
65CONFIG_INET_ESP=y
66CONFIG_INET_IPCOMP=y
67# CONFIG_INET_LRO is not set
68CONFIG_IPV6=y
69CONFIG_IP_SCTP=m
70CONFIG_TIPC=y
71CONFIG_NET_SCHED=y
72CONFIG_NET_SCH_CBQ=y
73CONFIG_NET_SCH_HTB=y
74CONFIG_NET_SCH_HFSC=y
75CONFIG_NET_SCH_PRIO=y
76CONFIG_NET_SCH_MULTIQ=y
77CONFIG_NET_SCH_RED=y
78CONFIG_NET_SCH_SFQ=y
79CONFIG_NET_SCH_TEQL=y
80CONFIG_NET_SCH_TBF=y
81CONFIG_NET_SCH_GRED=y
82CONFIG_NET_CLS_BASIC=y
83CONFIG_NET_CLS_TCINDEX=y
84CONFIG_NET_CLS_U32=y
85CONFIG_CLS_U32_PERF=y
86CONFIG_CLS_U32_MARK=y
87CONFIG_NET_CLS_FLOW=y
88CONFIG_NET_CLS_CGROUP=y
89CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
90CONFIG_DEVTMPFS=y
91CONFIG_MTD=y
92CONFIG_MTD_CMDLINE_PARTS=y
93CONFIG_MTD_BLOCK=y
94CONFIG_MTD_CFI=y
95CONFIG_MTD_CFI_AMDSTD=y
96CONFIG_MTD_PHYSMAP_OF=y
97CONFIG_MTD_M25P80=y
98CONFIG_MTD_PHRAM=y
99CONFIG_MTD_NAND=y
100CONFIG_MTD_NAND_ECC_BCH=y
101CONFIG_MTD_NAND_FSL_ELBC=y
102CONFIG_MTD_UBI=y
103CONFIG_MTD_UBI_GLUEBI=y
104CONFIG_BLK_DEV_LOOP=y
105CONFIG_BLK_DEV_RAM=y
106CONFIG_BLK_DEV_RAM_COUNT=2
107CONFIG_BLK_DEV_RAM_SIZE=2048
108CONFIG_EEPROM_AT24=y
109CONFIG_SCSI=y
110CONFIG_BLK_DEV_SD=y
111CONFIG_CHR_DEV_ST=y
112CONFIG_BLK_DEV_SR=y
113CONFIG_CHR_DEV_SG=y
114CONFIG_SCSI_MULTI_LUN=y
115CONFIG_SCSI_LOGGING=y
116CONFIG_SCSI_SYM53C8XX_2=y
117CONFIG_NETDEVICES=y
118# CONFIG_NET_VENDOR_3COM is not set
119# CONFIG_NET_VENDOR_ADAPTEC is not set
120# CONFIG_NET_VENDOR_ALTEON is not set
121# CONFIG_NET_VENDOR_AMD is not set
122# CONFIG_NET_VENDOR_ATHEROS is not set
123# CONFIG_NET_CADENCE is not set
124# CONFIG_NET_VENDOR_BROADCOM is not set
125# CONFIG_NET_VENDOR_BROCADE is not set
126# CONFIG_NET_VENDOR_CHELSIO is not set
127# CONFIG_NET_VENDOR_CISCO is not set
128# CONFIG_NET_VENDOR_DEC is not set
129# CONFIG_NET_VENDOR_DLINK is not set
130# CONFIG_NET_VENDOR_EMULEX is not set
131# CONFIG_NET_VENDOR_EXAR is not set
132CONFIG_FSL_PQ_MDIO=y
133CONFIG_FSL_XGMAC_MDIO=y
134# CONFIG_NET_VENDOR_HP is not set
135# CONFIG_NET_VENDOR_INTEL is not set
136# CONFIG_NET_VENDOR_MARVELL is not set
137# CONFIG_NET_VENDOR_MELLANOX is not set
138# CONFIG_NET_VENDOR_MICREL is not set
139# CONFIG_NET_VENDOR_MICROCHIP is not set
140# CONFIG_NET_VENDOR_MYRI is not set
141# CONFIG_NET_VENDOR_NATSEMI is not set
142# CONFIG_NET_VENDOR_NVIDIA is not set
143# CONFIG_NET_VENDOR_OKI is not set
144# CONFIG_NET_PACKET_ENGINE is not set
145# CONFIG_NET_VENDOR_QLOGIC is not set
146# CONFIG_NET_VENDOR_REALTEK is not set
147# CONFIG_NET_VENDOR_RDC is not set
148# CONFIG_NET_VENDOR_SEEQ is not set
149# CONFIG_NET_VENDOR_SILAN is not set
150# CONFIG_NET_VENDOR_SIS is not set
151# CONFIG_NET_VENDOR_SMSC is not set
152# CONFIG_NET_VENDOR_STMICRO is not set
153# CONFIG_NET_VENDOR_SUN is not set
154# CONFIG_NET_VENDOR_TEHUTI is not set
155# CONFIG_NET_VENDOR_TI is not set
156# CONFIG_NET_VENDOR_VIA is not set
157# CONFIG_NET_VENDOR_WIZNET is not set
158# CONFIG_NET_VENDOR_XILINX is not set
159CONFIG_MARVELL_PHY=y
160CONFIG_VITESSE_PHY=y
161CONFIG_FIXED_PHY=y
162# CONFIG_WLAN is not set
163# CONFIG_INPUT_MOUSEDEV is not set
164# CONFIG_INPUT_KEYBOARD is not set
165# CONFIG_INPUT_MOUSE is not set
166CONFIG_SERIO_LIBPS2=y
167# CONFIG_LEGACY_PTYS is not set
168CONFIG_PPC_EPAPR_HV_BYTECHAN=y
169CONFIG_SERIAL_8250=y
170CONFIG_SERIAL_8250_CONSOLE=y
171CONFIG_SERIAL_8250_MANY_PORTS=y
172CONFIG_SERIAL_8250_DETECT_IRQ=y
173CONFIG_SERIAL_8250_RSA=y
174CONFIG_NVRAM=y
175CONFIG_I2C=y
176CONFIG_I2C_CHARDEV=y
177CONFIG_I2C_MUX=y
178CONFIG_I2C_MUX_PCA954x=y
179CONFIG_I2C_MPC=y
180CONFIG_SPI=y
181CONFIG_SPI_FSL_SPI=y
182CONFIG_SPI_FSL_ESPI=y
183CONFIG_SPI_SPIDEV=m
184CONFIG_PTP_1588_CLOCK=y
185# CONFIG_HWMON is not set
186# CONFIG_USB_SUPPORT is not set
187CONFIG_EDAC=y
188CONFIG_EDAC_MM_EDAC=y
189CONFIG_EDAC_MPC85XX=y
190CONFIG_RTC_CLASS=y
191CONFIG_RTC_DRV_DS3232=y
192CONFIG_RTC_DRV_CMOS=y
193CONFIG_UIO=y
194CONFIG_STAGING=y
195# CONFIG_NET_VENDOR_SILICOM is not set
196CONFIG_CLK_PPC_CORENET=y
197CONFIG_EXT2_FS=y
198CONFIG_NTFS_FS=y
199CONFIG_PROC_KCORE=y
200CONFIG_TMPFS=y
201CONFIG_JFFS2_FS=y
202CONFIG_UBIFS_FS=y
203CONFIG_CRAMFS=y
204CONFIG_SQUASHFS=y
205CONFIG_SQUASHFS_XZ=y
206CONFIG_NFS_FS=y
207CONFIG_NFS_V4=y
208CONFIG_ROOT_NFS=y
209CONFIG_NLS_ISO8859_1=y
210CONFIG_NLS_UTF8=m
211CONFIG_CRC_ITU_T=m
212CONFIG_DEBUG_INFO=y
213CONFIG_MAGIC_SYSRQ=y
214CONFIG_DEBUG_SHIRQ=y
215CONFIG_DETECT_HUNG_TASK=y
216CONFIG_SCHEDSTATS=y
217CONFIG_RCU_TRACE=y
218CONFIG_UPROBE_EVENT=y
219CONFIG_CRYPTO_NULL=y
220CONFIG_CRYPTO_PCBC=m
221CONFIG_CRYPTO_MD4=y
222CONFIG_CRYPTO_SHA256=y
223CONFIG_CRYPTO_SHA512=y
224# CONFIG_CRYPTO_ANSI_CPRNG is not set
225CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794deb6eb..c19ff057d0f9 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -72,6 +72,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
72CONFIG_MTD_CHAR=y 72CONFIG_MTD_CHAR=y
73CONFIG_MTD_BLOCK=y 73CONFIG_MTD_BLOCK=y
74CONFIG_MTD_CFI=y 74CONFIG_MTD_CFI=y
75CONFIG_MTD_CFI_INTELEXT=y
75CONFIG_MTD_CFI_AMDSTD=y 76CONFIG_MTD_CFI_AMDSTD=y
76CONFIG_MTD_PHYSMAP_OF=y 77CONFIG_MTD_PHYSMAP_OF=y
77CONFIG_MTD_M25P80=y 78CONFIG_MTD_M25P80=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 19f0fbe5ba4b..55765c8cb08f 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -32,7 +32,6 @@ CONFIG_P1010_RDB=y
32CONFIG_P1022_DS=y 32CONFIG_P1022_DS=y
33CONFIG_P1022_RDK=y 33CONFIG_P1022_RDK=y
34CONFIG_P1023_RDB=y 34CONFIG_P1023_RDB=y
35CONFIG_P1023_RDS=y
36CONFIG_SOCRATES=y 35CONFIG_SOCRATES=y
37CONFIG_KSI8560=y 36CONFIG_KSI8560=y
38CONFIG_XES_MPC85xx=y 37CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 062312e1fe1a..5c6ecdc0f70e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -35,7 +35,6 @@ CONFIG_P1010_RDB=y
35CONFIG_P1022_DS=y 35CONFIG_P1022_DS=y
36CONFIG_P1022_RDK=y 36CONFIG_P1022_RDK=y
37CONFIG_P1023_RDB=y 37CONFIG_P1023_RDB=y
38CONFIG_P1023_RDS=y
39CONFIG_SOCRATES=y 38CONFIG_SOCRATES=y
40CONFIG_KSI8560=y 39CONFIG_KSI8560=y
41CONFIG_XES_MPC85xx=y 40CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c
index 7898be90f2dc..2d7eeae5b4d0 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -30,6 +30,7 @@ extern u32 epapr_ev_idle_start[];
30#endif 30#endif
31 31
32bool epapr_paravirt_enabled; 32bool epapr_paravirt_enabled;
33static bool __maybe_unused epapr_has_idle;
33 34
34static int __init early_init_dt_scan_epapr(unsigned long node, 35static int __init early_init_dt_scan_epapr(unsigned long node,
35 const char *uname, 36 const char *uname,
@@ -47,15 +48,16 @@ static int __init early_init_dt_scan_epapr(unsigned long node,
47 return -1; 48 return -1;
48 49
49 for (i = 0; i < (len / 4); i++) { 50 for (i = 0; i < (len / 4); i++) {
50 patch_instruction(epapr_hypercall_start + i, insts[i]); 51 u32 inst = be32_to_cpu(insts[i]);
52 patch_instruction(epapr_hypercall_start + i, inst);
51#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64) 53#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
52 patch_instruction(epapr_ev_idle_start + i, insts[i]); 54 patch_instruction(epapr_ev_idle_start + i, inst);
53#endif 55#endif
54 } 56 }
55 57
56#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64) 58#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
57 if (of_get_flat_dt_prop(node, "has-idle", NULL)) 59 if (of_get_flat_dt_prop(node, "has-idle", NULL))
58 ppc_md.power_save = epapr_ev_idle; 60 epapr_has_idle = true;
59#endif 61#endif
60 62
61 epapr_paravirt_enabled = true; 63 epapr_paravirt_enabled = true;
@@ -70,3 +72,14 @@ int __init epapr_paravirt_early_init(void)
70 return 0; 72 return 0;
71} 73}
72 74
75static int __init epapr_idle_init(void)
76{
77#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
78 if (epapr_has_idle)
79 ppc_md.power_save = epapr_ev_idle;
80#endif
81
82 return 0;
83}
84
85postcore_initcall(epapr_idle_init);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index ae3d5b799b90..92cb18d52ea8 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -596,8 +596,13 @@ static void __early_init_mmu(int boot_cpu)
596 /* XXX This should be decided at runtime based on supported 596 /* XXX This should be decided at runtime based on supported
597 * page sizes in the TLB, but for now let's assume 16M is 597 * page sizes in the TLB, but for now let's assume 16M is
598 * always there and a good fit (which it probably is) 598 * always there and a good fit (which it probably is)
599 *
600 * Freescale booke only supports 4K pages in TLB0, so use that.
599 */ 601 */
600 mmu_vmemmap_psize = MMU_PAGE_16M; 602 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
603 mmu_vmemmap_psize = MMU_PAGE_4K;
604 else
605 mmu_vmemmap_psize = MMU_PAGE_16M;
601 606
602 /* XXX This code only checks for TLB 0 capabilities and doesn't 607 /* XXX This code only checks for TLB 0 capabilities and doesn't
603 * check what page size combos are supported by the HW. It 608 * check what page size combos are supported by the HW. It
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index c17aae80e7ff..f442120e0033 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -38,6 +38,15 @@ config C293_PCIE
38 help 38 help
39 This option enables support for the C293PCIE board 39 This option enables support for the C293PCIE board
40 40
41config BSC9132_QDS
42 bool "Freescale BSC9132QDS"
43 select DEFAULT_UIMAGE
44 help
45 This option enables support for the Freescale BSC9132 QDS board.
46 BSC9132 is a heterogeneous SoC containing dual e500v2 powerpc cores
47 and dual StarCore SC3850 DSP cores.
48 Manufacturer : Freescale Semiconductor, Inc
49
41config MPC8540_ADS 50config MPC8540_ADS
42 bool "Freescale MPC8540 ADS" 51 bool "Freescale MPC8540 ADS"
43 select DEFAULT_UIMAGE 52 select DEFAULT_UIMAGE
@@ -117,11 +126,11 @@ config P1022_RDK
117 This option enables support for the Freescale / iVeia P1022RDK 126 This option enables support for the Freescale / iVeia P1022RDK
118 reference board. 127 reference board.
119 128
120config P1023_RDS 129config P1023_RDB
121 bool "Freescale P1023 RDS/RDB" 130 bool "Freescale P1023 RDB"
122 select DEFAULT_UIMAGE 131 select DEFAULT_UIMAGE
123 help 132 help
124 This option enables support for the P1023 RDS and RDB boards 133 This option enables support for the P1023 RDB board.
125 134
126config TWR_P102x 135config TWR_P102x
127 bool "Freescale TWR-P102x" 136 bool "Freescale TWR-P102x"
@@ -263,11 +272,11 @@ config CORENET_GENERIC
263 help 272 help
264 This option enables support for the FSL CoreNet based boards. 273 This option enables support for the FSL CoreNet based boards.
265 For 32bit kernel, the following boards are supported: 274 For 32bit kernel, the following boards are supported:
266 P2041 RDB, P3041 DS and P4080 DS 275 P2041 RDB, P3041 DS, P4080 DS, kmcoge4, and OCA4080
267 For 64bit kernel, the following boards are supported: 276 For 64bit kernel, the following boards are supported:
268 T4240 QDS and B4 QDS 277 T4240 QDS and B4 QDS
269 The following boards are supported for both 32bit and 64bit kernel: 278 The following boards are supported for both 32bit and 64bit kernel:
270 P5020 DS and P5040 DS 279 P5020 DS, P5040 DS and T104xQDS
271 280
272endif # FSL_SOC_BOOKE 281endif # FSL_SOC_BOOKE
273 282
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 25cebe74ac46..730326046625 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
6obj-y += common.o 6obj-y += common.o
7 7
8obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o 8obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
9obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
9obj-$(CONFIG_C293_PCIE) += c293pcie.o 10obj-$(CONFIG_C293_PCIE) += c293pcie.o
10obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o 11obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
11obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o 12obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
@@ -17,7 +18,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
17obj-$(CONFIG_P1010_RDB) += p1010rdb.o 18obj-$(CONFIG_P1010_RDB) += p1010rdb.o
18obj-$(CONFIG_P1022_DS) += p1022_ds.o 19obj-$(CONFIG_P1022_DS) += p1022_ds.o
19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o 20obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
20obj-$(CONFIG_P1023_RDS) += p1023_rds.o 21obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
21obj-$(CONFIG_TWR_P102x) += twr_p102x.o 22obj-$(CONFIG_TWR_P102x) += twr_p102x.o
22obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o 23obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
23obj-$(CONFIG_STX_GP3) += stx_gp3.o 24obj-$(CONFIG_STX_GP3) += stx_gp3.o
diff --git a/arch/powerpc/platforms/85xx/bsc913x_qds.c b/arch/powerpc/platforms/85xx/bsc913x_qds.c
new file mode 100644
index 000000000000..f0927e58af25
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/bsc913x_qds.c
@@ -0,0 +1,74 @@
1/*
2 * BSC913xQDS Board Setup
3 *
4 * Author:
5 * Harninder Rai <harninder.rai@freescale.com>
6 * Priyanka Jain <Priyanka.Jain@freescale.com>
7 *
8 * Copyright 2014 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/of_platform.h>
17#include <linux/pci.h>
18#include <asm/mpic.h>
19#include <sysdev/fsl_soc.h>
20#include <asm/udbg.h>
21
22#include "mpc85xx.h"
23#include "smp.h"
24
25void __init bsc913x_qds_pic_init(void)
26{
27 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
28 MPIC_SINGLE_DEST_CPU,
29 0, 256, " OpenPIC ");
30
31 if (!mpic)
32 pr_err("bsc913x: Failed to allocate MPIC structure\n");
33 else
34 mpic_init(mpic);
35}
36
37/*
38 * Setup the architecture
39 */
40static void __init bsc913x_qds_setup_arch(void)
41{
42 if (ppc_md.progress)
43 ppc_md.progress("bsc913x_qds_setup_arch()", 0);
44
45#if defined(CONFIG_SMP)
46 mpc85xx_smp_init();
47#endif
48
49 pr_info("bsc913x board from Freescale Semiconductor\n");
50}
51
52machine_device_initcall(bsc9132_qds, mpc85xx_common_publish_devices);
53
54/*
55 * Called very early, device-tree isn't unflattened
56 */
57
58static int __init bsc9132_qds_probe(void)
59{
60 unsigned long root = of_get_flat_dt_root();
61
62 return of_flat_dt_is_compatible(root, "fsl,bsc9132qds");
63}
64
65define_machine(bsc9132_qds) {
66 .name = "BSC9132 QDS",
67 .probe = bsc9132_qds_probe,
68 .setup_arch = bsc913x_qds_setup_arch,
69 .init_IRQ = bsc913x_qds_pic_init,
70 .get_irq = mpic_get_irq,
71 .restart = fsl_rstcr_restart,
72 .calibrate_decr = generic_calibrate_decr,
73 .progress = udbg_progress,
74};
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8e4b1e1a4911..5db1e117fdde 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -67,7 +67,7 @@ void __init corenet_gen_setup_arch(void)
67 67
68 swiotlb_detect_4g(); 68 swiotlb_detect_4g();
69 69
70 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); 70 pr_info("%s board\n", ppc_md.name);
71 71
72 mpc85xx_qe_init(); 72 mpc85xx_qe_init();
73} 73}
@@ -115,6 +115,7 @@ int __init corenet_gen_publish_devices(void)
115static const char * const boards[] __initconst = { 115static const char * const boards[] __initconst = {
116 "fsl,P2041RDB", 116 "fsl,P2041RDB",
117 "fsl,P3041DS", 117 "fsl,P3041DS",
118 "fsl,OCA4080",
118 "fsl,P4080DS", 119 "fsl,P4080DS",
119 "fsl,P5020DS", 120 "fsl,P5020DS",
120 "fsl,P5040DS", 121 "fsl,P5040DS",
@@ -122,12 +123,16 @@ static const char * const boards[] __initconst = {
122 "fsl,B4860QDS", 123 "fsl,B4860QDS",
123 "fsl,B4420QDS", 124 "fsl,B4420QDS",
124 "fsl,B4220QDS", 125 "fsl,B4220QDS",
126 "fsl,T1040QDS",
127 "fsl,T1042QDS",
128 "keymile,kmcoge4",
125 NULL 129 NULL
126}; 130};
127 131
128static const char * const hv_boards[] __initconst = { 132static const char * const hv_boards[] __initconst = {
129 "fsl,P2041RDB-hv", 133 "fsl,P2041RDB-hv",
130 "fsl,P3041DS-hv", 134 "fsl,P3041DS-hv",
135 "fsl,OCA4080-hv",
131 "fsl,P4080DS-hv", 136 "fsl,P4080DS-hv",
132 "fsl,P5020DS-hv", 137 "fsl,P5020DS-hv",
133 "fsl,P5040DS-hv", 138 "fsl,P5040DS-hv",
@@ -135,6 +140,8 @@ static const char * const hv_boards[] __initconst = {
135 "fsl,B4860QDS-hv", 140 "fsl,B4860QDS-hv",
136 "fsl,B4420QDS-hv", 141 "fsl,B4420QDS-hv",
137 "fsl,B4220QDS-hv", 142 "fsl,B4220QDS-hv",
143 "fsl,T1040QDS-hv",
144 "fsl,T1042QDS-hv",
138 NULL 145 NULL
139}; 146};
140 147
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rdb.c
index 0e614007acfb..d5b7509825de 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rdb.c
@@ -4,7 +4,7 @@
4 * Author: Roy Zang <tie-fei.zang@freescale.com> 4 * Author: Roy Zang <tie-fei.zang@freescale.com>
5 * 5 *
6 * Description: 6 * Description:
7 * P1023 RDS Board Setup 7 * P1023 RDB Board Setup
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -41,12 +41,12 @@
41 * Setup the architecture 41 * Setup the architecture
42 * 42 *
43 */ 43 */
44static void __init mpc85xx_rds_setup_arch(void) 44static void __init mpc85xx_rdb_setup_arch(void)
45{ 45{
46 struct device_node *np; 46 struct device_node *np;
47 47
48 if (ppc_md.progress) 48 if (ppc_md.progress)
49 ppc_md.progress("p1023_rds_setup_arch()", 0); 49 ppc_md.progress("p1023_rdb_setup_arch()", 0);
50 50
51 /* Map BCSR area */ 51 /* Map BCSR area */
52 np = of_find_node_by_name(NULL, "bcsr"); 52 np = of_find_node_by_name(NULL, "bcsr");
@@ -85,10 +85,9 @@ static void __init mpc85xx_rds_setup_arch(void)
85 fsl_pci_assign_primary(); 85 fsl_pci_assign_primary();
86} 86}
87 87
88machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
89machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices); 88machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
90 89
91static void __init mpc85xx_rds_pic_init(void) 90static void __init mpc85xx_rdb_pic_init(void)
92{ 91{
93 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | 92 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
94 MPIC_SINGLE_DEST_CPU, 93 MPIC_SINGLE_DEST_CPU,
@@ -99,14 +98,6 @@ static void __init mpc85xx_rds_pic_init(void)
99 mpic_init(mpic); 98 mpic_init(mpic);
100} 99}
101 100
102static int __init p1023_rds_probe(void)
103{
104 unsigned long root = of_get_flat_dt_root();
105
106 return of_flat_dt_is_compatible(root, "fsl,P1023RDS");
107
108}
109
110static int __init p1023_rdb_probe(void) 101static int __init p1023_rdb_probe(void)
111{ 102{
112 unsigned long root = of_get_flat_dt_root(); 103 unsigned long root = of_get_flat_dt_root();
@@ -115,26 +106,11 @@ static int __init p1023_rdb_probe(void)
115 106
116} 107}
117 108
118define_machine(p1023_rds) {
119 .name = "P1023 RDS",
120 .probe = p1023_rds_probe,
121 .setup_arch = mpc85xx_rds_setup_arch,
122 .init_IRQ = mpc85xx_rds_pic_init,
123 .get_irq = mpic_get_irq,
124 .restart = fsl_rstcr_restart,
125 .calibrate_decr = generic_calibrate_decr,
126 .progress = udbg_progress,
127#ifdef CONFIG_PCI
128 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
129 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
130#endif
131};
132
133define_machine(p1023_rdb) { 109define_machine(p1023_rdb) {
134 .name = "P1023 RDB", 110 .name = "P1023 RDB",
135 .probe = p1023_rdb_probe, 111 .probe = p1023_rdb_probe,
136 .setup_arch = mpc85xx_rds_setup_arch, 112 .setup_arch = mpc85xx_rdb_setup_arch,
137 .init_IRQ = mpc85xx_rds_pic_init, 113 .init_IRQ = mpc85xx_rdb_pic_init,
138 .get_irq = mpic_get_irq, 114 .get_irq = mpic_get_irq,
139 .restart = fsl_rstcr_restart, 115 .restart = fsl_rstcr_restart,
140 .calibrate_decr = generic_calibrate_decr, 116 .calibrate_decr = generic_calibrate_decr,
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3f415e252ea5..4bd091a05583 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1150,8 +1150,7 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
1150 pci = hose->private_data; 1150 pci = hose->private_data;
1151 1151
1152 /* Enable PTOD, ENL23D & EXL23D */ 1152 /* Enable PTOD, ENL23D & EXL23D */
1153 out_be32(&pci->pex_pme_mes_disr, 0); 1153 clrbits32(&pci->pex_pme_mes_disr,
1154 setbits32(&pci->pex_pme_mes_disr,
1155 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1154 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1156 1155
1157 out_be32(&pci->pex_pme_mes_ier, 0); 1156 out_be32(&pci->pex_pme_mes_ier, 0);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cf2b0840a672..c04b718307c8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -391,8 +391,10 @@ int fsl_rio_setup(struct platform_device *dev)
391 ops->get_inb_message = fsl_get_inb_message; 391 ops->get_inb_message = fsl_get_inb_message;
392 392
393 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0); 393 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
394 if (!rmu_node) 394 if (!rmu_node) {
395 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
395 goto err_rmu; 396 goto err_rmu;
397 }
396 rc = of_address_to_resource(rmu_node, 0, &rmu_regs); 398 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
397 if (rc) { 399 if (rc) {
398 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 400 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
@@ -413,6 +415,7 @@ int fsl_rio_setup(struct platform_device *dev)
413 /*set up doobell node*/ 415 /*set up doobell node*/
414 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit"); 416 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
415 if (!np) { 417 if (!np) {
418 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
416 rc = -ENODEV; 419 rc = -ENODEV;
417 goto err_dbell; 420 goto err_dbell;
418 } 421 }
@@ -441,6 +444,7 @@ int fsl_rio_setup(struct platform_device *dev)
441 /*set up port write node*/ 444 /*set up port write node*/
442 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit"); 445 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
443 if (!np) { 446 if (!np) {
447 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
444 rc = -ENODEV; 448 rc = -ENODEV;
445 goto err_pw; 449 goto err_pw;
446 } 450 }
@@ -633,14 +637,18 @@ int fsl_rio_setup(struct platform_device *dev)
633 return 0; 637 return 0;
634err: 638err:
635 kfree(pw); 639 kfree(pw);
640 pw = NULL;
636err_pw: 641err_pw:
637 kfree(dbell); 642 kfree(dbell);
643 dbell = NULL;
638err_dbell: 644err_dbell:
639 iounmap(rmu_regs_win); 645 iounmap(rmu_regs_win);
646 rmu_regs_win = NULL;
640err_rmu: 647err_rmu:
641 kfree(ops); 648 kfree(ops);
642err_ops: 649err_ops:
643 iounmap(rio_regs_win); 650 iounmap(rio_regs_win);
651 rio_regs_win = NULL;
644err_rio_regs: 652err_rio_regs:
645 return rc; 653 return rc;
646} 654}
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 00e224a1048c..b48197ae44d0 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -881,9 +881,9 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
881 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 881 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
882 "msg_rx", (void *)mport); 882 "msg_rx", (void *)mport);
883 if (rc < 0) { 883 if (rc < 0) {
884 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 884 dma_free_coherent(priv->dev,
885 rmu->msg_tx_ring.virt_buffer[i], 885 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
886 rmu->msg_tx_ring.phys_buffer[i]); 886 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
887 goto out; 887 goto out;
888 } 888 }
889 889
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8209744b2829..be33c9768ea1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1588,10 +1588,6 @@ void __init mpic_init(struct mpic *mpic)
1588 num_timers = 8; 1588 num_timers = 8;
1589 } 1589 }
1590 1590
1591 /* FSL mpic error interrupt intialization */
1592 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1593 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1594
1595 /* Initialize timers to our reserved vectors and mask them for now */ 1591 /* Initialize timers to our reserved vectors and mask them for now */
1596 for (i = 0; i < num_timers; i++) { 1592 for (i = 0; i < num_timers; i++) {
1597 unsigned int offset = mpic_tm_offset(mpic, i); 1593 unsigned int offset = mpic_tm_offset(mpic, i);
@@ -1675,6 +1671,10 @@ void __init mpic_init(struct mpic *mpic)
1675 irq_set_chained_handler(virq, &mpic_cascade); 1671 irq_set_chained_handler(virq, &mpic_cascade);
1676 } 1672 }
1677 } 1673 }
1674
1675 /* FSL mpic error interrupt intialization */
1676 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1677 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1678} 1678}
1679 1679
1680void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1680void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 07:03:36 -0500