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-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be4e1a8..12bd4ea07eac 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
37 device_type = "cpu"; 37 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 reg = <0>; 39 reg = <0>;
40 cci-control-port = <&cci_control1>;
40 }; 41 };
41 42
42 cpu1: cpu@1 { 43 cpu1: cpu@1 {
43 device_type = "cpu"; 44 device_type = "cpu";
44 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
45 reg = <1>; 46 reg = <1>;
47 cci-control-port = <&cci_control1>;
46 }; 48 };
47 49
48 cpu2: cpu@2 { 50 cpu2: cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
50 compatible = "arm,cortex-a7"; 52 compatible = "arm,cortex-a7";
51 reg = <0x100>; 53 reg = <0x100>;
54 cci-control-port = <&cci_control2>;
52 }; 55 };
53 56
54 cpu3: cpu@3 { 57 cpu3: cpu@3 {
55 device_type = "cpu"; 58 device_type = "cpu";
56 compatible = "arm,cortex-a7"; 59 compatible = "arm,cortex-a7";
57 reg = <0x101>; 60 reg = <0x101>;
61 cci-control-port = <&cci_control2>;
58 }; 62 };
59 63
60 cpu4: cpu@4 { 64 cpu4: cpu@4 {
61 device_type = "cpu"; 65 device_type = "cpu";
62 compatible = "arm,cortex-a7"; 66 compatible = "arm,cortex-a7";
63 reg = <0x102>; 67 reg = <0x102>;
68 cci-control-port = <&cci_control2>;
64 }; 69 };
65 }; 70 };
66 71
@@ -104,6 +109,26 @@
104 interrupts = <1 9 0xf04>; 109 interrupts = <1 9 0xf04>;
105 }; 110 };
106 111
112 cci@2c090000 {
113 compatible = "arm,cci-400";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0 0x2c090000 0 0x1000>;
117 ranges = <0x0 0x0 0x2c090000 0x10000>;
118
119 cci_control1: slave-if@4000 {
120 compatible = "arm,cci-400-ctrl-if";
121 interface-type = "ace";
122 reg = <0x4000 0x1000>;
123 };
124
125 cci_control2: slave-if@5000 {
126 compatible = "arm,cci-400-ctrl-if";
127 interface-type = "ace";
128 reg = <0x5000 0x1000>;
129 };
130 };
131
107 memory-controller@7ffd0000 { 132 memory-controller@7ffd0000 {
108 compatible = "arm,pl354", "arm,primecell"; 133 compatible = "arm,pl354", "arm,primecell";
109 reg = <0 0x7ffd0000 0 0x1000>; 134 reg = <0 0x7ffd0000 0 0x1000>;