1 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 586dba7e5f23..8833c349f23c 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -108,6 +108,8 @@
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 
+#define GPMC_NR_WAITPINS                4
+
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
 #define GPMC_NR_IRQ             2
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -1294,6 +1297,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1372,6 +1382,9 @@ static int gpmc_probe(struct platform_device *pdev)
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);