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-rw-r--r--arch/arm64/include/asm/atomic.h24
-rw-r--r--arch/arm64/include/asm/cmpxchg.h8
-rw-r--r--arch/arm64/include/asm/futex.h4
-rw-r--r--arch/arm64/include/asm/spinlock.h10
4 files changed, 21 insertions, 25 deletions
diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
index e32893e005d4..0237f0867e37 100644
--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -54,8 +54,7 @@ static inline void atomic_add(int i, atomic_t *v)
54" stxr %w1, %w0, %2\n" 54" stxr %w1, %w0, %2\n"
55" cbnz %w1, 1b" 55" cbnz %w1, 1b"
56 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 56 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
57 : "Ir" (i) 57 : "Ir" (i));
58 : "cc");
59} 58}
60 59
61static inline int atomic_add_return(int i, atomic_t *v) 60static inline int atomic_add_return(int i, atomic_t *v)
@@ -70,7 +69,7 @@ static inline int atomic_add_return(int i, atomic_t *v)
70" cbnz %w1, 1b" 69" cbnz %w1, 1b"
71 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 70 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
72 : "Ir" (i) 71 : "Ir" (i)
73 : "cc", "memory"); 72 : "memory");
74 73
75 smp_mb(); 74 smp_mb();
76 return result; 75 return result;
@@ -87,8 +86,7 @@ static inline void atomic_sub(int i, atomic_t *v)
87" stxr %w1, %w0, %2\n" 86" stxr %w1, %w0, %2\n"
88" cbnz %w1, 1b" 87" cbnz %w1, 1b"
89 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 88 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
90 : "Ir" (i) 89 : "Ir" (i));
91 : "cc");
92} 90}
93 91
94static inline int atomic_sub_return(int i, atomic_t *v) 92static inline int atomic_sub_return(int i, atomic_t *v)
@@ -103,7 +101,7 @@ static inline int atomic_sub_return(int i, atomic_t *v)
103" cbnz %w1, 1b" 101" cbnz %w1, 1b"
104 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 102 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
105 : "Ir" (i) 103 : "Ir" (i)
106 : "cc", "memory"); 104 : "memory");
107 105
108 smp_mb(); 106 smp_mb();
109 return result; 107 return result;
@@ -125,7 +123,7 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
125"2:" 123"2:"
126 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter) 124 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
127 : "Ir" (old), "r" (new) 125 : "Ir" (old), "r" (new)
128 : "cc", "memory"); 126 : "cc");
129 127
130 smp_mb(); 128 smp_mb();
131 return oldval; 129 return oldval;
@@ -178,8 +176,7 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
178" stxr %w1, %0, %2\n" 176" stxr %w1, %0, %2\n"
179" cbnz %w1, 1b" 177" cbnz %w1, 1b"
180 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 178 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
181 : "Ir" (i) 179 : "Ir" (i));
182 : "cc");
183} 180}
184 181
185static inline long atomic64_add_return(long i, atomic64_t *v) 182static inline long atomic64_add_return(long i, atomic64_t *v)
@@ -194,7 +191,7 @@ static inline long atomic64_add_return(long i, atomic64_t *v)
194" cbnz %w1, 1b" 191" cbnz %w1, 1b"
195 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 192 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
196 : "Ir" (i) 193 : "Ir" (i)
197 : "cc", "memory"); 194 : "memory");
198 195
199 smp_mb(); 196 smp_mb();
200 return result; 197 return result;
@@ -211,8 +208,7 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
211" stxr %w1, %0, %2\n" 208" stxr %w1, %0, %2\n"
212" cbnz %w1, 1b" 209" cbnz %w1, 1b"
213 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 210 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
214 : "Ir" (i) 211 : "Ir" (i));
215 : "cc");
216} 212}
217 213
218static inline long atomic64_sub_return(long i, atomic64_t *v) 214static inline long atomic64_sub_return(long i, atomic64_t *v)
@@ -227,7 +223,7 @@ static inline long atomic64_sub_return(long i, atomic64_t *v)
227" cbnz %w1, 1b" 223" cbnz %w1, 1b"
228 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) 224 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
229 : "Ir" (i) 225 : "Ir" (i)
230 : "cc", "memory"); 226 : "memory");
231 227
232 smp_mb(); 228 smp_mb();
233 return result; 229 return result;
@@ -249,7 +245,7 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
249"2:" 245"2:"
250 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter) 246 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
251 : "Ir" (old), "r" (new) 247 : "Ir" (old), "r" (new)
252 : "cc", "memory"); 248 : "cc");
253 249
254 smp_mb(); 250 smp_mb();
255 return oldval; 251 return oldval;
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 189390ce8653..57c0fa7bf711 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -34,7 +34,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
34 " cbnz %w1, 1b\n" 34 " cbnz %w1, 1b\n"
35 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr) 35 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
36 : "r" (x) 36 : "r" (x)
37 : "cc", "memory"); 37 : "memory");
38 break; 38 break;
39 case 2: 39 case 2:
40 asm volatile("// __xchg2\n" 40 asm volatile("// __xchg2\n"
@@ -43,7 +43,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
43 " cbnz %w1, 1b\n" 43 " cbnz %w1, 1b\n"
44 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr) 44 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
45 : "r" (x) 45 : "r" (x)
46 : "cc", "memory"); 46 : "memory");
47 break; 47 break;
48 case 4: 48 case 4:
49 asm volatile("// __xchg4\n" 49 asm volatile("// __xchg4\n"
@@ -52,7 +52,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
52 " cbnz %w1, 1b\n" 52 " cbnz %w1, 1b\n"
53 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr) 53 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
54 : "r" (x) 54 : "r" (x)
55 : "cc", "memory"); 55 : "memory");
56 break; 56 break;
57 case 8: 57 case 8:
58 asm volatile("// __xchg8\n" 58 asm volatile("// __xchg8\n"
@@ -61,7 +61,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
61 " cbnz %w1, 1b\n" 61 " cbnz %w1, 1b\n"
62 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr) 62 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
63 : "r" (x) 63 : "r" (x)
64 : "cc", "memory"); 64 : "memory");
65 break; 65 break;
66 default: 66 default:
67 BUILD_BUG(); 67 BUILD_BUG();
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 572193d0005d..5f750dc96e0f 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -41,7 +41,7 @@
41" .popsection\n" \ 41" .popsection\n" \
42 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ 42 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
43 : "r" (oparg), "Ir" (-EFAULT) \ 43 : "r" (oparg), "Ir" (-EFAULT) \
44 : "cc", "memory") 44 : "memory")
45 45
46static inline int 46static inline int
47futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) 47futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
@@ -129,7 +129,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
129" .popsection\n" 129" .popsection\n"
130 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) 130 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
131 : "r" (oldval), "r" (newval), "Ir" (-EFAULT) 131 : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
132 : "cc", "memory"); 132 : "memory");
133 133
134 *uval = val; 134 *uval = val;
135 return ret; 135 return ret;
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index 3d5cf064d7a1..c45b7b1b7197 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -132,7 +132,7 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
132 " cbnz %w0, 2b\n" 132 " cbnz %w0, 2b\n"
133 : "=&r" (tmp), "+Q" (rw->lock) 133 : "=&r" (tmp), "+Q" (rw->lock)
134 : "r" (0x80000000) 134 : "r" (0x80000000)
135 : "cc", "memory"); 135 : "memory");
136} 136}
137 137
138static inline int arch_write_trylock(arch_rwlock_t *rw) 138static inline int arch_write_trylock(arch_rwlock_t *rw)
@@ -146,7 +146,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
146 "1:\n" 146 "1:\n"
147 : "=&r" (tmp), "+Q" (rw->lock) 147 : "=&r" (tmp), "+Q" (rw->lock)
148 : "r" (0x80000000) 148 : "r" (0x80000000)
149 : "cc", "memory"); 149 : "memory");
150 150
151 return !tmp; 151 return !tmp;
152} 152}
@@ -187,7 +187,7 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
187 " cbnz %w1, 2b\n" 187 " cbnz %w1, 2b\n"
188 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) 188 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
189 : 189 :
190 : "cc", "memory"); 190 : "memory");
191} 191}
192 192
193static inline void arch_read_unlock(arch_rwlock_t *rw) 193static inline void arch_read_unlock(arch_rwlock_t *rw)
@@ -201,7 +201,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
201 " cbnz %w1, 1b\n" 201 " cbnz %w1, 1b\n"
202 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) 202 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
203 : 203 :
204 : "cc", "memory"); 204 : "memory");
205} 205}
206 206
207static inline int arch_read_trylock(arch_rwlock_t *rw) 207static inline int arch_read_trylock(arch_rwlock_t *rw)
@@ -216,7 +216,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
216 "1:\n" 216 "1:\n"
217 : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock) 217 : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
218 : 218 :
219 : "cc", "memory"); 219 : "memory");
220 220
221 return !tmp2; 221 return !tmp2;
222} 222}