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-rw-r--r--arch/mips/mm/c-r4k.c26
1 files changed, 18 insertions, 8 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ae500ca76580..627883bc6d5f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -786,20 +786,30 @@ static inline void rm7k_erratum31(void)
786 786
787static inline void alias_74k_erratum(struct cpuinfo_mips *c) 787static inline void alias_74k_erratum(struct cpuinfo_mips *c)
788{ 788{
789 unsigned int imp = c->processor_id & PRID_IMP_MASK;
790 unsigned int rev = c->processor_id & PRID_REV_MASK;
791
789 /* 792 /*
790 * Early versions of the 74K do not update the cache tags on a 793 * Early versions of the 74K do not update the cache tags on a
791 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 794 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
792 * aliases. In this case it is better to treat the cache as always 795 * aliases. In this case it is better to treat the cache as always
793 * having aliases. 796 * having aliases.
794 */ 797 */
795 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(2, 4, 0)) 798 switch (imp) {
796 c->dcache.flags |= MIPS_CACHE_VTAG; 799 case PRID_IMP_74K:
797 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_ENCODE_332(2, 4, 0)) 800 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
798 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 801 c->dcache.flags |= MIPS_CACHE_VTAG;
799 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_1074K && 802 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
800 (c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(1, 1, 0)) { 803 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
801 c->dcache.flags |= MIPS_CACHE_VTAG; 804 break;
802 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 805 case PRID_IMP_1074K:
806 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
807 c->dcache.flags |= MIPS_CACHE_VTAG;
808 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
809 }
810 break;
811 default:
812 BUG();
803 } 813 }
804} 814}
805 815