diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-at91/pm.c | 20 | ||||
-rw-r--r-- | arch/arm/mach-at91/pm_slowclock.S | 41 |
2 files changed, 26 insertions, 35 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index d554e6771b4e..aac00cecbf4f 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
@@ -188,13 +188,27 @@ int at91_suspend_entering_slow_clock(void) | |||
188 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | 188 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); |
189 | 189 | ||
190 | 190 | ||
191 | static void (*slow_clock)(void); | 191 | static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1); |
192 | 192 | ||
193 | #ifdef CONFIG_AT91_SLOW_CLOCK | 193 | #ifdef CONFIG_AT91_SLOW_CLOCK |
194 | extern void at91_slow_clock(void); | 194 | extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1); |
195 | extern u32 at91_slow_clock_sz; | 195 | extern u32 at91_slow_clock_sz; |
196 | #endif | 196 | #endif |
197 | 197 | ||
198 | static void __iomem *at91_pmc_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_PMC); | ||
199 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
200 | static void __iomem *at91_ramc0_base = (void __iomem*)AT91_VA_BASE_SYS; | ||
201 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
202 | static void __iomem *at91_ramc0_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_DDRSDRC0); | ||
203 | #else | ||
204 | static void __iomem *at91_ramc0_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_SDRAMC0); | ||
205 | #endif | ||
206 | |||
207 | #if defined(CONFIG_ARCH_AT91SAM9G45) | ||
208 | static void __iomem *at91_ramc1_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_DDRSDRC1); | ||
209 | #else | ||
210 | static void __iomem *at91_ramc1_base = NULL; | ||
211 | #endif | ||
198 | 212 | ||
199 | static int at91_pm_enter(suspend_state_t state) | 213 | static int at91_pm_enter(suspend_state_t state) |
200 | { | 214 | { |
@@ -232,7 +246,7 @@ static int at91_pm_enter(suspend_state_t state) | |||
232 | /* copy slow_clock handler to SRAM, and call it */ | 246 | /* copy slow_clock handler to SRAM, and call it */ |
233 | memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); | 247 | memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); |
234 | #endif | 248 | #endif |
235 | slow_clock(); | 249 | slow_clock(at91_pmc_base, at91_ramc0_base, at91_ramc1_base); |
236 | break; | 250 | break; |
237 | } else { | 251 | } else { |
238 | pr_info("AT91: PM - no slow clock mode enabled ...\n"); | 252 | pr_info("AT91: PM - no slow clock mode enabled ...\n"); |
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index c802d309582f..e31a5f222d86 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S | |||
@@ -46,11 +46,11 @@ | |||
46 | #define PLLALOCK_TIMEOUT 1000 | 46 | #define PLLALOCK_TIMEOUT 1000 |
47 | #define PLLBLOCK_TIMEOUT 1000 | 47 | #define PLLBLOCK_TIMEOUT 1000 |
48 | 48 | ||
49 | pmc .req r1 | 49 | pmc .req r0 |
50 | sdramc .req r2 | 50 | sdramc .req r1 |
51 | ramc1 .req r2 | ||
51 | tmp1 .req r3 | 52 | tmp1 .req r3 |
52 | tmp2 .req r4 | 53 | tmp2 .req r4 |
53 | ramc1 .req r5 | ||
54 | 54 | ||
55 | /* | 55 | /* |
56 | * Wait until master clock is ready (after switching master clock source) | 56 | * Wait until master clock is ready (after switching master clock source) |
@@ -110,21 +110,19 @@ ramc1 .req r5 | |||
110 | 110 | ||
111 | .text | 111 | .text |
112 | 112 | ||
113 | /* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, void __iomem *ramc1) */ | ||
113 | ENTRY(at91_slow_clock) | 114 | ENTRY(at91_slow_clock) |
114 | /* Save registers on stack */ | 115 | /* Save registers on stack */ |
115 | stmfd sp!, {r0 - r12, lr} | 116 | stmfd sp!, {r3 - r12, lr} |
116 | 117 | ||
117 | /* | 118 | /* |
118 | * Register usage: | 119 | * Register usage: |
119 | * R1 = Base address of AT91_PMC | 120 | * R0 = Base address of AT91_PMC |
120 | * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) | 121 | * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) |
122 | * R2 = Base address of second RAM Controller or 0 if not present | ||
121 | * R3 = temporary register | 123 | * R3 = temporary register |
122 | * R4 = temporary register | 124 | * R4 = temporary register |
123 | * R5 = Base address of second RAM Controller or 0 if not present | ||
124 | */ | 125 | */ |
125 | ldr pmc, .at91_va_base_pmc | ||
126 | ldr sdramc, .at91_va_base_sdramc | ||
127 | ldr ramc1, .at91_va_base_ramc1 | ||
128 | 126 | ||
129 | /* Drain write buffer */ | 127 | /* Drain write buffer */ |
130 | mov tmp1, #0 | 128 | mov tmp1, #0 |
@@ -283,7 +281,7 @@ ENTRY(at91_slow_clock) | |||
283 | #endif | 281 | #endif |
284 | 282 | ||
285 | /* Restore registers, and return */ | 283 | /* Restore registers, and return */ |
286 | ldmfd sp!, {r0 - r12, pc} | 284 | ldmfd sp!, {r3 - r12, pc} |
287 | 285 | ||
288 | 286 | ||
289 | .saved_mckr: | 287 | .saved_mckr: |
@@ -301,26 +299,5 @@ ENTRY(at91_slow_clock) | |||
301 | .saved_sam9_lpr1: | 299 | .saved_sam9_lpr1: |
302 | .word 0 | 300 | .word 0 |
303 | 301 | ||
304 | .at91_va_base_pmc: | ||
305 | .word AT91_VA_BASE_SYS + AT91_PMC | ||
306 | |||
307 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
308 | .at91_va_base_sdramc: | ||
309 | .word AT91_VA_BASE_SYS | ||
310 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
311 | .at91_va_base_sdramc: | ||
312 | .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 | ||
313 | #else | ||
314 | .at91_va_base_sdramc: | ||
315 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 | ||
316 | #endif | ||
317 | |||
318 | .at91_va_base_ramc1: | ||
319 | #if defined(CONFIG_ARCH_AT91SAM9G45) | ||
320 | .word AT91_VA_BASE_SYS + AT91_DDRSDRC1 | ||
321 | #else | ||
322 | .word 0 | ||
323 | #endif | ||
324 | |||
325 | ENTRY(at91_slow_clock_sz) | 302 | ENTRY(at91_slow_clock_sz) |
326 | .word .-at91_slow_clock | 303 | .word .-at91_slow_clock |