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-rw-r--r--arch/arm/mach-at91/Kconfig14
-rw-r--r--arch/arm/mach-at91/Makefile14
-rw-r--r--arch/arm/mach-at91/at91cap9.c9
-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam9_alt_reset.S7
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c7
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S40
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
-rw-r--r--arch/arm/mach-at91/pm.c9
-rw-r--r--arch/arm/mach-at91/pm.h8
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S5
-rw-r--r--arch/arm/mach-at91/setup.c16
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c11
-rw-r--r--arch/arm/mach-imx/mach-mx53_ard.c4
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c2
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c48
-rw-r--r--arch/arm/mach-ux500/usb.c6
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h2
32 files changed, 163 insertions, 216 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4f991f295284..71feb00a1e99 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,6 +18,12 @@ config HAVE_AT91_USART4
18config HAVE_AT91_USART5 18config HAVE_AT91_USART5
19 bool 19 bool
20 20
21config AT91_SAM9_ALT_RESET
22 bool
23
24config AT91_SAM9G45_RESET
25 bool
26
21menu "Atmel AT91 System-on-Chip" 27menu "Atmel AT91 System-on-Chip"
22 28
23choice 29choice
@@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
39 select HAVE_AT91_USART4 45 select HAVE_AT91_USART4
40 select HAVE_AT91_USART5 46 select HAVE_AT91_USART5
41 select HAVE_NET_MACB 47 select HAVE_NET_MACB
48 select AT91_SAM9_ALT_RESET
42 49
43config ARCH_AT91SAM9261 50config ARCH_AT91SAM9261
44 bool "AT91SAM9261" 51 bool "AT91SAM9261"
@@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
46 select GENERIC_CLOCKEVENTS 53 select GENERIC_CLOCKEVENTS
47 select HAVE_FB_ATMEL 54 select HAVE_FB_ATMEL
48 select HAVE_AT91_DBGU0 55 select HAVE_AT91_DBGU0
56 select AT91_SAM9_ALT_RESET
49 57
50config ARCH_AT91SAM9G10 58config ARCH_AT91SAM9G10
51 bool "AT91SAM9G10" 59 bool "AT91SAM9G10"
@@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
53 select GENERIC_CLOCKEVENTS 61 select GENERIC_CLOCKEVENTS
54 select HAVE_AT91_DBGU0 62 select HAVE_AT91_DBGU0
55 select HAVE_FB_ATMEL 63 select HAVE_FB_ATMEL
64 select AT91_SAM9_ALT_RESET
56 65
57config ARCH_AT91SAM9263 66config ARCH_AT91SAM9263
58 bool "AT91SAM9263" 67 bool "AT91SAM9263"
@@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
61 select HAVE_FB_ATMEL 70 select HAVE_FB_ATMEL
62 select HAVE_NET_MACB 71 select HAVE_NET_MACB
63 select HAVE_AT91_DBGU1 72 select HAVE_AT91_DBGU1
73 select AT91_SAM9_ALT_RESET
64 74
65config ARCH_AT91SAM9RL 75config ARCH_AT91SAM9RL
66 bool "AT91SAM9RL" 76 bool "AT91SAM9RL"
@@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
69 select HAVE_AT91_USART3 79 select HAVE_AT91_USART3
70 select HAVE_FB_ATMEL 80 select HAVE_FB_ATMEL
71 select HAVE_AT91_DBGU0 81 select HAVE_AT91_DBGU0
82 select AT91_SAM9_ALT_RESET
72 83
73config ARCH_AT91SAM9G20 84config ARCH_AT91SAM9G20
74 bool "AT91SAM9G20" 85 bool "AT91SAM9G20"
@@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
79 select HAVE_AT91_USART4 90 select HAVE_AT91_USART4
80 select HAVE_AT91_USART5 91 select HAVE_AT91_USART5
81 select HAVE_NET_MACB 92 select HAVE_NET_MACB
93 select AT91_SAM9_ALT_RESET
82 94
83config ARCH_AT91SAM9G45 95config ARCH_AT91SAM9G45
84 bool "AT91SAM9G45" 96 bool "AT91SAM9G45"
@@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
88 select HAVE_FB_ATMEL 100 select HAVE_FB_ATMEL
89 select HAVE_NET_MACB 101 select HAVE_NET_MACB
90 select HAVE_AT91_DBGU1 102 select HAVE_AT91_DBGU1
103 select AT91_SAM9G45_RESET
91 104
92config ARCH_AT91CAP9 105config ARCH_AT91CAP9
93 bool "AT91CAP9" 106 bool "AT91CAP9"
@@ -96,6 +109,7 @@ config ARCH_AT91CAP9
96 select HAVE_FB_ATMEL 109 select HAVE_FB_ATMEL
97 select HAVE_NET_MACB 110 select HAVE_NET_MACB
98 select HAVE_AT91_DBGU1 111 select HAVE_AT91_DBGU1
112 select AT91_SAM9G45_RESET
99 113
100config ARCH_AT91X40 114config ARCH_AT91X40
101 bool "AT91x40" 115 bool "AT91x40"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 242174f9f355..705e1fbded39 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -8,15 +8,17 @@ obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o 10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
11 13
12# CPU-specific support 14# CPU-specific support
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o 15obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o 16obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o 17obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
16obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o 18obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
17obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o 19obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
18obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o 20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o 21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
20obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 23obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index edb879ac04c8..a42edc25a87e 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -21,7 +21,6 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22#include <mach/at91cap9.h> 22#include <mach/at91cap9.h>
23#include <mach/at91_pmc.h> 23#include <mach/at91_pmc.h>
24#include <mach/at91_rstc.h>
25 24
26#include "soc.h" 25#include "soc.h"
27#include "generic.h" 26#include "generic.h"
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
314 } 313 }
315}; 314};
316 315
317static void at91cap9_restart(char mode, const char *cmd)
318{
319 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
320}
321
322/* -------------------------------------------------------------------- 316/* --------------------------------------------------------------------
323 * AT91CAP9 processor initialization 317 * AT91CAP9 processor initialization
324 * -------------------------------------------------------------------- */ 318 * -------------------------------------------------------------------- */
@@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
331static void __init at91cap9_ioremap_registers(void) 325static void __init at91cap9_ioremap_registers(void)
332{ 326{
333 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); 327 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
328 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
334 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); 329 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
335 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); 330 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
336} 331}
337 332
338static void __init at91cap9_initialize(void) 333static void __init at91cap9_initialize(void)
339{ 334{
340 arm_pm_restart = at91cap9_restart; 335 arm_pm_restart = at91sam9g45_restart;
341 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); 336 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
342 337
343 /* Register GPIO subsystem */ 338 /* Register GPIO subsystem */
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5e46e4a96430..d4036ba43612 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
323static void __init at91sam9260_ioremap_registers(void) 323static void __init at91sam9260_ioremap_registers(void)
324{ 324{
325 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); 325 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
326 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
326 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 327 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
327 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 328 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
328} 329}
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index b85b9ea60170..023c2ff138df 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
281static void __init at91sam9261_ioremap_registers(void) 281static void __init at91sam9261_ioremap_registers(void)
282{ 282{
283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); 283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
284 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
284 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 285 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
285 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 286 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
286} 287}
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 79e3669b1117..75e876c258af 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
301static void __init at91sam9263_ioremap_registers(void) 301static void __init at91sam9263_ioremap_registers(void)
302{ 302{
303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); 303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
304 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
304 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 305 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
305 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 306 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
306 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 307 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index d3f931c5942e..518e42377171 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -23,7 +23,8 @@
23 .globl at91sam9_alt_restart 23 .globl at91sam9_alt_restart
24 24
25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants 25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
26 ldr r1, .at91_va_base_rstc_cr 26 ldr r1, =at91_rstc_base
27 ldr r1, [r1]
27 28
28 mov r2, #1 29 mov r2, #1
29 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN 30 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
33 34
34 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access 35 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
35 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM 36 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
36 str r4, [r1] @ reset processor 37 str r4, [r1, #AT91_RSTC_CR] @ reset processor
37 38
38 b . 39 b .
39 40
40.at91_va_base_sdramc: 41.at91_va_base_sdramc:
41 .word AT91_VA_BASE_SYS + AT91_SDRAMC0 42 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
42.at91_va_base_rstc_cr:
43 .word AT91_VA_BASE_SYS + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 7032dd32cdf0..1cb6a96b1c1e 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,7 +18,6 @@
18#include <asm/mach/map.h> 18#include <asm/mach/map.h>
19#include <mach/at91sam9g45.h> 19#include <mach/at91sam9g45.h>
20#include <mach/at91_pmc.h> 20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h>
22#include <mach/cpu.h> 21#include <mach/cpu.h>
23 22
24#include "soc.h" 23#include "soc.h"
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
318 } 317 }
319}; 318};
320 319
321static void at91sam9g45_restart(char mode, const char *cmd)
322{
323 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
324}
325
326/* -------------------------------------------------------------------- 320/* --------------------------------------------------------------------
327 * AT91SAM9G45 processor initialization 321 * AT91SAM9G45 processor initialization
328 * -------------------------------------------------------------------- */ 322 * -------------------------------------------------------------------- */
@@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
336static void __init at91sam9g45_ioremap_registers(void) 330static void __init at91sam9g45_ioremap_registers(void)
337{ 331{
338 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); 332 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
333 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
339 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 334 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
340 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 335 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
341} 336}
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
new file mode 100644
index 000000000000..0468be10980b
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -0,0 +1,40 @@
1/*
2 * reset AT91SAM9G45 as per errata
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
5 *
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
9 *
10 * GPLv2 Only
11 */
12
13#include <linux/linkage.h>
14#include <mach/hardware.h>
15#include <mach/at91sam9_ddrsdr.h>
16#include <mach/at91_rstc.h>
17
18 .arm
19
20 .globl at91sam9g45_restart
21
22at91sam9g45_restart:
23 ldr r0, .at91_va_base_sdramc0 @ preload constants
24 ldr r1, =at91_rstc_base
25 ldr r1, [r1]
26
27 mov r2, #1
28 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
29 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
30
31 .balign 32 @ align to cache line
32
33 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
34 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
35 str r4, [r1, #AT91_RSTC_CR] @ reset processor
36
37 b .
38
39.at91_va_base_sdramc0:
40 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d6bcb1da11df..d2c91a841cb8 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
286static void __init at91sam9rl_ioremap_registers(void) 286static void __init at91sam9rl_ioremap_registers(void)
287{ 287{
288 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); 288 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
289 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
289 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 290 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
290 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 291 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
291} 292}
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 4866b8180d66..594133451c0c 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
58extern void at91_irq_resume(void); 58extern void at91_irq_resume(void);
59 59
60/* reset */ 60/* reset */
61extern void at91_ioremap_rstc(u32 base_addr);
61extern void at91sam9_alt_restart(char, const char *); 62extern void at91sam9_alt_restart(char, const char *);
63extern void at91sam9g45_restart(char, const char *);
62 64
63/* shutdown */ 65/* shutdown */
64extern void at91_ioremap_shdwc(u32 base_addr); 66extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index cbd2bf052c1f..875fa336800b 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,25 @@
16#ifndef AT91_RSTC_H 16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H 17#define AT91_RSTC_H
18 18
19#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_rstc_base;
21
22#define at91_rstc_read(field) \
23 __raw_readl(at91_rstc_base + field)
24
25#define at91_rstc_write(field, value) \
26 __raw_writel(value, at91_rstc_base + field);
27#else
28.extern at91_rstc_base
29#endif
30
31#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
20#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ 32#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
21#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ 33#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
22#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ 34#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
23#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ 35#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
24 36
25#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ 37#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
26#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ 38#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
27#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ 39#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
28#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) 40#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +45,7 @@
33#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ 45#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
34#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ 46#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
35 47
36#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ 48#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
37#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ 49#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
38#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ 50#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
39#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ 51#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 4c0e2f6011d7..61d952902f2b 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -83,7 +83,6 @@
83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 86#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
88 (0xfffffd50 - AT91_BASE_SYS) : \ 87 (0xfffffd50 - AT91_BASE_SYS) : \
89 (0xfffffd60 - AT91_BASE_SYS)) 88 (0xfffffd60 - AT91_BASE_SYS))
@@ -96,6 +95,7 @@
96#define AT91CAP9_BASE_PIOB 0xfffff400 95#define AT91CAP9_BASE_PIOB 0xfffff400
97#define AT91CAP9_BASE_PIOC 0xfffff600 96#define AT91CAP9_BASE_PIOC 0xfffff600
98#define AT91CAP9_BASE_PIOD 0xfffff800 97#define AT91CAP9_BASE_PIOD 0xfffff800
98#define AT91CAP9_BASE_RSTC 0xfffffd00
99#define AT91CAP9_BASE_SHDWC 0xfffffd10 99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20 100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30 101#define AT91CAP9_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644
index 976f4a6c3353..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
46#define AT91_DDRSDRC_CAS_2 (2 << 4)
47#define AT91_DDRSDRC_CAS_3 (3 << 4)
48#define AT91_DDRSDRC_CAS_25 (6 << 4)
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51
52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61
62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67
68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82
83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89
90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
107
108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index f937c476bb67..fa5ca278adeb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -83,7 +83,6 @@
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
88 87
89#define AT91SAM9260_BASE_ECC 0xffffe800 88#define AT91SAM9260_BASE_ECC 0xffffe800
@@ -92,6 +91,7 @@
92#define AT91SAM9260_BASE_PIOA 0xfffff400 91#define AT91SAM9260_BASE_PIOA 0xfffff400
93#define AT91SAM9260_BASE_PIOB 0xfffff600 92#define AT91SAM9260_BASE_PIOB 0xfffff600
94#define AT91SAM9260_BASE_PIOC 0xfffff800 93#define AT91SAM9260_BASE_PIOC 0xfffff800
94#define AT91SAM9260_BASE_RSTC 0xfffffd00
95#define AT91SAM9260_BASE_SHDWC 0xfffffd10 95#define AT91SAM9260_BASE_SHDWC 0xfffffd10
96#define AT91SAM9260_BASE_RTT 0xfffffd20 96#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30 97#define AT91SAM9260_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 175604e261be..7cde2d36570e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,6 @@
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
72#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
73 72
74#define AT91SAM9261_BASE_SMC 0xffffec00 73#define AT91SAM9261_BASE_SMC 0xffffec00
@@ -76,6 +75,7 @@
76#define AT91SAM9261_BASE_PIOA 0xfffff400 75#define AT91SAM9261_BASE_PIOA 0xfffff400
77#define AT91SAM9261_BASE_PIOB 0xfffff600 76#define AT91SAM9261_BASE_PIOB 0xfffff600
78#define AT91SAM9261_BASE_PIOC 0xfffff800 77#define AT91SAM9261_BASE_PIOC 0xfffff800
78#define AT91SAM9261_BASE_RSTC 0xfffffd00
79#define AT91SAM9261_BASE_SHDWC 0xfffffd10 79#define AT91SAM9261_BASE_SHDWC 0xfffffd10
80#define AT91SAM9261_BASE_RTT 0xfffffd20 80#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30 81#define AT91SAM9261_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 80c915002d83..5949abda962b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -78,7 +78,6 @@
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
82#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
83 82
84#define AT91SAM9263_BASE_ECC0 0xffffe000 83#define AT91SAM9263_BASE_ECC0 0xffffe000
@@ -91,6 +90,7 @@
91#define AT91SAM9263_BASE_PIOC 0xfffff600 90#define AT91SAM9263_BASE_PIOC 0xfffff600
92#define AT91SAM9263_BASE_PIOD 0xfffff800 91#define AT91SAM9263_BASE_PIOD 0xfffff800
93#define AT91SAM9263_BASE_PIOE 0xfffffa00 92#define AT91SAM9263_BASE_PIOE 0xfffffa00
93#define AT91SAM9263_BASE_RSTC 0xfffffd00
94#define AT91SAM9263_BASE_SHDWC 0xfffffd10 94#define AT91SAM9263_BASE_SHDWC 0xfffffd10
95#define AT91SAM9263_BASE_RTT0 0xfffffd20 95#define AT91SAM9263_BASE_RTT0 0xfffffd20
96#define AT91SAM9263_BASE_PIT 0xfffffd30 96#define AT91SAM9263_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index d27b15ba8ebf..e2f8da8ce5bc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -46,10 +46,10 @@
46#define AT91_DDRSDRC_CAS_25 (6 << 4) 46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ 49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ 50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ 51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ 52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
@@ -59,7 +59,8 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ 62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64 65
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 66#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
@@ -68,13 +69,14 @@
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 69#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 70#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70 71
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ 72#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ 73#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ 74#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ 75#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76 77
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0 81#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -92,32 +94,40 @@
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93 95
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0 99#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6 103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4) 105#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 106#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103 107
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
109 119
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ 120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112 122
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ 123#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114 124
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ 125#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ 126#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ 127#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ 128#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119 129
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ 130#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 131#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 132#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 133
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index f0c23c960dec..dd9c95ea0862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -90,7 +90,6 @@
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95 94
96#define AT91SAM9G45_BASE_ECC 0xffffe200 95#define AT91SAM9G45_BASE_ECC 0xffffe200
@@ -102,6 +101,7 @@
102#define AT91SAM9G45_BASE_PIOC 0xfffff600 101#define AT91SAM9G45_BASE_PIOC 0xfffff600
103#define AT91SAM9G45_BASE_PIOD 0xfffff800 102#define AT91SAM9G45_BASE_PIOD 0xfffff800
104#define AT91SAM9G45_BASE_PIOE 0xfffffa00 103#define AT91SAM9G45_BASE_PIOE 0xfffffa00
104#define AT91SAM9G45_BASE_RSTC 0xfffffd00
105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
106#define AT91SAM9G45_BASE_RTT 0xfffffd20 106#define AT91SAM9G45_BASE_RTT 0xfffffd20
107#define AT91SAM9G45_BASE_PIT 0xfffffd30 107#define AT91SAM9G45_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 2bb359e60b97..d7bead7118da 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -72,7 +72,6 @@
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
76#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
77#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
78 77
@@ -84,6 +83,7 @@
84#define AT91SAM9RL_BASE_PIOB 0xfffff600 83#define AT91SAM9RL_BASE_PIOB 0xfffff600
85#define AT91SAM9RL_BASE_PIOC 0xfffff800 84#define AT91SAM9RL_BASE_PIOC 0xfffff800
86#define AT91SAM9RL_BASE_PIOD 0xfffffa00 85#define AT91SAM9RL_BASE_PIOD 0xfffffa00
86#define AT91SAM9RL_BASE_RSTC 0xfffffd00
87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
88#define AT91SAM9RL_BASE_RTT 0xfffffd20 88#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30 89#define AT91SAM9RL_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index d0b377b21bd7..3b33f07b1e11 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
88struct at91_usbh_data { 88struct at91_usbh_data {
89 u8 ports; /* number of ports on root hub */ 89 u8 ports; /* number of ports on root hub */
90 int vbus_pin[2]; /* port power-control pin */ 90 int vbus_pin[2]; /* port power-control pin */
91 u8 vbus_pin_inverted; 91 u8 vbus_pin_active_low[2];
92 u8 overcurrent_supported; 92 u8 overcurrent_supported;
93 int overcurrent_pin[2]; 93 int overcurrent_pin[2];
94 u8 overcurrent_status[2]; 94 u8 overcurrent_status[2];
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 62ad95556c36..1606379ac284 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,7 +34,6 @@
34/* 34/*
35 * Show the reason for the previous system reset. 35 * Show the reason for the previous system reset.
36 */ 36 */
37#if defined(AT91_RSTC)
38 37
39#include <mach/at91_rstc.h> 38#include <mach/at91_rstc.h>
40#include <mach/at91_shdwc.h> 39#include <mach/at91_shdwc.h>
@@ -58,10 +57,10 @@ static void __init show_reset_status(void)
58 char *reason, *r2 = reset; 57 char *reason, *r2 = reset;
59 u32 reset_type, wake_type; 58 u32 reset_type, wake_type;
60 59
61 if (!at91_shdwc_base) 60 if (!at91_shdwc_base || !at91_rstc_base)
62 return; 61 return;
63 62
64 reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; 63 reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
65 wake_type = at91_shdwc_read(AT91_SHDW_SR); 64 wake_type = at91_shdwc_read(AT91_SHDW_SR);
66 65
67 switch (reset_type) { 66 switch (reset_type) {
@@ -102,10 +101,6 @@ static void __init show_reset_status(void)
102 } 101 }
103 pr_info("AT91: Starting after %s %s\n", reason, r2); 102 pr_info("AT91: Starting after %s %s\n", reason, r2);
104} 103}
105#else
106static void __init show_reset_status(void) {}
107#endif
108
109 104
110static int at91_pm_valid_state(suspend_state_t state) 105static int at91_pm_valid_state(suspend_state_t state)
111{ 106{
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ce9a20699111..7eb40d24242f 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
25 : : "r" (0)) 25 : : "r" (0))
26 26
27#elif defined(CONFIG_ARCH_AT91CAP9) 27#elif defined(CONFIG_ARCH_AT91CAP9)
28#include <mach/at91cap9_ddrsdr.h> 28#include <mach/at91sam9_ddrsdr.h>
29 29
30 30
31static inline u32 sdram_selfrefresh_enable(void) 31static inline u32 sdram_selfrefresh_enable(void)
32{ 32{
33 u32 saved_lpr, lpr; 33 u32 saved_lpr, lpr;
34 34
35 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); 35 saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
36 36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 38 at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr; 39 return saved_lpr;
40} 40}
41 41
42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) 42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
43#define wait_for_interrupt_enable() cpu_do_idle() 43#define wait_for_interrupt_enable() cpu_do_idle()
44 44
45#elif defined(CONFIG_ARCH_AT91SAM9G45) 45#elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f7922a436172..92dfb8461392 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,9 +18,8 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9) \
22#include <mach/at91cap9_ddrsdr.h> 22 || defined(CONFIG_ARCH_AT91SAM9G45)
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h> 23#include <mach/at91sam9_ddrsdr.h>
25#else 24#else
26#include <mach/at91sam9_sdramc.h> 25#include <mach/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 8bdcc3cb6012..69d3fc4c46f3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
29void __init at91rm9200_set_type(int type) 29void __init at91rm9200_set_type(int type)
30{ 30{
31 if (type == ARCH_REVISON_9200_PQFP) 31 if (type == ARCH_REVISON_9200_PQFP)
32 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
33 else
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; 32 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
33 else
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
35
36 pr_info("AT91: filled in soc subtype: %s\n",
37 at91_get_soc_subtype(&at91_soc_initdata));
35} 38}
36 39
37void __init at91_init_irq_default(void) 40void __init at91_init_irq_default(void)
@@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
281 pm_power_off = at91sam9_poweroff; 284 pm_power_off = at91sam9_poweroff;
282} 285}
283 286
287void __iomem *at91_rstc_base;
288
289void __init at91_ioremap_rstc(u32 base_addr)
290{
291 at91_rstc_base = ioremap(base_addr, 16);
292 if (!at91_rstc_base)
293 panic("Impossible to ioremap at91_rstc_base\n");
294}
295
284void __init at91_initialize(unsigned long main_clock) 296void __init at91_initialize(unsigned long main_clock)
285{ 297{
286 at91_boot_soc.ioremap_registers(); 298 at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 9273c2a24b54..2d88f8b9a454 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
814DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); 814DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
815DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); 815DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
816 816
817static unsigned long twd_clk_get_rate(struct clk *clk)
818{
819 return clk_get_rate(clk->parent) / 2;
820}
821
822static struct clk twd_clk = {
823 .parent = &arm_clk,
824 .get_rate = twd_clk_get_rate,
825};
826
817static unsigned long pll2_200m_get_rate(struct clk *clk) 827static unsigned long pll2_200m_get_rate(struct clk *clk)
818{ 828{
819 return clk_get_rate(clk->parent) / 2; 829 return clk_get_rate(clk->parent) / 2;
@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
1894 _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), 1904 _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
1895 _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), 1905 _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
1896 _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), 1906 _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
1907 _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
1897 _REGISTER_CLOCK(NULL, "ckih", ckih_clk), 1908 _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
1898 _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), 1909 _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
1899 _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), 1910 _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 08dfb7628d2d..753f4fc9ec04 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -188,8 +188,10 @@ static int weim_cs_config(void)
188 return -ENOMEM; 188 return -ENOMEM;
189 189
190 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); 190 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
191 if (!iomuxc_base) 191 if (!iomuxc_base) {
192 iounmap(weim_base);
192 return -ENOMEM; 193 return -ENOMEM;
194 }
193 195
194 /* CS1 timings for LAN9220 */ 196 /* CS1 timings for LAN9220 */
195 writel(0x20001, (weim_base + 0x18)); 197 writel(0x20001, (weim_base + 0x18));
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index a3e0c8692f0d..52af00446a63 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON
7 select HAS_MTU 7 select HAS_MTU
8 select ARM_ERRATA_753970 8 select ARM_ERRATA_753970
9 select ARM_ERRATA_754322 9 select ARM_ERRATA_754322
10 select ARM_ERRATA_764369
10 11
11menu "Ux500 SoC" 12menu "Ux500 SoC"
12 13
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 23be34b3bb6e..5dde4d4ebe88 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -261,6 +261,8 @@ void __init mop500_sdi_init(void)
261 261
262void __init snowball_sdi_init(void) 262void __init snowball_sdi_init(void)
263{ 263{
264 /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
265 mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
264 /* On-board eMMC */ 266 /* On-board eMMC */
265 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 267 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
266 /* External Micro SD slot */ 268 /* External Micro SD slot */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 122ddde00ba7..da5569d83d58 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -12,44 +12,6 @@
12 12
13static void __iomem *l2x0_base; 13static void __iomem *l2x0_base;
14 14
15static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
16{
17 /* wait for the operation to complete */
18 while (readl_relaxed(reg) & mask)
19 cpu_relax();
20}
21
22static inline void ux500_cache_sync(void)
23{
24 writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
25 ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
26}
27
28/*
29 * The L2 cache cannot be turned off in the non-secure world.
30 * Dummy until a secure service is in place.
31 */
32static void ux500_l2x0_disable(void)
33{
34}
35
36/*
37 * This is only called when doing a kexec, just after turning off the L2
38 * and L1 cache, and it is surrounded by a spinlock in the generic version.
39 * However, we're not really turning off the L2 cache right now and the
40 * PL310 does not support exclusive accesses (used to implement the spinlock).
41 * So, the invalidation needs to be done without the spinlock.
42 */
43static void ux500_l2x0_inv_all(void)
44{
45 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
46
47 /* invalidate all ways */
48 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
49 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
50 ux500_cache_sync();
51}
52
53static int __init ux500_l2x0_unlock(void) 15static int __init ux500_l2x0_unlock(void)
54{ 16{
55 int i; 17 int i;
@@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void)
85 /* 64KB way size, 8 way associativity, force WA */ 47 /* 64KB way size, 8 way associativity, force WA */
86 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); 48 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
87 49
88 /* Override invalidate function */ 50 /*
89 outer_cache.disable = ux500_l2x0_disable; 51 * We can't disable l2 as we are in non secure mode, currently
90 outer_cache.inv_all = ux500_l2x0_inv_all; 52 * this seems be called only during kexec path. So let's
53 * override outer.disable with nasty assignment until we have
54 * some SMI service available.
55 */
56 outer_cache.disable = NULL;
91 57
92 return 0; 58 return 0;
93} 59}
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 0a01cbdfe063..9f9e1c203061 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -95,13 +95,7 @@ static struct musb_hdrc_config musb_hdrc_config = {
95}; 95};
96 96
97static struct musb_hdrc_platform_data musb_platform_data = { 97static struct musb_hdrc_platform_data musb_platform_data = {
98#if defined(CONFIG_USB_MUSB_OTG)
99 .mode = MUSB_OTG, 98 .mode = MUSB_OTG,
100#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
101 .mode = MUSB_PERIPHERAL,
102#else /* defined(CONFIG_USB_MUSB_HOST) */
103 .mode = MUSB_HOST,
104#endif
105 .config = &musb_hdrc_config, 99 .config = &musb_hdrc_config,
106 .board_data = &musb_board_data, 100 .board_data = &musb_board_data,
107}; 101};
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 6fa8a707b9a0..f7d18046c04f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -96,6 +96,6 @@ extern int mxc_gpio_mode(int gpio_mode);
96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
97 const char *label); 97 const char *label);
98 98
99extern int __init imx_iomuxv1_init(void __iomem *base, int numports); 99extern int imx_iomuxv1_init(void __iomem *base, int numports);
100 100
101#endif /* __MACH_IOMUX_V1_H__ */ 101#endif /* __MACH_IOMUX_V1_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 08:41:30 -0500