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-rw-r--r--arch/sparc/Kconfig1
-rw-r--r--arch/sparc/defconfig139
-rw-r--r--arch/sparc/kernel/Makefile1
-rw-r--r--arch/sparc/kernel/entry.S125
-rw-r--r--arch/sparc/kernel/head.S9
-rw-r--r--arch/sparc/kernel/kgdb.c164
-rw-r--r--arch/sparc/kernel/sparc-stub.c724
-rw-r--r--arch/sparc/kernel/sun4d_smp.c32
-rw-r--r--arch/sparc/kernel/sun4m_smp.c45
-rw-r--r--arch/sparc64/Kconfig1
-rw-r--r--arch/sparc64/kernel/Makefile1
-rw-r--r--arch/sparc64/kernel/cherrs.S579
-rw-r--r--arch/sparc64/kernel/entry.S2575
-rw-r--r--arch/sparc64/kernel/fpu_traps.S384
-rw-r--r--arch/sparc64/kernel/getsetcc.S24
-rw-r--r--arch/sparc64/kernel/head.S15
-rw-r--r--arch/sparc64/kernel/helpers.S63
-rw-r--r--arch/sparc64/kernel/hvcalls.S886
-rw-r--r--arch/sparc64/kernel/ivec.S51
-rw-r--r--arch/sparc64/kernel/kgdb.c186
-rw-r--r--arch/sparc64/kernel/misctrap.S97
-rw-r--r--arch/sparc64/kernel/smp.c11
-rw-r--r--arch/sparc64/kernel/spiterrs.S245
-rw-r--r--arch/sparc64/kernel/syscalls.S279
-rw-r--r--arch/sparc64/kernel/ttable.S2
-rw-r--r--arch/sparc64/kernel/utrap.S29
-rw-r--r--arch/sparc64/mm/ultra.S27
27 files changed, 3169 insertions, 3526 deletions
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 49590f8fe98c..d211fdb24584 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -68,6 +68,7 @@ config SPARC
68 default y 68 default y
69 select HAVE_IDE 69 select HAVE_IDE
70 select HAVE_OPROFILE 70 select HAVE_OPROFILE
71 select HAVE_ARCH_KGDB if !SMP
71 72
72# Identify this as a Sparc32 build 73# Identify this as a Sparc32 build
73config SPARC32 74config SPARC32
diff --git a/arch/sparc/defconfig b/arch/sparc/defconfig
index 6a2c57a2fe71..2e3a149ea0e7 100644
--- a/arch/sparc/defconfig
+++ b/arch/sparc/defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25 3# Linux kernel version: 2.6.25
4# Sun Apr 20 01:49:51 2008 4# Tue Apr 29 01:28:58 2008
5# 5#
6CONFIG_MMU=y 6CONFIG_MMU=y
7CONFIG_HIGHMEM=y 7CONFIG_HIGHMEM=y
@@ -217,12 +217,7 @@ CONFIG_IPV6_TUNNEL=m
217# CONFIG_NETWORK_SECMARK is not set 217# CONFIG_NETWORK_SECMARK is not set
218# CONFIG_NETFILTER is not set 218# CONFIG_NETFILTER is not set
219# CONFIG_IP_DCCP is not set 219# CONFIG_IP_DCCP is not set
220CONFIG_IP_SCTP=m 220# CONFIG_IP_SCTP is not set
221# CONFIG_SCTP_DBG_MSG is not set
222CONFIG_SCTP_DBG_OBJCNT=y
223# CONFIG_SCTP_HMAC_NONE is not set
224# CONFIG_SCTP_HMAC_SHA1 is not set
225CONFIG_SCTP_HMAC_MD5=y
226# CONFIG_TIPC is not set 221# CONFIG_TIPC is not set
227# CONFIG_ATM is not set 222# CONFIG_ATM is not set
228# CONFIG_BRIDGE is not set 223# CONFIG_BRIDGE is not set
@@ -245,9 +240,7 @@ CONFIG_NET_PKTGEN=m
245# CONFIG_CAN is not set 240# CONFIG_CAN is not set
246# CONFIG_IRDA is not set 241# CONFIG_IRDA is not set
247# CONFIG_BT is not set 242# CONFIG_BT is not set
248CONFIG_AF_RXRPC=m 243# CONFIG_AF_RXRPC is not set
249# CONFIG_AF_RXRPC_DEBUG is not set
250# CONFIG_RXKAD is not set
251 244
252# 245#
253# Wireless 246# Wireless
@@ -390,7 +383,7 @@ CONFIG_DUMMY=m
390# CONFIG_BONDING is not set 383# CONFIG_BONDING is not set
391# CONFIG_MACVLAN is not set 384# CONFIG_MACVLAN is not set
392# CONFIG_EQUALIZER is not set 385# CONFIG_EQUALIZER is not set
393CONFIG_TUN=m 386# CONFIG_TUN is not set
394# CONFIG_VETH is not set 387# CONFIG_VETH is not set
395# CONFIG_ARCNET is not set 388# CONFIG_ARCNET is not set
396# CONFIG_PHYLIB is not set 389# CONFIG_PHYLIB is not set
@@ -544,6 +537,7 @@ CONFIG_SERIAL_SUNSU_CONSOLE=y
544# CONFIG_SERIAL_SUNSAB is not set 537# CONFIG_SERIAL_SUNSAB is not set
545CONFIG_SERIAL_CORE=y 538CONFIG_SERIAL_CORE=y
546CONFIG_SERIAL_CORE_CONSOLE=y 539CONFIG_SERIAL_CORE_CONSOLE=y
540CONFIG_CONSOLE_POLL=y
547# CONFIG_SERIAL_JSM is not set 541# CONFIG_SERIAL_JSM is not set
548CONFIG_UNIX98_PTYS=y 542CONFIG_UNIX98_PTYS=y
549CONFIG_LEGACY_PTYS=y 543CONFIG_LEGACY_PTYS=y
@@ -595,6 +589,7 @@ CONFIG_SSB_POSSIBLE=y
595# Multifunction device drivers 589# Multifunction device drivers
596# 590#
597# CONFIG_MFD_SM501 is not set 591# CONFIG_MFD_SM501 is not set
592# CONFIG_HTC_PASIC3 is not set
598 593
599# 594#
600# Multimedia devices 595# Multimedia devices
@@ -645,10 +640,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
645# CONFIG_NEW_LEDS is not set 640# CONFIG_NEW_LEDS is not set
646# CONFIG_INFINIBAND is not set 641# CONFIG_INFINIBAND is not set
647# CONFIG_RTC_CLASS is not set 642# CONFIG_RTC_CLASS is not set
648
649#
650# Userspace I/O
651#
652# CONFIG_UIO is not set 643# CONFIG_UIO is not set
653 644
654# 645#
@@ -680,16 +671,12 @@ CONFIG_FS_MBCACHE=y
680# CONFIG_REISERFS_FS is not set 671# CONFIG_REISERFS_FS is not set
681# CONFIG_JFS_FS is not set 672# CONFIG_JFS_FS is not set
682CONFIG_FS_POSIX_ACL=y 673CONFIG_FS_POSIX_ACL=y
683CONFIG_XFS_FS=m 674# CONFIG_XFS_FS is not set
684CONFIG_XFS_QUOTA=y
685CONFIG_XFS_POSIX_ACL=y
686CONFIG_XFS_RT=y
687# CONFIG_OCFS2_FS is not set 675# CONFIG_OCFS2_FS is not set
688CONFIG_DNOTIFY=y 676CONFIG_DNOTIFY=y
689CONFIG_INOTIFY=y 677CONFIG_INOTIFY=y
690CONFIG_INOTIFY_USER=y 678CONFIG_INOTIFY_USER=y
691# CONFIG_QUOTA is not set 679# CONFIG_QUOTA is not set
692CONFIG_QUOTACTL=y
693CONFIG_AUTOFS_FS=m 680CONFIG_AUTOFS_FS=m
694CONFIG_AUTOFS4_FS=m 681CONFIG_AUTOFS4_FS=m
695# CONFIG_FUSE_FS is not set 682# CONFIG_FUSE_FS is not set
@@ -725,11 +712,9 @@ CONFIG_SYSFS=y
725# 712#
726# CONFIG_ADFS_FS is not set 713# CONFIG_ADFS_FS is not set
727# CONFIG_AFFS_FS is not set 714# CONFIG_AFFS_FS is not set
728# CONFIG_ECRYPT_FS is not set
729# CONFIG_HFS_FS is not set 715# CONFIG_HFS_FS is not set
730# CONFIG_HFSPLUS_FS is not set 716# CONFIG_HFSPLUS_FS is not set
731CONFIG_BEFS_FS=m 717# CONFIG_BEFS_FS is not set
732# CONFIG_BEFS_DEBUG is not set
733# CONFIG_BFS_FS is not set 718# CONFIG_BFS_FS is not set
734# CONFIG_EFS_FS is not set 719# CONFIG_EFS_FS is not set
735# CONFIG_CRAMFS is not set 720# CONFIG_CRAMFS is not set
@@ -744,7 +729,6 @@ CONFIG_NETWORK_FILESYSTEMS=y
744CONFIG_NFS_FS=y 729CONFIG_NFS_FS=y
745# CONFIG_NFS_V3 is not set 730# CONFIG_NFS_V3 is not set
746# CONFIG_NFS_V4 is not set 731# CONFIG_NFS_V4 is not set
747# CONFIG_NFS_DIRECTIO is not set
748# CONFIG_NFSD is not set 732# CONFIG_NFSD is not set
749CONFIG_ROOT_NFS=y 733CONFIG_ROOT_NFS=y
750CONFIG_LOCKD=y 734CONFIG_LOCKD=y
@@ -755,16 +739,10 @@ CONFIG_SUNRPC_GSS=m
755CONFIG_RPCSEC_GSS_KRB5=m 739CONFIG_RPCSEC_GSS_KRB5=m
756# CONFIG_RPCSEC_GSS_SPKM3 is not set 740# CONFIG_RPCSEC_GSS_SPKM3 is not set
757# CONFIG_SMB_FS is not set 741# CONFIG_SMB_FS is not set
758CONFIG_CIFS=m 742# CONFIG_CIFS is not set
759# CONFIG_CIFS_STATS is not set
760# CONFIG_CIFS_WEAK_PW_HASH is not set
761# CONFIG_CIFS_XATTR is not set
762# CONFIG_CIFS_DEBUG2 is not set
763# CONFIG_CIFS_EXPERIMENTAL is not set
764# CONFIG_NCP_FS is not set 743# CONFIG_NCP_FS is not set
765# CONFIG_CODA_FS is not set 744# CONFIG_CODA_FS is not set
766CONFIG_AFS_FS=m 745# CONFIG_AFS_FS is not set
767# CONFIG_AFS_DEBUG is not set
768 746
769# 747#
770# Partition Types 748# Partition Types
@@ -821,6 +799,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
821# CONFIG_PRINTK_TIME is not set 799# CONFIG_PRINTK_TIME is not set
822# CONFIG_ENABLE_WARN_DEPRECATED is not set 800# CONFIG_ENABLE_WARN_DEPRECATED is not set
823CONFIG_ENABLE_MUST_CHECK=y 801CONFIG_ENABLE_MUST_CHECK=y
802CONFIG_FRAME_WARN=1024
824CONFIG_MAGIC_SYSRQ=y 803CONFIG_MAGIC_SYSRQ=y
825# CONFIG_UNUSED_SYMBOLS is not set 804# CONFIG_UNUSED_SYMBOLS is not set
826# CONFIG_DEBUG_FS is not set 805# CONFIG_DEBUG_FS is not set
@@ -842,70 +821,105 @@ CONFIG_DETECT_SOFTLOCKUP=y
842CONFIG_DEBUG_BUGVERBOSE=y 821CONFIG_DEBUG_BUGVERBOSE=y
843# CONFIG_DEBUG_INFO is not set 822# CONFIG_DEBUG_INFO is not set
844# CONFIG_DEBUG_VM is not set 823# CONFIG_DEBUG_VM is not set
824# CONFIG_DEBUG_WRITECOUNT is not set
845# CONFIG_DEBUG_LIST is not set 825# CONFIG_DEBUG_LIST is not set
846# CONFIG_DEBUG_SG is not set 826# CONFIG_DEBUG_SG is not set
827CONFIG_FRAME_POINTER=y
847# CONFIG_BOOT_PRINTK_DELAY is not set 828# CONFIG_BOOT_PRINTK_DELAY is not set
848# CONFIG_RCU_TORTURE_TEST is not set 829# CONFIG_RCU_TORTURE_TEST is not set
849# CONFIG_BACKTRACE_SELF_TEST is not set 830# CONFIG_BACKTRACE_SELF_TEST is not set
850# CONFIG_FAULT_INJECTION is not set 831# CONFIG_FAULT_INJECTION is not set
851# CONFIG_SAMPLES is not set 832# CONFIG_SAMPLES is not set
833CONFIG_KGDB=y
834CONFIG_HAVE_ARCH_KGDB=y
835CONFIG_KGDB_SERIAL_CONSOLE=y
836CONFIG_KGDB_TESTS=y
837# CONFIG_KGDB_TESTS_ON_BOOT is not set
852# CONFIG_DEBUG_STACK_USAGE is not set 838# CONFIG_DEBUG_STACK_USAGE is not set
853 839
854# 840#
855# Security options 841# Security options
856# 842#
857CONFIG_KEYS=y 843# CONFIG_KEYS is not set
858# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
859# CONFIG_SECURITY is not set 844# CONFIG_SECURITY is not set
860# CONFIG_SECURITY_FILE_CAPABILITIES is not set 845# CONFIG_SECURITY_FILE_CAPABILITIES is not set
861CONFIG_CRYPTO=y 846CONFIG_CRYPTO=y
847
848#
849# Crypto core or helper
850#
862CONFIG_CRYPTO_ALGAPI=y 851CONFIG_CRYPTO_ALGAPI=y
863CONFIG_CRYPTO_AEAD=y 852CONFIG_CRYPTO_AEAD=y
864CONFIG_CRYPTO_BLKCIPHER=y 853CONFIG_CRYPTO_BLKCIPHER=y
865# CONFIG_CRYPTO_SEQIV is not set
866CONFIG_CRYPTO_HASH=y 854CONFIG_CRYPTO_HASH=y
867CONFIG_CRYPTO_MANAGER=y 855CONFIG_CRYPTO_MANAGER=y
856# CONFIG_CRYPTO_GF128MUL is not set
857CONFIG_CRYPTO_NULL=m
858# CONFIG_CRYPTO_CRYPTD is not set
859CONFIG_CRYPTO_AUTHENC=y
860# CONFIG_CRYPTO_TEST is not set
861
862#
863# Authenticated Encryption with Associated Data
864#
865# CONFIG_CRYPTO_CCM is not set
866# CONFIG_CRYPTO_GCM is not set
867# CONFIG_CRYPTO_SEQIV is not set
868
869#
870# Block modes
871#
872CONFIG_CRYPTO_CBC=y
873# CONFIG_CRYPTO_CTR is not set
874# CONFIG_CRYPTO_CTS is not set
875CONFIG_CRYPTO_ECB=m
876# CONFIG_CRYPTO_LRW is not set
877CONFIG_CRYPTO_PCBC=m
878# CONFIG_CRYPTO_XTS is not set
879
880#
881# Hash modes
882#
868CONFIG_CRYPTO_HMAC=y 883CONFIG_CRYPTO_HMAC=y
869# CONFIG_CRYPTO_XCBC is not set 884# CONFIG_CRYPTO_XCBC is not set
870CONFIG_CRYPTO_NULL=m 885
886#
887# Digest
888#
889CONFIG_CRYPTO_CRC32C=m
871CONFIG_CRYPTO_MD4=y 890CONFIG_CRYPTO_MD4=y
872CONFIG_CRYPTO_MD5=y 891CONFIG_CRYPTO_MD5=y
892CONFIG_CRYPTO_MICHAEL_MIC=m
873CONFIG_CRYPTO_SHA1=y 893CONFIG_CRYPTO_SHA1=y
874CONFIG_CRYPTO_SHA256=m 894CONFIG_CRYPTO_SHA256=m
875CONFIG_CRYPTO_SHA512=m 895CONFIG_CRYPTO_SHA512=m
876# CONFIG_CRYPTO_WP512 is not set
877# CONFIG_CRYPTO_TGR192 is not set 896# CONFIG_CRYPTO_TGR192 is not set
878# CONFIG_CRYPTO_GF128MUL is not set 897# CONFIG_CRYPTO_WP512 is not set
879CONFIG_CRYPTO_ECB=m 898
880CONFIG_CRYPTO_CBC=y 899#
881CONFIG_CRYPTO_PCBC=m 900# Ciphers
882# CONFIG_CRYPTO_LRW is not set 901#
883# CONFIG_CRYPTO_XTS is not set
884# CONFIG_CRYPTO_CTR is not set
885# CONFIG_CRYPTO_GCM is not set
886# CONFIG_CRYPTO_CCM is not set
887# CONFIG_CRYPTO_CRYPTD is not set
888CONFIG_CRYPTO_DES=y
889# CONFIG_CRYPTO_FCRYPT is not set
890CONFIG_CRYPTO_BLOWFISH=m
891CONFIG_CRYPTO_TWOFISH=m
892CONFIG_CRYPTO_TWOFISH_COMMON=m
893CONFIG_CRYPTO_SERPENT=m
894CONFIG_CRYPTO_AES=m 902CONFIG_CRYPTO_AES=m
903# CONFIG_CRYPTO_ANUBIS is not set
904CONFIG_CRYPTO_ARC4=m
905CONFIG_CRYPTO_BLOWFISH=m
906# CONFIG_CRYPTO_CAMELLIA is not set
895CONFIG_CRYPTO_CAST5=m 907CONFIG_CRYPTO_CAST5=m
896CONFIG_CRYPTO_CAST6=m 908CONFIG_CRYPTO_CAST6=m
897# CONFIG_CRYPTO_TEA is not set 909CONFIG_CRYPTO_DES=y
898CONFIG_CRYPTO_ARC4=m 910# CONFIG_CRYPTO_FCRYPT is not set
899# CONFIG_CRYPTO_KHAZAD is not set 911# CONFIG_CRYPTO_KHAZAD is not set
900# CONFIG_CRYPTO_ANUBIS is not set
901# CONFIG_CRYPTO_SEED is not set
902# CONFIG_CRYPTO_SALSA20 is not set 912# CONFIG_CRYPTO_SALSA20 is not set
913# CONFIG_CRYPTO_SEED is not set
914CONFIG_CRYPTO_SERPENT=m
915# CONFIG_CRYPTO_TEA is not set
916CONFIG_CRYPTO_TWOFISH=m
917CONFIG_CRYPTO_TWOFISH_COMMON=m
918
919#
920# Compression
921#
903CONFIG_CRYPTO_DEFLATE=y 922CONFIG_CRYPTO_DEFLATE=y
904CONFIG_CRYPTO_MICHAEL_MIC=m
905CONFIG_CRYPTO_CRC32C=m
906# CONFIG_CRYPTO_CAMELLIA is not set
907# CONFIG_CRYPTO_TEST is not set
908CONFIG_CRYPTO_AUTHENC=y
909# CONFIG_CRYPTO_LZO is not set 923# CONFIG_CRYPTO_LZO is not set
910# CONFIG_CRYPTO_HW is not set 924# CONFIG_CRYPTO_HW is not set
911 925
@@ -913,6 +927,7 @@ CONFIG_CRYPTO_AUTHENC=y
913# Library routines 927# Library routines
914# 928#
915CONFIG_BITREVERSE=y 929CONFIG_BITREVERSE=y
930# CONFIG_GENERIC_FIND_FIRST_BIT is not set
916# CONFIG_CRC_CCITT is not set 931# CONFIG_CRC_CCITT is not set
917# CONFIG_CRC16 is not set 932# CONFIG_CRC16 is not set
918# CONFIG_CRC_ITU_T is not set 933# CONFIG_CRC_ITU_T is not set
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 59700aaaae93..6e03a2a7863c 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_PCI) += ebus.o
25obj-$(CONFIG_SUN_PM) += apc.o pmc.o 25obj-$(CONFIG_SUN_PM) += apc.o pmc.o
26obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o 26obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o
27obj-$(CONFIG_SPARC_LED) += led.o 27obj-$(CONFIG_SPARC_LED) += led.o
28obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 484c83d23eef..57d1bbdd0bd2 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -12,7 +12,6 @@
12#include <asm/head.h> 12#include <asm/head.h>
13#include <asm/asi.h> 13#include <asm/asi.h>
14#include <asm/smp.h> 14#include <asm/smp.h>
15#include <asm/kgdb.h>
16#include <asm/contregs.h> 15#include <asm/contregs.h>
17#include <asm/ptrace.h> 16#include <asm/ptrace.h>
18#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
@@ -45,91 +44,20 @@
45 _SV; _SV; _SV; _SV; _SV; _SV; _SV; \ 44 _SV; _SV; _SV; _SV; _SV; _SV; _SV; \
46 _RS; _RS; _RS; _RS; _RS; _RS; _RS; 45 _RS; _RS; _RS; _RS; _RS; _RS; _RS;
47 46
48/* First, KGDB low level things. This is a rewrite
49 * of the routines found in the sparc-stub.c asm() statement
50 * from the gdb distribution. This is also dual-purpose
51 * as a software trap for userlevel programs.
52 */
53 .data
54 .align 4
55
56in_trap_handler:
57 .word 0
58
59 .text 47 .text
60 .align 4
61 48
62#if 0 /* kgdb is dropped from 2.5.33 */ 49#ifdef CONFIG_KGDB
63! This function is called when any SPARC trap (except window overflow or 50 .align 4
64! underflow) occurs. It makes sure that the invalid register window is still 51 .globl arch_kgdb_breakpoint
65! available before jumping into C code. It will also restore the world if you 52 .type arch_kgdb_breakpoint,#function
66! return from handle_exception. 53arch_kgdb_breakpoint:
67 54 ta 0x7d
68 .globl trap_low 55 retl
69trap_low: 56 nop
70 rd %wim, %l3 57 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
71 SAVE_ALL
72
73 sethi %hi(in_trap_handler), %l4
74 ld [%lo(in_trap_handler) + %l4], %l5
75 inc %l5
76 st %l5, [%lo(in_trap_handler) + %l4]
77
78 /* Make sure kgdb sees the same state we just saved. */
79 LOAD_PT_GLOBALS(sp)
80 LOAD_PT_INS(sp)
81 ld [%sp + STACKFRAME_SZ + PT_Y], %l4
82 ld [%sp + STACKFRAME_SZ + PT_WIM], %l3
83 ld [%sp + STACKFRAME_SZ + PT_PSR], %l0
84 ld [%sp + STACKFRAME_SZ + PT_PC], %l1
85 ld [%sp + STACKFRAME_SZ + PT_NPC], %l2
86 rd %tbr, %l5 /* Never changes... */
87
88 /* Make kgdb exception frame. */
89 sub %sp,(16+1+6+1+72)*4,%sp ! Make room for input & locals
90 ! + hidden arg + arg spill
91 ! + doubleword alignment
92 ! + registers[72] local var
93 SAVE_KGDB_GLOBALS(sp)
94 SAVE_KGDB_INS(sp)
95 SAVE_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2)
96
97 /* We are increasing PIL, so two writes. */
98 or %l0, PSR_PIL, %l0
99 wr %l0, 0, %psr
100 WRITE_PAUSE
101 wr %l0, PSR_ET, %psr
102 WRITE_PAUSE
103
104 call handle_exception
105 add %sp, STACKFRAME_SZ, %o0 ! Pass address of registers
106
107 /* Load new kgdb register set. */
108 LOAD_KGDB_GLOBALS(sp)
109 LOAD_KGDB_INS(sp)
110 LOAD_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2)
111 wr %l4, 0x0, %y
112
113 sethi %hi(in_trap_handler), %l4
114 ld [%lo(in_trap_handler) + %l4], %l5
115 dec %l5
116 st %l5, [%lo(in_trap_handler) + %l4]
117
118 add %sp,(16+1+6+1+72)*4,%sp ! Undo the kgdb trap frame.
119
120 /* Now take what kgdb did and place it into the pt_regs
121 * frame which SparcLinux RESTORE_ALL understands.,
122 */
123 STORE_PT_INS(sp)
124 STORE_PT_GLOBALS(sp)
125 STORE_PT_YREG(sp, g2)
126 STORE_PT_PRIV(sp, l0, l1, l2)
127
128 RESTORE_ALL
129#endif 58#endif
130 59
131#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) 60#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
132 .text
133 .align 4 61 .align 4
134 .globl floppy_hardint 62 .globl floppy_hardint
135floppy_hardint: 63floppy_hardint:
@@ -1596,6 +1524,23 @@ breakpoint_trap:
1596 1524
1597 RESTORE_ALL 1525 RESTORE_ALL
1598 1526
1527#ifdef CONFIG_KGDB
1528 .align 4
1529 .globl kgdb_trap_low
1530 .type kgdb_trap_low,#function
1531kgdb_trap_low:
1532 rd %wim,%l3
1533 SAVE_ALL
1534 wr %l0, PSR_ET, %psr
1535 WRITE_PAUSE
1536
1537 call kgdb_trap
1538 add %sp, STACKFRAME_SZ, %o0
1539
1540 RESTORE_ALL
1541 .size kgdb_trap_low,.-kgdb_trap_low
1542#endif
1543
1599 .align 4 1544 .align 4
1600 .globl __handle_exception, flush_patch_exception 1545 .globl __handle_exception, flush_patch_exception
1601__handle_exception: 1546__handle_exception:
@@ -1698,4 +1643,22 @@ pcic_nmi_trap_patch:
1698 1643
1699#endif /* CONFIG_PCI */ 1644#endif /* CONFIG_PCI */
1700 1645
1646 .globl flushw_all
1647flushw_all:
1648 save %sp, -0x40, %sp
1649 save %sp, -0x40, %sp
1650 save %sp, -0x40, %sp
1651 save %sp, -0x40, %sp
1652 save %sp, -0x40, %sp
1653 save %sp, -0x40, %sp
1654 save %sp, -0x40, %sp
1655 restore
1656 restore
1657 restore
1658 restore
1659 restore
1660 restore
1661 ret
1662 restore
1663
1701/* End of entry.S */ 1664/* End of entry.S */
diff --git a/arch/sparc/kernel/head.S b/arch/sparc/kernel/head.S
index b7f1e81c8ff2..8bec05fa5795 100644
--- a/arch/sparc/kernel/head.S
+++ b/arch/sparc/kernel/head.S
@@ -191,7 +191,8 @@ t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xe
191t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) 191t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
192t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) 192t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
193t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) 193t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
194t_badfc:BAD_TRAP(0xfc) BAD_TRAP(0xfd) 194t_badfc:BAD_TRAP(0xfc)
195t_kgdb: KGDB_TRAP(0xfd)
195dbtrap: BAD_TRAP(0xfe) /* Debugger/PROM breakpoint #1 */ 196dbtrap: BAD_TRAP(0xfe) /* Debugger/PROM breakpoint #1 */
196dbtrap2:BAD_TRAP(0xff) /* Debugger/PROM breakpoint #2 */ 197dbtrap2:BAD_TRAP(0xff) /* Debugger/PROM breakpoint #2 */
197 198
@@ -267,7 +268,7 @@ trapbase_cpu1:
267 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) 268 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
268 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) 269 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
269 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) 270 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
270 BAD_TRAP(0xfc) BAD_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) 271 BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
271 272
272trapbase_cpu2: 273trapbase_cpu2:
273 BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction) 274 BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction)
@@ -335,7 +336,7 @@ trapbase_cpu2:
335 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) 336 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
336 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) 337 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
337 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) 338 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
338 BAD_TRAP(0xfc) BAD_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) 339 BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
339 340
340trapbase_cpu3: 341trapbase_cpu3:
341 BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction) 342 BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction)
@@ -403,7 +404,7 @@ trapbase_cpu3:
403 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) 404 BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
404 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) 405 BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
405 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) 406 BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
406 BAD_TRAP(0xfc) BAD_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) 407 BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
407 408
408#endif 409#endif
409 .align PAGE_SIZE 410 .align PAGE_SIZE
diff --git a/arch/sparc/kernel/kgdb.c b/arch/sparc/kernel/kgdb.c
new file mode 100644
index 000000000000..757805ce02ee
--- /dev/null
+++ b/arch/sparc/kernel/kgdb.c
@@ -0,0 +1,164 @@
1/* kgdb.c: KGDB support for 32-bit sparc.
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5
6#include <linux/kgdb.h>
7#include <linux/kdebug.h>
8
9#include <asm/kdebug.h>
10#include <asm/ptrace.h>
11#include <asm/irq.h>
12
13extern unsigned long trapbase;
14
15void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
16{
17 struct reg_window *win;
18 int i;
19
20 gdb_regs[GDB_G0] = 0;
21 for (i = 0; i < 15; i++)
22 gdb_regs[GDB_G1 + i] = regs->u_regs[UREG_G1 + i];
23
24 win = (struct reg_window *) regs->u_regs[UREG_FP];
25 for (i = 0; i < 8; i++)
26 gdb_regs[GDB_L0 + i] = win->locals[i];
27 for (i = 0; i < 8; i++)
28 gdb_regs[GDB_I0 + i] = win->ins[i];
29
30 for (i = GDB_F0; i <= GDB_F31; i++)
31 gdb_regs[i] = 0;
32
33 gdb_regs[GDB_Y] = regs->y;
34 gdb_regs[GDB_PSR] = regs->psr;
35 gdb_regs[GDB_WIM] = 0;
36 gdb_regs[GDB_TBR] = (unsigned long) &trapbase;
37 gdb_regs[GDB_PC] = regs->pc;
38 gdb_regs[GDB_NPC] = regs->npc;
39 gdb_regs[GDB_FSR] = 0;
40 gdb_regs[GDB_CSR] = 0;
41}
42
43void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
44{
45 struct thread_info *t = task_thread_info(p);
46 struct reg_window *win;
47 int i;
48
49 for (i = GDB_G0; i < GDB_G6; i++)
50 gdb_regs[i] = 0;
51 gdb_regs[GDB_G6] = (unsigned long) t;
52 gdb_regs[GDB_G7] = 0;
53 for (i = GDB_O0; i < GDB_SP; i++)
54 gdb_regs[i] = 0;
55 gdb_regs[GDB_SP] = t->ksp;
56 gdb_regs[GDB_O7] = 0;
57
58 win = (struct reg_window *) t->ksp;
59 for (i = 0; i < 8; i++)
60 gdb_regs[GDB_L0 + i] = win->locals[i];
61 for (i = 0; i < 8; i++)
62 gdb_regs[GDB_I0 + i] = win->ins[i];
63
64 for (i = GDB_F0; i <= GDB_F31; i++)
65 gdb_regs[i] = 0;
66
67 gdb_regs[GDB_Y] = 0;
68
69 gdb_regs[GDB_PSR] = t->kpsr;
70 gdb_regs[GDB_WIM] = t->kwim;
71 gdb_regs[GDB_TBR] = (unsigned long) &trapbase;
72 gdb_regs[GDB_PC] = t->kpc;
73 gdb_regs[GDB_NPC] = t->kpc + 4;
74 gdb_regs[GDB_FSR] = 0;
75 gdb_regs[GDB_CSR] = 0;
76}
77
78void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
79{
80 struct reg_window *win;
81 int i;
82
83 for (i = 0; i < 15; i++)
84 regs->u_regs[UREG_G1 + i] = gdb_regs[GDB_G1 + i];
85
86 /* If the PSR register is changing, we have to preserve
87 * the CWP field, otherwise window save/restore explodes.
88 */
89 if (regs->psr != gdb_regs[GDB_PSR]) {
90 unsigned long cwp = regs->psr & PSR_CWP;
91
92 regs->psr = (gdb_regs[GDB_PSR] & ~PSR_CWP) | cwp;
93 }
94
95 regs->pc = gdb_regs[GDB_PC];
96 regs->npc = gdb_regs[GDB_NPC];
97 regs->y = gdb_regs[GDB_Y];
98
99 win = (struct reg_window *) regs->u_regs[UREG_FP];
100 for (i = 0; i < 8; i++)
101 win->locals[i] = gdb_regs[GDB_L0 + i];
102 for (i = 0; i < 8; i++)
103 win->ins[i] = gdb_regs[GDB_I0 + i];
104}
105
106int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
107 char *remcomInBuffer, char *remcomOutBuffer,
108 struct pt_regs *linux_regs)
109{
110 unsigned long addr;
111 char *ptr;
112
113 switch (remcomInBuffer[0]) {
114 case 'c':
115 /* try to read optional parameter, pc unchanged if no parm */
116 ptr = &remcomInBuffer[1];
117 if (kgdb_hex2long(&ptr, &addr)) {
118 linux_regs->pc = addr;
119 linux_regs->npc = addr + 4;
120 }
121 /* fallthru */
122
123 case 'D':
124 case 'k':
125 if (linux_regs->pc == (unsigned long) arch_kgdb_breakpoint) {
126 linux_regs->pc = linux_regs->npc;
127 linux_regs->npc += 4;
128 }
129 return 0;
130 }
131 return -1;
132}
133
134extern void do_hw_interrupt(struct pt_regs *regs, unsigned long type);
135
136asmlinkage void kgdb_trap(struct pt_regs *regs)
137{
138 unsigned long flags;
139
140 if (user_mode(regs)) {
141 do_hw_interrupt(regs, 0xfd);
142 return;
143 }
144
145 flushw_all();
146
147 local_irq_save(flags);
148 kgdb_handle_exception(0x172, SIGTRAP, 0, regs);
149 local_irq_restore(flags);
150}
151
152int kgdb_arch_init(void)
153{
154 return 0;
155}
156
157void kgdb_arch_exit(void)
158{
159}
160
161struct kgdb_arch arch_kgdb_ops = {
162 /* Breakpoint instruction: ta 0x7d */
163 .gdb_bpt_instr = { 0x91, 0xd0, 0x20, 0x7d },
164};
diff --git a/arch/sparc/kernel/sparc-stub.c b/arch/sparc/kernel/sparc-stub.c
deleted file mode 100644
index e84f815e6903..000000000000
--- a/arch/sparc/kernel/sparc-stub.c
+++ /dev/null
@@ -1,724 +0,0 @@
1/* $Id: sparc-stub.c,v 1.28 2001/10/30 04:54:21 davem Exp $
2 * sparc-stub.c: KGDB support for the Linux kernel.
3 *
4 * Modifications to run under Linux
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 *
7 * This file originally came from the gdb sources, and the
8 * copyright notices have been retained below.
9 */
10
11/****************************************************************************
12
13 THIS SOFTWARE IS NOT COPYRIGHTED
14
15 HP offers the following for use in the public domain. HP makes no
16 warranty with regard to the software or its performance and the
17 user accepts the software "AS IS" with all faults.
18
19 HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
20 TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
21 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22
23****************************************************************************/
24
25/****************************************************************************
26 * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
27 *
28 * Module name: remcom.c $
29 * Revision: 1.34 $
30 * Date: 91/03/09 12:29:49 $
31 * Contributor: Lake Stevens Instrument Division$
32 *
33 * Description: low level support for gdb debugger. $
34 *
35 * Considerations: only works on target hardware $
36 *
37 * Written by: Glenn Engel $
38 * ModuleState: Experimental $
39 *
40 * NOTES: See Below $
41 *
42 * Modified for SPARC by Stu Grossman, Cygnus Support.
43 *
44 * This code has been extensively tested on the Fujitsu SPARClite demo board.
45 *
46 * To enable debugger support, two things need to happen. One, a
47 * call to set_debug_traps() is necessary in order to allow any breakpoints
48 * or error conditions to be properly intercepted and reported to gdb.
49 * Two, a breakpoint needs to be generated to begin communication. This
50 * is most easily accomplished by a call to breakpoint(). Breakpoint()
51 * simulates a breakpoint by executing a trap #1.
52 *
53 *************
54 *
55 * The following gdb commands are supported:
56 *
57 * command function Return value
58 *
59 * g return the value of the CPU registers hex data or ENN
60 * G set the value of the CPU registers OK or ENN
61 *
62 * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
63 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
64 *
65 * c Resume at current address SNN ( signal NN)
66 * cAA..AA Continue at address AA..AA SNN
67 *
68 * s Step one instruction SNN
69 * sAA..AA Step one instruction from AA..AA SNN
70 *
71 * k kill
72 *
73 * ? What was the last sigval ? SNN (signal NN)
74 *
75 * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
76 * baud rate
77 *
78 * All commands and responses are sent with a packet which includes a
79 * checksum. A packet consists of
80 *
81 * $<packet info>#<checksum>.
82 *
83 * where
84 * <packet info> :: <characters representing the command or response>
85 * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
86 *
87 * When a packet is received, it is first acknowledged with either '+' or '-'.
88 * '+' indicates a successful transfer. '-' indicates a failed transfer.
89 *
90 * Example:
91 *
92 * Host: Reply:
93 * $m0,10#2a +$00010203040506070809101112131415#42
94 *
95 ****************************************************************************/
96
97#include <linux/kernel.h>
98#include <linux/string.h>
99#include <linux/mm.h>
100#include <linux/smp.h>
101#include <linux/smp_lock.h>
102
103#include <asm/system.h>
104#include <asm/signal.h>
105#include <asm/oplib.h>
106#include <asm/head.h>
107#include <asm/traps.h>
108#include <asm/vac-ops.h>
109#include <asm/kgdb.h>
110#include <asm/pgalloc.h>
111#include <asm/pgtable.h>
112#include <asm/cacheflush.h>
113
114/*
115 *
116 * external low-level support routines
117 */
118
119extern void putDebugChar(char); /* write a single character */
120extern char getDebugChar(void); /* read and return a single char */
121
122/*
123 * BUFMAX defines the maximum number of characters in inbound/outbound buffers
124 * at least NUMREGBYTES*2 are needed for register packets
125 */
126#define BUFMAX 2048
127
128static int initialized; /* !0 means we've been initialized */
129
130static const char hexchars[]="0123456789abcdef";
131
132#define NUMREGS 72
133
134/* Number of bytes of registers. */
135#define NUMREGBYTES (NUMREGS * 4)
136enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
137 O0, O1, O2, O3, O4, O5, SP, O7,
138 L0, L1, L2, L3, L4, L5, L6, L7,
139 I0, I1, I2, I3, I4, I5, FP, I7,
140
141 F0, F1, F2, F3, F4, F5, F6, F7,
142 F8, F9, F10, F11, F12, F13, F14, F15,
143 F16, F17, F18, F19, F20, F21, F22, F23,
144 F24, F25, F26, F27, F28, F29, F30, F31,
145 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
146
147
148extern void trap_low(void); /* In arch/sparc/kernel/entry.S */
149
150unsigned long get_sun4cpte(unsigned long addr)
151{
152 unsigned long entry;
153
154 __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
155 "=r" (entry) :
156 "r" (addr), "i" (ASI_PTE));
157 return entry;
158}
159
160unsigned long get_sun4csegmap(unsigned long addr)
161{
162 unsigned long entry;
163
164 __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
165 "=r" (entry) :
166 "r" (addr), "i" (ASI_SEGMAP));
167 return entry;
168}
169
170#if 0
171/* Have to sort this out. This cannot be done after initialization. */
172static void flush_cache_all_nop(void) {}
173#endif
174
175/* Place where we save old trap entries for restoration */
176struct tt_entry kgdb_savettable[256];
177typedef void (*trapfunc_t)(void);
178
179/* Helper routine for manipulation of kgdb_savettable */
180static inline void copy_ttentry(struct tt_entry *src, struct tt_entry *dest)
181{
182 dest->inst_one = src->inst_one;
183 dest->inst_two = src->inst_two;
184 dest->inst_three = src->inst_three;
185 dest->inst_four = src->inst_four;
186}
187
188/* Initialize the kgdb_savettable so that debugging can commence */
189static void eh_init(void)
190{
191 int i;
192
193 for(i=0; i < 256; i++)
194 copy_ttentry(&sparc_ttable[i], &kgdb_savettable[i]);
195}
196
197/* Install an exception handler for kgdb */
198static void exceptionHandler(int tnum, trapfunc_t trap_entry)
199{
200 unsigned long te_addr = (unsigned long) trap_entry;
201
202 /* Make new vector */
203 sparc_ttable[tnum].inst_one =
204 SPARC_BRANCH((unsigned long) te_addr,
205 (unsigned long) &sparc_ttable[tnum].inst_one);
206 sparc_ttable[tnum].inst_two = SPARC_RD_PSR_L0;
207 sparc_ttable[tnum].inst_three = SPARC_NOP;
208 sparc_ttable[tnum].inst_four = SPARC_NOP;
209}
210
211/* Convert ch from a hex digit to an int */
212static int
213hex(unsigned char ch)
214{
215 if (ch >= 'a' && ch <= 'f')
216 return ch-'a'+10;
217 if (ch >= '0' && ch <= '9')
218 return ch-'0';
219 if (ch >= 'A' && ch <= 'F')
220 return ch-'A'+10;
221 return -1;
222}
223
224/* scan for the sequence $<data>#<checksum> */
225static void
226getpacket(char *buffer)
227{
228 unsigned char checksum;
229 unsigned char xmitcsum;
230 int i;
231 int count;
232 unsigned char ch;
233
234 do {
235 /* wait around for the start character, ignore all other characters */
236 while ((ch = (getDebugChar() & 0x7f)) != '$') ;
237
238 checksum = 0;
239 xmitcsum = -1;
240
241 count = 0;
242
243 /* now, read until a # or end of buffer is found */
244 while (count < BUFMAX) {
245 ch = getDebugChar() & 0x7f;
246 if (ch == '#')
247 break;
248 checksum = checksum + ch;
249 buffer[count] = ch;
250 count = count + 1;
251 }
252
253 if (count >= BUFMAX)
254 continue;
255
256 buffer[count] = 0;
257
258 if (ch == '#') {
259 xmitcsum = hex(getDebugChar() & 0x7f) << 4;
260 xmitcsum |= hex(getDebugChar() & 0x7f);
261 if (checksum != xmitcsum)
262 putDebugChar('-'); /* failed checksum */
263 else {
264 putDebugChar('+'); /* successful transfer */
265 /* if a sequence char is present, reply the ID */
266 if (buffer[2] == ':') {
267 putDebugChar(buffer[0]);
268 putDebugChar(buffer[1]);
269 /* remove sequence chars from buffer */
270 count = strlen(buffer);
271 for (i=3; i <= count; i++)
272 buffer[i-3] = buffer[i];
273 }
274 }
275 }
276 } while (checksum != xmitcsum);
277}
278
279/* send the packet in buffer. */
280
281static void
282putpacket(unsigned char *buffer)
283{
284 unsigned char checksum;
285 int count;
286 unsigned char ch, recv;
287
288 /* $<packet info>#<checksum>. */
289 do {
290 putDebugChar('$');
291 checksum = 0;
292 count = 0;
293
294 while ((ch = buffer[count])) {
295 putDebugChar(ch);
296 checksum += ch;
297 count += 1;
298 }
299
300 putDebugChar('#');
301 putDebugChar(hexchars[checksum >> 4]);
302 putDebugChar(hexchars[checksum & 0xf]);
303 recv = getDebugChar();
304 } while ((recv & 0x7f) != '+');
305}
306
307static char remcomInBuffer[BUFMAX];
308static char remcomOutBuffer[BUFMAX];
309
310/* Convert the memory pointed to by mem into hex, placing result in buf.
311 * Return a pointer to the last char put in buf (null), in case of mem fault,
312 * return 0.
313 */
314
315static unsigned char *
316mem2hex(char *mem, char *buf, int count)
317{
318 unsigned char ch;
319
320 while (count-- > 0) {
321 /* This assembler code is basically: ch = *mem++;
322 * except that we use the SPARC/Linux exception table
323 * mechanism (see how "fixup" works in kernel_mna_trap_fault)
324 * to arrange for a "return 0" upon a memory fault
325 */
326 __asm__(
327 "\n1:\n\t"
328 "ldub [%0], %1\n\t"
329 "inc %0\n\t"
330 ".section .fixup,#alloc,#execinstr\n\t"
331 ".align 4\n"
332 "2:\n\t"
333 "retl\n\t"
334 " mov 0, %%o0\n\t"
335 ".section __ex_table, #alloc\n\t"
336 ".align 4\n\t"
337 ".word 1b, 2b\n\t"
338 ".text\n"
339 : "=r" (mem), "=r" (ch) : "0" (mem));
340 *buf++ = hexchars[ch >> 4];
341 *buf++ = hexchars[ch & 0xf];
342 }
343
344 *buf = 0;
345 return buf;
346}
347
348/* convert the hex array pointed to by buf into binary to be placed in mem
349 * return a pointer to the character AFTER the last byte written.
350*/
351static char *
352hex2mem(char *buf, char *mem, int count)
353{
354 int i;
355 unsigned char ch;
356
357 for (i=0; i<count; i++) {
358
359 ch = hex(*buf++) << 4;
360 ch |= hex(*buf++);
361 /* Assembler code is *mem++ = ch; with return 0 on fault */
362 __asm__(
363 "\n1:\n\t"
364 "stb %1, [%0]\n\t"
365 "inc %0\n\t"
366 ".section .fixup,#alloc,#execinstr\n\t"
367 ".align 4\n"
368 "2:\n\t"
369 "retl\n\t"
370 " mov 0, %%o0\n\t"
371 ".section __ex_table, #alloc\n\t"
372 ".align 4\n\t"
373 ".word 1b, 2b\n\t"
374 ".text\n"
375 : "=r" (mem) : "r" (ch) , "0" (mem));
376 }
377 return mem;
378}
379
380/* This table contains the mapping between SPARC hardware trap types, and
381 signals, which are primarily what GDB understands. It also indicates
382 which hardware traps we need to commandeer when initializing the stub. */
383
384static struct hard_trap_info
385{
386 unsigned char tt; /* Trap type code for SPARC */
387 unsigned char signo; /* Signal that we map this trap into */
388} hard_trap_info[] = {
389 {SP_TRAP_SBPT, SIGTRAP}, /* ta 1 - Linux/KGDB software breakpoint */
390 {0, 0} /* Must be last */
391};
392
393/* Set up exception handlers for tracing and breakpoints */
394
395void
396set_debug_traps(void)
397{
398 struct hard_trap_info *ht;
399 unsigned long flags;
400
401 local_irq_save(flags);
402#if 0
403/* Have to sort this out. This cannot be done after initialization. */
404 BTFIXUPSET_CALL(flush_cache_all, flush_cache_all_nop, BTFIXUPCALL_NOP);
405#endif
406
407 /* Initialize our copy of the Linux Sparc trap table */
408 eh_init();
409
410 for (ht = hard_trap_info; ht->tt && ht->signo; ht++) {
411 /* Only if it doesn't destroy our fault handlers */
412 if((ht->tt != SP_TRAP_TFLT) &&
413 (ht->tt != SP_TRAP_DFLT))
414 exceptionHandler(ht->tt, trap_low);
415 }
416
417 /* In case GDB is started before us, ack any packets (presumably
418 * "$?#xx") sitting there.
419 *
420 * I've found this code causes more problems than it solves,
421 * so that's why it's commented out. GDB seems to work fine
422 * now starting either before or after the kernel -bwb
423 */
424#if 0
425 while((c = getDebugChar()) != '$');
426 while((c = getDebugChar()) != '#');
427 c = getDebugChar(); /* eat first csum byte */
428 c = getDebugChar(); /* eat second csum byte */
429 putDebugChar('+'); /* ack it */
430#endif
431
432 initialized = 1; /* connect! */
433 local_irq_restore(flags);
434}
435
436/* Convert the SPARC hardware trap type code to a unix signal number. */
437
438static int
439computeSignal(int tt)
440{
441 struct hard_trap_info *ht;
442
443 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
444 if (ht->tt == tt)
445 return ht->signo;
446
447 return SIGHUP; /* default for things we don't know about */
448}
449
450/*
451 * While we find nice hex chars, build an int.
452 * Return number of chars processed.
453 */
454
455static int
456hexToInt(char **ptr, int *intValue)
457{
458 int numChars = 0;
459 int hexValue;
460
461 *intValue = 0;
462
463 while (**ptr) {
464 hexValue = hex(**ptr);
465 if (hexValue < 0)
466 break;
467
468 *intValue = (*intValue << 4) | hexValue;
469 numChars ++;
470
471 (*ptr)++;
472 }
473
474 return (numChars);
475}
476
477/*
478 * This function does all command processing for interfacing to gdb. It
479 * returns 1 if you should skip the instruction at the trap address, 0
480 * otherwise.
481 */
482
483extern void breakinst(void);
484
485void
486handle_exception (unsigned long *registers)
487{
488 int tt; /* Trap type */
489 int sigval;
490 int addr;
491 int length;
492 char *ptr;
493 unsigned long *sp;
494
495 /* First, we must force all of the windows to be spilled out */
496
497 asm("save %sp, -64, %sp\n\t"
498 "save %sp, -64, %sp\n\t"
499 "save %sp, -64, %sp\n\t"
500 "save %sp, -64, %sp\n\t"
501 "save %sp, -64, %sp\n\t"
502 "save %sp, -64, %sp\n\t"
503 "save %sp, -64, %sp\n\t"
504 "save %sp, -64, %sp\n\t"
505 "restore\n\t"
506 "restore\n\t"
507 "restore\n\t"
508 "restore\n\t"
509 "restore\n\t"
510 "restore\n\t"
511 "restore\n\t"
512 "restore\n\t");
513
514 lock_kernel();
515 if (registers[PC] == (unsigned long)breakinst) {
516 /* Skip over breakpoint trap insn */
517 registers[PC] = registers[NPC];
518 registers[NPC] += 4;
519 }
520
521 sp = (unsigned long *)registers[SP];
522
523 tt = (registers[TBR] >> 4) & 0xff;
524
525 /* reply to host that an exception has occurred */
526 sigval = computeSignal(tt);
527 ptr = remcomOutBuffer;
528
529 *ptr++ = 'T';
530 *ptr++ = hexchars[sigval >> 4];
531 *ptr++ = hexchars[sigval & 0xf];
532
533 *ptr++ = hexchars[PC >> 4];
534 *ptr++ = hexchars[PC & 0xf];
535 *ptr++ = ':';
536 ptr = mem2hex((char *)&registers[PC], ptr, 4);
537 *ptr++ = ';';
538
539 *ptr++ = hexchars[FP >> 4];
540 *ptr++ = hexchars[FP & 0xf];
541 *ptr++ = ':';
542 ptr = mem2hex((char *) (sp + 8 + 6), ptr, 4); /* FP */
543 *ptr++ = ';';
544
545 *ptr++ = hexchars[SP >> 4];
546 *ptr++ = hexchars[SP & 0xf];
547 *ptr++ = ':';
548 ptr = mem2hex((char *)&sp, ptr, 4);
549 *ptr++ = ';';
550
551 *ptr++ = hexchars[NPC >> 4];
552 *ptr++ = hexchars[NPC & 0xf];
553 *ptr++ = ':';
554 ptr = mem2hex((char *)&registers[NPC], ptr, 4);
555 *ptr++ = ';';
556
557 *ptr++ = hexchars[O7 >> 4];
558 *ptr++ = hexchars[O7 & 0xf];
559 *ptr++ = ':';
560 ptr = mem2hex((char *)&registers[O7], ptr, 4);
561 *ptr++ = ';';
562
563 *ptr++ = 0;
564
565 putpacket(remcomOutBuffer);
566
567 /* XXX We may want to add some features dealing with poking the
568 * XXX page tables, the real ones on the srmmu, and what is currently
569 * XXX loaded in the sun4/sun4c tlb at this point in time. But this
570 * XXX also required hacking to the gdb sources directly...
571 */
572
573 while (1) {
574 remcomOutBuffer[0] = 0;
575
576 getpacket(remcomInBuffer);
577 switch (remcomInBuffer[0]) {
578 case '?':
579 remcomOutBuffer[0] = 'S';
580 remcomOutBuffer[1] = hexchars[sigval >> 4];
581 remcomOutBuffer[2] = hexchars[sigval & 0xf];
582 remcomOutBuffer[3] = 0;
583 break;
584
585 case 'd':
586 /* toggle debug flag */
587 break;
588
589 case 'g': /* return the value of the CPU registers */
590 {
591 ptr = remcomOutBuffer;
592 /* G & O regs */
593 ptr = mem2hex((char *)registers, ptr, 16 * 4);
594 /* L & I regs */
595 ptr = mem2hex((char *) (sp + 0), ptr, 16 * 4);
596 /* Floating point */
597 memset(ptr, '0', 32 * 8);
598 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
599 mem2hex((char *)&registers[Y], (ptr + 32 * 4 * 2), (8 * 4));
600 }
601 break;
602
603 case 'G': /* set the value of the CPU registers - return OK */
604 {
605 unsigned long *newsp, psr;
606
607 psr = registers[PSR];
608
609 ptr = &remcomInBuffer[1];
610 /* G & O regs */
611 hex2mem(ptr, (char *)registers, 16 * 4);
612 /* L & I regs */
613 hex2mem(ptr + 16 * 4 * 2, (char *) (sp + 0), 16 * 4);
614 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
615 hex2mem(ptr + 64 * 4 * 2, (char *)&registers[Y], 8 * 4);
616
617 /* See if the stack pointer has moved. If so,
618 * then copy the saved locals and ins to the
619 * new location. This keeps the window
620 * overflow and underflow routines happy.
621 */
622
623 newsp = (unsigned long *)registers[SP];
624 if (sp != newsp)
625 sp = memcpy(newsp, sp, 16 * 4);
626
627 /* Don't allow CWP to be modified. */
628
629 if (psr != registers[PSR])
630 registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
631
632 strcpy(remcomOutBuffer,"OK");
633 }
634 break;
635
636 case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
637 /* Try to read %x,%x. */
638
639 ptr = &remcomInBuffer[1];
640
641 if (hexToInt(&ptr, &addr)
642 && *ptr++ == ','
643 && hexToInt(&ptr, &length)) {
644 if (mem2hex((char *)addr, remcomOutBuffer, length))
645 break;
646
647 strcpy (remcomOutBuffer, "E03");
648 } else {
649 strcpy(remcomOutBuffer,"E01");
650 }
651 break;
652
653 case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
654 /* Try to read '%x,%x:'. */
655
656 ptr = &remcomInBuffer[1];
657
658 if (hexToInt(&ptr, &addr)
659 && *ptr++ == ','
660 && hexToInt(&ptr, &length)
661 && *ptr++ == ':') {
662 if (hex2mem(ptr, (char *)addr, length)) {
663 strcpy(remcomOutBuffer, "OK");
664 } else {
665 strcpy(remcomOutBuffer, "E03");
666 }
667 } else {
668 strcpy(remcomOutBuffer, "E02");
669 }
670 break;
671
672 case 'c': /* cAA..AA Continue at address AA..AA(optional) */
673 /* try to read optional parameter, pc unchanged if no parm */
674
675 ptr = &remcomInBuffer[1];
676 if (hexToInt(&ptr, &addr)) {
677 registers[PC] = addr;
678 registers[NPC] = addr + 4;
679 }
680
681/* Need to flush the instruction cache here, as we may have deposited a
682 * breakpoint, and the icache probably has no way of knowing that a data ref to
683 * some location may have changed something that is in the instruction cache.
684 */
685 flush_cache_all();
686 unlock_kernel();
687 return;
688
689 /* kill the program */
690 case 'k' : /* do nothing */
691 break;
692 case 'r': /* Reset */
693 asm ("call 0\n\t"
694 "nop\n\t");
695 break;
696 } /* switch */
697
698 /* reply to the request */
699 putpacket(remcomOutBuffer);
700 } /* while(1) */
701}
702
703/* This function will generate a breakpoint exception. It is used at the
704 beginning of a program to sync up with a debugger and can be used
705 otherwise as a quick means to stop program execution and "break" into
706 the debugger. */
707
708void
709breakpoint(void)
710{
711 if (!initialized)
712 return;
713
714 /* Again, watch those c-prefixes for ELF kernels */
715#if defined(__svr4__) || defined(__ELF__)
716 asm(".globl breakinst\n"
717 "breakinst:\n\t"
718 "ta 1\n");
719#else
720 asm(".globl _breakinst\n"
721 "_breakinst:\n\t"
722 "ta 1\n");
723#endif
724}
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 0def48158c7d..dfde77ff0848 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -335,37 +335,6 @@ void smp4d_cross_call_irq(void)
335 ccall_info.processors_out[i] = 1; 335 ccall_info.processors_out[i] = 1;
336} 336}
337 337
338static int smp4d_stop_cpu_sender;
339
340static void smp4d_stop_cpu(void)
341{
342 int me = hard_smp4d_processor_id();
343
344 if (me != smp4d_stop_cpu_sender)
345 while(1) barrier();
346}
347
348/* Cross calls, in order to work efficiently and atomically do all
349 * the message passing work themselves, only stopcpu and reschedule
350 * messages come through here.
351 */
352void smp4d_message_pass(int target, int msg, unsigned long data, int wait)
353{
354 int me = hard_smp4d_processor_id();
355
356 SMP_PRINTK(("smp4d_message_pass %d %d %08lx %d\n", target, msg, data, wait));
357 if (msg == MSG_STOP_CPU && target == MSG_ALL_BUT_SELF) {
358 unsigned long flags;
359 static DEFINE_SPINLOCK(stop_cpu_lock);
360 spin_lock_irqsave(&stop_cpu_lock, flags);
361 smp4d_stop_cpu_sender = me;
362 smp4d_cross_call((smpfunc_t)smp4d_stop_cpu, 0, 0, 0, 0, 0);
363 spin_unlock_irqrestore(&stop_cpu_lock, flags);
364 }
365 printk("Yeeee, trying to send SMP msg(%d) to %d on cpu %d\n", msg, target, me);
366 panic("Bogon SMP message pass.");
367}
368
369void smp4d_percpu_timer_interrupt(struct pt_regs *regs) 338void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
370{ 339{
371 struct pt_regs *old_regs; 340 struct pt_regs *old_regs;
@@ -439,7 +408,6 @@ void __init sun4d_init_smp(void)
439 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); 408 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
440 BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); 409 BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
441 BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); 410 BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
442 BTFIXUPSET_CALL(smp_message_pass, smp4d_message_pass, BTFIXUPCALL_NORM);
443 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); 411 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
444 412
445 for (i = 0; i < NR_CPUS; i++) { 413 for (i = 0; i < NR_CPUS; i++) {
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 0b9407267162..ffb875aacb7e 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -34,8 +34,6 @@
34 34
35#include "irq.h" 35#include "irq.h"
36 36
37#define IRQ_RESCHEDULE 13
38#define IRQ_STOP_CPU 14
39#define IRQ_CROSS_CALL 15 37#define IRQ_CROSS_CALL 15
40 38
41extern ctxd_t *srmmu_ctx_table_phys; 39extern ctxd_t *srmmu_ctx_table_phys;
@@ -232,48 +230,6 @@ void smp4m_irq_rotate(int cpu)
232 set_irq_udt(next); 230 set_irq_udt(next);
233} 231}
234 232
235/* Cross calls, in order to work efficiently and atomically do all
236 * the message passing work themselves, only stopcpu and reschedule
237 * messages come through here.
238 */
239void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
240{
241 static unsigned long smp_cpu_in_msg[NR_CPUS];
242 cpumask_t mask;
243 int me = smp_processor_id();
244 int irq, i;
245
246 if(msg == MSG_RESCHEDULE) {
247 irq = IRQ_RESCHEDULE;
248
249 if(smp_cpu_in_msg[me])
250 return;
251 } else if(msg == MSG_STOP_CPU) {
252 irq = IRQ_STOP_CPU;
253 } else {
254 goto barf;
255 }
256
257 smp_cpu_in_msg[me]++;
258 if(target == MSG_ALL_BUT_SELF || target == MSG_ALL) {
259 mask = cpu_online_map;
260 if(target == MSG_ALL_BUT_SELF)
261 cpu_clear(me, mask);
262 for(i = 0; i < 4; i++) {
263 if (cpu_isset(i, mask))
264 set_cpu_int(i, irq);
265 }
266 } else {
267 set_cpu_int(target, irq);
268 }
269 smp_cpu_in_msg[me]--;
270
271 return;
272barf:
273 printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
274 panic("Bogon SMP message pass.");
275}
276
277static struct smp_funcall { 233static struct smp_funcall {
278 smpfunc_t func; 234 smpfunc_t func;
279 unsigned long arg1; 235 unsigned long arg1;
@@ -413,6 +369,5 @@ void __init sun4m_init_smp(void)
413 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); 369 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
414 BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); 370 BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
415 BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); 371 BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
416 BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
417 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); 372 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
418} 373}
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index edbe71e3fab9..eb36f3b746b8 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -13,6 +13,7 @@ config SPARC64
13 default y 13 default y
14 select HAVE_IDE 14 select HAVE_IDE
15 select HAVE_LMB 15 select HAVE_LMB
16 select HAVE_ARCH_KGDB
16 17
17config GENERIC_TIME 18config GENERIC_TIME
18 bool 19 bool
diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile
index 2bd0340b743d..ec4f5ebb1ca6 100644
--- a/arch/sparc64/kernel/Makefile
+++ b/arch/sparc64/kernel/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o
29obj-$(CONFIG_AUDIT) += audit.o 29obj-$(CONFIG_AUDIT) += audit.o
30obj-$(CONFIG_AUDIT)$(CONFIG_COMPAT) += compat_audit.o 30obj-$(CONFIG_AUDIT)$(CONFIG_COMPAT) += compat_audit.o
31obj-y += $(obj-yy) 31obj-y += $(obj-yy)
32obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/sparc64/kernel/cherrs.S b/arch/sparc64/kernel/cherrs.S
new file mode 100644
index 000000000000..89afebd7eca0
--- /dev/null
+++ b/arch/sparc64/kernel/cherrs.S
@@ -0,0 +1,579 @@
1 /* These get patched into the trap table at boot time
2 * once we know we have a cheetah processor.
3 */
4 .globl cheetah_fecc_trap_vector
5 .type cheetah_fecc_trap_vector,#function
6cheetah_fecc_trap_vector:
7 membar #Sync
8 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
9 andn %g1, DCU_DC | DCU_IC, %g1
10 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
11 membar #Sync
12 sethi %hi(cheetah_fast_ecc), %g2
13 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
14 mov 0, %g1
15 .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
16
17 .globl cheetah_fecc_trap_vector_tl1
18 .type cheetah_fecc_trap_vector_tl1,#function
19cheetah_fecc_trap_vector_tl1:
20 membar #Sync
21 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
22 andn %g1, DCU_DC | DCU_IC, %g1
23 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
24 membar #Sync
25 sethi %hi(cheetah_fast_ecc), %g2
26 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
27 mov 1, %g1
28 .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
29
30 .globl cheetah_cee_trap_vector
31 .type cheetah_cee_trap_vector,#function
32cheetah_cee_trap_vector:
33 membar #Sync
34 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
35 andn %g1, DCU_IC, %g1
36 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
37 membar #Sync
38 sethi %hi(cheetah_cee), %g2
39 jmpl %g2 + %lo(cheetah_cee), %g0
40 mov 0, %g1
41 .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
42
43 .globl cheetah_cee_trap_vector_tl1
44 .type cheetah_cee_trap_vector_tl1,#function
45cheetah_cee_trap_vector_tl1:
46 membar #Sync
47 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
48 andn %g1, DCU_IC, %g1
49 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
50 membar #Sync
51 sethi %hi(cheetah_cee), %g2
52 jmpl %g2 + %lo(cheetah_cee), %g0
53 mov 1, %g1
54 .size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1
55
56 .globl cheetah_deferred_trap_vector
57 .type cheetah_deferred_trap_vector,#function
58cheetah_deferred_trap_vector:
59 membar #Sync
60 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
61 andn %g1, DCU_DC | DCU_IC, %g1;
62 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
63 membar #Sync;
64 sethi %hi(cheetah_deferred_trap), %g2
65 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
66 mov 0, %g1
67 .size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector
68
69 .globl cheetah_deferred_trap_vector_tl1
70 .type cheetah_deferred_trap_vector_tl1,#function
71cheetah_deferred_trap_vector_tl1:
72 membar #Sync;
73 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
74 andn %g1, DCU_DC | DCU_IC, %g1;
75 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
76 membar #Sync;
77 sethi %hi(cheetah_deferred_trap), %g2
78 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
79 mov 1, %g1
80 .size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1
81
82 /* Cheetah+ specific traps. These are for the new I/D cache parity
83 * error traps. The first argument to cheetah_plus_parity_handler
84 * is encoded as follows:
85 *
86 * Bit0: 0=dcache,1=icache
87 * Bit1: 0=recoverable,1=unrecoverable
88 */
89 .globl cheetah_plus_dcpe_trap_vector
90 .type cheetah_plus_dcpe_trap_vector,#function
91cheetah_plus_dcpe_trap_vector:
92 membar #Sync
93 sethi %hi(do_cheetah_plus_data_parity), %g7
94 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
95 nop
96 nop
97 nop
98 nop
99 nop
100 .size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector
101
102 .type do_cheetah_plus_data_parity,#function
103do_cheetah_plus_data_parity:
104 rdpr %pil, %g2
105 wrpr %g0, 15, %pil
106 ba,pt %xcc, etrap_irq
107 rd %pc, %g7
108#ifdef CONFIG_TRACE_IRQFLAGS
109 call trace_hardirqs_off
110 nop
111#endif
112 mov 0x0, %o0
113 call cheetah_plus_parity_error
114 add %sp, PTREGS_OFF, %o1
115 ba,a,pt %xcc, rtrap_irq
116 .size do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity
117
118 .globl cheetah_plus_dcpe_trap_vector_tl1
119 .type cheetah_plus_dcpe_trap_vector_tl1,#function
120cheetah_plus_dcpe_trap_vector_tl1:
121 membar #Sync
122 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
123 sethi %hi(do_dcpe_tl1), %g3
124 jmpl %g3 + %lo(do_dcpe_tl1), %g0
125 nop
126 nop
127 nop
128 nop
129 .size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1
130
131 .globl cheetah_plus_icpe_trap_vector
132 .type cheetah_plus_icpe_trap_vector,#function
133cheetah_plus_icpe_trap_vector:
134 membar #Sync
135 sethi %hi(do_cheetah_plus_insn_parity), %g7
136 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
137 nop
138 nop
139 nop
140 nop
141 nop
142 .size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector
143
144 .type do_cheetah_plus_insn_parity,#function
145do_cheetah_plus_insn_parity:
146 rdpr %pil, %g2
147 wrpr %g0, 15, %pil
148 ba,pt %xcc, etrap_irq
149 rd %pc, %g7
150#ifdef CONFIG_TRACE_IRQFLAGS
151 call trace_hardirqs_off
152 nop
153#endif
154 mov 0x1, %o0
155 call cheetah_plus_parity_error
156 add %sp, PTREGS_OFF, %o1
157 ba,a,pt %xcc, rtrap_irq
158 .size do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity
159
160 .globl cheetah_plus_icpe_trap_vector_tl1
161 .type cheetah_plus_icpe_trap_vector_tl1,#function
162cheetah_plus_icpe_trap_vector_tl1:
163 membar #Sync
164 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
165 sethi %hi(do_icpe_tl1), %g3
166 jmpl %g3 + %lo(do_icpe_tl1), %g0
167 nop
168 nop
169 nop
170 nop
171 .size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1
172
173 /* If we take one of these traps when tl >= 1, then we
174 * jump to interrupt globals. If some trap level above us
175 * was also using interrupt globals, we cannot recover.
176 * We may use all interrupt global registers except %g6.
177 */
178 .globl do_dcpe_tl1
179 .type do_dcpe_tl1,#function
180do_dcpe_tl1:
181 rdpr %tl, %g1 ! Save original trap level
182 mov 1, %g2 ! Setup TSTATE checking loop
183 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1841: wrpr %g2, %tl ! Set trap level to check
185 rdpr %tstate, %g4 ! Read TSTATE for this level
186 andcc %g4, %g3, %g0 ! Interrupt globals in use?
187 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
188 wrpr %g1, %tl ! Restore original trap level
189 add %g2, 1, %g2 ! Next trap level
190 cmp %g2, %g1 ! Hit them all yet?
191 ble,pt %icc, 1b ! Not yet
192 nop
193 wrpr %g1, %tl ! Restore original trap level
194do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
195 sethi %hi(dcache_parity_tl1_occurred), %g2
196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
197 add %g1, 1, %g1
198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
199 /* Reset D-cache parity */
200 sethi %hi(1 << 16), %g1 ! D-cache size
201 mov (1 << 5), %g2 ! D-cache line size
202 sub %g1, %g2, %g1 ! Move down 1 cacheline
2031: srl %g1, 14, %g3 ! Compute UTAG
204 membar #Sync
205 stxa %g3, [%g1] ASI_DCACHE_UTAG
206 membar #Sync
207 sub %g2, 8, %g3 ! 64-bit data word within line
2082: membar #Sync
209 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
210 membar #Sync
211 subcc %g3, 8, %g3 ! Next 64-bit data word
212 bge,pt %icc, 2b
213 nop
214 subcc %g1, %g2, %g1 ! Next cacheline
215 bge,pt %icc, 1b
216 nop
217 ba,pt %xcc, dcpe_icpe_tl1_common
218 nop
219
220do_dcpe_tl1_fatal:
221 sethi %hi(1f), %g7
222 ba,pt %xcc, etraptl1
2231: or %g7, %lo(1b), %g7
224 mov 0x2, %o0
225 call cheetah_plus_parity_error
226 add %sp, PTREGS_OFF, %o1
227 ba,pt %xcc, rtrap
228 nop
229 .size do_dcpe_tl1,.-do_dcpe_tl1
230
231 .globl do_icpe_tl1
232 .type do_icpe_tl1,#function
233do_icpe_tl1:
234 rdpr %tl, %g1 ! Save original trap level
235 mov 1, %g2 ! Setup TSTATE checking loop
236 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
2371: wrpr %g2, %tl ! Set trap level to check
238 rdpr %tstate, %g4 ! Read TSTATE for this level
239 andcc %g4, %g3, %g0 ! Interrupt globals in use?
240 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
241 wrpr %g1, %tl ! Restore original trap level
242 add %g2, 1, %g2 ! Next trap level
243 cmp %g2, %g1 ! Hit them all yet?
244 ble,pt %icc, 1b ! Not yet
245 nop
246 wrpr %g1, %tl ! Restore original trap level
247do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
248 sethi %hi(icache_parity_tl1_occurred), %g2
249 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
250 add %g1, 1, %g1
251 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
252 /* Flush I-cache */
253 sethi %hi(1 << 15), %g1 ! I-cache size
254 mov (1 << 5), %g2 ! I-cache line size
255 sub %g1, %g2, %g1
2561: or %g1, (2 << 3), %g3
257 stxa %g0, [%g3] ASI_IC_TAG
258 membar #Sync
259 subcc %g1, %g2, %g1
260 bge,pt %icc, 1b
261 nop
262 ba,pt %xcc, dcpe_icpe_tl1_common
263 nop
264
265do_icpe_tl1_fatal:
266 sethi %hi(1f), %g7
267 ba,pt %xcc, etraptl1
2681: or %g7, %lo(1b), %g7
269 mov 0x3, %o0
270 call cheetah_plus_parity_error
271 add %sp, PTREGS_OFF, %o1
272 ba,pt %xcc, rtrap
273 nop
274 .size do_icpe_tl1,.-do_icpe_tl1
275
276 .type dcpe_icpe_tl1_common,#function
277dcpe_icpe_tl1_common:
278 /* Flush D-cache, re-enable D/I caches in DCU and finally
279 * retry the trapping instruction.
280 */
281 sethi %hi(1 << 16), %g1 ! D-cache size
282 mov (1 << 5), %g2 ! D-cache line size
283 sub %g1, %g2, %g1
2841: stxa %g0, [%g1] ASI_DCACHE_TAG
285 membar #Sync
286 subcc %g1, %g2, %g1
287 bge,pt %icc, 1b
288 nop
289 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
290 or %g1, (DCU_DC | DCU_IC), %g1
291 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
292 membar #Sync
293 retry
294 .size dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common
295
296 /* Capture I/D/E-cache state into per-cpu error scoreboard.
297 *
298 * %g1: (TL>=0) ? 1 : 0
299 * %g2: scratch
300 * %g3: scratch
301 * %g4: AFSR
302 * %g5: AFAR
303 * %g6: unused, will have current thread ptr after etrap
304 * %g7: scratch
305 */
306 .type __cheetah_log_error,#function
307__cheetah_log_error:
308 /* Put "TL1" software bit into AFSR. */
309 and %g1, 0x1, %g1
310 sllx %g1, 63, %g2
311 or %g4, %g2, %g4
312
313 /* Get log entry pointer for this cpu at this trap level. */
314 BRANCH_IF_JALAPENO(g2,g3,50f)
315 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
316 srlx %g2, 17, %g2
317 ba,pt %xcc, 60f
318 and %g2, 0x3ff, %g2
319
32050: ldxa [%g0] ASI_JBUS_CONFIG, %g2
321 srlx %g2, 17, %g2
322 and %g2, 0x1f, %g2
323
32460: sllx %g2, 9, %g2
325 sethi %hi(cheetah_error_log), %g3
326 ldx [%g3 + %lo(cheetah_error_log)], %g3
327 brz,pn %g3, 80f
328 nop
329
330 add %g3, %g2, %g3
331 sllx %g1, 8, %g1
332 add %g3, %g1, %g1
333
334 /* %g1 holds pointer to the top of the logging scoreboard */
335 ldx [%g1 + 0x0], %g7
336 cmp %g7, -1
337 bne,pn %xcc, 80f
338 nop
339
340 stx %g4, [%g1 + 0x0]
341 stx %g5, [%g1 + 0x8]
342 add %g1, 0x10, %g1
343
344 /* %g1 now points to D-cache logging area */
345 set 0x3ff8, %g2 /* DC_addr mask */
346 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
347 srlx %g5, 12, %g3
348 or %g3, 1, %g3 /* PHYS tag + valid */
349
35010: ldxa [%g2] ASI_DCACHE_TAG, %g7
351 cmp %g3, %g7 /* TAG match? */
352 bne,pt %xcc, 13f
353 nop
354
355 /* Yep, what we want, capture state. */
356 stx %g2, [%g1 + 0x20]
357 stx %g7, [%g1 + 0x28]
358
359 /* A membar Sync is required before and after utag access. */
360 membar #Sync
361 ldxa [%g2] ASI_DCACHE_UTAG, %g7
362 membar #Sync
363 stx %g7, [%g1 + 0x30]
364 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
365 stx %g7, [%g1 + 0x38]
366 clr %g3
367
36812: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
369 stx %g7, [%g1]
370 add %g3, (1 << 5), %g3
371 cmp %g3, (4 << 5)
372 bl,pt %xcc, 12b
373 add %g1, 0x8, %g1
374
375 ba,pt %xcc, 20f
376 add %g1, 0x20, %g1
377
37813: sethi %hi(1 << 14), %g7
379 add %g2, %g7, %g2
380 srlx %g2, 14, %g7
381 cmp %g7, 4
382 bl,pt %xcc, 10b
383 nop
384
385 add %g1, 0x40, %g1
386
387 /* %g1 now points to I-cache logging area */
38820: set 0x1fe0, %g2 /* IC_addr mask */
389 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
390 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
391 srlx %g5, (13 - 8), %g3 /* Make PTAG */
392 andn %g3, 0xff, %g3 /* Mask off undefined bits */
393
39421: ldxa [%g2] ASI_IC_TAG, %g7
395 andn %g7, 0xff, %g7
396 cmp %g3, %g7
397 bne,pt %xcc, 23f
398 nop
399
400 /* Yep, what we want, capture state. */
401 stx %g2, [%g1 + 0x40]
402 stx %g7, [%g1 + 0x48]
403 add %g2, (1 << 3), %g2
404 ldxa [%g2] ASI_IC_TAG, %g7
405 add %g2, (1 << 3), %g2
406 stx %g7, [%g1 + 0x50]
407 ldxa [%g2] ASI_IC_TAG, %g7
408 add %g2, (1 << 3), %g2
409 stx %g7, [%g1 + 0x60]
410 ldxa [%g2] ASI_IC_TAG, %g7
411 stx %g7, [%g1 + 0x68]
412 sub %g2, (3 << 3), %g2
413 ldxa [%g2] ASI_IC_STAG, %g7
414 stx %g7, [%g1 + 0x58]
415 clr %g3
416 srlx %g2, 2, %g2
417
41822: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
419 stx %g7, [%g1]
420 add %g3, (1 << 3), %g3
421 cmp %g3, (8 << 3)
422 bl,pt %xcc, 22b
423 add %g1, 0x8, %g1
424
425 ba,pt %xcc, 30f
426 add %g1, 0x30, %g1
427
42823: sethi %hi(1 << 14), %g7
429 add %g2, %g7, %g2
430 srlx %g2, 14, %g7
431 cmp %g7, 4
432 bl,pt %xcc, 21b
433 nop
434
435 add %g1, 0x70, %g1
436
437 /* %g1 now points to E-cache logging area */
43830: andn %g5, (32 - 1), %g2
439 stx %g2, [%g1 + 0x20]
440 ldxa [%g2] ASI_EC_TAG_DATA, %g7
441 stx %g7, [%g1 + 0x28]
442 ldxa [%g2] ASI_EC_R, %g0
443 clr %g3
444
44531: ldxa [%g3] ASI_EC_DATA, %g7
446 stx %g7, [%g1 + %g3]
447 add %g3, 0x8, %g3
448 cmp %g3, 0x20
449
450 bl,pt %xcc, 31b
451 nop
45280:
453 rdpr %tt, %g2
454 cmp %g2, 0x70
455 be c_fast_ecc
456 cmp %g2, 0x63
457 be c_cee
458 nop
459 ba,pt %xcc, c_deferred
460 .size __cheetah_log_error,.-__cheetah_log_error
461
462 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
463 * in the trap table. That code has done a memory barrier
464 * and has disabled both the I-cache and D-cache in the DCU
465 * control register. The I-cache is disabled so that we may
466 * capture the corrupted cache line, and the D-cache is disabled
467 * because corrupt data may have been placed there and we don't
468 * want to reference it.
469 *
470 * %g1 is one if this trap occurred at %tl >= 1.
471 *
472 * Next, we turn off error reporting so that we don't recurse.
473 */
474 .globl cheetah_fast_ecc
475 .type cheetah_fast_ecc,#function
476cheetah_fast_ecc:
477 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
478 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
479 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
480 membar #Sync
481
482 /* Fetch and clear AFSR/AFAR */
483 ldxa [%g0] ASI_AFSR, %g4
484 ldxa [%g0] ASI_AFAR, %g5
485 stxa %g4, [%g0] ASI_AFSR
486 membar #Sync
487
488 ba,pt %xcc, __cheetah_log_error
489 nop
490 .size cheetah_fast_ecc,.-cheetah_fast_ecc
491
492 .type c_fast_ecc,#function
493c_fast_ecc:
494 rdpr %pil, %g2
495 wrpr %g0, 15, %pil
496 ba,pt %xcc, etrap_irq
497 rd %pc, %g7
498#ifdef CONFIG_TRACE_IRQFLAGS
499 call trace_hardirqs_off
500 nop
501#endif
502 mov %l4, %o1
503 mov %l5, %o2
504 call cheetah_fecc_handler
505 add %sp, PTREGS_OFF, %o0
506 ba,a,pt %xcc, rtrap_irq
507 .size c_fast_ecc,.-c_fast_ecc
508
509 /* Our caller has disabled I-cache and performed membar Sync. */
510 .globl cheetah_cee
511 .type cheetah_cee,#function
512cheetah_cee:
513 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
514 andn %g2, ESTATE_ERROR_CEEN, %g2
515 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
516 membar #Sync
517
518 /* Fetch and clear AFSR/AFAR */
519 ldxa [%g0] ASI_AFSR, %g4
520 ldxa [%g0] ASI_AFAR, %g5
521 stxa %g4, [%g0] ASI_AFSR
522 membar #Sync
523
524 ba,pt %xcc, __cheetah_log_error
525 nop
526 .size cheetah_cee,.-cheetah_cee
527
528 .type c_cee,#function
529c_cee:
530 rdpr %pil, %g2
531 wrpr %g0, 15, %pil
532 ba,pt %xcc, etrap_irq
533 rd %pc, %g7
534#ifdef CONFIG_TRACE_IRQFLAGS
535 call trace_hardirqs_off
536 nop
537#endif
538 mov %l4, %o1
539 mov %l5, %o2
540 call cheetah_cee_handler
541 add %sp, PTREGS_OFF, %o0
542 ba,a,pt %xcc, rtrap_irq
543 .size c_cee,.-c_cee
544
545 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
546 .globl cheetah_deferred_trap
547 .type cheetah_deferred_trap,#function
548cheetah_deferred_trap:
549 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
550 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
551 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
552 membar #Sync
553
554 /* Fetch and clear AFSR/AFAR */
555 ldxa [%g0] ASI_AFSR, %g4
556 ldxa [%g0] ASI_AFAR, %g5
557 stxa %g4, [%g0] ASI_AFSR
558 membar #Sync
559
560 ba,pt %xcc, __cheetah_log_error
561 nop
562 .size cheetah_deferred_trap,.-cheetah_deferred_trap
563
564 .type c_deferred,#function
565c_deferred:
566 rdpr %pil, %g2
567 wrpr %g0, 15, %pil
568 ba,pt %xcc, etrap_irq
569 rd %pc, %g7
570#ifdef CONFIG_TRACE_IRQFLAGS
571 call trace_hardirqs_off
572 nop
573#endif
574 mov %l4, %o1
575 mov %l5, %o2
576 call cheetah_deferred_handler
577 add %sp, PTREGS_OFF, %o0
578 ba,a,pt %xcc, rtrap_irq
579 .size c_deferred,.-c_deferred
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
deleted file mode 100644
index fd06e937ae1e..000000000000
--- a/arch/sparc64/kernel/entry.S
+++ /dev/null
@@ -1,2575 +0,0 @@
1/* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/errno.h>
11
12#include <asm/head.h>
13#include <asm/asi.h>
14#include <asm/smp.h>
15#include <asm/ptrace.h>
16#include <asm/page.h>
17#include <asm/signal.h>
18#include <asm/pgtable.h>
19#include <asm/processor.h>
20#include <asm/visasm.h>
21#include <asm/estate.h>
22#include <asm/auxio.h>
23#include <asm/sfafsr.h>
24#include <asm/pil.h>
25#include <asm/unistd.h>
26
27#define curptr g6
28
29 .text
30 .align 32
31
32 /* This is trivial with the new code... */
33 .globl do_fpdis
34do_fpdis:
35 sethi %hi(TSTATE_PEF), %g4
36 rdpr %tstate, %g5
37 andcc %g5, %g4, %g0
38 be,pt %xcc, 1f
39 nop
40 rd %fprs, %g5
41 andcc %g5, FPRS_FEF, %g0
42 be,pt %xcc, 1f
43 nop
44
45 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
46 sethi %hi(109f), %g7
47 ba,pt %xcc, etrap
48109: or %g7, %lo(109b), %g7
49 add %g0, %g0, %g0
50 ba,a,pt %xcc, rtrap
51
521: TRAP_LOAD_THREAD_REG(%g6, %g1)
53 ldub [%g6 + TI_FPSAVED], %g5
54 wr %g0, FPRS_FEF, %fprs
55 andcc %g5, FPRS_FEF, %g0
56 be,a,pt %icc, 1f
57 clr %g7
58 ldx [%g6 + TI_GSR], %g7
591: andcc %g5, FPRS_DL, %g0
60 bne,pn %icc, 2f
61 fzero %f0
62 andcc %g5, FPRS_DU, %g0
63 bne,pn %icc, 1f
64 fzero %f2
65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8
68 fmuld %f0, %f2, %f10
69 faddd %f0, %f2, %f12
70 fmuld %f0, %f2, %f14
71 faddd %f0, %f2, %f16
72 fmuld %f0, %f2, %f18
73 faddd %f0, %f2, %f20
74 fmuld %f0, %f2, %f22
75 faddd %f0, %f2, %f24
76 fmuld %f0, %f2, %f26
77 faddd %f0, %f2, %f28
78 fmuld %f0, %f2, %f30
79 faddd %f0, %f2, %f32
80 fmuld %f0, %f2, %f34
81 faddd %f0, %f2, %f36
82 fmuld %f0, %f2, %f38
83 faddd %f0, %f2, %f40
84 fmuld %f0, %f2, %f42
85 faddd %f0, %f2, %f44
86 fmuld %f0, %f2, %f46
87 faddd %f0, %f2, %f48
88 fmuld %f0, %f2, %f50
89 faddd %f0, %f2, %f52
90 fmuld %f0, %f2, %f54
91 faddd %f0, %f2, %f56
92 fmuld %f0, %f2, %f58
93 b,pt %xcc, fpdis_exit2
94 faddd %f0, %f2, %f60
951: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6
99
100661: ldxa [%g3] ASI_DMMU, %g5
101 .section .sun4v_1insn_patch, "ax"
102 .word 661b
103 ldxa [%g3] ASI_MMU, %g5
104 .previous
105
106 sethi %hi(sparc64_kern_sec_context), %g2
107 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
108
109661: stxa %g2, [%g3] ASI_DMMU
110 .section .sun4v_1insn_patch, "ax"
111 .word 661b
112 stxa %g2, [%g3] ASI_MMU
113 .previous
114
115 membar #Sync
116 add %g6, TI_FPREGS + 0xc0, %g2
117 faddd %f0, %f2, %f8
118 fmuld %f0, %f2, %f10
119 membar #Sync
120 ldda [%g1] ASI_BLK_S, %f32
121 ldda [%g2] ASI_BLK_S, %f48
122 membar #Sync
123 faddd %f0, %f2, %f12
124 fmuld %f0, %f2, %f14
125 faddd %f0, %f2, %f16
126 fmuld %f0, %f2, %f18
127 faddd %f0, %f2, %f20
128 fmuld %f0, %f2, %f22
129 faddd %f0, %f2, %f24
130 fmuld %f0, %f2, %f26
131 faddd %f0, %f2, %f28
132 fmuld %f0, %f2, %f30
133 b,pt %xcc, fpdis_exit
134 nop
1352: andcc %g5, FPRS_DU, %g0
136 bne,pt %icc, 3f
137 fzero %f32
138 mov SECONDARY_CONTEXT, %g3
139 fzero %f34
140
141661: ldxa [%g3] ASI_DMMU, %g5
142 .section .sun4v_1insn_patch, "ax"
143 .word 661b
144 ldxa [%g3] ASI_MMU, %g5
145 .previous
146
147 add %g6, TI_FPREGS, %g1
148 sethi %hi(sparc64_kern_sec_context), %g2
149 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
150
151661: stxa %g2, [%g3] ASI_DMMU
152 .section .sun4v_1insn_patch, "ax"
153 .word 661b
154 stxa %g2, [%g3] ASI_MMU
155 .previous
156
157 membar #Sync
158 add %g6, TI_FPREGS + 0x40, %g2
159 faddd %f32, %f34, %f36
160 fmuld %f32, %f34, %f38
161 membar #Sync
162 ldda [%g1] ASI_BLK_S, %f0
163 ldda [%g2] ASI_BLK_S, %f16
164 membar #Sync
165 faddd %f32, %f34, %f40
166 fmuld %f32, %f34, %f42
167 faddd %f32, %f34, %f44
168 fmuld %f32, %f34, %f46
169 faddd %f32, %f34, %f48
170 fmuld %f32, %f34, %f50
171 faddd %f32, %f34, %f52
172 fmuld %f32, %f34, %f54
173 faddd %f32, %f34, %f56
174 fmuld %f32, %f34, %f58
175 faddd %f32, %f34, %f60
176 fmuld %f32, %f34, %f62
177 ba,pt %xcc, fpdis_exit
178 nop
1793: mov SECONDARY_CONTEXT, %g3
180 add %g6, TI_FPREGS, %g1
181
182661: ldxa [%g3] ASI_DMMU, %g5
183 .section .sun4v_1insn_patch, "ax"
184 .word 661b
185 ldxa [%g3] ASI_MMU, %g5
186 .previous
187
188 sethi %hi(sparc64_kern_sec_context), %g2
189 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
190
191661: stxa %g2, [%g3] ASI_DMMU
192 .section .sun4v_1insn_patch, "ax"
193 .word 661b
194 stxa %g2, [%g3] ASI_MMU
195 .previous
196
197 membar #Sync
198 mov 0x40, %g2
199 membar #Sync
200 ldda [%g1] ASI_BLK_S, %f0
201 ldda [%g1 + %g2] ASI_BLK_S, %f16
202 add %g1, 0x80, %g1
203 ldda [%g1] ASI_BLK_S, %f32
204 ldda [%g1 + %g2] ASI_BLK_S, %f48
205 membar #Sync
206fpdis_exit:
207
208661: stxa %g5, [%g3] ASI_DMMU
209 .section .sun4v_1insn_patch, "ax"
210 .word 661b
211 stxa %g5, [%g3] ASI_MMU
212 .previous
213
214 membar #Sync
215fpdis_exit2:
216 wr %g7, 0, %gsr
217 ldx [%g6 + TI_XFSR], %fsr
218 rdpr %tstate, %g3
219 or %g3, %g4, %g3 ! anal...
220 wrpr %g3, %tstate
221 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
222 retry
223
224 .align 32
225fp_other_bounce:
226 call do_fpother
227 add %sp, PTREGS_OFF, %o0
228 ba,pt %xcc, rtrap
229 nop
230
231 .globl do_fpother_check_fitos
232 .align 32
233do_fpother_check_fitos:
234 TRAP_LOAD_THREAD_REG(%g6, %g1)
235 sethi %hi(fp_other_bounce - 4), %g7
236 or %g7, %lo(fp_other_bounce - 4), %g7
237
238 /* NOTE: Need to preserve %g7 until we fully commit
239 * to the fitos fixup.
240 */
241 stx %fsr, [%g6 + TI_XFSR]
242 rdpr %tstate, %g3
243 andcc %g3, TSTATE_PRIV, %g0
244 bne,pn %xcc, do_fptrap_after_fsr
245 nop
246 ldx [%g6 + TI_XFSR], %g3
247 srlx %g3, 14, %g1
248 and %g1, 7, %g1
249 cmp %g1, 2 ! Unfinished FP-OP
250 bne,pn %xcc, do_fptrap_after_fsr
251 sethi %hi(1 << 23), %g1 ! Inexact
252 andcc %g3, %g1, %g0
253 bne,pn %xcc, do_fptrap_after_fsr
254 rdpr %tpc, %g1
255 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
256#define FITOS_MASK 0xc1f83fe0
257#define FITOS_COMPARE 0x81a01880
258 sethi %hi(FITOS_MASK), %g1
259 or %g1, %lo(FITOS_MASK), %g1
260 and %g3, %g1, %g1
261 sethi %hi(FITOS_COMPARE), %g2
262 or %g2, %lo(FITOS_COMPARE), %g2
263 cmp %g1, %g2
264 bne,pn %xcc, do_fptrap_after_fsr
265 nop
266 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
267 sethi %hi(fitos_table_1), %g1
268 and %g3, 0x1f, %g2
269 or %g1, %lo(fitos_table_1), %g1
270 sllx %g2, 2, %g2
271 jmpl %g1 + %g2, %g0
272 ba,pt %xcc, fitos_emul_continue
273
274fitos_table_1:
275 fitod %f0, %f62
276 fitod %f1, %f62
277 fitod %f2, %f62
278 fitod %f3, %f62
279 fitod %f4, %f62
280 fitod %f5, %f62
281 fitod %f6, %f62
282 fitod %f7, %f62
283 fitod %f8, %f62
284 fitod %f9, %f62
285 fitod %f10, %f62
286 fitod %f11, %f62
287 fitod %f12, %f62
288 fitod %f13, %f62
289 fitod %f14, %f62
290 fitod %f15, %f62
291 fitod %f16, %f62
292 fitod %f17, %f62
293 fitod %f18, %f62
294 fitod %f19, %f62
295 fitod %f20, %f62
296 fitod %f21, %f62
297 fitod %f22, %f62
298 fitod %f23, %f62
299 fitod %f24, %f62
300 fitod %f25, %f62
301 fitod %f26, %f62
302 fitod %f27, %f62
303 fitod %f28, %f62
304 fitod %f29, %f62
305 fitod %f30, %f62
306 fitod %f31, %f62
307
308fitos_emul_continue:
309 sethi %hi(fitos_table_2), %g1
310 srl %g3, 25, %g2
311 or %g1, %lo(fitos_table_2), %g1
312 and %g2, 0x1f, %g2
313 sllx %g2, 2, %g2
314 jmpl %g1 + %g2, %g0
315 ba,pt %xcc, fitos_emul_fini
316
317fitos_table_2:
318 fdtos %f62, %f0
319 fdtos %f62, %f1
320 fdtos %f62, %f2
321 fdtos %f62, %f3
322 fdtos %f62, %f4
323 fdtos %f62, %f5
324 fdtos %f62, %f6
325 fdtos %f62, %f7
326 fdtos %f62, %f8
327 fdtos %f62, %f9
328 fdtos %f62, %f10
329 fdtos %f62, %f11
330 fdtos %f62, %f12
331 fdtos %f62, %f13
332 fdtos %f62, %f14
333 fdtos %f62, %f15
334 fdtos %f62, %f16
335 fdtos %f62, %f17
336 fdtos %f62, %f18
337 fdtos %f62, %f19
338 fdtos %f62, %f20
339 fdtos %f62, %f21
340 fdtos %f62, %f22
341 fdtos %f62, %f23
342 fdtos %f62, %f24
343 fdtos %f62, %f25
344 fdtos %f62, %f26
345 fdtos %f62, %f27
346 fdtos %f62, %f28
347 fdtos %f62, %f29
348 fdtos %f62, %f30
349 fdtos %f62, %f31
350
351fitos_emul_fini:
352 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
353 done
354
355 .globl do_fptrap
356 .align 32
357do_fptrap:
358 TRAP_LOAD_THREAD_REG(%g6, %g1)
359 stx %fsr, [%g6 + TI_XFSR]
360do_fptrap_after_fsr:
361 ldub [%g6 + TI_FPSAVED], %g3
362 rd %fprs, %g1
363 or %g3, %g1, %g3
364 stb %g3, [%g6 + TI_FPSAVED]
365 rd %gsr, %g3
366 stx %g3, [%g6 + TI_GSR]
367 mov SECONDARY_CONTEXT, %g3
368
369661: ldxa [%g3] ASI_DMMU, %g5
370 .section .sun4v_1insn_patch, "ax"
371 .word 661b
372 ldxa [%g3] ASI_MMU, %g5
373 .previous
374
375 sethi %hi(sparc64_kern_sec_context), %g2
376 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
377
378661: stxa %g2, [%g3] ASI_DMMU
379 .section .sun4v_1insn_patch, "ax"
380 .word 661b
381 stxa %g2, [%g3] ASI_MMU
382 .previous
383
384 membar #Sync
385 add %g6, TI_FPREGS, %g2
386 andcc %g1, FPRS_DL, %g0
387 be,pn %icc, 4f
388 mov 0x40, %g3
389 stda %f0, [%g2] ASI_BLK_S
390 stda %f16, [%g2 + %g3] ASI_BLK_S
391 andcc %g1, FPRS_DU, %g0
392 be,pn %icc, 5f
3934: add %g2, 128, %g2
394 stda %f32, [%g2] ASI_BLK_S
395 stda %f48, [%g2 + %g3] ASI_BLK_S
3965: mov SECONDARY_CONTEXT, %g1
397 membar #Sync
398
399661: stxa %g5, [%g1] ASI_DMMU
400 .section .sun4v_1insn_patch, "ax"
401 .word 661b
402 stxa %g5, [%g1] ASI_MMU
403 .previous
404
405 membar #Sync
406 ba,pt %xcc, etrap
407 wr %g0, 0, %fprs
408
409 /* The registers for cross calls will be:
410 *
411 * DATA 0: [low 32-bits] Address of function to call, jmp to this
412 * [high 32-bits] MMU Context Argument 0, place in %g5
413 * DATA 1: Address Argument 1, place in %g1
414 * DATA 2: Address Argument 2, place in %g7
415 *
416 * With this method we can do most of the cross-call tlb/cache
417 * flushing very quickly.
418 */
419 .text
420 .align 32
421 .globl do_ivec
422do_ivec:
423 mov 0x40, %g3
424 ldxa [%g3 + %g0] ASI_INTR_R, %g3
425 sethi %hi(KERNBASE), %g4
426 cmp %g3, %g4
427 bgeu,pn %xcc, do_ivec_xcall
428 srlx %g3, 32, %g5
429 stxa %g0, [%g0] ASI_INTR_RECEIVE
430 membar #Sync
431
432 sethi %hi(ivector_table_pa), %g2
433 ldx [%g2 + %lo(ivector_table_pa)], %g2
434 sllx %g3, 4, %g3
435 add %g2, %g3, %g3
436
437 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
438
439 ldx [%g6], %g5
440 stxa %g5, [%g3] ASI_PHYS_USE_EC
441 stx %g3, [%g6]
442 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
443 retry
444do_ivec_xcall:
445 mov 0x50, %g1
446 ldxa [%g1 + %g0] ASI_INTR_R, %g1
447 srl %g3, 0, %g3
448
449 mov 0x60, %g7
450 ldxa [%g7 + %g0] ASI_INTR_R, %g7
451 stxa %g0, [%g0] ASI_INTR_RECEIVE
452 membar #Sync
453 ba,pt %xcc, 1f
454 nop
455
456 .align 32
4571: jmpl %g3, %g0
458 nop
459
460 .globl getcc, setcc
461getcc:
462 ldx [%o0 + PT_V9_TSTATE], %o1
463 srlx %o1, 32, %o1
464 and %o1, 0xf, %o1
465 retl
466 stx %o1, [%o0 + PT_V9_G1]
467setcc:
468 ldx [%o0 + PT_V9_TSTATE], %o1
469 ldx [%o0 + PT_V9_G1], %o2
470 or %g0, %ulo(TSTATE_ICC), %o3
471 sllx %o3, 32, %o3
472 andn %o1, %o3, %o1
473 sllx %o2, 32, %o2
474 and %o2, %o3, %o2
475 or %o1, %o2, %o1
476 retl
477 stx %o1, [%o0 + PT_V9_TSTATE]
478
479 .globl utrap_trap
480utrap_trap: /* %g3=handler,%g4=level */
481 TRAP_LOAD_THREAD_REG(%g6, %g1)
482 ldx [%g6 + TI_UTRAPS], %g1
483 brnz,pt %g1, invoke_utrap
484 nop
485
486 ba,pt %xcc, etrap
487 rd %pc, %g7
488 mov %l4, %o1
489 call bad_trap
490 add %sp, PTREGS_OFF, %o0
491 ba,pt %xcc, rtrap
492 nop
493
494invoke_utrap:
495 sllx %g3, 3, %g3
496 ldx [%g1 + %g3], %g1
497 save %sp, -128, %sp
498 rdpr %tstate, %l6
499 rdpr %cwp, %l7
500 andn %l6, TSTATE_CWP, %l6
501 wrpr %l6, %l7, %tstate
502 rdpr %tpc, %l6
503 rdpr %tnpc, %l7
504 wrpr %g1, 0, %tnpc
505 done
506
507 /* We need to carefully read the error status, ACK
508 * the errors, prevent recursive traps, and pass the
509 * information on to C code for logging.
510 *
511 * We pass the AFAR in as-is, and we encode the status
512 * information as described in asm-sparc64/sfafsr.h
513 */
514 .globl __spitfire_access_error
515__spitfire_access_error:
516 /* Disable ESTATE error reporting so that we do not
517 * take recursive traps and RED state the processor.
518 */
519 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
520 membar #Sync
521
522 mov UDBE_UE, %g1
523 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
524
525 /* __spitfire_cee_trap branches here with AFSR in %g4 and
526 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
527 * ESTATE Error Enable register.
528 */
529__spitfire_cee_trap_continue:
530 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
531
532 rdpr %tt, %g3
533 and %g3, 0x1ff, %g3 ! Paranoia
534 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
535 or %g4, %g3, %g4
536 rdpr %tl, %g3
537 cmp %g3, 1
538 mov 1, %g3
539 bleu %xcc, 1f
540 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
541
542 or %g4, %g3, %g4
543
544 /* Read in the UDB error register state, clearing the
545 * sticky error bits as-needed. We only clear them if
546 * the UE bit is set. Likewise, __spitfire_cee_trap
547 * below will only do so if the CE bit is set.
548 *
549 * NOTE: UltraSparc-I/II have high and low UDB error
550 * registers, corresponding to the two UDB units
551 * present on those chips. UltraSparc-IIi only
552 * has a single UDB, called "SDB" in the manual.
553 * For IIi the upper UDB register always reads
554 * as zero so for our purposes things will just
555 * work with the checks below.
556 */
5571: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
558 and %g3, 0x3ff, %g7 ! Paranoia
559 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
560 or %g4, %g7, %g4
561 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
562 be,pn %xcc, 1f
563 nop
564 stxa %g3, [%g0] ASI_UDB_ERROR_W
565 membar #Sync
566
5671: mov 0x18, %g3
568 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
569 and %g3, 0x3ff, %g7 ! Paranoia
570 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
571 or %g4, %g7, %g4
572 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
573 be,pn %xcc, 1f
574 nop
575 mov 0x18, %g7
576 stxa %g3, [%g7] ASI_UDB_ERROR_W
577 membar #Sync
578
5791: /* Ok, now that we've latched the error state,
580 * clear the sticky bits in the AFSR.
581 */
582 stxa %g4, [%g0] ASI_AFSR
583 membar #Sync
584
585 rdpr %tl, %g2
586 cmp %g2, 1
587 rdpr %pil, %g2
588 bleu,pt %xcc, 1f
589 wrpr %g0, 15, %pil
590
591 ba,pt %xcc, etraptl1
592 rd %pc, %g7
593
594 ba,pt %xcc, 2f
595 nop
596
5971: ba,pt %xcc, etrap_irq
598 rd %pc, %g7
599
6002:
601#ifdef CONFIG_TRACE_IRQFLAGS
602 call trace_hardirqs_off
603 nop
604#endif
605 mov %l4, %o1
606 mov %l5, %o2
607 call spitfire_access_error
608 add %sp, PTREGS_OFF, %o0
609 ba,pt %xcc, rtrap
610 nop
611
612 /* This is the trap handler entry point for ECC correctable
613 * errors. They are corrected, but we listen for the trap
614 * so that the event can be logged.
615 *
616 * Disrupting errors are either:
617 * 1) single-bit ECC errors during UDB reads to system
618 * memory
619 * 2) data parity errors during write-back events
620 *
621 * As far as I can make out from the manual, the CEE trap
622 * is only for correctable errors during memory read
623 * accesses by the front-end of the processor.
624 *
625 * The code below is only for trap level 1 CEE events,
626 * as it is the only situation where we can safely record
627 * and log. For trap level >1 we just clear the CE bit
628 * in the AFSR and return.
629 *
630 * This is just like __spiftire_access_error above, but it
631 * specifically handles correctable errors. If an
632 * uncorrectable error is indicated in the AFSR we
633 * will branch directly above to __spitfire_access_error
634 * to handle it instead. Uncorrectable therefore takes
635 * priority over correctable, and the error logging
636 * C code will notice this case by inspecting the
637 * trap type.
638 */
639 .globl __spitfire_cee_trap
640__spitfire_cee_trap:
641 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
642 mov 1, %g3
643 sllx %g3, SFAFSR_UE_SHIFT, %g3
644 andcc %g4, %g3, %g0 ! Check for UE
645 bne,pn %xcc, __spitfire_access_error
646 nop
647
648 /* Ok, in this case we only have a correctable error.
649 * Indicate we only wish to capture that state in register
650 * %g1, and we only disable CE error reporting unlike UE
651 * handling which disables all errors.
652 */
653 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
654 andn %g3, ESTATE_ERR_CE, %g3
655 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
656 membar #Sync
657
658 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
659 ba,pt %xcc, __spitfire_cee_trap_continue
660 mov UDBE_CE, %g1
661
662 .globl __spitfire_data_access_exception
663 .globl __spitfire_data_access_exception_tl1
664__spitfire_data_access_exception_tl1:
665 rdpr %pstate, %g4
666 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
667 mov TLB_SFSR, %g3
668 mov DMMU_SFAR, %g5
669 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
670 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
671 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
672 membar #Sync
673 rdpr %tt, %g3
674 cmp %g3, 0x80 ! first win spill/fill trap
675 blu,pn %xcc, 1f
676 cmp %g3, 0xff ! last win spill/fill trap
677 bgu,pn %xcc, 1f
678 nop
679 ba,pt %xcc, winfix_dax
680 rdpr %tpc, %g3
6811: sethi %hi(109f), %g7
682 ba,pt %xcc, etraptl1
683109: or %g7, %lo(109b), %g7
684 mov %l4, %o1
685 mov %l5, %o2
686 call spitfire_data_access_exception_tl1
687 add %sp, PTREGS_OFF, %o0
688 ba,pt %xcc, rtrap
689 nop
690
691__spitfire_data_access_exception:
692 rdpr %pstate, %g4
693 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
694 mov TLB_SFSR, %g3
695 mov DMMU_SFAR, %g5
696 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
697 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
698 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
699 membar #Sync
700 sethi %hi(109f), %g7
701 ba,pt %xcc, etrap
702109: or %g7, %lo(109b), %g7
703 mov %l4, %o1
704 mov %l5, %o2
705 call spitfire_data_access_exception
706 add %sp, PTREGS_OFF, %o0
707 ba,pt %xcc, rtrap
708 nop
709
710 .globl __spitfire_insn_access_exception
711 .globl __spitfire_insn_access_exception_tl1
712__spitfire_insn_access_exception_tl1:
713 rdpr %pstate, %g4
714 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
715 mov TLB_SFSR, %g3
716 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
717 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
718 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
719 membar #Sync
720 sethi %hi(109f), %g7
721 ba,pt %xcc, etraptl1
722109: or %g7, %lo(109b), %g7
723 mov %l4, %o1
724 mov %l5, %o2
725 call spitfire_insn_access_exception_tl1
726 add %sp, PTREGS_OFF, %o0
727 ba,pt %xcc, rtrap
728 nop
729
730__spitfire_insn_access_exception:
731 rdpr %pstate, %g4
732 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
733 mov TLB_SFSR, %g3
734 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
735 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
736 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
737 membar #Sync
738 sethi %hi(109f), %g7
739 ba,pt %xcc, etrap
740109: or %g7, %lo(109b), %g7
741 mov %l4, %o1
742 mov %l5, %o2
743 call spitfire_insn_access_exception
744 add %sp, PTREGS_OFF, %o0
745 ba,pt %xcc, rtrap
746 nop
747
748 /* These get patched into the trap table at boot time
749 * once we know we have a cheetah processor.
750 */
751 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
752cheetah_fecc_trap_vector:
753 membar #Sync
754 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
755 andn %g1, DCU_DC | DCU_IC, %g1
756 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
757 membar #Sync
758 sethi %hi(cheetah_fast_ecc), %g2
759 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
760 mov 0, %g1
761cheetah_fecc_trap_vector_tl1:
762 membar #Sync
763 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
764 andn %g1, DCU_DC | DCU_IC, %g1
765 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
766 membar #Sync
767 sethi %hi(cheetah_fast_ecc), %g2
768 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
769 mov 1, %g1
770 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
771cheetah_cee_trap_vector:
772 membar #Sync
773 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
774 andn %g1, DCU_IC, %g1
775 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
776 membar #Sync
777 sethi %hi(cheetah_cee), %g2
778 jmpl %g2 + %lo(cheetah_cee), %g0
779 mov 0, %g1
780cheetah_cee_trap_vector_tl1:
781 membar #Sync
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 membar #Sync
786 sethi %hi(cheetah_cee), %g2
787 jmpl %g2 + %lo(cheetah_cee), %g0
788 mov 1, %g1
789 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
790cheetah_deferred_trap_vector:
791 membar #Sync
792 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
793 andn %g1, DCU_DC | DCU_IC, %g1;
794 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
795 membar #Sync;
796 sethi %hi(cheetah_deferred_trap), %g2
797 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
798 mov 0, %g1
799cheetah_deferred_trap_vector_tl1:
800 membar #Sync;
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
802 andn %g1, DCU_DC | DCU_IC, %g1;
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
804 membar #Sync;
805 sethi %hi(cheetah_deferred_trap), %g2
806 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
807 mov 1, %g1
808
809 /* Cheetah+ specific traps. These are for the new I/D cache parity
810 * error traps. The first argument to cheetah_plus_parity_handler
811 * is encoded as follows:
812 *
813 * Bit0: 0=dcache,1=icache
814 * Bit1: 0=recoverable,1=unrecoverable
815 */
816 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
817cheetah_plus_dcpe_trap_vector:
818 membar #Sync
819 sethi %hi(do_cheetah_plus_data_parity), %g7
820 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
821 nop
822 nop
823 nop
824 nop
825 nop
826
827do_cheetah_plus_data_parity:
828 rdpr %pil, %g2
829 wrpr %g0, 15, %pil
830 ba,pt %xcc, etrap_irq
831 rd %pc, %g7
832#ifdef CONFIG_TRACE_IRQFLAGS
833 call trace_hardirqs_off
834 nop
835#endif
836 mov 0x0, %o0
837 call cheetah_plus_parity_error
838 add %sp, PTREGS_OFF, %o1
839 ba,a,pt %xcc, rtrap_irq
840
841cheetah_plus_dcpe_trap_vector_tl1:
842 membar #Sync
843 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
844 sethi %hi(do_dcpe_tl1), %g3
845 jmpl %g3 + %lo(do_dcpe_tl1), %g0
846 nop
847 nop
848 nop
849 nop
850
851 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
852cheetah_plus_icpe_trap_vector:
853 membar #Sync
854 sethi %hi(do_cheetah_plus_insn_parity), %g7
855 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
856 nop
857 nop
858 nop
859 nop
860 nop
861
862do_cheetah_plus_insn_parity:
863 rdpr %pil, %g2
864 wrpr %g0, 15, %pil
865 ba,pt %xcc, etrap_irq
866 rd %pc, %g7
867#ifdef CONFIG_TRACE_IRQFLAGS
868 call trace_hardirqs_off
869 nop
870#endif
871 mov 0x1, %o0
872 call cheetah_plus_parity_error
873 add %sp, PTREGS_OFF, %o1
874 ba,a,pt %xcc, rtrap_irq
875
876cheetah_plus_icpe_trap_vector_tl1:
877 membar #Sync
878 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
879 sethi %hi(do_icpe_tl1), %g3
880 jmpl %g3 + %lo(do_icpe_tl1), %g0
881 nop
882 nop
883 nop
884 nop
885
886 /* If we take one of these traps when tl >= 1, then we
887 * jump to interrupt globals. If some trap level above us
888 * was also using interrupt globals, we cannot recover.
889 * We may use all interrupt global registers except %g6.
890 */
891 .globl do_dcpe_tl1, do_icpe_tl1
892do_dcpe_tl1:
893 rdpr %tl, %g1 ! Save original trap level
894 mov 1, %g2 ! Setup TSTATE checking loop
895 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
8961: wrpr %g2, %tl ! Set trap level to check
897 rdpr %tstate, %g4 ! Read TSTATE for this level
898 andcc %g4, %g3, %g0 ! Interrupt globals in use?
899 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
900 wrpr %g1, %tl ! Restore original trap level
901 add %g2, 1, %g2 ! Next trap level
902 cmp %g2, %g1 ! Hit them all yet?
903 ble,pt %icc, 1b ! Not yet
904 nop
905 wrpr %g1, %tl ! Restore original trap level
906do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
907 sethi %hi(dcache_parity_tl1_occurred), %g2
908 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
909 add %g1, 1, %g1
910 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
911 /* Reset D-cache parity */
912 sethi %hi(1 << 16), %g1 ! D-cache size
913 mov (1 << 5), %g2 ! D-cache line size
914 sub %g1, %g2, %g1 ! Move down 1 cacheline
9151: srl %g1, 14, %g3 ! Compute UTAG
916 membar #Sync
917 stxa %g3, [%g1] ASI_DCACHE_UTAG
918 membar #Sync
919 sub %g2, 8, %g3 ! 64-bit data word within line
9202: membar #Sync
921 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
922 membar #Sync
923 subcc %g3, 8, %g3 ! Next 64-bit data word
924 bge,pt %icc, 2b
925 nop
926 subcc %g1, %g2, %g1 ! Next cacheline
927 bge,pt %icc, 1b
928 nop
929 ba,pt %xcc, dcpe_icpe_tl1_common
930 nop
931
932do_dcpe_tl1_fatal:
933 sethi %hi(1f), %g7
934 ba,pt %xcc, etraptl1
9351: or %g7, %lo(1b), %g7
936 mov 0x2, %o0
937 call cheetah_plus_parity_error
938 add %sp, PTREGS_OFF, %o1
939 ba,pt %xcc, rtrap
940 nop
941
942do_icpe_tl1:
943 rdpr %tl, %g1 ! Save original trap level
944 mov 1, %g2 ! Setup TSTATE checking loop
945 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
9461: wrpr %g2, %tl ! Set trap level to check
947 rdpr %tstate, %g4 ! Read TSTATE for this level
948 andcc %g4, %g3, %g0 ! Interrupt globals in use?
949 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
950 wrpr %g1, %tl ! Restore original trap level
951 add %g2, 1, %g2 ! Next trap level
952 cmp %g2, %g1 ! Hit them all yet?
953 ble,pt %icc, 1b ! Not yet
954 nop
955 wrpr %g1, %tl ! Restore original trap level
956do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
957 sethi %hi(icache_parity_tl1_occurred), %g2
958 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
959 add %g1, 1, %g1
960 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
961 /* Flush I-cache */
962 sethi %hi(1 << 15), %g1 ! I-cache size
963 mov (1 << 5), %g2 ! I-cache line size
964 sub %g1, %g2, %g1
9651: or %g1, (2 << 3), %g3
966 stxa %g0, [%g3] ASI_IC_TAG
967 membar #Sync
968 subcc %g1, %g2, %g1
969 bge,pt %icc, 1b
970 nop
971 ba,pt %xcc, dcpe_icpe_tl1_common
972 nop
973
974do_icpe_tl1_fatal:
975 sethi %hi(1f), %g7
976 ba,pt %xcc, etraptl1
9771: or %g7, %lo(1b), %g7
978 mov 0x3, %o0
979 call cheetah_plus_parity_error
980 add %sp, PTREGS_OFF, %o1
981 ba,pt %xcc, rtrap
982 nop
983
984dcpe_icpe_tl1_common:
985 /* Flush D-cache, re-enable D/I caches in DCU and finally
986 * retry the trapping instruction.
987 */
988 sethi %hi(1 << 16), %g1 ! D-cache size
989 mov (1 << 5), %g2 ! D-cache line size
990 sub %g1, %g2, %g1
9911: stxa %g0, [%g1] ASI_DCACHE_TAG
992 membar #Sync
993 subcc %g1, %g2, %g1
994 bge,pt %icc, 1b
995 nop
996 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
997 or %g1, (DCU_DC | DCU_IC), %g1
998 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
999 membar #Sync
1000 retry
1001
1002 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1003 *
1004 * %g1: (TL>=0) ? 1 : 0
1005 * %g2: scratch
1006 * %g3: scratch
1007 * %g4: AFSR
1008 * %g5: AFAR
1009 * %g6: unused, will have current thread ptr after etrap
1010 * %g7: scratch
1011 */
1012__cheetah_log_error:
1013 /* Put "TL1" software bit into AFSR. */
1014 and %g1, 0x1, %g1
1015 sllx %g1, 63, %g2
1016 or %g4, %g2, %g4
1017
1018 /* Get log entry pointer for this cpu at this trap level. */
1019 BRANCH_IF_JALAPENO(g2,g3,50f)
1020 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1021 srlx %g2, 17, %g2
1022 ba,pt %xcc, 60f
1023 and %g2, 0x3ff, %g2
1024
102550: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1026 srlx %g2, 17, %g2
1027 and %g2, 0x1f, %g2
1028
102960: sllx %g2, 9, %g2
1030 sethi %hi(cheetah_error_log), %g3
1031 ldx [%g3 + %lo(cheetah_error_log)], %g3
1032 brz,pn %g3, 80f
1033 nop
1034
1035 add %g3, %g2, %g3
1036 sllx %g1, 8, %g1
1037 add %g3, %g1, %g1
1038
1039 /* %g1 holds pointer to the top of the logging scoreboard */
1040 ldx [%g1 + 0x0], %g7
1041 cmp %g7, -1
1042 bne,pn %xcc, 80f
1043 nop
1044
1045 stx %g4, [%g1 + 0x0]
1046 stx %g5, [%g1 + 0x8]
1047 add %g1, 0x10, %g1
1048
1049 /* %g1 now points to D-cache logging area */
1050 set 0x3ff8, %g2 /* DC_addr mask */
1051 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1052 srlx %g5, 12, %g3
1053 or %g3, 1, %g3 /* PHYS tag + valid */
1054
105510: ldxa [%g2] ASI_DCACHE_TAG, %g7
1056 cmp %g3, %g7 /* TAG match? */
1057 bne,pt %xcc, 13f
1058 nop
1059
1060 /* Yep, what we want, capture state. */
1061 stx %g2, [%g1 + 0x20]
1062 stx %g7, [%g1 + 0x28]
1063
1064 /* A membar Sync is required before and after utag access. */
1065 membar #Sync
1066 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1067 membar #Sync
1068 stx %g7, [%g1 + 0x30]
1069 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1070 stx %g7, [%g1 + 0x38]
1071 clr %g3
1072
107312: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1074 stx %g7, [%g1]
1075 add %g3, (1 << 5), %g3
1076 cmp %g3, (4 << 5)
1077 bl,pt %xcc, 12b
1078 add %g1, 0x8, %g1
1079
1080 ba,pt %xcc, 20f
1081 add %g1, 0x20, %g1
1082
108313: sethi %hi(1 << 14), %g7
1084 add %g2, %g7, %g2
1085 srlx %g2, 14, %g7
1086 cmp %g7, 4
1087 bl,pt %xcc, 10b
1088 nop
1089
1090 add %g1, 0x40, %g1
1091
1092 /* %g1 now points to I-cache logging area */
109320: set 0x1fe0, %g2 /* IC_addr mask */
1094 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1095 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1096 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1097 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1098
109921: ldxa [%g2] ASI_IC_TAG, %g7
1100 andn %g7, 0xff, %g7
1101 cmp %g3, %g7
1102 bne,pt %xcc, 23f
1103 nop
1104
1105 /* Yep, what we want, capture state. */
1106 stx %g2, [%g1 + 0x40]
1107 stx %g7, [%g1 + 0x48]
1108 add %g2, (1 << 3), %g2
1109 ldxa [%g2] ASI_IC_TAG, %g7
1110 add %g2, (1 << 3), %g2
1111 stx %g7, [%g1 + 0x50]
1112 ldxa [%g2] ASI_IC_TAG, %g7
1113 add %g2, (1 << 3), %g2
1114 stx %g7, [%g1 + 0x60]
1115 ldxa [%g2] ASI_IC_TAG, %g7
1116 stx %g7, [%g1 + 0x68]
1117 sub %g2, (3 << 3), %g2
1118 ldxa [%g2] ASI_IC_STAG, %g7
1119 stx %g7, [%g1 + 0x58]
1120 clr %g3
1121 srlx %g2, 2, %g2
1122
112322: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1124 stx %g7, [%g1]
1125 add %g3, (1 << 3), %g3
1126 cmp %g3, (8 << 3)
1127 bl,pt %xcc, 22b
1128 add %g1, 0x8, %g1
1129
1130 ba,pt %xcc, 30f
1131 add %g1, 0x30, %g1
1132
113323: sethi %hi(1 << 14), %g7
1134 add %g2, %g7, %g2
1135 srlx %g2, 14, %g7
1136 cmp %g7, 4
1137 bl,pt %xcc, 21b
1138 nop
1139
1140 add %g1, 0x70, %g1
1141
1142 /* %g1 now points to E-cache logging area */
114330: andn %g5, (32 - 1), %g2
1144 stx %g2, [%g1 + 0x20]
1145 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1146 stx %g7, [%g1 + 0x28]
1147 ldxa [%g2] ASI_EC_R, %g0
1148 clr %g3
1149
115031: ldxa [%g3] ASI_EC_DATA, %g7
1151 stx %g7, [%g1 + %g3]
1152 add %g3, 0x8, %g3
1153 cmp %g3, 0x20
1154
1155 bl,pt %xcc, 31b
1156 nop
115780:
1158 rdpr %tt, %g2
1159 cmp %g2, 0x70
1160 be c_fast_ecc
1161 cmp %g2, 0x63
1162 be c_cee
1163 nop
1164 ba,pt %xcc, c_deferred
1165
1166 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1167 * in the trap table. That code has done a memory barrier
1168 * and has disabled both the I-cache and D-cache in the DCU
1169 * control register. The I-cache is disabled so that we may
1170 * capture the corrupted cache line, and the D-cache is disabled
1171 * because corrupt data may have been placed there and we don't
1172 * want to reference it.
1173 *
1174 * %g1 is one if this trap occurred at %tl >= 1.
1175 *
1176 * Next, we turn off error reporting so that we don't recurse.
1177 */
1178 .globl cheetah_fast_ecc
1179cheetah_fast_ecc:
1180 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1181 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1182 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1183 membar #Sync
1184
1185 /* Fetch and clear AFSR/AFAR */
1186 ldxa [%g0] ASI_AFSR, %g4
1187 ldxa [%g0] ASI_AFAR, %g5
1188 stxa %g4, [%g0] ASI_AFSR
1189 membar #Sync
1190
1191 ba,pt %xcc, __cheetah_log_error
1192 nop
1193
1194c_fast_ecc:
1195 rdpr %pil, %g2
1196 wrpr %g0, 15, %pil
1197 ba,pt %xcc, etrap_irq
1198 rd %pc, %g7
1199#ifdef CONFIG_TRACE_IRQFLAGS
1200 call trace_hardirqs_off
1201 nop
1202#endif
1203 mov %l4, %o1
1204 mov %l5, %o2
1205 call cheetah_fecc_handler
1206 add %sp, PTREGS_OFF, %o0
1207 ba,a,pt %xcc, rtrap_irq
1208
1209 /* Our caller has disabled I-cache and performed membar Sync. */
1210 .globl cheetah_cee
1211cheetah_cee:
1212 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1213 andn %g2, ESTATE_ERROR_CEEN, %g2
1214 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1215 membar #Sync
1216
1217 /* Fetch and clear AFSR/AFAR */
1218 ldxa [%g0] ASI_AFSR, %g4
1219 ldxa [%g0] ASI_AFAR, %g5
1220 stxa %g4, [%g0] ASI_AFSR
1221 membar #Sync
1222
1223 ba,pt %xcc, __cheetah_log_error
1224 nop
1225
1226c_cee:
1227 rdpr %pil, %g2
1228 wrpr %g0, 15, %pil
1229 ba,pt %xcc, etrap_irq
1230 rd %pc, %g7
1231#ifdef CONFIG_TRACE_IRQFLAGS
1232 call trace_hardirqs_off
1233 nop
1234#endif
1235 mov %l4, %o1
1236 mov %l5, %o2
1237 call cheetah_cee_handler
1238 add %sp, PTREGS_OFF, %o0
1239 ba,a,pt %xcc, rtrap_irq
1240
1241 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1242 .globl cheetah_deferred_trap
1243cheetah_deferred_trap:
1244 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1245 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1246 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1247 membar #Sync
1248
1249 /* Fetch and clear AFSR/AFAR */
1250 ldxa [%g0] ASI_AFSR, %g4
1251 ldxa [%g0] ASI_AFAR, %g5
1252 stxa %g4, [%g0] ASI_AFSR
1253 membar #Sync
1254
1255 ba,pt %xcc, __cheetah_log_error
1256 nop
1257
1258c_deferred:
1259 rdpr %pil, %g2
1260 wrpr %g0, 15, %pil
1261 ba,pt %xcc, etrap_irq
1262 rd %pc, %g7
1263#ifdef CONFIG_TRACE_IRQFLAGS
1264 call trace_hardirqs_off
1265 nop
1266#endif
1267 mov %l4, %o1
1268 mov %l5, %o2
1269 call cheetah_deferred_handler
1270 add %sp, PTREGS_OFF, %o0
1271 ba,a,pt %xcc, rtrap_irq
1272
1273 .globl __do_privact
1274__do_privact:
1275 mov TLB_SFSR, %g3
1276 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1277 membar #Sync
1278 sethi %hi(109f), %g7
1279 ba,pt %xcc, etrap
1280109: or %g7, %lo(109b), %g7
1281 call do_privact
1282 add %sp, PTREGS_OFF, %o0
1283 ba,pt %xcc, rtrap
1284 nop
1285
1286 .globl do_mna
1287do_mna:
1288 rdpr %tl, %g3
1289 cmp %g3, 1
1290
1291 /* Setup %g4/%g5 now as they are used in the
1292 * winfixup code.
1293 */
1294 mov TLB_SFSR, %g3
1295 mov DMMU_SFAR, %g4
1296 ldxa [%g4] ASI_DMMU, %g4
1297 ldxa [%g3] ASI_DMMU, %g5
1298 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1299 membar #Sync
1300 bgu,pn %icc, winfix_mna
1301 rdpr %tpc, %g3
1302
13031: sethi %hi(109f), %g7
1304 ba,pt %xcc, etrap
1305109: or %g7, %lo(109b), %g7
1306 mov %l4, %o1
1307 mov %l5, %o2
1308 call mem_address_unaligned
1309 add %sp, PTREGS_OFF, %o0
1310 ba,pt %xcc, rtrap
1311 nop
1312
1313 .globl do_lddfmna
1314do_lddfmna:
1315 sethi %hi(109f), %g7
1316 mov TLB_SFSR, %g4
1317 ldxa [%g4] ASI_DMMU, %g5
1318 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1319 membar #Sync
1320 mov DMMU_SFAR, %g4
1321 ldxa [%g4] ASI_DMMU, %g4
1322 ba,pt %xcc, etrap
1323109: or %g7, %lo(109b), %g7
1324 mov %l4, %o1
1325 mov %l5, %o2
1326 call handle_lddfmna
1327 add %sp, PTREGS_OFF, %o0
1328 ba,pt %xcc, rtrap
1329 nop
1330
1331 .globl do_stdfmna
1332do_stdfmna:
1333 sethi %hi(109f), %g7
1334 mov TLB_SFSR, %g4
1335 ldxa [%g4] ASI_DMMU, %g5
1336 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1337 membar #Sync
1338 mov DMMU_SFAR, %g4
1339 ldxa [%g4] ASI_DMMU, %g4
1340 ba,pt %xcc, etrap
1341109: or %g7, %lo(109b), %g7
1342 mov %l4, %o1
1343 mov %l5, %o2
1344 call handle_stdfmna
1345 add %sp, PTREGS_OFF, %o0
1346 ba,pt %xcc, rtrap
1347 nop
1348
1349 .globl breakpoint_trap
1350breakpoint_trap:
1351 call sparc_breakpoint
1352 add %sp, PTREGS_OFF, %o0
1353 ba,pt %xcc, rtrap
1354 nop
1355
1356 /* SunOS's execv() call only specifies the argv argument, the
1357 * environment settings are the same as the calling processes.
1358 */
1359 .globl sunos_execv
1360sys_execve:
1361 sethi %hi(sparc_execve), %g1
1362 ba,pt %xcc, execve_merge
1363 or %g1, %lo(sparc_execve), %g1
1364#ifdef CONFIG_COMPAT
1365 .globl sys_execve
1366sunos_execv:
1367 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1368 .globl sys32_execve
1369sys32_execve:
1370 sethi %hi(sparc32_execve), %g1
1371 or %g1, %lo(sparc32_execve), %g1
1372#endif
1373execve_merge:
1374 flushw
1375 jmpl %g1, %g0
1376 add %sp, PTREGS_OFF, %o0
1377
1378 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1379 .globl sys_rt_sigreturn
1380 .globl sys_ptrace
1381 .globl sys_sigaltstack
1382 .align 32
1383sys_pipe: ba,pt %xcc, sparc_pipe
1384 add %sp, PTREGS_OFF, %o0
1385sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1386 add %sp, PTREGS_OFF, %o0
1387sys_memory_ordering:
1388 ba,pt %xcc, sparc_memory_ordering
1389 add %sp, PTREGS_OFF, %o1
1390sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1391 add %i6, STACK_BIAS, %o2
1392#ifdef CONFIG_COMPAT
1393 .globl sys32_sigstack
1394sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1395 mov %i6, %o2
1396 .globl sys32_sigaltstack
1397sys32_sigaltstack:
1398 ba,pt %xcc, do_sys32_sigaltstack
1399 mov %i6, %o2
1400#endif
1401 .align 32
1402#ifdef CONFIG_COMPAT
1403 .globl sys32_sigreturn
1404sys32_sigreturn:
1405 add %sp, PTREGS_OFF, %o0
1406 call do_sigreturn32
1407 add %o7, 1f-.-4, %o7
1408 nop
1409#endif
1410sys_rt_sigreturn:
1411 add %sp, PTREGS_OFF, %o0
1412 call do_rt_sigreturn
1413 add %o7, 1f-.-4, %o7
1414 nop
1415#ifdef CONFIG_COMPAT
1416 .globl sys32_rt_sigreturn
1417sys32_rt_sigreturn:
1418 add %sp, PTREGS_OFF, %o0
1419 call do_rt_sigreturn32
1420 add %o7, 1f-.-4, %o7
1421 nop
1422#endif
1423 .align 32
14241: ldx [%curptr + TI_FLAGS], %l5
1425 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1426 be,pt %icc, rtrap
1427 nop
1428 add %sp, PTREGS_OFF, %o0
1429 call syscall_trace
1430 mov 1, %o1
1431
1432 ba,pt %xcc, rtrap
1433 nop
1434
1435 /* This is how fork() was meant to be done, 8 instruction entry.
1436 *
1437 * I questioned the following code briefly, let me clear things
1438 * up so you must not reason on it like I did.
1439 *
1440 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1441 * need it here because the only piece of window state we copy to
1442 * the child is the CWP register. Even if the parent sleeps,
1443 * we are safe because we stuck it into pt_regs of the parent
1444 * so it will not change.
1445 *
1446 * XXX This raises the question, whether we can do the same on
1447 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1448 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1449 * XXX fork_kwim in UREG_G1 (global registers are considered
1450 * XXX volatile across a system call in the sparc ABI I think
1451 * XXX if it isn't we can use regs->y instead, anyone who depends
1452 * XXX upon the Y register being preserved across a fork deserves
1453 * XXX to lose).
1454 *
1455 * In fact we should take advantage of that fact for other things
1456 * during system calls...
1457 */
1458 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1459 .globl ret_from_syscall
1460 .align 32
1461sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1462 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1463 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1464 ba,pt %xcc, sys_clone
1465sys_fork: clr %o1
1466 mov SIGCHLD, %o0
1467sys_clone: flushw
1468 movrz %o1, %fp, %o1
1469 mov 0, %o3
1470 ba,pt %xcc, sparc_do_fork
1471 add %sp, PTREGS_OFF, %o2
1472ret_from_syscall:
1473 /* Clear current_thread_info()->new_child, and
1474 * check performance counter stuff too.
1475 */
1476 stb %g0, [%g6 + TI_NEW_CHILD]
1477 ldx [%g6 + TI_FLAGS], %l0
1478 call schedule_tail
1479 mov %g7, %o0
1480 andcc %l0, _TIF_PERFCTR, %g0
1481 be,pt %icc, 1f
1482 nop
1483 ldx [%g6 + TI_PCR], %o7
1484 wr %g0, %o7, %pcr
1485
1486 /* Blackbird errata workaround. See commentary in
1487 * smp.c:smp_percpu_timer_interrupt() for more
1488 * information.
1489 */
1490 ba,pt %xcc, 99f
1491 nop
1492 .align 64
149399: wr %g0, %g0, %pic
1494 rd %pic, %g0
1495
14961: b,pt %xcc, ret_sys_call
1497 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1498sparc_exit: rdpr %pstate, %g2
1499 wrpr %g2, PSTATE_IE, %pstate
1500 rdpr %otherwin, %g1
1501 rdpr %cansave, %g3
1502 add %g3, %g1, %g3
1503 wrpr %g3, 0x0, %cansave
1504 wrpr %g0, 0x0, %otherwin
1505 wrpr %g2, 0x0, %pstate
1506 ba,pt %xcc, sys_exit
1507 stb %g0, [%g6 + TI_WSAVED]
1508
1509linux_sparc_ni_syscall:
1510 sethi %hi(sys_ni_syscall), %l7
1511 b,pt %xcc, 4f
1512 or %l7, %lo(sys_ni_syscall), %l7
1513
1514linux_syscall_trace32:
1515 add %sp, PTREGS_OFF, %o0
1516 call syscall_trace
1517 clr %o1
1518 srl %i0, 0, %o0
1519 srl %i4, 0, %o4
1520 srl %i1, 0, %o1
1521 srl %i2, 0, %o2
1522 b,pt %xcc, 2f
1523 srl %i3, 0, %o3
1524
1525linux_syscall_trace:
1526 add %sp, PTREGS_OFF, %o0
1527 call syscall_trace
1528 clr %o1
1529 mov %i0, %o0
1530 mov %i1, %o1
1531 mov %i2, %o2
1532 mov %i3, %o3
1533 b,pt %xcc, 2f
1534 mov %i4, %o4
1535
1536
1537 /* Linux 32-bit system calls enter here... */
1538 .align 32
1539 .globl linux_sparc_syscall32
1540linux_sparc_syscall32:
1541 /* Direct access to user regs, much faster. */
1542 cmp %g1, NR_SYSCALLS ! IEU1 Group
1543 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1544 srl %i0, 0, %o0 ! IEU0
1545 sll %g1, 2, %l4 ! IEU0 Group
1546 srl %i4, 0, %o4 ! IEU1
1547 lduw [%l7 + %l4], %l7 ! Load
1548 srl %i1, 0, %o1 ! IEU0 Group
1549 ldx [%curptr + TI_FLAGS], %l0 ! Load
1550
1551 srl %i5, 0, %o5 ! IEU1
1552 srl %i2, 0, %o2 ! IEU0 Group
1553 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1554 bne,pn %icc, linux_syscall_trace32 ! CTI
1555 mov %i0, %l5 ! IEU1
1556 call %l7 ! CTI Group brk forced
1557 srl %i3, 0, %o3 ! IEU0
1558 ba,a,pt %xcc, 3f
1559
1560 /* Linux native system calls enter here... */
1561 .align 32
1562 .globl linux_sparc_syscall
1563linux_sparc_syscall:
1564 /* Direct access to user regs, much faster. */
1565 cmp %g1, NR_SYSCALLS ! IEU1 Group
1566 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1567 mov %i0, %o0 ! IEU0
1568 sll %g1, 2, %l4 ! IEU0 Group
1569 mov %i1, %o1 ! IEU1
1570 lduw [%l7 + %l4], %l7 ! Load
15714: mov %i2, %o2 ! IEU0 Group
1572 ldx [%curptr + TI_FLAGS], %l0 ! Load
1573
1574 mov %i3, %o3 ! IEU1
1575 mov %i4, %o4 ! IEU0 Group
1576 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1577 bne,pn %icc, linux_syscall_trace ! CTI Group
1578 mov %i0, %l5 ! IEU0
15792: call %l7 ! CTI Group brk forced
1580 mov %i5, %o5 ! IEU0
1581 nop
1582
15833: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1584ret_sys_call:
1585 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1586 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1587 sra %o0, 0, %o0
1588 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1589 sllx %g2, 32, %g2
1590
1591 /* Check if force_successful_syscall_return()
1592 * was invoked.
1593 */
1594 ldub [%curptr + TI_SYS_NOERROR], %l2
1595 brnz,a,pn %l2, 80f
1596 stb %g0, [%curptr + TI_SYS_NOERROR]
1597
1598 cmp %o0, -ERESTART_RESTARTBLOCK
1599 bgeu,pn %xcc, 1f
1600 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
160180:
1602 /* System call success, clear Carry condition code. */
1603 andn %g3, %g2, %g3
1604 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1605 bne,pn %icc, linux_syscall_trace2
1606 add %l1, 0x4, %l2 ! npc = npc+4
1607 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1608 ba,pt %xcc, rtrap
1609 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1610
16111:
1612 /* System call failure, set Carry condition code.
1613 * Also, get abs(errno) to return to the process.
1614 */
1615 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1616 sub %g0, %o0, %o0
1617 or %g3, %g2, %g3
1618 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1619 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1620 bne,pn %icc, linux_syscall_trace2
1621 add %l1, 0x4, %l2 ! npc = npc+4
1622 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1623
1624 b,pt %xcc, rtrap
1625 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1626linux_syscall_trace2:
1627 add %sp, PTREGS_OFF, %o0
1628 call syscall_trace
1629 mov 1, %o1
1630 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1631 ba,pt %xcc, rtrap
1632 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1633
1634 .align 32
1635 .globl __flushw_user
1636__flushw_user:
1637 rdpr %otherwin, %g1
1638 brz,pn %g1, 2f
1639 clr %g2
16401: save %sp, -128, %sp
1641 rdpr %otherwin, %g1
1642 brnz,pt %g1, 1b
1643 add %g2, 1, %g2
16441: sub %g2, 1, %g2
1645 brnz,pt %g2, 1b
1646 restore %g0, %g0, %g0
16472: retl
1648 nop
1649
1650 /* Flush %fp and %i7 to the stack for all register
1651 * windows active inside of the cpu. This allows
1652 * show_stack_trace() to avoid using an expensive
1653 * 'flushw'.
1654 */
1655 .globl stack_trace_flush
1656 .type stack_trace_flush,#function
1657stack_trace_flush:
1658 rdpr %pstate, %o0
1659 wrpr %o0, PSTATE_IE, %pstate
1660
1661 rdpr %cwp, %g1
1662 rdpr %canrestore, %g2
1663 sub %g1, 1, %g3
1664
16651: brz,pn %g2, 2f
1666 sub %g2, 1, %g2
1667 wrpr %g3, %cwp
1668 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
1669 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
1670 ba,pt %xcc, 1b
1671 sub %g3, 1, %g3
1672
16732: wrpr %g1, %cwp
1674 wrpr %o0, %pstate
1675
1676 retl
1677 nop
1678 .size stack_trace_flush,.-stack_trace_flush
1679
1680#ifdef CONFIG_SMP
1681 .globl hard_smp_processor_id
1682hard_smp_processor_id:
1683#endif
1684 .globl real_hard_smp_processor_id
1685real_hard_smp_processor_id:
1686 __GET_CPUID(%o0)
1687 retl
1688 nop
1689
1690 /* %o0: devhandle
1691 * %o1: devino
1692 *
1693 * returns %o0: sysino
1694 */
1695 .globl sun4v_devino_to_sysino
1696 .type sun4v_devino_to_sysino,#function
1697sun4v_devino_to_sysino:
1698 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
1699 ta HV_FAST_TRAP
1700 retl
1701 mov %o1, %o0
1702 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino
1703
1704 /* %o0: sysino
1705 *
1706 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1707 */
1708 .globl sun4v_intr_getenabled
1709 .type sun4v_intr_getenabled,#function
1710sun4v_intr_getenabled:
1711 mov HV_FAST_INTR_GETENABLED, %o5
1712 ta HV_FAST_TRAP
1713 retl
1714 mov %o1, %o0
1715 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled
1716
1717 /* %o0: sysino
1718 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1719 */
1720 .globl sun4v_intr_setenabled
1721 .type sun4v_intr_setenabled,#function
1722sun4v_intr_setenabled:
1723 mov HV_FAST_INTR_SETENABLED, %o5
1724 ta HV_FAST_TRAP
1725 retl
1726 nop
1727 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled
1728
1729 /* %o0: sysino
1730 *
1731 * returns %o0: intr_state (HV_INTR_STATE_*)
1732 */
1733 .globl sun4v_intr_getstate
1734 .type sun4v_intr_getstate,#function
1735sun4v_intr_getstate:
1736 mov HV_FAST_INTR_GETSTATE, %o5
1737 ta HV_FAST_TRAP
1738 retl
1739 mov %o1, %o0
1740 .size sun4v_intr_getstate, .-sun4v_intr_getstate
1741
1742 /* %o0: sysino
1743 * %o1: intr_state (HV_INTR_STATE_*)
1744 */
1745 .globl sun4v_intr_setstate
1746 .type sun4v_intr_setstate,#function
1747sun4v_intr_setstate:
1748 mov HV_FAST_INTR_SETSTATE, %o5
1749 ta HV_FAST_TRAP
1750 retl
1751 nop
1752 .size sun4v_intr_setstate, .-sun4v_intr_setstate
1753
1754 /* %o0: sysino
1755 *
1756 * returns %o0: cpuid
1757 */
1758 .globl sun4v_intr_gettarget
1759 .type sun4v_intr_gettarget,#function
1760sun4v_intr_gettarget:
1761 mov HV_FAST_INTR_GETTARGET, %o5
1762 ta HV_FAST_TRAP
1763 retl
1764 mov %o1, %o0
1765 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget
1766
1767 /* %o0: sysino
1768 * %o1: cpuid
1769 */
1770 .globl sun4v_intr_settarget
1771 .type sun4v_intr_settarget,#function
1772sun4v_intr_settarget:
1773 mov HV_FAST_INTR_SETTARGET, %o5
1774 ta HV_FAST_TRAP
1775 retl
1776 nop
1777 .size sun4v_intr_settarget, .-sun4v_intr_settarget
1778
1779 /* %o0: cpuid
1780 * %o1: pc
1781 * %o2: rtba
1782 * %o3: arg0
1783 *
1784 * returns %o0: status
1785 */
1786 .globl sun4v_cpu_start
1787 .type sun4v_cpu_start,#function
1788sun4v_cpu_start:
1789 mov HV_FAST_CPU_START, %o5
1790 ta HV_FAST_TRAP
1791 retl
1792 nop
1793 .size sun4v_cpu_start, .-sun4v_cpu_start
1794
1795 /* %o0: cpuid
1796 *
1797 * returns %o0: status
1798 */
1799 .globl sun4v_cpu_stop
1800 .type sun4v_cpu_stop,#function
1801sun4v_cpu_stop:
1802 mov HV_FAST_CPU_STOP, %o5
1803 ta HV_FAST_TRAP
1804 retl
1805 nop
1806 .size sun4v_cpu_stop, .-sun4v_cpu_stop
1807
1808 /* returns %o0: status */
1809 .globl sun4v_cpu_yield
1810 .type sun4v_cpu_yield, #function
1811sun4v_cpu_yield:
1812 mov HV_FAST_CPU_YIELD, %o5
1813 ta HV_FAST_TRAP
1814 retl
1815 nop
1816 .size sun4v_cpu_yield, .-sun4v_cpu_yield
1817
1818 /* %o0: type
1819 * %o1: queue paddr
1820 * %o2: num queue entries
1821 *
1822 * returns %o0: status
1823 */
1824 .globl sun4v_cpu_qconf
1825 .type sun4v_cpu_qconf,#function
1826sun4v_cpu_qconf:
1827 mov HV_FAST_CPU_QCONF, %o5
1828 ta HV_FAST_TRAP
1829 retl
1830 nop
1831 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf
1832
1833 /* %o0: num cpus in cpu list
1834 * %o1: cpu list paddr
1835 * %o2: mondo block paddr
1836 *
1837 * returns %o0: status
1838 */
1839 .globl sun4v_cpu_mondo_send
1840 .type sun4v_cpu_mondo_send,#function
1841sun4v_cpu_mondo_send:
1842 mov HV_FAST_CPU_MONDO_SEND, %o5
1843 ta HV_FAST_TRAP
1844 retl
1845 nop
1846 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send
1847
1848 /* %o0: CPU ID
1849 *
1850 * returns %o0: -status if status non-zero, else
1851 * %o0: cpu state as HV_CPU_STATE_*
1852 */
1853 .globl sun4v_cpu_state
1854 .type sun4v_cpu_state,#function
1855sun4v_cpu_state:
1856 mov HV_FAST_CPU_STATE, %o5
1857 ta HV_FAST_TRAP
1858 brnz,pn %o0, 1f
1859 sub %g0, %o0, %o0
1860 mov %o1, %o0
18611: retl
1862 nop
1863 .size sun4v_cpu_state, .-sun4v_cpu_state
1864
1865 /* %o0: virtual address
1866 * %o1: must be zero
1867 * %o2: TTE
1868 * %o3: HV_MMU_* flags
1869 *
1870 * returns %o0: status
1871 */
1872 .globl sun4v_mmu_map_perm_addr
1873 .type sun4v_mmu_map_perm_addr,#function
1874sun4v_mmu_map_perm_addr:
1875 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
1876 ta HV_FAST_TRAP
1877 retl
1878 nop
1879 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr
1880
1881 /* %o0: number of TSB descriptions
1882 * %o1: TSB descriptions real address
1883 *
1884 * returns %o0: status
1885 */
1886 .globl sun4v_mmu_tsb_ctx0
1887 .type sun4v_mmu_tsb_ctx0,#function
1888sun4v_mmu_tsb_ctx0:
1889 mov HV_FAST_MMU_TSB_CTX0, %o5
1890 ta HV_FAST_TRAP
1891 retl
1892 nop
1893 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0
1894
1895 /* %o0: API group number
1896 * %o1: pointer to unsigned long major number storage
1897 * %o2: pointer to unsigned long minor number storage
1898 *
1899 * returns %o0: status
1900 */
1901 .globl sun4v_get_version
1902 .type sun4v_get_version,#function
1903sun4v_get_version:
1904 mov HV_CORE_GET_VER, %o5
1905 mov %o1, %o3
1906 mov %o2, %o4
1907 ta HV_CORE_TRAP
1908 stx %o1, [%o3]
1909 retl
1910 stx %o2, [%o4]
1911 .size sun4v_get_version, .-sun4v_get_version
1912
1913 /* %o0: API group number
1914 * %o1: desired major number
1915 * %o2: desired minor number
1916 * %o3: pointer to unsigned long actual minor number storage
1917 *
1918 * returns %o0: status
1919 */
1920 .globl sun4v_set_version
1921 .type sun4v_set_version,#function
1922sun4v_set_version:
1923 mov HV_CORE_SET_VER, %o5
1924 mov %o3, %o4
1925 ta HV_CORE_TRAP
1926 retl
1927 stx %o1, [%o4]
1928 .size sun4v_set_version, .-sun4v_set_version
1929
1930 /* %o0: pointer to unsigned long time
1931 *
1932 * returns %o0: status
1933 */
1934 .globl sun4v_tod_get
1935 .type sun4v_tod_get,#function
1936sun4v_tod_get:
1937 mov %o0, %o4
1938 mov HV_FAST_TOD_GET, %o5
1939 ta HV_FAST_TRAP
1940 stx %o1, [%o4]
1941 retl
1942 nop
1943 .size sun4v_tod_get, .-sun4v_tod_get
1944
1945 /* %o0: time
1946 *
1947 * returns %o0: status
1948 */
1949 .globl sun4v_tod_set
1950 .type sun4v_tod_set,#function
1951sun4v_tod_set:
1952 mov HV_FAST_TOD_SET, %o5
1953 ta HV_FAST_TRAP
1954 retl
1955 nop
1956 .size sun4v_tod_set, .-sun4v_tod_set
1957
1958 /* %o0: pointer to unsigned long status
1959 *
1960 * returns %o0: signed character
1961 */
1962 .globl sun4v_con_getchar
1963 .type sun4v_con_getchar,#function
1964sun4v_con_getchar:
1965 mov %o0, %o4
1966 mov HV_FAST_CONS_GETCHAR, %o5
1967 clr %o0
1968 clr %o1
1969 ta HV_FAST_TRAP
1970 stx %o0, [%o4]
1971 retl
1972 sra %o1, 0, %o0
1973 .size sun4v_con_getchar, .-sun4v_con_getchar
1974
1975 /* %o0: signed long character
1976 *
1977 * returns %o0: status
1978 */
1979 .globl sun4v_con_putchar
1980 .type sun4v_con_putchar,#function
1981sun4v_con_putchar:
1982 mov HV_FAST_CONS_PUTCHAR, %o5
1983 ta HV_FAST_TRAP
1984 retl
1985 sra %o0, 0, %o0
1986 .size sun4v_con_putchar, .-sun4v_con_putchar
1987
1988 /* %o0: buffer real address
1989 * %o1: buffer size
1990 * %o2: pointer to unsigned long bytes_read
1991 *
1992 * returns %o0: status
1993 */
1994 .globl sun4v_con_read
1995 .type sun4v_con_read,#function
1996sun4v_con_read:
1997 mov %o2, %o4
1998 mov HV_FAST_CONS_READ, %o5
1999 ta HV_FAST_TRAP
2000 brnz %o0, 1f
2001 cmp %o1, -1 /* break */
2002 be,a,pn %icc, 1f
2003 mov %o1, %o0
2004 cmp %o1, -2 /* hup */
2005 be,a,pn %icc, 1f
2006 mov %o1, %o0
2007 stx %o1, [%o4]
20081: retl
2009 nop
2010 .size sun4v_con_read, .-sun4v_con_read
2011
2012 /* %o0: buffer real address
2013 * %o1: buffer size
2014 * %o2: pointer to unsigned long bytes_written
2015 *
2016 * returns %o0: status
2017 */
2018 .globl sun4v_con_write
2019 .type sun4v_con_write,#function
2020sun4v_con_write:
2021 mov %o2, %o4
2022 mov HV_FAST_CONS_WRITE, %o5
2023 ta HV_FAST_TRAP
2024 stx %o1, [%o4]
2025 retl
2026 nop
2027 .size sun4v_con_write, .-sun4v_con_write
2028
2029 /* %o0: soft state
2030 * %o1: address of description string
2031 *
2032 * returns %o0: status
2033 */
2034 .globl sun4v_mach_set_soft_state
2035 .type sun4v_mach_set_soft_state,#function
2036sun4v_mach_set_soft_state:
2037 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
2038 ta HV_FAST_TRAP
2039 retl
2040 nop
2041 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state
2042
2043 /* %o0: exit code
2044 *
2045 * Does not return.
2046 */
2047 .globl sun4v_mach_exit
2048 .type sun4v_mach_exit,#function
2049sun4v_mach_exit:
2050 mov HV_FAST_MACH_EXIT, %o5
2051 ta HV_FAST_TRAP
2052 retl
2053 nop
2054 .size sun4v_mach_exit, .-sun4v_mach_exit
2055
2056 /* %o0: buffer real address
2057 * %o1: buffer length
2058 * %o2: pointer to unsigned long real_buf_len
2059 *
2060 * returns %o0: status
2061 */
2062 .globl sun4v_mach_desc
2063 .type sun4v_mach_desc,#function
2064sun4v_mach_desc:
2065 mov %o2, %o4
2066 mov HV_FAST_MACH_DESC, %o5
2067 ta HV_FAST_TRAP
2068 stx %o1, [%o4]
2069 retl
2070 nop
2071 .size sun4v_mach_desc, .-sun4v_mach_desc
2072
2073 /* %o0: new timeout in milliseconds
2074 * %o1: pointer to unsigned long orig_timeout
2075 *
2076 * returns %o0: status
2077 */
2078 .globl sun4v_mach_set_watchdog
2079 .type sun4v_mach_set_watchdog,#function
2080sun4v_mach_set_watchdog:
2081 mov %o1, %o4
2082 mov HV_FAST_MACH_SET_WATCHDOG, %o5
2083 ta HV_FAST_TRAP
2084 stx %o1, [%o4]
2085 retl
2086 nop
2087 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog
2088
2089 /* No inputs and does not return. */
2090 .globl sun4v_mach_sir
2091 .type sun4v_mach_sir,#function
2092sun4v_mach_sir:
2093 mov %o1, %o4
2094 mov HV_FAST_MACH_SIR, %o5
2095 ta HV_FAST_TRAP
2096 stx %o1, [%o4]
2097 retl
2098 nop
2099 .size sun4v_mach_sir, .-sun4v_mach_sir
2100
2101 /* %o0: channel
2102 * %o1: ra
2103 * %o2: num_entries
2104 *
2105 * returns %o0: status
2106 */
2107 .globl sun4v_ldc_tx_qconf
2108 .type sun4v_ldc_tx_qconf,#function
2109sun4v_ldc_tx_qconf:
2110 mov HV_FAST_LDC_TX_QCONF, %o5
2111 ta HV_FAST_TRAP
2112 retl
2113 nop
2114 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf
2115
2116 /* %o0: channel
2117 * %o1: pointer to unsigned long ra
2118 * %o2: pointer to unsigned long num_entries
2119 *
2120 * returns %o0: status
2121 */
2122 .globl sun4v_ldc_tx_qinfo
2123 .type sun4v_ldc_tx_qinfo,#function
2124sun4v_ldc_tx_qinfo:
2125 mov %o1, %g1
2126 mov %o2, %g2
2127 mov HV_FAST_LDC_TX_QINFO, %o5
2128 ta HV_FAST_TRAP
2129 stx %o1, [%g1]
2130 stx %o2, [%g2]
2131 retl
2132 nop
2133 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo
2134
2135 /* %o0: channel
2136 * %o1: pointer to unsigned long head_off
2137 * %o2: pointer to unsigned long tail_off
2138 * %o2: pointer to unsigned long chan_state
2139 *
2140 * returns %o0: status
2141 */
2142 .globl sun4v_ldc_tx_get_state
2143 .type sun4v_ldc_tx_get_state,#function
2144sun4v_ldc_tx_get_state:
2145 mov %o1, %g1
2146 mov %o2, %g2
2147 mov %o3, %g3
2148 mov HV_FAST_LDC_TX_GET_STATE, %o5
2149 ta HV_FAST_TRAP
2150 stx %o1, [%g1]
2151 stx %o2, [%g2]
2152 stx %o3, [%g3]
2153 retl
2154 nop
2155 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state
2156
2157 /* %o0: channel
2158 * %o1: tail_off
2159 *
2160 * returns %o0: status
2161 */
2162 .globl sun4v_ldc_tx_set_qtail
2163 .type sun4v_ldc_tx_set_qtail,#function
2164sun4v_ldc_tx_set_qtail:
2165 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
2166 ta HV_FAST_TRAP
2167 retl
2168 nop
2169 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail
2170
2171 /* %o0: channel
2172 * %o1: ra
2173 * %o2: num_entries
2174 *
2175 * returns %o0: status
2176 */
2177 .globl sun4v_ldc_rx_qconf
2178 .type sun4v_ldc_rx_qconf,#function
2179sun4v_ldc_rx_qconf:
2180 mov HV_FAST_LDC_RX_QCONF, %o5
2181 ta HV_FAST_TRAP
2182 retl
2183 nop
2184 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf
2185
2186 /* %o0: channel
2187 * %o1: pointer to unsigned long ra
2188 * %o2: pointer to unsigned long num_entries
2189 *
2190 * returns %o0: status
2191 */
2192 .globl sun4v_ldc_rx_qinfo
2193 .type sun4v_ldc_rx_qinfo,#function
2194sun4v_ldc_rx_qinfo:
2195 mov %o1, %g1
2196 mov %o2, %g2
2197 mov HV_FAST_LDC_RX_QINFO, %o5
2198 ta HV_FAST_TRAP
2199 stx %o1, [%g1]
2200 stx %o2, [%g2]
2201 retl
2202 nop
2203 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo
2204
2205 /* %o0: channel
2206 * %o1: pointer to unsigned long head_off
2207 * %o2: pointer to unsigned long tail_off
2208 * %o2: pointer to unsigned long chan_state
2209 *
2210 * returns %o0: status
2211 */
2212 .globl sun4v_ldc_rx_get_state
2213 .type sun4v_ldc_rx_get_state,#function
2214sun4v_ldc_rx_get_state:
2215 mov %o1, %g1
2216 mov %o2, %g2
2217 mov %o3, %g3
2218 mov HV_FAST_LDC_RX_GET_STATE, %o5
2219 ta HV_FAST_TRAP
2220 stx %o1, [%g1]
2221 stx %o2, [%g2]
2222 stx %o3, [%g3]
2223 retl
2224 nop
2225 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state
2226
2227 /* %o0: channel
2228 * %o1: head_off
2229 *
2230 * returns %o0: status
2231 */
2232 .globl sun4v_ldc_rx_set_qhead
2233 .type sun4v_ldc_rx_set_qhead,#function
2234sun4v_ldc_rx_set_qhead:
2235 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
2236 ta HV_FAST_TRAP
2237 retl
2238 nop
2239 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead
2240
2241 /* %o0: channel
2242 * %o1: ra
2243 * %o2: num_entries
2244 *
2245 * returns %o0: status
2246 */
2247 .globl sun4v_ldc_set_map_table
2248 .type sun4v_ldc_set_map_table,#function
2249sun4v_ldc_set_map_table:
2250 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
2251 ta HV_FAST_TRAP
2252 retl
2253 nop
2254 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table
2255
2256 /* %o0: channel
2257 * %o1: pointer to unsigned long ra
2258 * %o2: pointer to unsigned long num_entries
2259 *
2260 * returns %o0: status
2261 */
2262 .globl sun4v_ldc_get_map_table
2263 .type sun4v_ldc_get_map_table,#function
2264sun4v_ldc_get_map_table:
2265 mov %o1, %g1
2266 mov %o2, %g2
2267 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
2268 ta HV_FAST_TRAP
2269 stx %o1, [%g1]
2270 stx %o2, [%g2]
2271 retl
2272 nop
2273 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table
2274
2275 /* %o0: channel
2276 * %o1: dir_code
2277 * %o2: tgt_raddr
2278 * %o3: lcl_raddr
2279 * %o4: len
2280 * %o5: pointer to unsigned long actual_len
2281 *
2282 * returns %o0: status
2283 */
2284 .globl sun4v_ldc_copy
2285 .type sun4v_ldc_copy,#function
2286sun4v_ldc_copy:
2287 mov %o5, %g1
2288 mov HV_FAST_LDC_COPY, %o5
2289 ta HV_FAST_TRAP
2290 stx %o1, [%g1]
2291 retl
2292 nop
2293 .size sun4v_ldc_copy, .-sun4v_ldc_copy
2294
2295 /* %o0: channel
2296 * %o1: cookie
2297 * %o2: pointer to unsigned long ra
2298 * %o3: pointer to unsigned long perm
2299 *
2300 * returns %o0: status
2301 */
2302 .globl sun4v_ldc_mapin
2303 .type sun4v_ldc_mapin,#function
2304sun4v_ldc_mapin:
2305 mov %o2, %g1
2306 mov %o3, %g2
2307 mov HV_FAST_LDC_MAPIN, %o5
2308 ta HV_FAST_TRAP
2309 stx %o1, [%g1]
2310 stx %o2, [%g2]
2311 retl
2312 nop
2313 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin
2314
2315 /* %o0: ra
2316 *
2317 * returns %o0: status
2318 */
2319 .globl sun4v_ldc_unmap
2320 .type sun4v_ldc_unmap,#function
2321sun4v_ldc_unmap:
2322 mov HV_FAST_LDC_UNMAP, %o5
2323 ta HV_FAST_TRAP
2324 retl
2325 nop
2326 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap
2327
2328 /* %o0: channel
2329 * %o1: cookie
2330 * %o2: mte_cookie
2331 *
2332 * returns %o0: status
2333 */
2334 .globl sun4v_ldc_revoke
2335 .type sun4v_ldc_revoke,#function
2336sun4v_ldc_revoke:
2337 mov HV_FAST_LDC_REVOKE, %o5
2338 ta HV_FAST_TRAP
2339 retl
2340 nop
2341 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke
2342
2343 /* %o0: device handle
2344 * %o1: device INO
2345 * %o2: pointer to unsigned long cookie
2346 *
2347 * returns %o0: status
2348 */
2349 .globl sun4v_vintr_get_cookie
2350 .type sun4v_vintr_get_cookie,#function
2351sun4v_vintr_get_cookie:
2352 mov %o2, %g1
2353 mov HV_FAST_VINTR_GET_COOKIE, %o5
2354 ta HV_FAST_TRAP
2355 stx %o1, [%g1]
2356 retl
2357 nop
2358 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie
2359
2360 /* %o0: device handle
2361 * %o1: device INO
2362 * %o2: cookie
2363 *
2364 * returns %o0: status
2365 */
2366 .globl sun4v_vintr_set_cookie
2367 .type sun4v_vintr_set_cookie,#function
2368sun4v_vintr_set_cookie:
2369 mov HV_FAST_VINTR_SET_COOKIE, %o5
2370 ta HV_FAST_TRAP
2371 retl
2372 nop
2373 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie
2374
2375 /* %o0: device handle
2376 * %o1: device INO
2377 * %o2: pointer to unsigned long valid_state
2378 *
2379 * returns %o0: status
2380 */
2381 .globl sun4v_vintr_get_valid
2382 .type sun4v_vintr_get_valid,#function
2383sun4v_vintr_get_valid:
2384 mov %o2, %g1
2385 mov HV_FAST_VINTR_GET_VALID, %o5
2386 ta HV_FAST_TRAP
2387 stx %o1, [%g1]
2388 retl
2389 nop
2390 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid
2391
2392 /* %o0: device handle
2393 * %o1: device INO
2394 * %o2: valid_state
2395 *
2396 * returns %o0: status
2397 */
2398 .globl sun4v_vintr_set_valid
2399 .type sun4v_vintr_set_valid,#function
2400sun4v_vintr_set_valid:
2401 mov HV_FAST_VINTR_SET_VALID, %o5
2402 ta HV_FAST_TRAP
2403 retl
2404 nop
2405 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid
2406
2407 /* %o0: device handle
2408 * %o1: device INO
2409 * %o2: pointer to unsigned long state
2410 *
2411 * returns %o0: status
2412 */
2413 .globl sun4v_vintr_get_state
2414 .type sun4v_vintr_get_state,#function
2415sun4v_vintr_get_state:
2416 mov %o2, %g1
2417 mov HV_FAST_VINTR_GET_STATE, %o5
2418 ta HV_FAST_TRAP
2419 stx %o1, [%g1]
2420 retl
2421 nop
2422 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state
2423
2424 /* %o0: device handle
2425 * %o1: device INO
2426 * %o2: state
2427 *
2428 * returns %o0: status
2429 */
2430 .globl sun4v_vintr_set_state
2431 .type sun4v_vintr_set_state,#function
2432sun4v_vintr_set_state:
2433 mov HV_FAST_VINTR_SET_STATE, %o5
2434 ta HV_FAST_TRAP
2435 retl
2436 nop
2437 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state
2438
2439 /* %o0: device handle
2440 * %o1: device INO
2441 * %o2: pointer to unsigned long cpuid
2442 *
2443 * returns %o0: status
2444 */
2445 .globl sun4v_vintr_get_target
2446 .type sun4v_vintr_get_target,#function
2447sun4v_vintr_get_target:
2448 mov %o2, %g1
2449 mov HV_FAST_VINTR_GET_TARGET, %o5
2450 ta HV_FAST_TRAP
2451 stx %o1, [%g1]
2452 retl
2453 nop
2454 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target
2455
2456 /* %o0: device handle
2457 * %o1: device INO
2458 * %o2: cpuid
2459 *
2460 * returns %o0: status
2461 */
2462 .globl sun4v_vintr_set_target
2463 .type sun4v_vintr_set_target,#function
2464sun4v_vintr_set_target:
2465 mov HV_FAST_VINTR_SET_TARGET, %o5
2466 ta HV_FAST_TRAP
2467 retl
2468 nop
2469 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target
2470
2471 /* %o0: NCS sub-function
2472 * %o1: sub-function arg real-address
2473 * %o2: sub-function arg size
2474 *
2475 * returns %o0: status
2476 */
2477 .globl sun4v_ncs_request
2478 .type sun4v_ncs_request,#function
2479sun4v_ncs_request:
2480 mov HV_FAST_NCS_REQUEST, %o5
2481 ta HV_FAST_TRAP
2482 retl
2483 nop
2484 .size sun4v_ncs_request, .-sun4v_ncs_request
2485
2486 .globl sun4v_svc_send
2487 .type sun4v_svc_send,#function
2488sun4v_svc_send:
2489 save %sp, -192, %sp
2490 mov %i0, %o0
2491 mov %i1, %o1
2492 mov %i2, %o2
2493 mov HV_FAST_SVC_SEND, %o5
2494 ta HV_FAST_TRAP
2495 stx %o1, [%i3]
2496 ret
2497 restore
2498 .size sun4v_svc_send, .-sun4v_svc_send
2499
2500 .globl sun4v_svc_recv
2501 .type sun4v_svc_recv,#function
2502sun4v_svc_recv:
2503 save %sp, -192, %sp
2504 mov %i0, %o0
2505 mov %i1, %o1
2506 mov %i2, %o2
2507 mov HV_FAST_SVC_RECV, %o5
2508 ta HV_FAST_TRAP
2509 stx %o1, [%i3]
2510 ret
2511 restore
2512 .size sun4v_svc_recv, .-sun4v_svc_recv
2513
2514 .globl sun4v_svc_getstatus
2515 .type sun4v_svc_getstatus,#function
2516sun4v_svc_getstatus:
2517 mov HV_FAST_SVC_GETSTATUS, %o5
2518 mov %o1, %o4
2519 ta HV_FAST_TRAP
2520 stx %o1, [%o4]
2521 retl
2522 nop
2523 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus
2524
2525 .globl sun4v_svc_setstatus
2526 .type sun4v_svc_setstatus,#function
2527sun4v_svc_setstatus:
2528 mov HV_FAST_SVC_SETSTATUS, %o5
2529 ta HV_FAST_TRAP
2530 retl
2531 nop
2532 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus
2533
2534 .globl sun4v_svc_clrstatus
2535 .type sun4v_svc_clrstatus,#function
2536sun4v_svc_clrstatus:
2537 mov HV_FAST_SVC_CLRSTATUS, %o5
2538 ta HV_FAST_TRAP
2539 retl
2540 nop
2541 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus
2542
2543 .globl sun4v_mmustat_conf
2544 .type sun4v_mmustat_conf,#function
2545sun4v_mmustat_conf:
2546 mov %o1, %o4
2547 mov HV_FAST_MMUSTAT_CONF, %o5
2548 ta HV_FAST_TRAP
2549 stx %o1, [%o4]
2550 retl
2551 nop
2552 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf
2553
2554 .globl sun4v_mmustat_info
2555 .type sun4v_mmustat_info,#function
2556sun4v_mmustat_info:
2557 mov %o0, %o4
2558 mov HV_FAST_MMUSTAT_INFO, %o5
2559 ta HV_FAST_TRAP
2560 stx %o1, [%o4]
2561 retl
2562 nop
2563 .size sun4v_mmustat_info, .-sun4v_mmustat_info
2564
2565 .globl sun4v_mmu_demap_all
2566 .type sun4v_mmu_demap_all,#function
2567sun4v_mmu_demap_all:
2568 clr %o0
2569 clr %o1
2570 mov HV_MMU_ALL, %o2
2571 mov HV_FAST_MMU_DEMAP_ALL, %o5
2572 ta HV_FAST_TRAP
2573 retl
2574 nop
2575 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all
diff --git a/arch/sparc64/kernel/fpu_traps.S b/arch/sparc64/kernel/fpu_traps.S
new file mode 100644
index 000000000000..a6864826a4bd
--- /dev/null
+++ b/arch/sparc64/kernel/fpu_traps.S
@@ -0,0 +1,384 @@
1 /* This is trivial with the new code... */
2 .globl do_fpdis
3 .type do_fpdis,#function
4do_fpdis:
5 sethi %hi(TSTATE_PEF), %g4
6 rdpr %tstate, %g5
7 andcc %g5, %g4, %g0
8 be,pt %xcc, 1f
9 nop
10 rd %fprs, %g5
11 andcc %g5, FPRS_FEF, %g0
12 be,pt %xcc, 1f
13 nop
14
15 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
16 sethi %hi(109f), %g7
17 ba,pt %xcc, etrap
18109: or %g7, %lo(109b), %g7
19 add %g0, %g0, %g0
20 ba,a,pt %xcc, rtrap
21
221: TRAP_LOAD_THREAD_REG(%g6, %g1)
23 ldub [%g6 + TI_FPSAVED], %g5
24 wr %g0, FPRS_FEF, %fprs
25 andcc %g5, FPRS_FEF, %g0
26 be,a,pt %icc, 1f
27 clr %g7
28 ldx [%g6 + TI_GSR], %g7
291: andcc %g5, FPRS_DL, %g0
30 bne,pn %icc, 2f
31 fzero %f0
32 andcc %g5, FPRS_DU, %g0
33 bne,pn %icc, 1f
34 fzero %f2
35 faddd %f0, %f2, %f4
36 fmuld %f0, %f2, %f6
37 faddd %f0, %f2, %f8
38 fmuld %f0, %f2, %f10
39 faddd %f0, %f2, %f12
40 fmuld %f0, %f2, %f14
41 faddd %f0, %f2, %f16
42 fmuld %f0, %f2, %f18
43 faddd %f0, %f2, %f20
44 fmuld %f0, %f2, %f22
45 faddd %f0, %f2, %f24
46 fmuld %f0, %f2, %f26
47 faddd %f0, %f2, %f28
48 fmuld %f0, %f2, %f30
49 faddd %f0, %f2, %f32
50 fmuld %f0, %f2, %f34
51 faddd %f0, %f2, %f36
52 fmuld %f0, %f2, %f38
53 faddd %f0, %f2, %f40
54 fmuld %f0, %f2, %f42
55 faddd %f0, %f2, %f44
56 fmuld %f0, %f2, %f46
57 faddd %f0, %f2, %f48
58 fmuld %f0, %f2, %f50
59 faddd %f0, %f2, %f52
60 fmuld %f0, %f2, %f54
61 faddd %f0, %f2, %f56
62 fmuld %f0, %f2, %f58
63 b,pt %xcc, fpdis_exit2
64 faddd %f0, %f2, %f60
651: mov SECONDARY_CONTEXT, %g3
66 add %g6, TI_FPREGS + 0x80, %g1
67 faddd %f0, %f2, %f4
68 fmuld %f0, %f2, %f6
69
70661: ldxa [%g3] ASI_DMMU, %g5
71 .section .sun4v_1insn_patch, "ax"
72 .word 661b
73 ldxa [%g3] ASI_MMU, %g5
74 .previous
75
76 sethi %hi(sparc64_kern_sec_context), %g2
77 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
78
79661: stxa %g2, [%g3] ASI_DMMU
80 .section .sun4v_1insn_patch, "ax"
81 .word 661b
82 stxa %g2, [%g3] ASI_MMU
83 .previous
84
85 membar #Sync
86 add %g6, TI_FPREGS + 0xc0, %g2
87 faddd %f0, %f2, %f8
88 fmuld %f0, %f2, %f10
89 membar #Sync
90 ldda [%g1] ASI_BLK_S, %f32
91 ldda [%g2] ASI_BLK_S, %f48
92 membar #Sync
93 faddd %f0, %f2, %f12
94 fmuld %f0, %f2, %f14
95 faddd %f0, %f2, %f16
96 fmuld %f0, %f2, %f18
97 faddd %f0, %f2, %f20
98 fmuld %f0, %f2, %f22
99 faddd %f0, %f2, %f24
100 fmuld %f0, %f2, %f26
101 faddd %f0, %f2, %f28
102 fmuld %f0, %f2, %f30
103 b,pt %xcc, fpdis_exit
104 nop
1052: andcc %g5, FPRS_DU, %g0
106 bne,pt %icc, 3f
107 fzero %f32
108 mov SECONDARY_CONTEXT, %g3
109 fzero %f34
110
111661: ldxa [%g3] ASI_DMMU, %g5
112 .section .sun4v_1insn_patch, "ax"
113 .word 661b
114 ldxa [%g3] ASI_MMU, %g5
115 .previous
116
117 add %g6, TI_FPREGS, %g1
118 sethi %hi(sparc64_kern_sec_context), %g2
119 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
120
121661: stxa %g2, [%g3] ASI_DMMU
122 .section .sun4v_1insn_patch, "ax"
123 .word 661b
124 stxa %g2, [%g3] ASI_MMU
125 .previous
126
127 membar #Sync
128 add %g6, TI_FPREGS + 0x40, %g2
129 faddd %f32, %f34, %f36
130 fmuld %f32, %f34, %f38
131 membar #Sync
132 ldda [%g1] ASI_BLK_S, %f0
133 ldda [%g2] ASI_BLK_S, %f16
134 membar #Sync
135 faddd %f32, %f34, %f40
136 fmuld %f32, %f34, %f42
137 faddd %f32, %f34, %f44
138 fmuld %f32, %f34, %f46
139 faddd %f32, %f34, %f48
140 fmuld %f32, %f34, %f50
141 faddd %f32, %f34, %f52
142 fmuld %f32, %f34, %f54
143 faddd %f32, %f34, %f56
144 fmuld %f32, %f34, %f58
145 faddd %f32, %f34, %f60
146 fmuld %f32, %f34, %f62
147 ba,pt %xcc, fpdis_exit
148 nop
1493: mov SECONDARY_CONTEXT, %g3
150 add %g6, TI_FPREGS, %g1
151
152661: ldxa [%g3] ASI_DMMU, %g5
153 .section .sun4v_1insn_patch, "ax"
154 .word 661b
155 ldxa [%g3] ASI_MMU, %g5
156 .previous
157
158 sethi %hi(sparc64_kern_sec_context), %g2
159 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
160
161661: stxa %g2, [%g3] ASI_DMMU
162 .section .sun4v_1insn_patch, "ax"
163 .word 661b
164 stxa %g2, [%g3] ASI_MMU
165 .previous
166
167 membar #Sync
168 mov 0x40, %g2
169 membar #Sync
170 ldda [%g1] ASI_BLK_S, %f0
171 ldda [%g1 + %g2] ASI_BLK_S, %f16
172 add %g1, 0x80, %g1
173 ldda [%g1] ASI_BLK_S, %f32
174 ldda [%g1 + %g2] ASI_BLK_S, %f48
175 membar #Sync
176fpdis_exit:
177
178661: stxa %g5, [%g3] ASI_DMMU
179 .section .sun4v_1insn_patch, "ax"
180 .word 661b
181 stxa %g5, [%g3] ASI_MMU
182 .previous
183
184 membar #Sync
185fpdis_exit2:
186 wr %g7, 0, %gsr
187 ldx [%g6 + TI_XFSR], %fsr
188 rdpr %tstate, %g3
189 or %g3, %g4, %g3 ! anal...
190 wrpr %g3, %tstate
191 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
192 retry
193 .size do_fpdis,.-do_fpdis
194
195 .align 32
196 .type fp_other_bounce,#function
197fp_other_bounce:
198 call do_fpother
199 add %sp, PTREGS_OFF, %o0
200 ba,pt %xcc, rtrap
201 nop
202 .size fp_other_bounce,.-fp_other_bounce
203
204 .align 32
205 .globl do_fpother_check_fitos
206 .type do_fpother_check_fitos,#function
207do_fpother_check_fitos:
208 TRAP_LOAD_THREAD_REG(%g6, %g1)
209 sethi %hi(fp_other_bounce - 4), %g7
210 or %g7, %lo(fp_other_bounce - 4), %g7
211
212 /* NOTE: Need to preserve %g7 until we fully commit
213 * to the fitos fixup.
214 */
215 stx %fsr, [%g6 + TI_XFSR]
216 rdpr %tstate, %g3
217 andcc %g3, TSTATE_PRIV, %g0
218 bne,pn %xcc, do_fptrap_after_fsr
219 nop
220 ldx [%g6 + TI_XFSR], %g3
221 srlx %g3, 14, %g1
222 and %g1, 7, %g1
223 cmp %g1, 2 ! Unfinished FP-OP
224 bne,pn %xcc, do_fptrap_after_fsr
225 sethi %hi(1 << 23), %g1 ! Inexact
226 andcc %g3, %g1, %g0
227 bne,pn %xcc, do_fptrap_after_fsr
228 rdpr %tpc, %g1
229 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
230#define FITOS_MASK 0xc1f83fe0
231#define FITOS_COMPARE 0x81a01880
232 sethi %hi(FITOS_MASK), %g1
233 or %g1, %lo(FITOS_MASK), %g1
234 and %g3, %g1, %g1
235 sethi %hi(FITOS_COMPARE), %g2
236 or %g2, %lo(FITOS_COMPARE), %g2
237 cmp %g1, %g2
238 bne,pn %xcc, do_fptrap_after_fsr
239 nop
240 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
241 sethi %hi(fitos_table_1), %g1
242 and %g3, 0x1f, %g2
243 or %g1, %lo(fitos_table_1), %g1
244 sllx %g2, 2, %g2
245 jmpl %g1 + %g2, %g0
246 ba,pt %xcc, fitos_emul_continue
247
248fitos_table_1:
249 fitod %f0, %f62
250 fitod %f1, %f62
251 fitod %f2, %f62
252 fitod %f3, %f62
253 fitod %f4, %f62
254 fitod %f5, %f62
255 fitod %f6, %f62
256 fitod %f7, %f62
257 fitod %f8, %f62
258 fitod %f9, %f62
259 fitod %f10, %f62
260 fitod %f11, %f62
261 fitod %f12, %f62
262 fitod %f13, %f62
263 fitod %f14, %f62
264 fitod %f15, %f62
265 fitod %f16, %f62
266 fitod %f17, %f62
267 fitod %f18, %f62
268 fitod %f19, %f62
269 fitod %f20, %f62
270 fitod %f21, %f62
271 fitod %f22, %f62
272 fitod %f23, %f62
273 fitod %f24, %f62
274 fitod %f25, %f62
275 fitod %f26, %f62
276 fitod %f27, %f62
277 fitod %f28, %f62
278 fitod %f29, %f62
279 fitod %f30, %f62
280 fitod %f31, %f62
281
282fitos_emul_continue:
283 sethi %hi(fitos_table_2), %g1
284 srl %g3, 25, %g2
285 or %g1, %lo(fitos_table_2), %g1
286 and %g2, 0x1f, %g2
287 sllx %g2, 2, %g2
288 jmpl %g1 + %g2, %g0
289 ba,pt %xcc, fitos_emul_fini
290
291fitos_table_2:
292 fdtos %f62, %f0
293 fdtos %f62, %f1
294 fdtos %f62, %f2
295 fdtos %f62, %f3
296 fdtos %f62, %f4
297 fdtos %f62, %f5
298 fdtos %f62, %f6
299 fdtos %f62, %f7
300 fdtos %f62, %f8
301 fdtos %f62, %f9
302 fdtos %f62, %f10
303 fdtos %f62, %f11
304 fdtos %f62, %f12
305 fdtos %f62, %f13
306 fdtos %f62, %f14
307 fdtos %f62, %f15
308 fdtos %f62, %f16
309 fdtos %f62, %f17
310 fdtos %f62, %f18
311 fdtos %f62, %f19
312 fdtos %f62, %f20
313 fdtos %f62, %f21
314 fdtos %f62, %f22
315 fdtos %f62, %f23
316 fdtos %f62, %f24
317 fdtos %f62, %f25
318 fdtos %f62, %f26
319 fdtos %f62, %f27
320 fdtos %f62, %f28
321 fdtos %f62, %f29
322 fdtos %f62, %f30
323 fdtos %f62, %f31
324
325fitos_emul_fini:
326 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
327 done
328 .size do_fpother_check_fitos,.-do_fpother_check_fitos
329
330 .align 32
331 .globl do_fptrap
332 .type do_fptrap,#function
333do_fptrap:
334 TRAP_LOAD_THREAD_REG(%g6, %g1)
335 stx %fsr, [%g6 + TI_XFSR]
336do_fptrap_after_fsr:
337 ldub [%g6 + TI_FPSAVED], %g3
338 rd %fprs, %g1
339 or %g3, %g1, %g3
340 stb %g3, [%g6 + TI_FPSAVED]
341 rd %gsr, %g3
342 stx %g3, [%g6 + TI_GSR]
343 mov SECONDARY_CONTEXT, %g3
344
345661: ldxa [%g3] ASI_DMMU, %g5
346 .section .sun4v_1insn_patch, "ax"
347 .word 661b
348 ldxa [%g3] ASI_MMU, %g5
349 .previous
350
351 sethi %hi(sparc64_kern_sec_context), %g2
352 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
353
354661: stxa %g2, [%g3] ASI_DMMU
355 .section .sun4v_1insn_patch, "ax"
356 .word 661b
357 stxa %g2, [%g3] ASI_MMU
358 .previous
359
360 membar #Sync
361 add %g6, TI_FPREGS, %g2
362 andcc %g1, FPRS_DL, %g0
363 be,pn %icc, 4f
364 mov 0x40, %g3
365 stda %f0, [%g2] ASI_BLK_S
366 stda %f16, [%g2 + %g3] ASI_BLK_S
367 andcc %g1, FPRS_DU, %g0
368 be,pn %icc, 5f
3694: add %g2, 128, %g2
370 stda %f32, [%g2] ASI_BLK_S
371 stda %f48, [%g2 + %g3] ASI_BLK_S
3725: mov SECONDARY_CONTEXT, %g1
373 membar #Sync
374
375661: stxa %g5, [%g1] ASI_DMMU
376 .section .sun4v_1insn_patch, "ax"
377 .word 661b
378 stxa %g5, [%g1] ASI_MMU
379 .previous
380
381 membar #Sync
382 ba,pt %xcc, etrap
383 wr %g0, 0, %fprs
384 .size do_fptrap,.-do_fptrap
diff --git a/arch/sparc64/kernel/getsetcc.S b/arch/sparc64/kernel/getsetcc.S
new file mode 100644
index 000000000000..a14d272d2061
--- /dev/null
+++ b/arch/sparc64/kernel/getsetcc.S
@@ -0,0 +1,24 @@
1 .globl getcc
2 .type getcc,#function
3getcc:
4 ldx [%o0 + PT_V9_TSTATE], %o1
5 srlx %o1, 32, %o1
6 and %o1, 0xf, %o1
7 retl
8 stx %o1, [%o0 + PT_V9_G1]
9 .size getcc,.-getcc
10
11 .globl setcc
12 .type setcc,#function
13setcc:
14 ldx [%o0 + PT_V9_TSTATE], %o1
15 ldx [%o0 + PT_V9_G1], %o2
16 or %g0, %ulo(TSTATE_ICC), %o3
17 sllx %o3, 32, %o3
18 andn %o1, %o3, %o1
19 sllx %o2, 32, %o2
20 and %o2, %o3, %o2
21 or %o1, %o2, %o1
22 retl
23 stx %o1, [%o0 + PT_V9_TSTATE]
24 .size setcc,.-setcc
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 34f8ff57c56b..c9afef093d51 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -27,6 +27,10 @@
27#include <asm/ttable.h> 27#include <asm/ttable.h>
28#include <asm/mmu.h> 28#include <asm/mmu.h>
29#include <asm/cpudata.h> 29#include <asm/cpudata.h>
30#include <asm/pil.h>
31#include <asm/estate.h>
32#include <asm/sfafsr.h>
33#include <asm/unistd.h>
30 34
31/* This section from from _start to sparc64_boot_end should fit into 35/* This section from from _start to sparc64_boot_end should fit into
32 * 0x0000000000404000 to 0x0000000000408000. 36 * 0x0000000000404000 to 0x0000000000408000.
@@ -823,7 +827,16 @@ sparc64_boot_end:
823#include "etrap.S" 827#include "etrap.S"
824#include "rtrap.S" 828#include "rtrap.S"
825#include "winfixup.S" 829#include "winfixup.S"
826#include "entry.S" 830#include "fpu_traps.S"
831#include "ivec.S"
832#include "getsetcc.S"
833#include "utrap.S"
834#include "spiterrs.S"
835#include "cherrs.S"
836#include "misctrap.S"
837#include "syscalls.S"
838#include "helpers.S"
839#include "hvcalls.S"
827#include "sun4v_tlb_miss.S" 840#include "sun4v_tlb_miss.S"
828#include "sun4v_ivec.S" 841#include "sun4v_ivec.S"
829#include "ktlb.S" 842#include "ktlb.S"
diff --git a/arch/sparc64/kernel/helpers.S b/arch/sparc64/kernel/helpers.S
new file mode 100644
index 000000000000..314dd0c9fc5b
--- /dev/null
+++ b/arch/sparc64/kernel/helpers.S
@@ -0,0 +1,63 @@
1 .align 32
2 .globl __flushw_user
3 .type __flushw_user,#function
4__flushw_user:
5 rdpr %otherwin, %g1
6 brz,pn %g1, 2f
7 clr %g2
81: save %sp, -128, %sp
9 rdpr %otherwin, %g1
10 brnz,pt %g1, 1b
11 add %g2, 1, %g2
121: sub %g2, 1, %g2
13 brnz,pt %g2, 1b
14 restore %g0, %g0, %g0
152: retl
16 nop
17 .size __flushw_user,.-__flushw_user
18
19 /* Flush %fp and %i7 to the stack for all register
20 * windows active inside of the cpu. This allows
21 * show_stack_trace() to avoid using an expensive
22 * 'flushw'.
23 */
24 .globl stack_trace_flush
25 .type stack_trace_flush,#function
26stack_trace_flush:
27 rdpr %pstate, %o0
28 wrpr %o0, PSTATE_IE, %pstate
29
30 rdpr %cwp, %g1
31 rdpr %canrestore, %g2
32 sub %g1, 1, %g3
33
341: brz,pn %g2, 2f
35 sub %g2, 1, %g2
36 wrpr %g3, %cwp
37 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
38 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
39 ba,pt %xcc, 1b
40 sub %g3, 1, %g3
41
422: wrpr %g1, %cwp
43 wrpr %o0, %pstate
44
45 retl
46 nop
47 .size stack_trace_flush,.-stack_trace_flush
48
49#ifdef CONFIG_SMP
50 .globl hard_smp_processor_id
51 .type hard_smp_processor_id,#function
52hard_smp_processor_id:
53#endif
54 .globl real_hard_smp_processor_id
55 .type real_hard_smp_processor_id,#function
56real_hard_smp_processor_id:
57 __GET_CPUID(%o0)
58 retl
59 nop
60#ifdef CONFIG_SMP
61 .size hard_smp_processor_id,.-hard_smp_processor_id
62#endif
63 .size real_hard_smp_processor_id,.-real_hard_smp_processor_id
diff --git a/arch/sparc64/kernel/hvcalls.S b/arch/sparc64/kernel/hvcalls.S
new file mode 100644
index 000000000000..a2810f3ac70f
--- /dev/null
+++ b/arch/sparc64/kernel/hvcalls.S
@@ -0,0 +1,886 @@
1 /* %o0: devhandle
2 * %o1: devino
3 *
4 * returns %o0: sysino
5 */
6 .globl sun4v_devino_to_sysino
7 .type sun4v_devino_to_sysino,#function
8sun4v_devino_to_sysino:
9 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
10 ta HV_FAST_TRAP
11 retl
12 mov %o1, %o0
13 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino
14
15 /* %o0: sysino
16 *
17 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
18 */
19 .globl sun4v_intr_getenabled
20 .type sun4v_intr_getenabled,#function
21sun4v_intr_getenabled:
22 mov HV_FAST_INTR_GETENABLED, %o5
23 ta HV_FAST_TRAP
24 retl
25 mov %o1, %o0
26 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled
27
28 /* %o0: sysino
29 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
30 */
31 .globl sun4v_intr_setenabled
32 .type sun4v_intr_setenabled,#function
33sun4v_intr_setenabled:
34 mov HV_FAST_INTR_SETENABLED, %o5
35 ta HV_FAST_TRAP
36 retl
37 nop
38 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled
39
40 /* %o0: sysino
41 *
42 * returns %o0: intr_state (HV_INTR_STATE_*)
43 */
44 .globl sun4v_intr_getstate
45 .type sun4v_intr_getstate,#function
46sun4v_intr_getstate:
47 mov HV_FAST_INTR_GETSTATE, %o5
48 ta HV_FAST_TRAP
49 retl
50 mov %o1, %o0
51 .size sun4v_intr_getstate, .-sun4v_intr_getstate
52
53 /* %o0: sysino
54 * %o1: intr_state (HV_INTR_STATE_*)
55 */
56 .globl sun4v_intr_setstate
57 .type sun4v_intr_setstate,#function
58sun4v_intr_setstate:
59 mov HV_FAST_INTR_SETSTATE, %o5
60 ta HV_FAST_TRAP
61 retl
62 nop
63 .size sun4v_intr_setstate, .-sun4v_intr_setstate
64
65 /* %o0: sysino
66 *
67 * returns %o0: cpuid
68 */
69 .globl sun4v_intr_gettarget
70 .type sun4v_intr_gettarget,#function
71sun4v_intr_gettarget:
72 mov HV_FAST_INTR_GETTARGET, %o5
73 ta HV_FAST_TRAP
74 retl
75 mov %o1, %o0
76 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget
77
78 /* %o0: sysino
79 * %o1: cpuid
80 */
81 .globl sun4v_intr_settarget
82 .type sun4v_intr_settarget,#function
83sun4v_intr_settarget:
84 mov HV_FAST_INTR_SETTARGET, %o5
85 ta HV_FAST_TRAP
86 retl
87 nop
88 .size sun4v_intr_settarget, .-sun4v_intr_settarget
89
90 /* %o0: cpuid
91 * %o1: pc
92 * %o2: rtba
93 * %o3: arg0
94 *
95 * returns %o0: status
96 */
97 .globl sun4v_cpu_start
98 .type sun4v_cpu_start,#function
99sun4v_cpu_start:
100 mov HV_FAST_CPU_START, %o5
101 ta HV_FAST_TRAP
102 retl
103 nop
104 .size sun4v_cpu_start, .-sun4v_cpu_start
105
106 /* %o0: cpuid
107 *
108 * returns %o0: status
109 */
110 .globl sun4v_cpu_stop
111 .type sun4v_cpu_stop,#function
112sun4v_cpu_stop:
113 mov HV_FAST_CPU_STOP, %o5
114 ta HV_FAST_TRAP
115 retl
116 nop
117 .size sun4v_cpu_stop, .-sun4v_cpu_stop
118
119 /* returns %o0: status */
120 .globl sun4v_cpu_yield
121 .type sun4v_cpu_yield, #function
122sun4v_cpu_yield:
123 mov HV_FAST_CPU_YIELD, %o5
124 ta HV_FAST_TRAP
125 retl
126 nop
127 .size sun4v_cpu_yield, .-sun4v_cpu_yield
128
129 /* %o0: type
130 * %o1: queue paddr
131 * %o2: num queue entries
132 *
133 * returns %o0: status
134 */
135 .globl sun4v_cpu_qconf
136 .type sun4v_cpu_qconf,#function
137sun4v_cpu_qconf:
138 mov HV_FAST_CPU_QCONF, %o5
139 ta HV_FAST_TRAP
140 retl
141 nop
142 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf
143
144 /* %o0: num cpus in cpu list
145 * %o1: cpu list paddr
146 * %o2: mondo block paddr
147 *
148 * returns %o0: status
149 */
150 .globl sun4v_cpu_mondo_send
151 .type sun4v_cpu_mondo_send,#function
152sun4v_cpu_mondo_send:
153 mov HV_FAST_CPU_MONDO_SEND, %o5
154 ta HV_FAST_TRAP
155 retl
156 nop
157 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send
158
159 /* %o0: CPU ID
160 *
161 * returns %o0: -status if status non-zero, else
162 * %o0: cpu state as HV_CPU_STATE_*
163 */
164 .globl sun4v_cpu_state
165 .type sun4v_cpu_state,#function
166sun4v_cpu_state:
167 mov HV_FAST_CPU_STATE, %o5
168 ta HV_FAST_TRAP
169 brnz,pn %o0, 1f
170 sub %g0, %o0, %o0
171 mov %o1, %o0
1721: retl
173 nop
174 .size sun4v_cpu_state, .-sun4v_cpu_state
175
176 /* %o0: virtual address
177 * %o1: must be zero
178 * %o2: TTE
179 * %o3: HV_MMU_* flags
180 *
181 * returns %o0: status
182 */
183 .globl sun4v_mmu_map_perm_addr
184 .type sun4v_mmu_map_perm_addr,#function
185sun4v_mmu_map_perm_addr:
186 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
187 ta HV_FAST_TRAP
188 retl
189 nop
190 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr
191
192 /* %o0: number of TSB descriptions
193 * %o1: TSB descriptions real address
194 *
195 * returns %o0: status
196 */
197 .globl sun4v_mmu_tsb_ctx0
198 .type sun4v_mmu_tsb_ctx0,#function
199sun4v_mmu_tsb_ctx0:
200 mov HV_FAST_MMU_TSB_CTX0, %o5
201 ta HV_FAST_TRAP
202 retl
203 nop
204 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0
205
206 /* %o0: API group number
207 * %o1: pointer to unsigned long major number storage
208 * %o2: pointer to unsigned long minor number storage
209 *
210 * returns %o0: status
211 */
212 .globl sun4v_get_version
213 .type sun4v_get_version,#function
214sun4v_get_version:
215 mov HV_CORE_GET_VER, %o5
216 mov %o1, %o3
217 mov %o2, %o4
218 ta HV_CORE_TRAP
219 stx %o1, [%o3]
220 retl
221 stx %o2, [%o4]
222 .size sun4v_get_version, .-sun4v_get_version
223
224 /* %o0: API group number
225 * %o1: desired major number
226 * %o2: desired minor number
227 * %o3: pointer to unsigned long actual minor number storage
228 *
229 * returns %o0: status
230 */
231 .globl sun4v_set_version
232 .type sun4v_set_version,#function
233sun4v_set_version:
234 mov HV_CORE_SET_VER, %o5
235 mov %o3, %o4
236 ta HV_CORE_TRAP
237 retl
238 stx %o1, [%o4]
239 .size sun4v_set_version, .-sun4v_set_version
240
241 /* %o0: pointer to unsigned long time
242 *
243 * returns %o0: status
244 */
245 .globl sun4v_tod_get
246 .type sun4v_tod_get,#function
247sun4v_tod_get:
248 mov %o0, %o4
249 mov HV_FAST_TOD_GET, %o5
250 ta HV_FAST_TRAP
251 stx %o1, [%o4]
252 retl
253 nop
254 .size sun4v_tod_get, .-sun4v_tod_get
255
256 /* %o0: time
257 *
258 * returns %o0: status
259 */
260 .globl sun4v_tod_set
261 .type sun4v_tod_set,#function
262sun4v_tod_set:
263 mov HV_FAST_TOD_SET, %o5
264 ta HV_FAST_TRAP
265 retl
266 nop
267 .size sun4v_tod_set, .-sun4v_tod_set
268
269 /* %o0: pointer to unsigned long status
270 *
271 * returns %o0: signed character
272 */
273 .globl sun4v_con_getchar
274 .type sun4v_con_getchar,#function
275sun4v_con_getchar:
276 mov %o0, %o4
277 mov HV_FAST_CONS_GETCHAR, %o5
278 clr %o0
279 clr %o1
280 ta HV_FAST_TRAP
281 stx %o0, [%o4]
282 retl
283 sra %o1, 0, %o0
284 .size sun4v_con_getchar, .-sun4v_con_getchar
285
286 /* %o0: signed long character
287 *
288 * returns %o0: status
289 */
290 .globl sun4v_con_putchar
291 .type sun4v_con_putchar,#function
292sun4v_con_putchar:
293 mov HV_FAST_CONS_PUTCHAR, %o5
294 ta HV_FAST_TRAP
295 retl
296 sra %o0, 0, %o0
297 .size sun4v_con_putchar, .-sun4v_con_putchar
298
299 /* %o0: buffer real address
300 * %o1: buffer size
301 * %o2: pointer to unsigned long bytes_read
302 *
303 * returns %o0: status
304 */
305 .globl sun4v_con_read
306 .type sun4v_con_read,#function
307sun4v_con_read:
308 mov %o2, %o4
309 mov HV_FAST_CONS_READ, %o5
310 ta HV_FAST_TRAP
311 brnz %o0, 1f
312 cmp %o1, -1 /* break */
313 be,a,pn %icc, 1f
314 mov %o1, %o0
315 cmp %o1, -2 /* hup */
316 be,a,pn %icc, 1f
317 mov %o1, %o0
318 stx %o1, [%o4]
3191: retl
320 nop
321 .size sun4v_con_read, .-sun4v_con_read
322
323 /* %o0: buffer real address
324 * %o1: buffer size
325 * %o2: pointer to unsigned long bytes_written
326 *
327 * returns %o0: status
328 */
329 .globl sun4v_con_write
330 .type sun4v_con_write,#function
331sun4v_con_write:
332 mov %o2, %o4
333 mov HV_FAST_CONS_WRITE, %o5
334 ta HV_FAST_TRAP
335 stx %o1, [%o4]
336 retl
337 nop
338 .size sun4v_con_write, .-sun4v_con_write
339
340 /* %o0: soft state
341 * %o1: address of description string
342 *
343 * returns %o0: status
344 */
345 .globl sun4v_mach_set_soft_state
346 .type sun4v_mach_set_soft_state,#function
347sun4v_mach_set_soft_state:
348 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
349 ta HV_FAST_TRAP
350 retl
351 nop
352 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state
353
354 /* %o0: exit code
355 *
356 * Does not return.
357 */
358 .globl sun4v_mach_exit
359 .type sun4v_mach_exit,#function
360sun4v_mach_exit:
361 mov HV_FAST_MACH_EXIT, %o5
362 ta HV_FAST_TRAP
363 retl
364 nop
365 .size sun4v_mach_exit, .-sun4v_mach_exit
366
367 /* %o0: buffer real address
368 * %o1: buffer length
369 * %o2: pointer to unsigned long real_buf_len
370 *
371 * returns %o0: status
372 */
373 .globl sun4v_mach_desc
374 .type sun4v_mach_desc,#function
375sun4v_mach_desc:
376 mov %o2, %o4
377 mov HV_FAST_MACH_DESC, %o5
378 ta HV_FAST_TRAP
379 stx %o1, [%o4]
380 retl
381 nop
382 .size sun4v_mach_desc, .-sun4v_mach_desc
383
384 /* %o0: new timeout in milliseconds
385 * %o1: pointer to unsigned long orig_timeout
386 *
387 * returns %o0: status
388 */
389 .globl sun4v_mach_set_watchdog
390 .type sun4v_mach_set_watchdog,#function
391sun4v_mach_set_watchdog:
392 mov %o1, %o4
393 mov HV_FAST_MACH_SET_WATCHDOG, %o5
394 ta HV_FAST_TRAP
395 stx %o1, [%o4]
396 retl
397 nop
398 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog
399
400 /* No inputs and does not return. */
401 .globl sun4v_mach_sir
402 .type sun4v_mach_sir,#function
403sun4v_mach_sir:
404 mov %o1, %o4
405 mov HV_FAST_MACH_SIR, %o5
406 ta HV_FAST_TRAP
407 stx %o1, [%o4]
408 retl
409 nop
410 .size sun4v_mach_sir, .-sun4v_mach_sir
411
412 /* %o0: channel
413 * %o1: ra
414 * %o2: num_entries
415 *
416 * returns %o0: status
417 */
418 .globl sun4v_ldc_tx_qconf
419 .type sun4v_ldc_tx_qconf,#function
420sun4v_ldc_tx_qconf:
421 mov HV_FAST_LDC_TX_QCONF, %o5
422 ta HV_FAST_TRAP
423 retl
424 nop
425 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf
426
427 /* %o0: channel
428 * %o1: pointer to unsigned long ra
429 * %o2: pointer to unsigned long num_entries
430 *
431 * returns %o0: status
432 */
433 .globl sun4v_ldc_tx_qinfo
434 .type sun4v_ldc_tx_qinfo,#function
435sun4v_ldc_tx_qinfo:
436 mov %o1, %g1
437 mov %o2, %g2
438 mov HV_FAST_LDC_TX_QINFO, %o5
439 ta HV_FAST_TRAP
440 stx %o1, [%g1]
441 stx %o2, [%g2]
442 retl
443 nop
444 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo
445
446 /* %o0: channel
447 * %o1: pointer to unsigned long head_off
448 * %o2: pointer to unsigned long tail_off
449 * %o2: pointer to unsigned long chan_state
450 *
451 * returns %o0: status
452 */
453 .globl sun4v_ldc_tx_get_state
454 .type sun4v_ldc_tx_get_state,#function
455sun4v_ldc_tx_get_state:
456 mov %o1, %g1
457 mov %o2, %g2
458 mov %o3, %g3
459 mov HV_FAST_LDC_TX_GET_STATE, %o5
460 ta HV_FAST_TRAP
461 stx %o1, [%g1]
462 stx %o2, [%g2]
463 stx %o3, [%g3]
464 retl
465 nop
466 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state
467
468 /* %o0: channel
469 * %o1: tail_off
470 *
471 * returns %o0: status
472 */
473 .globl sun4v_ldc_tx_set_qtail
474 .type sun4v_ldc_tx_set_qtail,#function
475sun4v_ldc_tx_set_qtail:
476 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
477 ta HV_FAST_TRAP
478 retl
479 nop
480 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail
481
482 /* %o0: channel
483 * %o1: ra
484 * %o2: num_entries
485 *
486 * returns %o0: status
487 */
488 .globl sun4v_ldc_rx_qconf
489 .type sun4v_ldc_rx_qconf,#function
490sun4v_ldc_rx_qconf:
491 mov HV_FAST_LDC_RX_QCONF, %o5
492 ta HV_FAST_TRAP
493 retl
494 nop
495 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf
496
497 /* %o0: channel
498 * %o1: pointer to unsigned long ra
499 * %o2: pointer to unsigned long num_entries
500 *
501 * returns %o0: status
502 */
503 .globl sun4v_ldc_rx_qinfo
504 .type sun4v_ldc_rx_qinfo,#function
505sun4v_ldc_rx_qinfo:
506 mov %o1, %g1
507 mov %o2, %g2
508 mov HV_FAST_LDC_RX_QINFO, %o5
509 ta HV_FAST_TRAP
510 stx %o1, [%g1]
511 stx %o2, [%g2]
512 retl
513 nop
514 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo
515
516 /* %o0: channel
517 * %o1: pointer to unsigned long head_off
518 * %o2: pointer to unsigned long tail_off
519 * %o2: pointer to unsigned long chan_state
520 *
521 * returns %o0: status
522 */
523 .globl sun4v_ldc_rx_get_state
524 .type sun4v_ldc_rx_get_state,#function
525sun4v_ldc_rx_get_state:
526 mov %o1, %g1
527 mov %o2, %g2
528 mov %o3, %g3
529 mov HV_FAST_LDC_RX_GET_STATE, %o5
530 ta HV_FAST_TRAP
531 stx %o1, [%g1]
532 stx %o2, [%g2]
533 stx %o3, [%g3]
534 retl
535 nop
536 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state
537
538 /* %o0: channel
539 * %o1: head_off
540 *
541 * returns %o0: status
542 */
543 .globl sun4v_ldc_rx_set_qhead
544 .type sun4v_ldc_rx_set_qhead,#function
545sun4v_ldc_rx_set_qhead:
546 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
547 ta HV_FAST_TRAP
548 retl
549 nop
550 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead
551
552 /* %o0: channel
553 * %o1: ra
554 * %o2: num_entries
555 *
556 * returns %o0: status
557 */
558 .globl sun4v_ldc_set_map_table
559 .type sun4v_ldc_set_map_table,#function
560sun4v_ldc_set_map_table:
561 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
562 ta HV_FAST_TRAP
563 retl
564 nop
565 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table
566
567 /* %o0: channel
568 * %o1: pointer to unsigned long ra
569 * %o2: pointer to unsigned long num_entries
570 *
571 * returns %o0: status
572 */
573 .globl sun4v_ldc_get_map_table
574 .type sun4v_ldc_get_map_table,#function
575sun4v_ldc_get_map_table:
576 mov %o1, %g1
577 mov %o2, %g2
578 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
579 ta HV_FAST_TRAP
580 stx %o1, [%g1]
581 stx %o2, [%g2]
582 retl
583 nop
584 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table
585
586 /* %o0: channel
587 * %o1: dir_code
588 * %o2: tgt_raddr
589 * %o3: lcl_raddr
590 * %o4: len
591 * %o5: pointer to unsigned long actual_len
592 *
593 * returns %o0: status
594 */
595 .globl sun4v_ldc_copy
596 .type sun4v_ldc_copy,#function
597sun4v_ldc_copy:
598 mov %o5, %g1
599 mov HV_FAST_LDC_COPY, %o5
600 ta HV_FAST_TRAP
601 stx %o1, [%g1]
602 retl
603 nop
604 .size sun4v_ldc_copy, .-sun4v_ldc_copy
605
606 /* %o0: channel
607 * %o1: cookie
608 * %o2: pointer to unsigned long ra
609 * %o3: pointer to unsigned long perm
610 *
611 * returns %o0: status
612 */
613 .globl sun4v_ldc_mapin
614 .type sun4v_ldc_mapin,#function
615sun4v_ldc_mapin:
616 mov %o2, %g1
617 mov %o3, %g2
618 mov HV_FAST_LDC_MAPIN, %o5
619 ta HV_FAST_TRAP
620 stx %o1, [%g1]
621 stx %o2, [%g2]
622 retl
623 nop
624 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin
625
626 /* %o0: ra
627 *
628 * returns %o0: status
629 */
630 .globl sun4v_ldc_unmap
631 .type sun4v_ldc_unmap,#function
632sun4v_ldc_unmap:
633 mov HV_FAST_LDC_UNMAP, %o5
634 ta HV_FAST_TRAP
635 retl
636 nop
637 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap
638
639 /* %o0: channel
640 * %o1: cookie
641 * %o2: mte_cookie
642 *
643 * returns %o0: status
644 */
645 .globl sun4v_ldc_revoke
646 .type sun4v_ldc_revoke,#function
647sun4v_ldc_revoke:
648 mov HV_FAST_LDC_REVOKE, %o5
649 ta HV_FAST_TRAP
650 retl
651 nop
652 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke
653
654 /* %o0: device handle
655 * %o1: device INO
656 * %o2: pointer to unsigned long cookie
657 *
658 * returns %o0: status
659 */
660 .globl sun4v_vintr_get_cookie
661 .type sun4v_vintr_get_cookie,#function
662sun4v_vintr_get_cookie:
663 mov %o2, %g1
664 mov HV_FAST_VINTR_GET_COOKIE, %o5
665 ta HV_FAST_TRAP
666 stx %o1, [%g1]
667 retl
668 nop
669 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie
670
671 /* %o0: device handle
672 * %o1: device INO
673 * %o2: cookie
674 *
675 * returns %o0: status
676 */
677 .globl sun4v_vintr_set_cookie
678 .type sun4v_vintr_set_cookie,#function
679sun4v_vintr_set_cookie:
680 mov HV_FAST_VINTR_SET_COOKIE, %o5
681 ta HV_FAST_TRAP
682 retl
683 nop
684 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie
685
686 /* %o0: device handle
687 * %o1: device INO
688 * %o2: pointer to unsigned long valid_state
689 *
690 * returns %o0: status
691 */
692 .globl sun4v_vintr_get_valid
693 .type sun4v_vintr_get_valid,#function
694sun4v_vintr_get_valid:
695 mov %o2, %g1
696 mov HV_FAST_VINTR_GET_VALID, %o5
697 ta HV_FAST_TRAP
698 stx %o1, [%g1]
699 retl
700 nop
701 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid
702
703 /* %o0: device handle
704 * %o1: device INO
705 * %o2: valid_state
706 *
707 * returns %o0: status
708 */
709 .globl sun4v_vintr_set_valid
710 .type sun4v_vintr_set_valid,#function
711sun4v_vintr_set_valid:
712 mov HV_FAST_VINTR_SET_VALID, %o5
713 ta HV_FAST_TRAP
714 retl
715 nop
716 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid
717
718 /* %o0: device handle
719 * %o1: device INO
720 * %o2: pointer to unsigned long state
721 *
722 * returns %o0: status
723 */
724 .globl sun4v_vintr_get_state
725 .type sun4v_vintr_get_state,#function
726sun4v_vintr_get_state:
727 mov %o2, %g1
728 mov HV_FAST_VINTR_GET_STATE, %o5
729 ta HV_FAST_TRAP
730 stx %o1, [%g1]
731 retl
732 nop
733 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state
734
735 /* %o0: device handle
736 * %o1: device INO
737 * %o2: state
738 *
739 * returns %o0: status
740 */
741 .globl sun4v_vintr_set_state
742 .type sun4v_vintr_set_state,#function
743sun4v_vintr_set_state:
744 mov HV_FAST_VINTR_SET_STATE, %o5
745 ta HV_FAST_TRAP
746 retl
747 nop
748 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state
749
750 /* %o0: device handle
751 * %o1: device INO
752 * %o2: pointer to unsigned long cpuid
753 *
754 * returns %o0: status
755 */
756 .globl sun4v_vintr_get_target
757 .type sun4v_vintr_get_target,#function
758sun4v_vintr_get_target:
759 mov %o2, %g1
760 mov HV_FAST_VINTR_GET_TARGET, %o5
761 ta HV_FAST_TRAP
762 stx %o1, [%g1]
763 retl
764 nop
765 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target
766
767 /* %o0: device handle
768 * %o1: device INO
769 * %o2: cpuid
770 *
771 * returns %o0: status
772 */
773 .globl sun4v_vintr_set_target
774 .type sun4v_vintr_set_target,#function
775sun4v_vintr_set_target:
776 mov HV_FAST_VINTR_SET_TARGET, %o5
777 ta HV_FAST_TRAP
778 retl
779 nop
780 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target
781
782 /* %o0: NCS sub-function
783 * %o1: sub-function arg real-address
784 * %o2: sub-function arg size
785 *
786 * returns %o0: status
787 */
788 .globl sun4v_ncs_request
789 .type sun4v_ncs_request,#function
790sun4v_ncs_request:
791 mov HV_FAST_NCS_REQUEST, %o5
792 ta HV_FAST_TRAP
793 retl
794 nop
795 .size sun4v_ncs_request, .-sun4v_ncs_request
796
797 .globl sun4v_svc_send
798 .type sun4v_svc_send,#function
799sun4v_svc_send:
800 save %sp, -192, %sp
801 mov %i0, %o0
802 mov %i1, %o1
803 mov %i2, %o2
804 mov HV_FAST_SVC_SEND, %o5
805 ta HV_FAST_TRAP
806 stx %o1, [%i3]
807 ret
808 restore
809 .size sun4v_svc_send, .-sun4v_svc_send
810
811 .globl sun4v_svc_recv
812 .type sun4v_svc_recv,#function
813sun4v_svc_recv:
814 save %sp, -192, %sp
815 mov %i0, %o0
816 mov %i1, %o1
817 mov %i2, %o2
818 mov HV_FAST_SVC_RECV, %o5
819 ta HV_FAST_TRAP
820 stx %o1, [%i3]
821 ret
822 restore
823 .size sun4v_svc_recv, .-sun4v_svc_recv
824
825 .globl sun4v_svc_getstatus
826 .type sun4v_svc_getstatus,#function
827sun4v_svc_getstatus:
828 mov HV_FAST_SVC_GETSTATUS, %o5
829 mov %o1, %o4
830 ta HV_FAST_TRAP
831 stx %o1, [%o4]
832 retl
833 nop
834 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus
835
836 .globl sun4v_svc_setstatus
837 .type sun4v_svc_setstatus,#function
838sun4v_svc_setstatus:
839 mov HV_FAST_SVC_SETSTATUS, %o5
840 ta HV_FAST_TRAP
841 retl
842 nop
843 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus
844
845 .globl sun4v_svc_clrstatus
846 .type sun4v_svc_clrstatus,#function
847sun4v_svc_clrstatus:
848 mov HV_FAST_SVC_CLRSTATUS, %o5
849 ta HV_FAST_TRAP
850 retl
851 nop
852 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus
853
854 .globl sun4v_mmustat_conf
855 .type sun4v_mmustat_conf,#function
856sun4v_mmustat_conf:
857 mov %o1, %o4
858 mov HV_FAST_MMUSTAT_CONF, %o5
859 ta HV_FAST_TRAP
860 stx %o1, [%o4]
861 retl
862 nop
863 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf
864
865 .globl sun4v_mmustat_info
866 .type sun4v_mmustat_info,#function
867sun4v_mmustat_info:
868 mov %o0, %o4
869 mov HV_FAST_MMUSTAT_INFO, %o5
870 ta HV_FAST_TRAP
871 stx %o1, [%o4]
872 retl
873 nop
874 .size sun4v_mmustat_info, .-sun4v_mmustat_info
875
876 .globl sun4v_mmu_demap_all
877 .type sun4v_mmu_demap_all,#function
878sun4v_mmu_demap_all:
879 clr %o0
880 clr %o1
881 mov HV_MMU_ALL, %o2
882 mov HV_FAST_MMU_DEMAP_ALL, %o5
883 ta HV_FAST_TRAP
884 retl
885 nop
886 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all
diff --git a/arch/sparc64/kernel/ivec.S b/arch/sparc64/kernel/ivec.S
new file mode 100644
index 000000000000..d29f92ebca5e
--- /dev/null
+++ b/arch/sparc64/kernel/ivec.S
@@ -0,0 +1,51 @@
1 /* The registers for cross calls will be:
2 *
3 * DATA 0: [low 32-bits] Address of function to call, jmp to this
4 * [high 32-bits] MMU Context Argument 0, place in %g5
5 * DATA 1: Address Argument 1, place in %g1
6 * DATA 2: Address Argument 2, place in %g7
7 *
8 * With this method we can do most of the cross-call tlb/cache
9 * flushing very quickly.
10 */
11 .align 32
12 .globl do_ivec
13 .type do_ivec,#function
14do_ivec:
15 mov 0x40, %g3
16 ldxa [%g3 + %g0] ASI_INTR_R, %g3
17 sethi %hi(KERNBASE), %g4
18 cmp %g3, %g4
19 bgeu,pn %xcc, do_ivec_xcall
20 srlx %g3, 32, %g5
21 stxa %g0, [%g0] ASI_INTR_RECEIVE
22 membar #Sync
23
24 sethi %hi(ivector_table_pa), %g2
25 ldx [%g2 + %lo(ivector_table_pa)], %g2
26 sllx %g3, 4, %g3
27 add %g2, %g3, %g3
28
29 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
30
31 ldx [%g6], %g5
32 stxa %g5, [%g3] ASI_PHYS_USE_EC
33 stx %g3, [%g6]
34 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
35 retry
36do_ivec_xcall:
37 mov 0x50, %g1
38 ldxa [%g1 + %g0] ASI_INTR_R, %g1
39 srl %g3, 0, %g3
40
41 mov 0x60, %g7
42 ldxa [%g7 + %g0] ASI_INTR_R, %g7
43 stxa %g0, [%g0] ASI_INTR_RECEIVE
44 membar #Sync
45 ba,pt %xcc, 1f
46 nop
47
48 .align 32
491: jmpl %g3, %g0
50 nop
51 .size do_ivec,.-do_ivec
diff --git a/arch/sparc64/kernel/kgdb.c b/arch/sparc64/kernel/kgdb.c
new file mode 100644
index 000000000000..fefbe6dc51be
--- /dev/null
+++ b/arch/sparc64/kernel/kgdb.c
@@ -0,0 +1,186 @@
1/* kgdb.c: KGDB support for 64-bit sparc.
2 *
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */
5
6#include <linux/kgdb.h>
7#include <linux/kdebug.h>
8
9#include <asm/kdebug.h>
10#include <asm/ptrace.h>
11#include <asm/irq.h>
12
13void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
14{
15 struct reg_window *win;
16 int i;
17
18 gdb_regs[GDB_G0] = 0;
19 for (i = 0; i < 15; i++)
20 gdb_regs[GDB_G1 + i] = regs->u_regs[UREG_G1 + i];
21
22 win = (struct reg_window *) (regs->u_regs[UREG_FP] + STACK_BIAS);
23 for (i = 0; i < 8; i++)
24 gdb_regs[GDB_L0 + i] = win->locals[i];
25 for (i = 0; i < 8; i++)
26 gdb_regs[GDB_I0 + i] = win->ins[i];
27
28 for (i = GDB_F0; i <= GDB_F62; i++)
29 gdb_regs[i] = 0;
30
31 gdb_regs[GDB_PC] = regs->tpc;
32 gdb_regs[GDB_NPC] = regs->tnpc;
33 gdb_regs[GDB_STATE] = regs->tstate;
34 gdb_regs[GDB_FSR] = 0;
35 gdb_regs[GDB_FPRS] = 0;
36 gdb_regs[GDB_Y] = regs->y;
37}
38
39void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
40{
41 struct thread_info *t = task_thread_info(p);
42 extern unsigned int switch_to_pc;
43 extern unsigned int ret_from_syscall;
44 struct reg_window *win;
45 unsigned long pc, cwp;
46 int i;
47
48 for (i = GDB_G0; i < GDB_G6; i++)
49 gdb_regs[i] = 0;
50 gdb_regs[GDB_G6] = (unsigned long) t;
51 gdb_regs[GDB_G7] = (unsigned long) p;
52 for (i = GDB_O0; i < GDB_SP; i++)
53 gdb_regs[i] = 0;
54 gdb_regs[GDB_SP] = t->ksp;
55 gdb_regs[GDB_O7] = 0;
56
57 win = (struct reg_window *) (t->ksp + STACK_BIAS);
58 for (i = 0; i < 8; i++)
59 gdb_regs[GDB_L0 + i] = win->locals[i];
60 for (i = 0; i < 8; i++)
61 gdb_regs[GDB_I0 + i] = win->ins[i];
62
63 for (i = GDB_F0; i <= GDB_F62; i++)
64 gdb_regs[i] = 0;
65
66 if (t->new_child)
67 pc = (unsigned long) &ret_from_syscall;
68 else
69 pc = (unsigned long) &switch_to_pc;
70
71 gdb_regs[GDB_PC] = pc;
72 gdb_regs[GDB_NPC] = pc + 4;
73
74 cwp = __thread_flag_byte_ptr(t)[TI_FLAG_BYTE_CWP];
75
76 gdb_regs[GDB_STATE] = (TSTATE_PRIV | TSTATE_IE | cwp);
77 gdb_regs[GDB_FSR] = 0;
78 gdb_regs[GDB_FPRS] = 0;
79 gdb_regs[GDB_Y] = 0;
80}
81
82void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
83{
84 struct reg_window *win;
85 int i;
86
87 for (i = 0; i < 15; i++)
88 regs->u_regs[UREG_G1 + i] = gdb_regs[GDB_G1 + i];
89
90 /* If the TSTATE register is changing, we have to preserve
91 * the CWP field, otherwise window save/restore explodes.
92 */
93 if (regs->tstate != gdb_regs[GDB_STATE]) {
94 unsigned long cwp = regs->tstate & TSTATE_CWP;
95
96 regs->tstate = (gdb_regs[GDB_STATE] & ~TSTATE_CWP) | cwp;
97 }
98
99 regs->tpc = gdb_regs[GDB_PC];
100 regs->tnpc = gdb_regs[GDB_NPC];
101 regs->y = gdb_regs[GDB_Y];
102
103 win = (struct reg_window *) (regs->u_regs[UREG_FP] + STACK_BIAS);
104 for (i = 0; i < 8; i++)
105 win->locals[i] = gdb_regs[GDB_L0 + i];
106 for (i = 0; i < 8; i++)
107 win->ins[i] = gdb_regs[GDB_I0 + i];
108}
109
110#ifdef CONFIG_SMP
111void smp_kgdb_capture_client(struct pt_regs *regs)
112{
113 unsigned long flags;
114
115 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
116 "wrpr %0, %1, %%pstate"
117 : "=r" (flags)
118 : "i" (PSTATE_IE));
119
120 flushw_all();
121
122 if (atomic_read(&kgdb_active) != -1)
123 kgdb_nmicallback(raw_smp_processor_id(), regs);
124
125 __asm__ __volatile__("wrpr %0, 0, %%pstate"
126 : : "r" (flags));
127}
128#endif
129
130int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
131 char *remcomInBuffer, char *remcomOutBuffer,
132 struct pt_regs *linux_regs)
133{
134 unsigned long addr;
135 char *ptr;
136
137 switch (remcomInBuffer[0]) {
138 case 'c':
139 /* try to read optional parameter, pc unchanged if no parm */
140 ptr = &remcomInBuffer[1];
141 if (kgdb_hex2long(&ptr, &addr)) {
142 linux_regs->tpc = addr;
143 linux_regs->tnpc = addr + 4;
144 }
145 /* fallthru */
146
147 case 'D':
148 case 'k':
149 if (linux_regs->tpc == (unsigned long) arch_kgdb_breakpoint) {
150 linux_regs->tpc = linux_regs->tnpc;
151 linux_regs->tnpc += 4;
152 }
153 return 0;
154 }
155 return -1;
156}
157
158asmlinkage void kgdb_trap(unsigned long trap_level, struct pt_regs *regs)
159{
160 unsigned long flags;
161
162 if (user_mode(regs)) {
163 bad_trap(regs, trap_level);
164 return;
165 }
166
167 flushw_all();
168
169 local_irq_save(flags);
170 kgdb_handle_exception(0x172, SIGTRAP, 0, regs);
171 local_irq_restore(flags);
172}
173
174int kgdb_arch_init(void)
175{
176 return 0;
177}
178
179void kgdb_arch_exit(void)
180{
181}
182
183struct kgdb_arch arch_kgdb_ops = {
184 /* Breakpoint instruction: ta 0x72 */
185 .gdb_bpt_instr = { 0x91, 0xd0, 0x20, 0x72 },
186};
diff --git a/arch/sparc64/kernel/misctrap.S b/arch/sparc64/kernel/misctrap.S
new file mode 100644
index 000000000000..753b4f031bfb
--- /dev/null
+++ b/arch/sparc64/kernel/misctrap.S
@@ -0,0 +1,97 @@
1#ifdef CONFIG_KGDB
2 .globl arch_kgdb_breakpoint
3 .type arch_kgdb_breakpoint,#function
4arch_kgdb_breakpoint:
5 ta 0x72
6 retl
7 nop
8 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
9#endif
10
11 .type __do_privact,#function
12__do_privact:
13 mov TLB_SFSR, %g3
14 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
15 membar #Sync
16 sethi %hi(109f), %g7
17 ba,pt %xcc, etrap
18109: or %g7, %lo(109b), %g7
19 call do_privact
20 add %sp, PTREGS_OFF, %o0
21 ba,pt %xcc, rtrap
22 nop
23 .size __do_privact,.-__do_privact
24
25 .type do_mna,#function
26do_mna:
27 rdpr %tl, %g3
28 cmp %g3, 1
29
30 /* Setup %g4/%g5 now as they are used in the
31 * winfixup code.
32 */
33 mov TLB_SFSR, %g3
34 mov DMMU_SFAR, %g4
35 ldxa [%g4] ASI_DMMU, %g4
36 ldxa [%g3] ASI_DMMU, %g5
37 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
38 membar #Sync
39 bgu,pn %icc, winfix_mna
40 rdpr %tpc, %g3
41
421: sethi %hi(109f), %g7
43 ba,pt %xcc, etrap
44109: or %g7, %lo(109b), %g7
45 mov %l4, %o1
46 mov %l5, %o2
47 call mem_address_unaligned
48 add %sp, PTREGS_OFF, %o0
49 ba,pt %xcc, rtrap
50 nop
51 .size do_mna,.-do_mna
52
53 .type do_lddfmna,#function
54do_lddfmna:
55 sethi %hi(109f), %g7
56 mov TLB_SFSR, %g4
57 ldxa [%g4] ASI_DMMU, %g5
58 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
59 membar #Sync
60 mov DMMU_SFAR, %g4
61 ldxa [%g4] ASI_DMMU, %g4
62 ba,pt %xcc, etrap
63109: or %g7, %lo(109b), %g7
64 mov %l4, %o1
65 mov %l5, %o2
66 call handle_lddfmna
67 add %sp, PTREGS_OFF, %o0
68 ba,pt %xcc, rtrap
69 nop
70 .size do_lddfmna,.-do_lddfmna
71
72 .type do_stdfmna,#function
73do_stdfmna:
74 sethi %hi(109f), %g7
75 mov TLB_SFSR, %g4
76 ldxa [%g4] ASI_DMMU, %g5
77 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
78 membar #Sync
79 mov DMMU_SFAR, %g4
80 ldxa [%g4] ASI_DMMU, %g4
81 ba,pt %xcc, etrap
82109: or %g7, %lo(109b), %g7
83 mov %l4, %o1
84 mov %l5, %o2
85 call handle_stdfmna
86 add %sp, PTREGS_OFF, %o0
87 ba,pt %xcc, rtrap
88 nop
89 .size do_stdfmna,.-do_stdfmna
90
91 .type breakpoint_trap,#function
92breakpoint_trap:
93 call sparc_breakpoint
94 add %sp, PTREGS_OFF, %o0
95 ba,pt %xcc, rtrap
96 nop
97 .size breakpoint_trap,.-breakpoint_trap
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 409dd71f2738..3aba47624df4 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -38,7 +38,6 @@
38#include <asm/pgtable.h> 38#include <asm/pgtable.h>
39#include <asm/oplib.h> 39#include <asm/oplib.h>
40#include <asm/uaccess.h> 40#include <asm/uaccess.h>
41#include <asm/timer.h>
42#include <asm/starfire.h> 41#include <asm/starfire.h>
43#include <asm/tlb.h> 42#include <asm/tlb.h>
44#include <asm/sections.h> 43#include <asm/sections.h>
@@ -910,6 +909,9 @@ extern unsigned long xcall_flush_tlb_kernel_range;
910extern unsigned long xcall_report_regs; 909extern unsigned long xcall_report_regs;
911extern unsigned long xcall_receive_signal; 910extern unsigned long xcall_receive_signal;
912extern unsigned long xcall_new_mmu_context_version; 911extern unsigned long xcall_new_mmu_context_version;
912#ifdef CONFIG_KGDB
913extern unsigned long xcall_kgdb_capture;
914#endif
913 915
914#ifdef DCACHE_ALIASING_POSSIBLE 916#ifdef DCACHE_ALIASING_POSSIBLE
915extern unsigned long xcall_flush_dcache_page_cheetah; 917extern unsigned long xcall_flush_dcache_page_cheetah;
@@ -1079,6 +1081,13 @@ void smp_new_mmu_context_version(void)
1079 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); 1081 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1080} 1082}
1081 1083
1084#ifdef CONFIG_KGDB
1085void kgdb_roundup_cpus(unsigned long flags)
1086{
1087 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1088}
1089#endif
1090
1082void smp_report_regs(void) 1091void smp_report_regs(void)
1083{ 1092{
1084 smp_cross_call(&xcall_report_regs, 0, 0, 0); 1093 smp_cross_call(&xcall_report_regs, 0, 0, 0);
diff --git a/arch/sparc64/kernel/spiterrs.S b/arch/sparc64/kernel/spiterrs.S
new file mode 100644
index 000000000000..ef902c6f8e3c
--- /dev/null
+++ b/arch/sparc64/kernel/spiterrs.S
@@ -0,0 +1,245 @@
1 /* We need to carefully read the error status, ACK the errors,
2 * prevent recursive traps, and pass the information on to C
3 * code for logging.
4 *
5 * We pass the AFAR in as-is, and we encode the status
6 * information as described in asm-sparc64/sfafsr.h
7 */
8 .type __spitfire_access_error,#function
9__spitfire_access_error:
10 /* Disable ESTATE error reporting so that we do not take
11 * recursive traps and RED state the processor.
12 */
13 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
14 membar #Sync
15
16 mov UDBE_UE, %g1
17 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
18
19 /* __spitfire_cee_trap branches here with AFSR in %g4 and
20 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the ESTATE
21 * Error Enable register.
22 */
23__spitfire_cee_trap_continue:
24 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
25
26 rdpr %tt, %g3
27 and %g3, 0x1ff, %g3 ! Paranoia
28 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
29 or %g4, %g3, %g4
30 rdpr %tl, %g3
31 cmp %g3, 1
32 mov 1, %g3
33 bleu %xcc, 1f
34 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
35
36 or %g4, %g3, %g4
37
38 /* Read in the UDB error register state, clearing the sticky
39 * error bits as-needed. We only clear them if the UE bit is
40 * set. Likewise, __spitfire_cee_trap below will only do so
41 * if the CE bit is set.
42 *
43 * NOTE: UltraSparc-I/II have high and low UDB error
44 * registers, corresponding to the two UDB units
45 * present on those chips. UltraSparc-IIi only
46 * has a single UDB, called "SDB" in the manual.
47 * For IIi the upper UDB register always reads
48 * as zero so for our purposes things will just
49 * work with the checks below.
50 */
511: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
52 and %g3, 0x3ff, %g7 ! Paranoia
53 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
54 or %g4, %g7, %g4
55 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
56 be,pn %xcc, 1f
57 nop
58 stxa %g3, [%g0] ASI_UDB_ERROR_W
59 membar #Sync
60
611: mov 0x18, %g3
62 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
63 and %g3, 0x3ff, %g7 ! Paranoia
64 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
65 or %g4, %g7, %g4
66 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
67 be,pn %xcc, 1f
68 nop
69 mov 0x18, %g7
70 stxa %g3, [%g7] ASI_UDB_ERROR_W
71 membar #Sync
72
731: /* Ok, now that we've latched the error state, clear the
74 * sticky bits in the AFSR.
75 */
76 stxa %g4, [%g0] ASI_AFSR
77 membar #Sync
78
79 rdpr %tl, %g2
80 cmp %g2, 1
81 rdpr %pil, %g2
82 bleu,pt %xcc, 1f
83 wrpr %g0, 15, %pil
84
85 ba,pt %xcc, etraptl1
86 rd %pc, %g7
87
88 ba,pt %xcc, 2f
89 nop
90
911: ba,pt %xcc, etrap_irq
92 rd %pc, %g7
93
942:
95#ifdef CONFIG_TRACE_IRQFLAGS
96 call trace_hardirqs_off
97 nop
98#endif
99 mov %l4, %o1
100 mov %l5, %o2
101 call spitfire_access_error
102 add %sp, PTREGS_OFF, %o0
103 ba,pt %xcc, rtrap
104 nop
105 .size __spitfire_access_error,.-__spitfire_access_error
106
107 /* This is the trap handler entry point for ECC correctable
108 * errors. They are corrected, but we listen for the trap so
109 * that the event can be logged.
110 *
111 * Disrupting errors are either:
112 * 1) single-bit ECC errors during UDB reads to system
113 * memory
114 * 2) data parity errors during write-back events
115 *
116 * As far as I can make out from the manual, the CEE trap is
117 * only for correctable errors during memory read accesses by
118 * the front-end of the processor.
119 *
120 * The code below is only for trap level 1 CEE events, as it
121 * is the only situation where we can safely record and log.
122 * For trap level >1 we just clear the CE bit in the AFSR and
123 * return.
124 *
125 * This is just like __spiftire_access_error above, but it
126 * specifically handles correctable errors. If an
127 * uncorrectable error is indicated in the AFSR we will branch
128 * directly above to __spitfire_access_error to handle it
129 * instead. Uncorrectable therefore takes priority over
130 * correctable, and the error logging C code will notice this
131 * case by inspecting the trap type.
132 */
133 .type __spitfire_cee_trap,#function
134__spitfire_cee_trap:
135 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
136 mov 1, %g3
137 sllx %g3, SFAFSR_UE_SHIFT, %g3
138 andcc %g4, %g3, %g0 ! Check for UE
139 bne,pn %xcc, __spitfire_access_error
140 nop
141
142 /* Ok, in this case we only have a correctable error.
143 * Indicate we only wish to capture that state in register
144 * %g1, and we only disable CE error reporting unlike UE
145 * handling which disables all errors.
146 */
147 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
148 andn %g3, ESTATE_ERR_CE, %g3
149 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
150 membar #Sync
151
152 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
153 ba,pt %xcc, __spitfire_cee_trap_continue
154 mov UDBE_CE, %g1
155 .size __spitfire_cee_trap,.-__spitfire_cee_trap
156
157 .type __spitfire_data_access_exception_tl1,#function
158__spitfire_data_access_exception_tl1:
159 rdpr %pstate, %g4
160 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
161 mov TLB_SFSR, %g3
162 mov DMMU_SFAR, %g5
163 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
164 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
165 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
166 membar #Sync
167 rdpr %tt, %g3
168 cmp %g3, 0x80 ! first win spill/fill trap
169 blu,pn %xcc, 1f
170 cmp %g3, 0xff ! last win spill/fill trap
171 bgu,pn %xcc, 1f
172 nop
173 ba,pt %xcc, winfix_dax
174 rdpr %tpc, %g3
1751: sethi %hi(109f), %g7
176 ba,pt %xcc, etraptl1
177109: or %g7, %lo(109b), %g7
178 mov %l4, %o1
179 mov %l5, %o2
180 call spitfire_data_access_exception_tl1
181 add %sp, PTREGS_OFF, %o0
182 ba,pt %xcc, rtrap
183 nop
184 .size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
185
186 .type __spitfire_data_access_exception,#function
187__spitfire_data_access_exception:
188 rdpr %pstate, %g4
189 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
190 mov TLB_SFSR, %g3
191 mov DMMU_SFAR, %g5
192 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
193 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
194 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
195 membar #Sync
196 sethi %hi(109f), %g7
197 ba,pt %xcc, etrap
198109: or %g7, %lo(109b), %g7
199 mov %l4, %o1
200 mov %l5, %o2
201 call spitfire_data_access_exception
202 add %sp, PTREGS_OFF, %o0
203 ba,pt %xcc, rtrap
204 nop
205 .size __spitfire_data_access_exception,.-__spitfire_data_access_exception
206
207 .type __spitfire_insn_access_exception_tl1,#function
208__spitfire_insn_access_exception_tl1:
209 rdpr %pstate, %g4
210 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
211 mov TLB_SFSR, %g3
212 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
213 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
214 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
215 membar #Sync
216 sethi %hi(109f), %g7
217 ba,pt %xcc, etraptl1
218109: or %g7, %lo(109b), %g7
219 mov %l4, %o1
220 mov %l5, %o2
221 call spitfire_insn_access_exception_tl1
222 add %sp, PTREGS_OFF, %o0
223 ba,pt %xcc, rtrap
224 nop
225 .size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
226
227 .type __spitfire_insn_access_exception,#function
228__spitfire_insn_access_exception:
229 rdpr %pstate, %g4
230 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
231 mov TLB_SFSR, %g3
232 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
233 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
234 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
235 membar #Sync
236 sethi %hi(109f), %g7
237 ba,pt %xcc, etrap
238109: or %g7, %lo(109b), %g7
239 mov %l4, %o1
240 mov %l5, %o2
241 call spitfire_insn_access_exception
242 add %sp, PTREGS_OFF, %o0
243 ba,pt %xcc, rtrap
244 nop
245 .size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception
diff --git a/arch/sparc64/kernel/syscalls.S b/arch/sparc64/kernel/syscalls.S
new file mode 100644
index 000000000000..db19ed67acf6
--- /dev/null
+++ b/arch/sparc64/kernel/syscalls.S
@@ -0,0 +1,279 @@
1 /* SunOS's execv() call only specifies the argv argument, the
2 * environment settings are the same as the calling processes.
3 */
4sys_execve:
5 sethi %hi(sparc_execve), %g1
6 ba,pt %xcc, execve_merge
7 or %g1, %lo(sparc_execve), %g1
8
9#ifdef CONFIG_COMPAT
10sunos_execv:
11 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
12sys32_execve:
13 sethi %hi(sparc32_execve), %g1
14 or %g1, %lo(sparc32_execve), %g1
15#endif
16
17execve_merge:
18 flushw
19 jmpl %g1, %g0
20 add %sp, PTREGS_OFF, %o0
21
22 .align 32
23sys_pipe:
24 ba,pt %xcc, sparc_pipe
25 add %sp, PTREGS_OFF, %o0
26sys_nis_syscall:
27 ba,pt %xcc, c_sys_nis_syscall
28 add %sp, PTREGS_OFF, %o0
29sys_memory_ordering:
30 ba,pt %xcc, sparc_memory_ordering
31 add %sp, PTREGS_OFF, %o1
32sys_sigaltstack:
33 ba,pt %xcc, do_sigaltstack
34 add %i6, STACK_BIAS, %o2
35#ifdef CONFIG_COMPAT
36sys32_sigstack:
37 ba,pt %xcc, do_sys32_sigstack
38 mov %i6, %o2
39sys32_sigaltstack:
40 ba,pt %xcc, do_sys32_sigaltstack
41 mov %i6, %o2
42#endif
43 .align 32
44#ifdef CONFIG_COMPAT
45sys32_sigreturn:
46 add %sp, PTREGS_OFF, %o0
47 call do_sigreturn32
48 add %o7, 1f-.-4, %o7
49 nop
50#endif
51sys_rt_sigreturn:
52 add %sp, PTREGS_OFF, %o0
53 call do_rt_sigreturn
54 add %o7, 1f-.-4, %o7
55 nop
56#ifdef CONFIG_COMPAT
57sys32_rt_sigreturn:
58 add %sp, PTREGS_OFF, %o0
59 call do_rt_sigreturn32
60 add %o7, 1f-.-4, %o7
61 nop
62#endif
63 .align 32
641: ldx [%g6 + TI_FLAGS], %l5
65 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
66 be,pt %icc, rtrap
67 nop
68 add %sp, PTREGS_OFF, %o0
69 call syscall_trace
70 mov 1, %o1
71 ba,pt %xcc, rtrap
72 nop
73
74 /* This is how fork() was meant to be done, 8 instruction entry.
75 *
76 * I questioned the following code briefly, let me clear things
77 * up so you must not reason on it like I did.
78 *
79 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
80 * need it here because the only piece of window state we copy to
81 * the child is the CWP register. Even if the parent sleeps,
82 * we are safe because we stuck it into pt_regs of the parent
83 * so it will not change.
84 *
85 * XXX This raises the question, whether we can do the same on
86 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
87 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
88 * XXX fork_kwim in UREG_G1 (global registers are considered
89 * XXX volatile across a system call in the sparc ABI I think
90 * XXX if it isn't we can use regs->y instead, anyone who depends
91 * XXX upon the Y register being preserved across a fork deserves
92 * XXX to lose).
93 *
94 * In fact we should take advantage of that fact for other things
95 * during system calls...
96 */
97 .align 32
98sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
99 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
100 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
101 ba,pt %xcc, sys_clone
102sys_fork:
103 clr %o1
104 mov SIGCHLD, %o0
105sys_clone:
106 flushw
107 movrz %o1, %fp, %o1
108 mov 0, %o3
109 ba,pt %xcc, sparc_do_fork
110 add %sp, PTREGS_OFF, %o2
111
112 .globl ret_from_syscall
113ret_from_syscall:
114 /* Clear current_thread_info()->new_child, and
115 * check performance counter stuff too.
116 */
117 stb %g0, [%g6 + TI_NEW_CHILD]
118 ldx [%g6 + TI_FLAGS], %l0
119 call schedule_tail
120 mov %g7, %o0
121 andcc %l0, _TIF_PERFCTR, %g0
122 be,pt %icc, 1f
123 nop
124 ldx [%g6 + TI_PCR], %o7
125 wr %g0, %o7, %pcr
126
127 /* Blackbird errata workaround. See commentary in
128 * smp.c:smp_percpu_timer_interrupt() for more
129 * information.
130 */
131 ba,pt %xcc, 99f
132 nop
133
134 .align 64
13599: wr %g0, %g0, %pic
136 rd %pic, %g0
137
1381: ba,pt %xcc, ret_sys_call
139 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
140
141 .globl sparc_exit
142 .type sparc_exit,#function
143sparc_exit:
144 rdpr %pstate, %g2
145 wrpr %g2, PSTATE_IE, %pstate
146 rdpr %otherwin, %g1
147 rdpr %cansave, %g3
148 add %g3, %g1, %g3
149 wrpr %g3, 0x0, %cansave
150 wrpr %g0, 0x0, %otherwin
151 wrpr %g2, 0x0, %pstate
152 ba,pt %xcc, sys_exit
153 stb %g0, [%g6 + TI_WSAVED]
154 .size sparc_exit,.-sparc_exit
155
156linux_sparc_ni_syscall:
157 sethi %hi(sys_ni_syscall), %l7
158 ba,pt %xcc, 4f
159 or %l7, %lo(sys_ni_syscall), %l7
160
161linux_syscall_trace32:
162 add %sp, PTREGS_OFF, %o0
163 call syscall_trace
164 clr %o1
165 srl %i0, 0, %o0
166 srl %i4, 0, %o4
167 srl %i1, 0, %o1
168 srl %i2, 0, %o2
169 ba,pt %xcc, 2f
170 srl %i3, 0, %o3
171
172linux_syscall_trace:
173 add %sp, PTREGS_OFF, %o0
174 call syscall_trace
175 clr %o1
176 mov %i0, %o0
177 mov %i1, %o1
178 mov %i2, %o2
179 mov %i3, %o3
180 b,pt %xcc, 2f
181 mov %i4, %o4
182
183
184 /* Linux 32-bit system calls enter here... */
185 .align 32
186 .globl linux_sparc_syscall32
187linux_sparc_syscall32:
188 /* Direct access to user regs, much faster. */
189 cmp %g1, NR_SYSCALLS ! IEU1 Group
190 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
191 srl %i0, 0, %o0 ! IEU0
192 sll %g1, 2, %l4 ! IEU0 Group
193 srl %i4, 0, %o4 ! IEU1
194 lduw [%l7 + %l4], %l7 ! Load
195 srl %i1, 0, %o1 ! IEU0 Group
196 ldx [%g6 + TI_FLAGS], %l0 ! Load
197
198 srl %i5, 0, %o5 ! IEU1
199 srl %i2, 0, %o2 ! IEU0 Group
200 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
201 bne,pn %icc, linux_syscall_trace32 ! CTI
202 mov %i0, %l5 ! IEU1
203 call %l7 ! CTI Group brk forced
204 srl %i3, 0, %o3 ! IEU0
205 ba,a,pt %xcc, 3f
206
207 /* Linux native system calls enter here... */
208 .align 32
209 .globl linux_sparc_syscall
210linux_sparc_syscall:
211 /* Direct access to user regs, much faster. */
212 cmp %g1, NR_SYSCALLS ! IEU1 Group
213 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
214 mov %i0, %o0 ! IEU0
215 sll %g1, 2, %l4 ! IEU0 Group
216 mov %i1, %o1 ! IEU1
217 lduw [%l7 + %l4], %l7 ! Load
2184: mov %i2, %o2 ! IEU0 Group
219 ldx [%g6 + TI_FLAGS], %l0 ! Load
220
221 mov %i3, %o3 ! IEU1
222 mov %i4, %o4 ! IEU0 Group
223 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
224 bne,pn %icc, linux_syscall_trace ! CTI Group
225 mov %i0, %l5 ! IEU0
2262: call %l7 ! CTI Group brk forced
227 mov %i5, %o5 ! IEU0
228 nop
229
2303: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
231ret_sys_call:
232 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
233 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
234 sra %o0, 0, %o0
235 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
236 sllx %g2, 32, %g2
237
238 /* Check if force_successful_syscall_return()
239 * was invoked.
240 */
241 ldub [%g6 + TI_SYS_NOERROR], %l2
242 brnz,a,pn %l2, 80f
243 stb %g0, [%g6 + TI_SYS_NOERROR]
244
245 cmp %o0, -ERESTART_RESTARTBLOCK
246 bgeu,pn %xcc, 1f
247 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
24880:
249 /* System call success, clear Carry condition code. */
250 andn %g3, %g2, %g3
251 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
252 bne,pn %icc, linux_syscall_trace2
253 add %l1, 0x4, %l2 ! npc = npc+4
254 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
255 ba,pt %xcc, rtrap
256 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
257
2581:
259 /* System call failure, set Carry condition code.
260 * Also, get abs(errno) to return to the process.
261 */
262 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
263 sub %g0, %o0, %o0
264 or %g3, %g2, %g3
265 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
266 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
267 bne,pn %icc, linux_syscall_trace2
268 add %l1, 0x4, %l2 ! npc = npc+4
269 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
270
271 b,pt %xcc, rtrap
272 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
273linux_syscall_trace2:
274 add %sp, PTREGS_OFF, %o0
275 call syscall_trace
276 mov 1, %o1
277 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
278 ba,pt %xcc, rtrap
279 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
diff --git a/arch/sparc64/kernel/ttable.S b/arch/sparc64/kernel/ttable.S
index b0de4c00b11a..450053af039e 100644
--- a/arch/sparc64/kernel/ttable.S
+++ b/arch/sparc64/kernel/ttable.S
@@ -153,7 +153,7 @@ tl0_resv164: BTRAP(0x164) BTRAP(0x165) BTRAP(0x166) BTRAP(0x167) BTRAP(0x168)
153tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c) 153tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c)
154tl0_linux64: LINUX_64BIT_SYSCALL_TRAP 154tl0_linux64: LINUX_64BIT_SYSCALL_TRAP
155tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context) 155tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context)
156tl0_resv170: KPROBES_TRAP(0x170) KPROBES_TRAP(0x171) BTRAP(0x172) 156tl0_resv170: KPROBES_TRAP(0x170) KPROBES_TRAP(0x171) KGDB_TRAP(0x172)
157tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177) 157tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177)
158tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c) 158tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c)
159tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f) 159tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f)
diff --git a/arch/sparc64/kernel/utrap.S b/arch/sparc64/kernel/utrap.S
new file mode 100644
index 000000000000..b7f0f3f3a909
--- /dev/null
+++ b/arch/sparc64/kernel/utrap.S
@@ -0,0 +1,29 @@
1 .globl utrap_trap
2 .type utrap_trap,#function
3utrap_trap: /* %g3=handler,%g4=level */
4 TRAP_LOAD_THREAD_REG(%g6, %g1)
5 ldx [%g6 + TI_UTRAPS], %g1
6 brnz,pt %g1, invoke_utrap
7 nop
8
9 ba,pt %xcc, etrap
10 rd %pc, %g7
11 mov %l4, %o1
12 call bad_trap
13 add %sp, PTREGS_OFF, %o0
14 ba,pt %xcc, rtrap
15 nop
16
17invoke_utrap:
18 sllx %g3, 3, %g3
19 ldx [%g1 + %g3], %g1
20 save %sp, -128, %sp
21 rdpr %tstate, %l6
22 rdpr %cwp, %l7
23 andn %l6, TSTATE_CWP, %l6
24 wrpr %l6, %l7, %tstate
25 rdpr %tpc, %l6
26 rdpr %tnpc, %l7
27 wrpr %g1, 0, %tnpc
28 done
29 .size utrap_trap,.-utrap_trap
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index e686a67561af..796e005dad8b 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -676,6 +676,33 @@ xcall_new_mmu_context_version:
676 wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint 676 wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
677 retry 677 retry
678 678
679#ifdef CONFIG_KGDB
680 .globl xcall_kgdb_capture
681xcall_kgdb_capture:
682661: rdpr %pstate, %g2
683 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
684 .section .sun4v_2insn_patch, "ax"
685 .word 661b
686 nop
687 nop
688 .previous
689
690 rdpr %pil, %g2
691 wrpr %g0, 15, %pil
692 sethi %hi(109f), %g7
693 ba,pt %xcc, etrap_irq
694109: or %g7, %lo(109b), %g7
695#ifdef CONFIG_TRACE_IRQFLAGS
696 call trace_hardirqs_off
697 nop
698#endif
699 call smp_kgdb_capture_client
700 add %sp, PTREGS_OFF, %o0
701 /* Has to be a non-v9 branch due to the large distance. */
702 ba rtrap_xcall
703 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
704#endif
705
679#endif /* CONFIG_SMP */ 706#endif /* CONFIG_SMP */
680 707
681 708
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 20:22:19 -0500