3 files changed, 17 insertions, 26 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index aef562c0a647..06e4cf0d3846 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -71,11 +71,14 @@
 #define MSR_IA32_LASTINTTOIP            0x000001de
 
 /* DEBUGCTLMSR bits (others vary by model): */
-#define _DEBUGCTLMSR_LBR        0 /* last branch recording */
-#define _DEBUGCTLMSR_BTF        1 /* single-step on branches */
-
-#define DEBUGCTLMSR_LBR         (1UL << _DEBUGCTLMSR_LBR)
-#define DEBUGCTLMSR_BTF         (1UL << _DEBUGCTLMSR_BTF)
+#define DEBUGCTLMSR_LBR                 (1UL <<  0) /* last branch recording */
+#define DEBUGCTLMSR_BTF                 (1UL <<  1) /* single-step on branches */
+#define DEBUGCTLMSR_TR                  (1UL <<  6)
+#define DEBUGCTLMSR_BTS                 (1UL <<  7)
+#define DEBUGCTLMSR_BTINT               (1UL <<  8)
+#define DEBUGCTLMSR_BTS_OFF_OS          (1UL <<  9)
+#define DEBUGCTLMSR_BTS_OFF_USR         (1UL << 10)
+#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1UL << 11)
 
 #define MSR_IA32_MC0_CTL                0x00000400
 #define MSR_IA32_MC0_STATUS             0x00000401
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index c59678a14a2e..2fea3622af7f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -38,15 +38,6 @@ struct pebs_record_nhm {
 };
 
 /*
- * Bits in the debugctlmsr controlling branch tracing.
- */
-#define X86_DEBUGCTL_TR                 (1 << 6)
-#define X86_DEBUGCTL_BTS                (1 << 7)
-#define X86_DEBUGCTL_BTINT              (1 << 8)
-#define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
-#define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
-
-/*
  * A debug store configuration.
  *
  * We only support architectures that use 64bit fields.
@@ -193,15 +184,15 @@ static void intel_pmu_enable_bts(u64 config)
 
         debugctlmsr = get_debugctlmsr();
 
-        debugctlmsr |= X86_DEBUGCTL_TR;
-        debugctlmsr |= X86_DEBUGCTL_BTS;
-        debugctlmsr |= X86_DEBUGCTL_BTINT;
+        debugctlmsr |= DEBUGCTLMSR_TR;
+        debugctlmsr |= DEBUGCTLMSR_BTS;
+        debugctlmsr |= DEBUGCTLMSR_BTINT;
 
         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
-                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
+                debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 
         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
-                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
+                debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 
         update_debugctlmsr(debugctlmsr);
 }
@@ -217,8 +208,8 @@ static void intel_pmu_disable_bts(void)
         debugctlmsr = get_debugctlmsr();
 
         debugctlmsr &=
-                ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
-                  X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
+                ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
+                  DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 
         update_debugctlmsr(debugctlmsr);
 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index df4c98e26c5b..d202c1bece1a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -12,15 +12,12 @@ enum {
  * otherwise it becomes near impossible to get a reliable stack.
  */
 
-#define X86_DEBUGCTL_LBR                        (1 << 0)
-#define X86_DEBUGCTL_FREEZE_LBRS_ON_PMI         (1 << 11)
-
 static void __intel_pmu_lbr_enable(void)
 {
         u64 debugctl;
 
         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
-        debugctl |= (X86_DEBUGCTL_LBR | X86_DEBUGCTL_FREEZE_LBRS_ON_PMI);
+        debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 }
 
@@ -29,7 +26,7 @@ static void __intel_pmu_lbr_disable(void)
         u64 debugctl;
 
         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
-        debugctl &= ~(X86_DEBUGCTL_LBR | X86_DEBUGCTL_FREEZE_LBRS_ON_PMI);
+        debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 }