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-rw-r--r--arch/arm/mach-pxa/pxa25x.c1
-rw-r--r--arch/arm/mach-pxa/tosa-bt.c2
-rw-r--r--arch/arm/mach-pxa/tosa.c6
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h69
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h83
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h193
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h168
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c15
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c15
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h149
-rw-r--r--arch/arm/plat-s5p/dev-uart.c12
-rw-r--r--arch/arm/plat-samsung/dev-ts.c1
-rw-r--r--arch/s390/boot/compressed/misc.c5
-rw-r--r--arch/s390/include/asm/atomic.h26
-rw-r--r--arch/s390/include/asm/cache.h1
15 files changed, 371 insertions, 375 deletions
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index fbc5b775f895..b166b1d845d7 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -347,6 +347,7 @@ static struct platform_device *pxa25x_devices[] __initdata = {
347 &pxa25x_device_assp, 347 &pxa25x_device_assp,
348 &pxa25x_device_pwm0, 348 &pxa25x_device_pwm0,
349 &pxa25x_device_pwm1, 349 &pxa25x_device_pwm1,
350 &pxa_device_asoc_platform,
350}; 351};
351 352
352static struct sys_device pxa25x_sysdev[] = { 353static struct sys_device pxa25x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index c31e601eb49c..b9b1e5c2b290 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -81,8 +81,6 @@ static int tosa_bt_probe(struct platform_device *dev)
81 goto err_rfk_alloc; 81 goto err_rfk_alloc;
82 } 82 }
83 83
84 rfkill_set_led_trigger_name(rfk, "tosa-bt");
85
86 rc = rfkill_register(rfk); 84 rc = rfkill_register(rfk);
87 if (rc) 85 if (rc)
88 goto err_rfkill; 86 goto err_rfkill;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index af152e70cfcf..f2582ec300d9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -875,6 +875,11 @@ static struct platform_device sharpsl_rom_device = {
875 .dev.platform_data = &sharpsl_rom_data, 875 .dev.platform_data = &sharpsl_rom_data,
876}; 876};
877 877
878static struct platform_device wm9712_device = {
879 .name = "wm9712-codec",
880 .id = -1,
881};
882
878static struct platform_device *devices[] __initdata = { 883static struct platform_device *devices[] __initdata = {
879 &tosascoop_device, 884 &tosascoop_device,
880 &tosascoop_jc_device, 885 &tosascoop_jc_device,
@@ -885,6 +890,7 @@ static struct platform_device *devices[] __initdata = {
885 &tosaled_device, 890 &tosaled_device,
886 &tosa_bt_device, 891 &tosa_bt_device,
887 &sharpsl_rom_device, 892 &sharpsl_rom_device,
893 &wm9712_device,
888}; 894};
889 895
890static void tosa_poweroff(void) 896static void tosa_poweroff(void)
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 203dd5a18bd5..058dab4482a1 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/map.h 1/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5P6442 - Memory map definitions 6 * S5P6442 - Memory map definitions
@@ -16,56 +16,61 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5P6442_PA_CHIPID (0xE0000000) 19#define S5P6442_PA_SDRAM 0x20000000
20#define S5P_PA_CHIPID S5P6442_PA_CHIPID
21 20
22#define S5P6442_PA_SYSCON (0xE0100000) 21#define S5P6442_PA_I2S0 0xC0B00000
23#define S5P_PA_SYSCON S5P6442_PA_SYSCON 22#define S5P6442_PA_I2S1 0xF2200000
24 23
25#define S5P6442_PA_GPIO (0xE0200000) 24#define S5P6442_PA_CHIPID 0xE0000000
26 25
27#define S5P6442_PA_VIC0 (0xE4000000) 26#define S5P6442_PA_SYSCON 0xE0100000
28#define S5P6442_PA_VIC1 (0xE4100000)
29#define S5P6442_PA_VIC2 (0xE4200000)
30 27
31#define S5P6442_PA_SROMC (0xE7000000) 28#define S5P6442_PA_GPIO 0xE0200000
32#define S5P_PA_SROMC S5P6442_PA_SROMC
33 29
34#define S5P6442_PA_MDMA 0xE8000000 30#define S5P6442_PA_VIC0 0xE4000000
35#define S5P6442_PA_PDMA 0xE9000000 31#define S5P6442_PA_VIC1 0xE4100000
32#define S5P6442_PA_VIC2 0xE4200000
36 33
37#define S5P6442_PA_TIMER (0xEA000000) 34#define S5P6442_PA_SROMC 0xE7000000
38#define S5P_PA_TIMER S5P6442_PA_TIMER
39 35
40#define S5P6442_PA_SYSTIMER (0xEA100000) 36#define S5P6442_PA_MDMA 0xE8000000
37#define S5P6442_PA_PDMA 0xE9000000
41 38
42#define S5P6442_PA_WATCHDOG (0xEA200000) 39#define S5P6442_PA_TIMER 0xEA000000
43 40
44#define S5P6442_PA_UART (0xEC000000) 41#define S5P6442_PA_SYSTIMER 0xEA100000
45 42
46#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) 43#define S5P6442_PA_WATCHDOG 0xEA200000
47#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
48#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
49#define S5P_SZ_UART SZ_256
50 44
51#define S5P6442_PA_IIC0 (0xEC100000) 45#define S5P6442_PA_UART 0xEC000000
52 46
53#define S5P6442_PA_SDRAM (0x20000000) 47#define S5P6442_PA_IIC0 0xEC100000
54#define S5P_PA_SDRAM S5P6442_PA_SDRAM
55 48
56#define S5P6442_PA_SPI 0xEC300000 49#define S5P6442_PA_SPI 0xEC300000
57 50
58/* I2S */
59#define S5P6442_PA_I2S0 0xC0B00000
60#define S5P6442_PA_I2S1 0xF2200000
61
62/* PCM */
63#define S5P6442_PA_PCM0 0xF2400000 51#define S5P6442_PA_PCM0 0xF2400000
64#define S5P6442_PA_PCM1 0xF2500000 52#define S5P6442_PA_PCM1 0xF2500000
65 53
66/* compatibiltiy defines. */ 54/* Compatibiltiy Defines */
55
56#define S3C_PA_IIC S5P6442_PA_IIC0
67#define S3C_PA_WDT S5P6442_PA_WATCHDOG 57#define S3C_PA_WDT S5P6442_PA_WATCHDOG
58
59#define S5P_PA_CHIPID S5P6442_PA_CHIPID
60#define S5P_PA_SDRAM S5P6442_PA_SDRAM
61#define S5P_PA_SROMC S5P6442_PA_SROMC
62#define S5P_PA_SYSCON S5P6442_PA_SYSCON
63#define S5P_PA_TIMER S5P6442_PA_TIMER
64
65/* UART */
66
68#define S3C_PA_UART S5P6442_PA_UART 67#define S3C_PA_UART S5P6442_PA_UART
69#define S3C_PA_IIC S5P6442_PA_IIC0 68
69#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
70#define S5P_PA_UART0 S5P_PA_UART(0)
71#define S5P_PA_UART1 S5P_PA_UART(1)
72#define S5P_PA_UART2 S5P_PA_UART(2)
73
74#define S5P_SZ_UART SZ_256
70 75
71#endif /* __ASM_ARCH_MAP_H */ 76#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index a9365e5ba614..95c91257c7ca 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5P64X0 - Memory map definitions 6 * S5P64X0 - Memory map definitions
@@ -16,64 +16,46 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5P64X0_PA_SDRAM (0x20000000) 19#define S5P64X0_PA_SDRAM 0x20000000
20 20
21#define S5P64X0_PA_CHIPID (0xE0000000) 21#define S5P64X0_PA_CHIPID 0xE0000000
22#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
23
24#define S5P64X0_PA_SYSCON (0xE0100000)
25#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
26
27#define S5P64X0_PA_GPIO (0xE0308000)
28
29#define S5P64X0_PA_VIC0 (0xE4000000)
30#define S5P64X0_PA_VIC1 (0xE4100000)
31 22
32#define S5P64X0_PA_SROMC (0xE7000000) 23#define S5P64X0_PA_SYSCON 0xE0100000
33#define S5P_PA_SROMC S5P64X0_PA_SROMC
34
35#define S5P64X0_PA_PDMA (0xE9000000)
36
37#define S5P64X0_PA_TIMER (0xEA000000)
38#define S5P_PA_TIMER S5P64X0_PA_TIMER
39 24
40#define S5P64X0_PA_RTC (0xEA100000) 25#define S5P64X0_PA_GPIO 0xE0308000
41 26
42#define S5P64X0_PA_WDT (0xEA200000) 27#define S5P64X0_PA_VIC0 0xE4000000
28#define S5P64X0_PA_VIC1 0xE4100000
43 29
44#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET)) 30#define S5P64X0_PA_SROMC 0xE7000000
45#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
46 31
47#define S5P_PA_UART0 S5P6450_PA_UART(0) 32#define S5P64X0_PA_PDMA 0xE9000000
48#define S5P_PA_UART1 S5P6450_PA_UART(1)
49#define S5P_PA_UART2 S5P6450_PA_UART(2)
50#define S5P_PA_UART3 S5P6450_PA_UART(3)
51#define S5P_PA_UART4 S5P6450_PA_UART(4)
52#define S5P_PA_UART5 S5P6450_PA_UART(5)
53 33
54#define S5P_SZ_UART SZ_256 34#define S5P64X0_PA_TIMER 0xEA000000
35#define S5P64X0_PA_RTC 0xEA100000
36#define S5P64X0_PA_WDT 0xEA200000
55 37
56#define S5P6440_PA_IIC0 (0xEC104000) 38#define S5P6440_PA_IIC0 0xEC104000
57#define S5P6440_PA_IIC1 (0xEC20F000) 39#define S5P6440_PA_IIC1 0xEC20F000
58#define S5P6450_PA_IIC0 (0xEC100000) 40#define S5P6450_PA_IIC0 0xEC100000
59#define S5P6450_PA_IIC1 (0xEC200000) 41#define S5P6450_PA_IIC1 0xEC200000
60 42
61#define S5P64X0_PA_SPI0 (0xEC400000) 43#define S5P64X0_PA_SPI0 0xEC400000
62#define S5P64X0_PA_SPI1 (0xEC500000) 44#define S5P64X0_PA_SPI1 0xEC500000
63 45
64#define S5P64X0_PA_HSOTG (0xED100000) 46#define S5P64X0_PA_HSOTG 0xED100000
65 47
66#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
67 49
68#define S5P64X0_PA_I2S (0xF2000000) 50#define S5P64X0_PA_I2S 0xF2000000
69#define S5P6450_PA_I2S1 0xF2800000 51#define S5P6450_PA_I2S1 0xF2800000
70#define S5P6450_PA_I2S2 0xF2900000 52#define S5P6450_PA_I2S2 0xF2900000
71 53
72#define S5P64X0_PA_PCM (0xF2100000) 54#define S5P64X0_PA_PCM 0xF2100000
73 55
74#define S5P64X0_PA_ADC (0xF3000000) 56#define S5P64X0_PA_ADC 0xF3000000
75 57
76/* compatibiltiy defines. */ 58/* Compatibiltiy Defines */
77 59
78#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0) 60#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
79#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1) 61#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
@@ -83,6 +65,25 @@
83#define S3C_PA_RTC S5P64X0_PA_RTC 65#define S3C_PA_RTC S5P64X0_PA_RTC
84#define S3C_PA_WDT S5P64X0_PA_WDT 66#define S3C_PA_WDT S5P64X0_PA_WDT
85 67
68#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
69#define S5P_PA_SROMC S5P64X0_PA_SROMC
70#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
71#define S5P_PA_TIMER S5P64X0_PA_TIMER
72
86#define SAMSUNG_PA_ADC S5P64X0_PA_ADC 73#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
87 74
75/* UART */
76
77#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
78#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
79
80#define S5P_PA_UART0 S5P6450_PA_UART(0)
81#define S5P_PA_UART1 S5P6450_PA_UART(1)
82#define S5P_PA_UART2 S5P6450_PA_UART(2)
83#define S5P_PA_UART3 S5P6450_PA_UART(3)
84#define S5P_PA_UART4 S5P6450_PA_UART(4)
85#define S5P_PA_UART5 S5P6450_PA_UART(5)
86
87#define S5P_SZ_UART SZ_256
88
88#endif /* __ASM_ARCH_MAP_H */ 89#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 328467b346aa..ccbe6b767f7d 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -1,5 +1,8 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/map.h 1/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright 2009 Samsung Electronics Co. 6 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 7 * Byungho Min <bhmin@samsung.com>
5 * 8 *
@@ -16,145 +19,115 @@
16#include <plat/map-base.h> 19#include <plat/map-base.h>
17#include <plat/map-s5p.h> 20#include <plat/map-s5p.h>
18 21
19/* 22#define S5PC100_PA_SDRAM 0x20000000
20 * map-base.h has already defined virtual memory address 23
21 * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) 24#define S5PC100_PA_ONENAND 0xE7100000
22 * S3C_VA_SYS S3C_ADDR(0x00100000) system control 25#define S5PC100_PA_ONENAND_BUF 0xB0000000
23 * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) 26
24 * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block 27#define S5PC100_PA_CHIPID 0xE0000000
25 * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
26 * S3C_VA_UART S3C_ADDR(0x01000000) UART
27 *
28 * S5PC100 specific virtual memory address can be defined here
29 * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
30 *
31 */
32 28
33#define S5PC100_PA_ONENAND_BUF (0xB0000000) 29#define S5PC100_PA_SYSCON 0xE0100000
34#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
35 30
36/* Chip ID */ 31#define S5PC100_PA_OTHERS 0xE0200000
37 32
38#define S5PC100_PA_CHIPID (0xE0000000) 33#define S5PC100_PA_GPIO 0xE0300000
39#define S5P_PA_CHIPID S5PC100_PA_CHIPID
40 34
41#define S5PC100_PA_SYSCON (0xE0100000) 35#define S5PC100_PA_VIC0 0xE4000000
42#define S5P_PA_SYSCON S5PC100_PA_SYSCON 36#define S5PC100_PA_VIC1 0xE4100000
37#define S5PC100_PA_VIC2 0xE4200000
43 38
44#define S5PC100_PA_OTHERS (0xE0200000) 39#define S5PC100_PA_SROMC 0xE7000000
45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
46 40
47#define S5PC100_PA_GPIO (0xE0300000) 41#define S5PC100_PA_CFCON 0xE7800000
48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
49 42
50/* Interrupt */ 43#define S5PC100_PA_MDMA 0xE8100000
51#define S5PC100_PA_VIC0 (0xE4000000) 44#define S5PC100_PA_PDMA0 0xE9000000
52#define S5PC100_PA_VIC1 (0xE4100000) 45#define S5PC100_PA_PDMA1 0xE9200000
53#define S5PC100_PA_VIC2 (0xE4200000)
54#define S5PC100_VA_VIC S3C_VA_IRQ
55#define S5PC100_VA_VIC_OFFSET 0x10000
56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57 46
58#define S5PC100_PA_SROMC (0xE7000000) 47#define S5PC100_PA_TIMER 0xEA000000
59#define S5P_PA_SROMC S5PC100_PA_SROMC 48#define S5PC100_PA_SYSTIMER 0xEA100000
49#define S5PC100_PA_WATCHDOG 0xEA200000
50#define S5PC100_PA_RTC 0xEA300000
60 51
61#define S5PC100_PA_ONENAND (0xE7100000) 52#define S5PC100_PA_UART 0xEC000000
62 53
63#define S5PC100_PA_CFCON (0xE7800000) 54#define S5PC100_PA_IIC0 0xEC100000
55#define S5PC100_PA_IIC1 0xEC200000
64 56
65/* DMA */ 57#define S5PC100_PA_SPI0 0xEC300000
66#define S5PC100_PA_MDMA (0xE8100000) 58#define S5PC100_PA_SPI1 0xEC400000
67#define S5PC100_PA_PDMA0 (0xE9000000) 59#define S5PC100_PA_SPI2 0xEC500000
68#define S5PC100_PA_PDMA1 (0xE9200000)
69 60
70/* Timer */ 61#define S5PC100_PA_USB_HSOTG 0xED200000
71#define S5PC100_PA_TIMER (0xEA000000) 62#define S5PC100_PA_USB_HSPHY 0xED300000
72#define S5P_PA_TIMER S5PC100_PA_TIMER
73 63
74#define S5PC100_PA_SYSTIMER (0xEA100000) 64#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
75 65
76#define S5PC100_PA_WATCHDOG (0xEA200000) 66#define S5PC100_PA_FB 0xEE000000
77#define S5PC100_PA_RTC (0xEA300000)
78 67
79#define S5PC100_PA_UART (0xEC000000) 68#define S5PC100_PA_FIMC0 0xEE200000
69#define S5PC100_PA_FIMC1 0xEE300000
70#define S5PC100_PA_FIMC2 0xEE400000
80 71
81#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) 72#define S5PC100_PA_I2S0 0xF2000000
82#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) 73#define S5PC100_PA_I2S1 0xF2100000
83#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) 74#define S5PC100_PA_I2S2 0xF2200000
84#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
85#define S5P_SZ_UART SZ_256
86 75
87#define S5PC100_PA_IIC0 (0xEC100000) 76#define S5PC100_PA_AC97 0xF2300000
88#define S5PC100_PA_IIC1 (0xEC200000)
89 77
90/* SPI */ 78#define S5PC100_PA_PCM0 0xF2400000
91#define S5PC100_PA_SPI0 0xEC300000 79#define S5PC100_PA_PCM1 0xF2500000
92#define S5PC100_PA_SPI1 0xEC400000
93#define S5PC100_PA_SPI2 0xEC500000
94 80
95/* USB HS OTG */ 81#define S5PC100_PA_SPDIF 0xF2600000
96#define S5PC100_PA_USB_HSOTG (0xED200000)
97#define S5PC100_PA_USB_HSPHY (0xED300000)
98 82
99#define S5PC100_PA_FB (0xEE000000) 83#define S5PC100_PA_TSADC 0xF3000000
100 84
101#define S5PC100_PA_FIMC0 (0xEE200000) 85#define S5PC100_PA_KEYPAD 0xF3100000
102#define S5PC100_PA_FIMC1 (0xEE300000)
103#define S5PC100_PA_FIMC2 (0xEE400000)
104 86
105#define S5PC100_PA_I2S0 (0xF2000000) 87/* Compatibiltiy Defines */
106#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000)
108 88
109#define S5PC100_PA_AC97 0xF2300000 89#define S3C_PA_FB S5PC100_PA_FB
90#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
91#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
92#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
93#define S3C_PA_IIC S5PC100_PA_IIC0
94#define S3C_PA_IIC1 S5PC100_PA_IIC1
95#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
96#define S3C_PA_ONENAND S5PC100_PA_ONENAND
97#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
98#define S3C_PA_RTC S5PC100_PA_RTC
99#define S3C_PA_TSADC S5PC100_PA_TSADC
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
110 103
111/* PCM */ 104#define S5P_PA_CHIPID S5PC100_PA_CHIPID
112#define S5PC100_PA_PCM0 0xF2400000 105#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
113#define S5PC100_PA_PCM1 0xF2500000 106#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
107#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
108#define S5P_PA_SDRAM S5PC100_PA_SDRAM
109#define S5P_PA_SROMC S5PC100_PA_SROMC
110#define S5P_PA_SYSCON S5PC100_PA_SYSCON
111#define S5P_PA_TIMER S5PC100_PA_TIMER
114 112
115#define S5PC100_PA_SPDIF 0xF2600000 113#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
114#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
115#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
116 116
117#define S5PC100_PA_TSADC (0xF3000000) 117#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
118 118
119/* KEYPAD */ 119#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
120#define S5PC100_PA_KEYPAD (0xF3100000)
121 120
122#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 121/* UART */
123 122
124#define S5PC100_PA_SDRAM (0x20000000) 123#define S3C_PA_UART S5PC100_PA_UART
125#define S5P_PA_SDRAM S5PC100_PA_SDRAM
126 124
127/* compatibiltiy defines. */ 125#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
128#define S3C_PA_UART S5PC100_PA_UART 126#define S5P_PA_UART0 S5P_PA_UART(0)
129#define S3C_PA_IIC S5PC100_PA_IIC0 127#define S5P_PA_UART1 S5P_PA_UART(1)
130#define S3C_PA_IIC1 S5PC100_PA_IIC1 128#define S5P_PA_UART2 S5P_PA_UART(2)
131#define S3C_PA_FB S5PC100_PA_FB 129#define S5P_PA_UART3 S5P_PA_UART(3)
132#define S3C_PA_G2D S5PC100_PA_G2D
133#define S3C_PA_G3D S5PC100_PA_G3D
134#define S3C_PA_JPEG S5PC100_PA_JPEG
135#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
136#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
137#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
138#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
139#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
140#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
141#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
142#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
143#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
144#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
145#define S3C_PA_WDT S5PC100_PA_WATCHDOG
146#define S3C_PA_TSADC S5PC100_PA_TSADC
147#define S3C_PA_ONENAND S5PC100_PA_ONENAND
148#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
149#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
150#define S3C_PA_RTC S5PC100_PA_RTC
151
152#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
153#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
154#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
155 130
156#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 131#define S5P_SZ_UART SZ_256
157#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
158#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
159 132
160#endif /* __ASM_ARCH_C100_MAP_H */ 133#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 3611492ad681..1dd58836fd4f 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/map.h 1/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV210 - Memory map definitions 6 * S5PV210 - Memory map definitions
@@ -16,122 +16,120 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PV210_PA_SROM_BANK5 (0xA8000000) 19#define S5PV210_PA_SDRAM 0x20000000
20 20
21#define S5PC110_PA_ONENAND (0xB0000000) 21#define S5PV210_PA_SROM_BANK5 0xA8000000
22#define S5P_PA_ONENAND S5PC110_PA_ONENAND
23 22
24#define S5PC110_PA_ONENAND_DMA (0xB0600000) 23#define S5PC110_PA_ONENAND 0xB0000000
25#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 24#define S5PC110_PA_ONENAND_DMA 0xB0600000
26 25
27#define S5PV210_PA_CHIPID (0xE0000000) 26#define S5PV210_PA_CHIPID 0xE0000000
28#define S5P_PA_CHIPID S5PV210_PA_CHIPID
29 27
30#define S5PV210_PA_SYSCON (0xE0100000) 28#define S5PV210_PA_SYSCON 0xE0100000
31#define S5P_PA_SYSCON S5PV210_PA_SYSCON
32 29
33#define S5PV210_PA_GPIO (0xE0200000) 30#define S5PV210_PA_GPIO 0xE0200000
34 31
35/* SPI */ 32#define S5PV210_PA_SPDIF 0xE1100000
36#define S5PV210_PA_SPI0 0xE1300000
37#define S5PV210_PA_SPI1 0xE1400000
38 33
39#define S5PV210_PA_KEYPAD (0xE1600000) 34#define S5PV210_PA_SPI0 0xE1300000
35#define S5PV210_PA_SPI1 0xE1400000
40 36
41#define S5PV210_PA_IIC0 (0xE1800000) 37#define S5PV210_PA_KEYPAD 0xE1600000
42#define S5PV210_PA_IIC1 (0xFAB00000)
43#define S5PV210_PA_IIC2 (0xE1A00000)
44 38
45#define S5PV210_PA_TIMER (0xE2500000) 39#define S5PV210_PA_ADC 0xE1700000
46#define S5P_PA_TIMER S5PV210_PA_TIMER
47 40
48#define S5PV210_PA_SYSTIMER (0xE2600000) 41#define S5PV210_PA_IIC0 0xE1800000
42#define S5PV210_PA_IIC1 0xFAB00000
43#define S5PV210_PA_IIC2 0xE1A00000
49 44
50#define S5PV210_PA_WATCHDOG (0xE2700000) 45#define S5PV210_PA_AC97 0xE2200000
51 46
52#define S5PV210_PA_RTC (0xE2800000) 47#define S5PV210_PA_PCM0 0xE2300000
53#define S5PV210_PA_UART (0xE2900000) 48#define S5PV210_PA_PCM1 0xE1200000
49#define S5PV210_PA_PCM2 0xE2B00000
54 50
55#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) 51#define S5PV210_PA_TIMER 0xE2500000
56#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400) 52#define S5PV210_PA_SYSTIMER 0xE2600000
57#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800) 53#define S5PV210_PA_WATCHDOG 0xE2700000
58#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00) 54#define S5PV210_PA_RTC 0xE2800000
59 55
60#define S5P_SZ_UART SZ_256 56#define S5PV210_PA_UART 0xE2900000
61 57
62#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 58#define S5PV210_PA_SROMC 0xE8000000
63 59
64#define S5PV210_PA_SROMC (0xE8000000) 60#define S5PV210_PA_CFCON 0xE8200000
65#define S5P_PA_SROMC S5PV210_PA_SROMC
66 61
67#define S5PV210_PA_CFCON (0xE8200000) 62#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
68 63
69#define S5PV210_PA_MDMA 0xFA200000 64#define S5PV210_PA_HSOTG 0xEC000000
70#define S5PV210_PA_PDMA0 0xE0900000 65#define S5PV210_PA_HSPHY 0xEC100000
71#define S5PV210_PA_PDMA1 0xE0A00000
72 66
73#define S5PV210_PA_FB (0xF8000000) 67#define S5PV210_PA_IIS0 0xEEE30000
68#define S5PV210_PA_IIS1 0xE2100000
69#define S5PV210_PA_IIS2 0xE2A00000
74 70
75#define S5PV210_PA_FIMC0 (0xFB200000) 71#define S5PV210_PA_DMC0 0xF0000000
76#define S5PV210_PA_FIMC1 (0xFB300000) 72#define S5PV210_PA_DMC1 0xF1400000
77#define S5PV210_PA_FIMC2 (0xFB400000)
78 73
79#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74#define S5PV210_PA_VIC0 0xF2000000
75#define S5PV210_PA_VIC1 0xF2100000
76#define S5PV210_PA_VIC2 0xF2200000
77#define S5PV210_PA_VIC3 0xF2300000
80 78
81#define S5PV210_PA_HSOTG (0xEC000000) 79#define S5PV210_PA_FB 0xF8000000
82#define S5PV210_PA_HSPHY (0xEC100000)
83 80
84#define S5PV210_PA_VIC0 (0xF2000000) 81#define S5PV210_PA_MDMA 0xFA200000
85#define S5PV210_PA_VIC1 (0xF2100000) 82#define S5PV210_PA_PDMA0 0xE0900000
86#define S5PV210_PA_VIC2 (0xF2200000) 83#define S5PV210_PA_PDMA1 0xE0A00000
87#define S5PV210_PA_VIC3 (0xF2300000)
88 84
89#define S5PV210_PA_SDRAM (0x20000000) 85#define S5PV210_PA_MIPI_CSIS 0xFA600000
90#define S5P_PA_SDRAM S5PV210_PA_SDRAM
91 86
92/* S/PDIF */ 87#define S5PV210_PA_FIMC0 0xFB200000
93#define S5PV210_PA_SPDIF 0xE1100000 88#define S5PV210_PA_FIMC1 0xFB300000
89#define S5PV210_PA_FIMC2 0xFB400000
94 90
95/* I2S */ 91/* Compatibiltiy Defines */
96#define S5PV210_PA_IIS0 0xEEE30000
97#define S5PV210_PA_IIS1 0xE2100000
98#define S5PV210_PA_IIS2 0xE2A00000
99 92
100/* PCM */ 93#define S3C_PA_FB S5PV210_PA_FB
101#define S5PV210_PA_PCM0 0xE2300000 94#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
102#define S5PV210_PA_PCM1 0xE1200000 95#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
103#define S5PV210_PA_PCM2 0xE2B00000 96#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
97#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
98#define S3C_PA_IIC S5PV210_PA_IIC0
99#define S3C_PA_IIC1 S5PV210_PA_IIC1
100#define S3C_PA_IIC2 S5PV210_PA_IIC2
101#define S3C_PA_RTC S5PV210_PA_RTC
102#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
103#define S3C_PA_WDT S5PV210_PA_WATCHDOG
104 104
105/* AC97 */ 105#define S5P_PA_CHIPID S5PV210_PA_CHIPID
106#define S5PV210_PA_AC97 0xE2200000 106#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
107#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
110#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112#define S5P_PA_SDRAM S5PV210_PA_SDRAM
113#define S5P_PA_SROMC S5PV210_PA_SROMC
114#define S5P_PA_SYSCON S5PV210_PA_SYSCON
115#define S5P_PA_TIMER S5PV210_PA_TIMER
107 116
108#define S5PV210_PA_ADC (0xE1700000) 117#define SAMSUNG_PA_ADC S5PV210_PA_ADC
118#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
119#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
109 120
110#define S5PV210_PA_DMC0 (0xF0000000) 121/* UART */
111#define S5PV210_PA_DMC1 (0xF1400000)
112 122
113#define S5PV210_PA_MIPI_CSIS 0xFA600000 123#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
114 124
115/* compatibiltiy defines. */ 125#define S3C_PA_UART S5PV210_PA_UART
116#define S3C_PA_UART S5PV210_PA_UART
117#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
118#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
119#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
120#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
121#define S3C_PA_IIC S5PV210_PA_IIC0
122#define S3C_PA_IIC1 S5PV210_PA_IIC1
123#define S3C_PA_IIC2 S5PV210_PA_IIC2
124#define S3C_PA_FB S5PV210_PA_FB
125#define S3C_PA_RTC S5PV210_PA_RTC
126#define S3C_PA_WDT S5PV210_PA_WATCHDOG
127#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
128#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
129#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
130#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
131#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
132 126
133#define SAMSUNG_PA_ADC S5PV210_PA_ADC 127#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
134#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 128#define S5P_PA_UART0 S5P_PA_UART(0)
135#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 129#define S5P_PA_UART1 S5P_PA_UART(1)
130#define S5P_PA_UART2 S5P_PA_UART(2)
131#define S5P_PA_UART3 S5P_PA_UART(3)
132
133#define S5P_SZ_UART SZ_256
136 134
137#endif /* __ASM_ARCH_MAP_H */ 135#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 461aa035afc0..557add4fc56c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
149 149
150static struct regulator_init_data aquila_ldo3_data = { 150static struct regulator_init_data aquila_ldo3_data = {
151 .constraints = { 151 .constraints = {
152 .name = "VUSB/MIPI_1.1V", 152 .name = "VUSB+MIPI_1.1V",
153 .min_uV = 1100000, 153 .min_uV = 1100000,
154 .max_uV = 1100000, 154 .max_uV = 1100000,
155 .apply_uV = 1, 155 .apply_uV = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
197 197
198static struct regulator_init_data aquila_ldo8_data = { 198static struct regulator_init_data aquila_ldo8_data = {
199 .constraints = { 199 .constraints = {
200 .name = "VUSB/VADC_3.3V", 200 .name = "VUSB+VADC_3.3V",
201 .min_uV = 3300000, 201 .min_uV = 3300000,
202 .max_uV = 3300000, 202 .max_uV = 3300000,
203 .apply_uV = 1, 203 .apply_uV = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
207 207
208static struct regulator_init_data aquila_ldo9_data = { 208static struct regulator_init_data aquila_ldo9_data = {
209 .constraints = { 209 .constraints = {
210 .name = "VCC/VCAM_2.8V", 210 .name = "VCC+VCAM_2.8V",
211 .min_uV = 2800000, 211 .min_uV = 2800000,
212 .max_uV = 2800000, 212 .max_uV = 2800000,
213 .apply_uV = 1, 213 .apply_uV = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
381 .buck1_set1 = S5PV210_GPH0(3), 381 .buck1_set1 = S5PV210_GPH0(3),
382 .buck1_set2 = S5PV210_GPH0(4), 382 .buck1_set2 = S5PV210_GPH0(4),
383 .buck2_set3 = S5PV210_GPH0(5), 383 .buck2_set3 = S5PV210_GPH0(5),
384 .buck1_max_voltage1 = 1200000, 384 .buck1_voltage1 = 1200000,
385 .buck1_max_voltage2 = 1200000, 385 .buck1_voltage2 = 1200000,
386 .buck2_max_voltage = 1200000, 386 .buck1_voltage3 = 1200000,
387 .buck1_voltage4 = 1200000,
388 .buck2_voltage1 = 1200000,
389 .buck2_voltage2 = 1200000,
387}; 390};
388#endif 391#endif
389 392
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e22d5112fd44..056f5c769b0a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
288 288
289static struct regulator_init_data goni_ldo3_data = { 289static struct regulator_init_data goni_ldo3_data = {
290 .constraints = { 290 .constraints = {
291 .name = "VUSB/MIPI_1.1V", 291 .name = "VUSB+MIPI_1.1V",
292 .min_uV = 1100000, 292 .min_uV = 1100000,
293 .max_uV = 1100000, 293 .max_uV = 1100000,
294 .apply_uV = 1, 294 .apply_uV = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
337 337
338static struct regulator_init_data goni_ldo8_data = { 338static struct regulator_init_data goni_ldo8_data = {
339 .constraints = { 339 .constraints = {
340 .name = "VUSB/VADC_3.3V", 340 .name = "VUSB+VADC_3.3V",
341 .min_uV = 3300000, 341 .min_uV = 3300000,
342 .max_uV = 3300000, 342 .max_uV = 3300000,
343 .apply_uV = 1, 343 .apply_uV = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
347 347
348static struct regulator_init_data goni_ldo9_data = { 348static struct regulator_init_data goni_ldo9_data = {
349 .constraints = { 349 .constraints = {
350 .name = "VCC/VCAM_2.8V", 350 .name = "VCC+VCAM_2.8V",
351 .min_uV = 2800000, 351 .min_uV = 2800000,
352 .max_uV = 2800000, 352 .max_uV = 2800000,
353 .apply_uV = 1, 353 .apply_uV = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
521 .buck1_set1 = S5PV210_GPH0(3), 521 .buck1_set1 = S5PV210_GPH0(3),
522 .buck1_set2 = S5PV210_GPH0(4), 522 .buck1_set2 = S5PV210_GPH0(4),
523 .buck2_set3 = S5PV210_GPH0(5), 523 .buck2_set3 = S5PV210_GPH0(5),
524 .buck1_max_voltage1 = 1200000, 524 .buck1_voltage1 = 1200000,
525 .buck1_max_voltage2 = 1200000, 525 .buck1_voltage2 = 1200000,
526 .buck2_max_voltage = 1200000, 526 .buck1_voltage3 = 1200000,
527 .buck1_voltage4 = 1200000,
528 .buck2_voltage1 = 1200000,
529 .buck2_voltage2 = 1200000,
527}; 530};
528#endif 531#endif
529 532
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 3060f78e12ab..901657fa7a12 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h 1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV310 - Memory map definitions 6 * S5PV310 - Memory map definitions
@@ -23,90 +23,43 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define S5PV310_PA_SYSRAM (0x02025000) 26#define S5PV310_PA_SYSRAM 0x02025000
27 27
28#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) 28#define S5PV310_PA_I2S0 0x03830000
29 29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PC210_PA_ONENAND (0x0C000000) 30#define S5PV310_PA_I2S2 0xE2A00000
31#define S5P_PA_ONENAND S5PC210_PA_ONENAND
32
33#define S5PC210_PA_ONENAND_DMA (0x0C600000)
34#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
35
36#define S5PV310_PA_CHIPID (0x10000000)
37#define S5P_PA_CHIPID S5PV310_PA_CHIPID
38
39#define S5PV310_PA_SYSCON (0x10010000)
40#define S5P_PA_SYSCON S5PV310_PA_SYSCON
41 31
42#define S5PV310_PA_PMU (0x10020000) 32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
43 35
44#define S5PV310_PA_CMU (0x10030000) 36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
45
46#define S5PV310_PA_WATCHDOG (0x10060000)
47#define S5PV310_PA_RTC (0x10070000)
48
49#define S5PV310_PA_DMC0 (0x10400000)
50
51#define S5PV310_PA_COMBINER (0x10448000)
52
53#define S5PV310_PA_COREPERI (0x10500000)
54#define S5PV310_PA_GIC_CPU (0x10500100)
55#define S5PV310_PA_TWD (0x10500600)
56#define S5PV310_PA_GIC_DIST (0x10501000)
57#define S5PV310_PA_L2CC (0x10502000)
58
59/* DMA */
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_GPIO1 (0x11400000)
65#define S5PV310_PA_GPIO2 (0x11000000)
66#define S5PV310_PA_GPIO3 (0x03860000)
67
68#define S5PV310_PA_MIPI_CSIS0 0x11880000
69#define S5PV310_PA_MIPI_CSIS1 0x11890000
70 37
71#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
72 40
73#define S5PV310_PA_SROMC (0x12570000) 41#define S5PV310_PA_CHIPID 0x10000000
74#define S5P_PA_SROMC S5PV310_PA_SROMC
75 42
76/* S/PDIF */ 43#define S5PV310_PA_SYSCON 0x10010000
77#define S5PV310_PA_SPDIF 0xE1100000 44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
78 46
79/* I2S */ 47#define S5PV310_PA_WATCHDOG 0x10060000
80#define S5PV310_PA_I2S0 0x03830000 48#define S5PV310_PA_RTC 0x10070000
81#define S5PV310_PA_I2S1 0xE3100000
82#define S5PV310_PA_I2S2 0xE2A00000
83 49
84/* PCM */ 50#define S5PV310_PA_DMC0 0x10400000
85#define S5PV310_PA_PCM0 0x03840000
86#define S5PV310_PA_PCM1 0x13980000
87#define S5PV310_PA_PCM2 0x13990000
88 51
89/* AC97 */ 52#define S5PV310_PA_COMBINER 0x10448000
90#define S5PV310_PA_AC97 0x139A0000
91 53
92#define S5PV310_PA_UART (0x13800000) 54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
93 59
94#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) 60#define S5PV310_PA_MDMA 0x10810000
95#define S5P_PA_UART0 S5P_PA_UART(0) 61#define S5PV310_PA_PDMA0 0x12680000
96#define S5P_PA_UART1 S5P_PA_UART(1) 62#define S5PV310_PA_PDMA1 0x12690000
97#define S5P_PA_UART2 S5P_PA_UART(2)
98#define S5P_PA_UART3 S5P_PA_UART(3)
99#define S5P_PA_UART4 S5P_PA_UART(4)
100
101#define S5P_SZ_UART SZ_256
102
103#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
104
105#define S5PV310_PA_TIMER (0x139D0000)
106#define S5P_PA_TIMER S5PV310_PA_TIMER
107
108#define S5PV310_PA_SDRAM (0x40000000)
109#define S5P_PA_SDRAM S5PV310_PA_SDRAM
110 63
111#define S5PV310_PA_SYSMMU_MDMA 0x10A40000 64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
112#define S5PV310_PA_SYSMMU_SSS 0x10A50000 65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
@@ -125,8 +78,31 @@
125#define S5PV310_PA_SYSMMU_MFC_L 0x13620000 78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
126#define S5PV310_PA_SYSMMU_MFC_R 0x13630000 79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
127 80
128/* compatibiltiy defines. */ 81#define S5PV310_PA_GPIO1 0x11400000
129#define S3C_PA_UART S5PV310_PA_UART 82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
130#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) 106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
131#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) 107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
132#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) 108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
@@ -141,7 +117,28 @@
141#define S3C_PA_IIC7 S5PV310_PA_IIC(7) 117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
142#define S3C_PA_RTC S5PV310_PA_RTC 118#define S3C_PA_RTC S5PV310_PA_RTC
143#define S3C_PA_WDT S5PV310_PA_WATCHDOG 119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
144#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
145#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
146 143
147#endif /* __ASM_ARCH_MAP_H */ 144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index 6a7342886171..afaf87fdb93e 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -28,7 +28,7 @@
28static struct resource s5p_uart0_resource[] = { 28static struct resource s5p_uart0_resource[] = {
29 [0] = { 29 [0] = {
30 .start = S5P_PA_UART0, 30 .start = S5P_PA_UART0,
31 .end = S5P_PA_UART0 + S5P_SZ_UART, 31 .end = S5P_PA_UART0 + S5P_SZ_UART - 1,
32 .flags = IORESOURCE_MEM, 32 .flags = IORESOURCE_MEM,
33 }, 33 },
34 [1] = { 34 [1] = {
@@ -51,7 +51,7 @@ static struct resource s5p_uart0_resource[] = {
51static struct resource s5p_uart1_resource[] = { 51static struct resource s5p_uart1_resource[] = {
52 [0] = { 52 [0] = {
53 .start = S5P_PA_UART1, 53 .start = S5P_PA_UART1,
54 .end = S5P_PA_UART1 + S5P_SZ_UART, 54 .end = S5P_PA_UART1 + S5P_SZ_UART - 1,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 }, 56 },
57 [1] = { 57 [1] = {
@@ -74,7 +74,7 @@ static struct resource s5p_uart1_resource[] = {
74static struct resource s5p_uart2_resource[] = { 74static struct resource s5p_uart2_resource[] = {
75 [0] = { 75 [0] = {
76 .start = S5P_PA_UART2, 76 .start = S5P_PA_UART2,
77 .end = S5P_PA_UART2 + S5P_SZ_UART, 77 .end = S5P_PA_UART2 + S5P_SZ_UART - 1,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79 }, 79 },
80 [1] = { 80 [1] = {
@@ -98,7 +98,7 @@ static struct resource s5p_uart3_resource[] = {
98#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 98#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
99 [0] = { 99 [0] = {
100 .start = S5P_PA_UART3, 100 .start = S5P_PA_UART3,
101 .end = S5P_PA_UART3 + S5P_SZ_UART, 101 .end = S5P_PA_UART3 + S5P_SZ_UART - 1,
102 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
103 }, 103 },
104 [1] = { 104 [1] = {
@@ -123,7 +123,7 @@ static struct resource s5p_uart4_resource[] = {
123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4 123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124 [0] = { 124 [0] = {
125 .start = S5P_PA_UART4, 125 .start = S5P_PA_UART4,
126 .end = S5P_PA_UART4 + S5P_SZ_UART, 126 .end = S5P_PA_UART4 + S5P_SZ_UART - 1,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, 128 },
129 [1] = { 129 [1] = {
@@ -148,7 +148,7 @@ static struct resource s5p_uart5_resource[] = {
148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5 148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149 [0] = { 149 [0] = {
150 .start = S5P_PA_UART5, 150 .start = S5P_PA_UART5,
151 .end = S5P_PA_UART5 + S5P_SZ_UART, 151 .end = S5P_PA_UART5 + S5P_SZ_UART - 1,
152 .flags = IORESOURCE_MEM, 152 .flags = IORESOURCE_MEM,
153 }, 153 },
154 [1] = { 154 [1] = {
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 236ef8427d7d..3e4bd8147bf4 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
58 58
59 s3c_device_ts.dev.platform_data = npd; 59 s3c_device_ts.dev.platform_data = npd;
60} 60}
61EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c
index 0851eb1e919e..2751b3a8a66f 100644
--- a/arch/s390/boot/compressed/misc.c
+++ b/arch/s390/boot/compressed/misc.c
@@ -133,11 +133,12 @@ unsigned long decompress_kernel(void)
133 unsigned long output_addr; 133 unsigned long output_addr;
134 unsigned char *output; 134 unsigned char *output;
135 135
136 check_ipl_parmblock((void *) 0, (unsigned long) output + SZ__bss_start); 136 output_addr = ((unsigned long) &_end + HEAP_SIZE + 4095UL) & -4096UL;
137 check_ipl_parmblock((void *) 0, output_addr + SZ__bss_start);
137 memset(&_bss, 0, &_ebss - &_bss); 138 memset(&_bss, 0, &_ebss - &_bss);
138 free_mem_ptr = (unsigned long)&_end; 139 free_mem_ptr = (unsigned long)&_end;
139 free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; 140 free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
140 output = (unsigned char *) ((free_mem_end_ptr + 4095UL) & -4096UL); 141 output = (unsigned char *) output_addr;
141 142
142#ifdef CONFIG_BLK_DEV_INITRD 143#ifdef CONFIG_BLK_DEV_INITRD
143 /* 144 /*
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index 76daea117181..5c5ba10384c2 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -36,14 +36,19 @@
36 36
37static inline int atomic_read(const atomic_t *v) 37static inline int atomic_read(const atomic_t *v)
38{ 38{
39 barrier(); 39 int c;
40 return v->counter; 40
41 asm volatile(
42 " l %0,%1\n"
43 : "=d" (c) : "Q" (v->counter));
44 return c;
41} 45}
42 46
43static inline void atomic_set(atomic_t *v, int i) 47static inline void atomic_set(atomic_t *v, int i)
44{ 48{
45 v->counter = i; 49 asm volatile(
46 barrier(); 50 " st %1,%0\n"
51 : "=Q" (v->counter) : "d" (i));
47} 52}
48 53
49static inline int atomic_add_return(int i, atomic_t *v) 54static inline int atomic_add_return(int i, atomic_t *v)
@@ -128,14 +133,19 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
128 133
129static inline long long atomic64_read(const atomic64_t *v) 134static inline long long atomic64_read(const atomic64_t *v)
130{ 135{
131 barrier(); 136 long long c;
132 return v->counter; 137
138 asm volatile(
139 " lg %0,%1\n"
140 : "=d" (c) : "Q" (v->counter));
141 return c;
133} 142}
134 143
135static inline void atomic64_set(atomic64_t *v, long long i) 144static inline void atomic64_set(atomic64_t *v, long long i)
136{ 145{
137 v->counter = i; 146 asm volatile(
138 barrier(); 147 " stg %1,%0\n"
148 : "=Q" (v->counter) : "d" (i));
139} 149}
140 150
141static inline long long atomic64_add_return(long long i, atomic64_t *v) 151static inline long long atomic64_add_return(long long i, atomic64_t *v)
diff --git a/arch/s390/include/asm/cache.h b/arch/s390/include/asm/cache.h
index 24aafa68b643..2a30d5ac0667 100644
--- a/arch/s390/include/asm/cache.h
+++ b/arch/s390/include/asm/cache.h
@@ -13,6 +13,7 @@
13 13
14#define L1_CACHE_BYTES 256 14#define L1_CACHE_BYTES 256
15#define L1_CACHE_SHIFT 8 15#define L1_CACHE_SHIFT 8
16#define NET_SKB_PAD 32
16 17
17#define __read_mostly __attribute__((__section__(".data..read_mostly"))) 18#define __read_mostly __attribute__((__section__(".data..read_mostly")))
18 19
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:10:06 -0500