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-rw-r--r--arch/arm/boot/Makefile10
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi4
-rw-r--r--arch/arm/include/asm/io.h4
-rw-r--r--arch/arm/include/asm/sched_clock.h2
-rw-r--r--arch/arm/include/asm/vfpmacros.h12
-rw-r--r--arch/arm/include/uapi/asm/hwcap.h3
-rw-r--r--arch/arm/kernel/sched_clock.c18
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c12
-rw-r--r--arch/arm/mach-highbank/system.c3
-rw-r--r--arch/arm/mach-imx/clk-gate2.c2
-rw-r--r--arch/arm/mach-imx/ehci-imx25.c2
-rw-r--r--arch/arm/mach-imx/ehci-imx35.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/devices.c79
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c63
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c36
-rw-r--r--arch/arm/mach-omap2/twl-common.c2
-rw-r--r--arch/arm/mach-omap2/vc.c2
-rw-r--r--arch/arm/mach-pxa/hx4700.c8
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c8
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h6
-rw-r--r--arch/arm/tools/Makefile2
-rw-r--r--arch/arm/vfp/vfpmodule.c9
-rw-r--r--arch/arm/xen/enlighten.c11
-rw-r--r--arch/arm64/Kconfig1
-rw-r--r--arch/arm64/include/asm/elf.h5
-rw-r--r--arch/arm64/include/asm/fpsimd.h5
-rw-r--r--arch/arm64/include/asm/io.h10
-rw-r--r--arch/arm64/include/asm/pgtable-hwdef.h6
-rw-r--r--arch/arm64/include/asm/pgtable.h40
-rw-r--r--arch/arm64/include/asm/processor.h2
-rw-r--r--arch/arm64/include/asm/unistd.h1
-rw-r--r--arch/arm64/kernel/perf_event.c10
-rw-r--r--arch/arm64/kernel/process.c18
-rw-r--r--arch/arm64/kernel/smp.c3
-rw-r--r--arch/arm64/mm/init.c2
-rw-r--r--arch/h8300/include/asm/cache.h3
-rw-r--r--arch/ia64/mm/init.c1
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c1
-rw-r--r--arch/mips/fw/arc/misc.c1
-rw-r--r--arch/mips/include/asm/bitops.h128
-rw-r--r--arch/mips/include/asm/compat.h2
-rw-r--r--arch/mips/include/asm/io.h1
-rw-r--r--arch/mips/include/asm/irqflags.h207
-rw-r--r--arch/mips/include/asm/thread_info.h6
-rw-r--r--arch/mips/lib/Makefile5
-rw-r--r--arch/mips/lib/bitops.c179
-rw-r--r--arch/mips/lib/mips-atomic.c176
-rw-r--r--arch/mips/mti-malta/malta-platform.c3
-rw-r--r--arch/s390/Kconfig1
-rw-r--r--arch/s390/include/asm/cio.h2
-rw-r--r--arch/s390/include/asm/compat.h2
-rw-r--r--arch/s390/include/asm/pgtable.h35
-rw-r--r--arch/s390/include/asm/topology.h3
-rw-r--r--arch/s390/include/uapi/asm/ptrace.h4
-rw-r--r--arch/s390/kernel/compat_signal.c14
-rw-r--r--arch/s390/kernel/sclp.S8
-rw-r--r--arch/s390/kernel/signal.c14
-rw-r--r--arch/s390/kernel/topology.c6
-rw-r--r--arch/s390/lib/uaccess_pt.c2
-rw-r--r--arch/s390/mm/gup.c7
-rw-r--r--arch/sparc/Kconfig1
-rw-r--r--arch/sparc/crypto/Makefile16
-rw-r--r--arch/sparc/crypto/aes_glue.c2
-rw-r--r--arch/sparc/crypto/camellia_glue.c2
-rw-r--r--arch/sparc/crypto/crc32c_glue.c2
-rw-r--r--arch/sparc/crypto/des_glue.c2
-rw-r--r--arch/sparc/crypto/md5_glue.c2
-rw-r--r--arch/sparc/crypto/sha1_glue.c2
-rw-r--r--arch/sparc/crypto/sha256_glue.c2
-rw-r--r--arch/sparc/crypto/sha512_glue.c2
-rw-r--r--arch/sparc/include/asm/atomic_64.h4
-rw-r--r--arch/sparc/include/asm/backoff.h69
-rw-r--r--arch/sparc/include/asm/compat.h5
-rw-r--r--arch/sparc/include/asm/processor_64.h17
-rw-r--r--arch/sparc/include/asm/prom.h5
-rw-r--r--arch/sparc/include/asm/thread_info_64.h5
-rw-r--r--arch/sparc/include/asm/ttable.h24
-rw-r--r--arch/sparc/include/uapi/asm/unistd.h7
-rw-r--r--arch/sparc/kernel/entry.h7
-rw-r--r--arch/sparc/kernel/leon_kernel.c6
-rw-r--r--arch/sparc/kernel/perf_event.c22
-rw-r--r--arch/sparc/kernel/process_64.c42
-rw-r--r--arch/sparc/kernel/ptrace_64.c4
-rw-r--r--arch/sparc/kernel/setup_64.c21
-rw-r--r--arch/sparc/kernel/sys_sparc_64.c5
-rw-r--r--arch/sparc/kernel/systbls_32.S1
-rw-r--r--arch/sparc/kernel/systbls_64.S2
-rw-r--r--arch/sparc/kernel/unaligned_64.c36
-rw-r--r--arch/sparc/kernel/visemul.c23
-rw-r--r--arch/sparc/kernel/vmlinux.lds.S5
-rw-r--r--arch/sparc/kernel/winfixup.S2
-rw-r--r--arch/sparc/lib/atomic_64.S16
-rw-r--r--arch/sparc/lib/ksyms.c1
-rw-r--r--arch/sparc/math-emu/math_64.c2
-rw-r--r--arch/unicore32/Kconfig7
-rw-r--r--arch/unicore32/include/asm/Kbuild1
-rw-r--r--arch/unicore32/include/asm/bug.h5
-rw-r--r--arch/unicore32/include/asm/cmpxchg.h2
-rw-r--r--arch/unicore32/include/asm/kvm_para.h1
-rw-r--r--arch/unicore32/include/asm/processor.h5
-rw-r--r--arch/unicore32/include/asm/ptrace.h76
-rw-r--r--arch/unicore32/include/uapi/asm/Kbuild7
-rw-r--r--arch/unicore32/include/uapi/asm/byteorder.h (renamed from arch/unicore32/include/asm/byteorder.h)0
-rw-r--r--arch/unicore32/include/uapi/asm/ptrace.h90
-rw-r--r--arch/unicore32/include/uapi/asm/sigcontext.h (renamed from arch/unicore32/include/asm/sigcontext.h)0
-rw-r--r--arch/unicore32/include/uapi/asm/unistd.h (renamed from arch/unicore32/include/asm/unistd.h)1
-rw-r--r--arch/unicore32/kernel/entry.S20
-rw-r--r--arch/unicore32/kernel/process.c58
-rw-r--r--arch/unicore32/kernel/setup.h6
-rw-r--r--arch/unicore32/kernel/sys.c63
-rw-r--r--arch/unicore32/mm/fault.c37
-rw-r--r--arch/x86/include/asm/xen/hypercall.h21
-rw-r--r--arch/x86/kvm/cpuid.h3
-rw-r--r--arch/x86/kvm/vmx.c11
-rw-r--r--arch/x86/kvm/x86.c3
121 files changed, 1286 insertions, 721 deletions
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index f2aa09eb658e..9137df539b61 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -33,7 +33,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y)
33 33
34$(obj)/xipImage: vmlinux FORCE 34$(obj)/xipImage: vmlinux FORCE
35 $(call if_changed,objcopy) 35 $(call if_changed,objcopy)
36 $(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))' 36 @$(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
37 37
38$(obj)/Image $(obj)/zImage: FORCE 38$(obj)/Image $(obj)/zImage: FORCE
39 @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)' 39 @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@@ -48,14 +48,14 @@ $(obj)/xipImage: FORCE
48 48
49$(obj)/Image: vmlinux FORCE 49$(obj)/Image: vmlinux FORCE
50 $(call if_changed,objcopy) 50 $(call if_changed,objcopy)
51 $(kecho) ' Kernel: $@ is ready' 51 @$(kecho) ' Kernel: $@ is ready'
52 52
53$(obj)/compressed/vmlinux: $(obj)/Image FORCE 53$(obj)/compressed/vmlinux: $(obj)/Image FORCE
54 $(Q)$(MAKE) $(build)=$(obj)/compressed $@ 54 $(Q)$(MAKE) $(build)=$(obj)/compressed $@
55 55
56$(obj)/zImage: $(obj)/compressed/vmlinux FORCE 56$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
57 $(call if_changed,objcopy) 57 $(call if_changed,objcopy)
58 $(kecho) ' Kernel: $@ is ready' 58 @$(kecho) ' Kernel: $@ is ready'
59 59
60endif 60endif
61 61
@@ -90,7 +90,7 @@ fi
90$(obj)/uImage: $(obj)/zImage FORCE 90$(obj)/uImage: $(obj)/zImage FORCE
91 @$(check_for_multiple_loadaddr) 91 @$(check_for_multiple_loadaddr)
92 $(call if_changed,uimage) 92 $(call if_changed,uimage)
93 $(kecho) ' Image $@ is ready' 93 @$(kecho) ' Image $@ is ready'
94 94
95$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE 95$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
96 $(Q)$(MAKE) $(build)=$(obj)/bootp $@ 96 $(Q)$(MAKE) $(build)=$(obj)/bootp $@
@@ -98,7 +98,7 @@ $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
98 98
99$(obj)/bootpImage: $(obj)/bootp/bootp FORCE 99$(obj)/bootpImage: $(obj)/bootp/bootp FORCE
100 $(call if_changed,objcopy) 100 $(call if_changed,objcopy)
101 $(kecho) ' Kernel: $@ is ready' 101 @$(kecho) ' Kernel: $@ is ready'
102 102
103PHONY += initrd FORCE 103PHONY += initrd FORCE
104initrd: 104initrd:
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d68..df7f2270fc91 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -73,8 +73,8 @@
73 73
74 pinmux: pinmux { 74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux"; 75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */ 76 reg = <0x70000868 0xd4 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */ 77 0x70003000 0x3e4>; /* Mux registers */
78 }; 78 };
79 79
80 serial@70006000 { 80 serial@70006000 {
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 35c1ed89b936..42f042ee4ada 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -64,7 +64,7 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
64static inline void __raw_writew(u16 val, volatile void __iomem *addr) 64static inline void __raw_writew(u16 val, volatile void __iomem *addr)
65{ 65{
66 asm volatile("strh %1, %0" 66 asm volatile("strh %1, %0"
67 : "+Qo" (*(volatile u16 __force *)addr) 67 : "+Q" (*(volatile u16 __force *)addr)
68 : "r" (val)); 68 : "r" (val));
69} 69}
70 70
@@ -72,7 +72,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr)
72{ 72{
73 u16 val; 73 u16 val;
74 asm volatile("ldrh %1, %0" 74 asm volatile("ldrh %1, %0"
75 : "+Qo" (*(volatile u16 __force *)addr), 75 : "+Q" (*(volatile u16 __force *)addr),
76 "=r" (val)); 76 "=r" (val));
77 return val; 77 return val;
78} 78}
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index 05b8e82ec9f5..e3f757263438 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -10,7 +10,5 @@
10 10
11extern void sched_clock_postinit(void); 11extern void sched_clock_postinit(void);
12extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate); 12extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
13extern void setup_sched_clock_needs_suspend(u32 (*read)(void), int bits,
14 unsigned long rate);
15 13
16#endif 14#endif
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 6a6f1e485f41..301c1db3e99b 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -27,9 +27,9 @@
27#if __LINUX_ARM_ARCH__ <= 6 27#if __LINUX_ARM_ARCH__ <= 6
28 ldr \tmp, =elf_hwcap @ may not have MVFR regs 28 ldr \tmp, =elf_hwcap @ may not have MVFR regs
29 ldr \tmp, [\tmp, #0] 29 ldr \tmp, [\tmp, #0]
30 tst \tmp, #HWCAP_VFPv3D16 30 tst \tmp, #HWCAP_VFPD32
31 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 31 ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
32 addne \base, \base, #32*4 @ step over unused register space 32 addeq \base, \base, #32*4 @ step over unused register space
33#else 33#else
34 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 34 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
35 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 35 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
@@ -51,9 +51,9 @@
51#if __LINUX_ARM_ARCH__ <= 6 51#if __LINUX_ARM_ARCH__ <= 6
52 ldr \tmp, =elf_hwcap @ may not have MVFR regs 52 ldr \tmp, =elf_hwcap @ may not have MVFR regs
53 ldr \tmp, [\tmp, #0] 53 ldr \tmp, [\tmp, #0]
54 tst \tmp, #HWCAP_VFPv3D16 54 tst \tmp, #HWCAP_VFPD32
55 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 55 stcnel p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
56 addne \base, \base, #32*4 @ step over unused register space 56 addeq \base, \base, #32*4 @ step over unused register space
57#else 57#else
58 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 58 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
59 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 59 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index f254f6503cce..3688fd15a32d 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -18,11 +18,12 @@
18#define HWCAP_THUMBEE (1 << 11) 18#define HWCAP_THUMBEE (1 << 11)
19#define HWCAP_NEON (1 << 12) 19#define HWCAP_NEON (1 << 12)
20#define HWCAP_VFPv3 (1 << 13) 20#define HWCAP_VFPv3 (1 << 13)
21#define HWCAP_VFPv3D16 (1 << 14) 21#define HWCAP_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */
22#define HWCAP_TLS (1 << 15) 22#define HWCAP_TLS (1 << 15)
23#define HWCAP_VFPv4 (1 << 16) 23#define HWCAP_VFPv4 (1 << 16)
24#define HWCAP_IDIVA (1 << 17) 24#define HWCAP_IDIVA (1 << 17)
25#define HWCAP_IDIVT (1 << 18) 25#define HWCAP_IDIVT (1 << 18)
26#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */
26#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) 27#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
27 28
28 29
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index e21bac20d90d..fc6692e2b603 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -107,13 +107,6 @@ static void sched_clock_poll(unsigned long wrap_ticks)
107 update_sched_clock(); 107 update_sched_clock();
108} 108}
109 109
110void __init setup_sched_clock_needs_suspend(u32 (*read)(void), int bits,
111 unsigned long rate)
112{
113 setup_sched_clock(read, bits, rate);
114 cd.needs_suspend = true;
115}
116
117void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) 110void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
118{ 111{
119 unsigned long r, w; 112 unsigned long r, w;
@@ -189,18 +182,15 @@ void __init sched_clock_postinit(void)
189static int sched_clock_suspend(void) 182static int sched_clock_suspend(void)
190{ 183{
191 sched_clock_poll(sched_clock_timer.data); 184 sched_clock_poll(sched_clock_timer.data);
192 if (cd.needs_suspend) 185 cd.suspended = true;
193 cd.suspended = true;
194 return 0; 186 return 0;
195} 187}
196 188
197static void sched_clock_resume(void) 189static void sched_clock_resume(void)
198{ 190{
199 if (cd.needs_suspend) { 191 cd.epoch_cyc = read_sched_clock();
200 cd.epoch_cyc = read_sched_clock(); 192 cd.epoch_cyc_copy = cd.epoch_cyc;
201 cd.epoch_cyc_copy = cd.epoch_cyc; 193 cd.suspended = false;
202 cd.suspended = false;
203 }
204} 194}
205 195
206static struct syscore_ops sched_clock_ops = { 196static struct syscore_ops sched_clock_ops = {
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 1e122bcd7845..3cee0e6ea7c3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -68,7 +68,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
68 68
69 /* Enable overcurrent notification */ 69 /* Enable overcurrent notification */
70 for (i = 0; i < data->ports; i++) { 70 for (i = 0; i < data->ports; i++) {
71 if (data->overcurrent_pin[i]) 71 if (gpio_is_valid(data->overcurrent_pin[i]))
72 at91_set_gpio_input(data->overcurrent_pin[i], 1); 72 at91_set_gpio_input(data->overcurrent_pin[i], 1);
73 } 73 }
74 74
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index aa1e58729885..414bd855fb0c 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
72 72
73 /* Enable overcurrent notification */ 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) { 74 for (i = 0; i < data->ports; i++) {
75 if (data->overcurrent_pin[i]) 75 if (gpio_is_valid(data->overcurrent_pin[i]))
76 at91_set_gpio_input(data->overcurrent_pin[i], 1); 76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 } 77 }
78 78
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index b9487696b7be..cd604aad8e96 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
72 72
73 /* Enable overcurrent notification */ 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) { 74 for (i = 0; i < data->ports; i++) {
75 if (data->overcurrent_pin[i]) 75 if (gpio_is_valid(data->overcurrent_pin[i]))
76 at91_set_gpio_input(data->overcurrent_pin[i], 1); 76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 } 77 }
78 78
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index cb85da2eccea..9c61e59a2104 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -78,7 +78,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
78 78
79 /* Enable overcurrent notification */ 79 /* Enable overcurrent notification */
80 for (i = 0; i < data->ports; i++) { 80 for (i = 0; i < data->ports; i++) {
81 if (data->overcurrent_pin[i]) 81 if (gpio_is_valid(data->overcurrent_pin[i]))
82 at91_set_gpio_input(data->overcurrent_pin[i], 1); 82 at91_set_gpio_input(data->overcurrent_pin[i], 1);
83 } 83 }
84 84
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b1596072dcc2..fcd233cb33d2 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -1841,8 +1841,8 @@ static struct resource sha_resources[] = {
1841 .flags = IORESOURCE_MEM, 1841 .flags = IORESOURCE_MEM,
1842 }, 1842 },
1843 [1] = { 1843 [1] = {
1844 .start = AT91SAM9G45_ID_AESTDESSHA, 1844 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1845 .end = AT91SAM9G45_ID_AESTDESSHA, 1845 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1846 .flags = IORESOURCE_IRQ, 1846 .flags = IORESOURCE_IRQ,
1847 }, 1847 },
1848}; 1848};
@@ -1874,8 +1874,8 @@ static struct resource tdes_resources[] = {
1874 .flags = IORESOURCE_MEM, 1874 .flags = IORESOURCE_MEM,
1875 }, 1875 },
1876 [1] = { 1876 [1] = {
1877 .start = AT91SAM9G45_ID_AESTDESSHA, 1877 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1878 .end = AT91SAM9G45_ID_AESTDESSHA, 1878 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1879 .flags = IORESOURCE_IRQ, 1879 .flags = IORESOURCE_IRQ,
1880 }, 1880 },
1881}; 1881};
@@ -1910,8 +1910,8 @@ static struct resource aes_resources[] = {
1910 .flags = IORESOURCE_MEM, 1910 .flags = IORESOURCE_MEM,
1911 }, 1911 },
1912 [1] = { 1912 [1] = {
1913 .start = AT91SAM9G45_ID_AESTDESSHA, 1913 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1914 .end = AT91SAM9G45_ID_AESTDESSHA, 1914 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1915 .flags = IORESOURCE_IRQ, 1915 .flags = IORESOURCE_IRQ,
1916 }, 1916 },
1917}; 1917};
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 82c27230d4a9..86e37cd9376c 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -28,6 +28,7 @@ void highbank_restart(char mode, const char *cmd)
28 hignbank_set_pwr_soft_reset(); 28 hignbank_set_pwr_soft_reset();
29 29
30 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); 30 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
31 cpu_do_idle(); 31 while (1)
32 cpu_do_idle();
32} 33}
33 34
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 3c1b8ff9a0a6..cc49c7ae186e 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -112,7 +112,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
112 112
113 clk = clk_register(dev, &gate->hw); 113 clk = clk_register(dev, &gate->hw);
114 if (IS_ERR(clk)) 114 if (IS_ERR(clk))
115 kfree(clk); 115 kfree(gate);
116 116
117 return clk; 117 return clk;
118} 118}
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 412c583a24b0..576af7446952 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -30,7 +30,7 @@
30#define MX25_H1_SIC_SHIFT 21 30#define MX25_H1_SIC_SHIFT 21
31#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) 31#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
32#define MX25_H1_PP_BIT (1 << 18) 32#define MX25_H1_PP_BIT (1 << 18)
33#define MX25_H1_PM_BIT (1 << 8) 33#define MX25_H1_PM_BIT (1 << 16)
34#define MX25_H1_IPPUE_UP_BIT (1 << 7) 34#define MX25_H1_IPPUE_UP_BIT (1 << 7)
35#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) 35#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
36#define MX25_H1_TLL_BIT (1 << 5) 36#define MX25_H1_TLL_BIT (1 << 5)
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 779e16eb65cb..293397852e4e 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -30,7 +30,7 @@
30#define MX35_H1_SIC_SHIFT 21 30#define MX35_H1_SIC_SHIFT 21
31#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) 31#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
32#define MX35_H1_PP_BIT (1 << 18) 32#define MX35_H1_PP_BIT (1 << 18)
33#define MX35_H1_PM_BIT (1 << 8) 33#define MX35_H1_PM_BIT (1 << 16)
34#define MX35_H1_IPPUE_UP_BIT (1 << 7) 34#define MX35_H1_IPPUE_UP_BIT (1 << 7)
35#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) 35#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
36#define MX35_H1_TLL_BIT (1 << 5) 36#define MX35_H1_TLL_BIT (1 << 5)
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index b56d06b48782..95192a062d5d 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -359,7 +359,7 @@ static struct clockdomain iss_44xx_clkdm = {
359 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, 359 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
360 .wkdep_srcs = iss_wkup_sleep_deps, 360 .wkdep_srcs = iss_wkup_sleep_deps,
361 .sleepdep_srcs = iss_wkup_sleep_deps, 361 .sleepdep_srcs = iss_wkup_sleep_deps,
362 .flags = CLKDM_CAN_HWSUP_SWSUP, 362 .flags = CLKDM_CAN_SWSUP,
363}; 363};
364 364
365static struct clockdomain l3_dss_44xx_clkdm = { 365static struct clockdomain l3_dss_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index cba60e05e32e..c72b5a727720 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/machine.h>
21#include <linux/platform_data/omap4-keypad.h> 21#include <linux/platform_data/omap4-keypad.h>
22#include <linux/platform_data/omap_ocp2scp.h>
22 23
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -613,6 +614,83 @@ static void omap_init_vout(void)
613static inline void omap_init_vout(void) {} 614static inline void omap_init_vout(void) {}
614#endif 615#endif
615 616
617#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
618static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
619{
620 int cnt = 0;
621
622 while (ocp2scp_dev->drv_name != NULL) {
623 cnt++;
624 ocp2scp_dev++;
625 }
626
627 return cnt;
628}
629
630static void omap_init_ocp2scp(void)
631{
632 struct omap_hwmod *oh;
633 struct platform_device *pdev;
634 int bus_id = -1, dev_cnt = 0, i;
635 struct omap_ocp2scp_dev *ocp2scp_dev;
636 const char *oh_name, *name;
637 struct omap_ocp2scp_platform_data *pdata;
638
639 if (!cpu_is_omap44xx())
640 return;
641
642 oh_name = "ocp2scp_usb_phy";
643 name = "omap-ocp2scp";
644
645 oh = omap_hwmod_lookup(oh_name);
646 if (!oh) {
647 pr_err("%s: could not find omap_hwmod for %s\n", __func__,
648 oh_name);
649 return;
650 }
651
652 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
653 if (!pdata) {
654 pr_err("%s: No memory for ocp2scp pdata\n", __func__);
655 return;
656 }
657
658 ocp2scp_dev = oh->dev_attr;
659 dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
660
661 if (!dev_cnt) {
662 pr_err("%s: No devices connected to ocp2scp\n", __func__);
663 kfree(pdata);
664 return;
665 }
666
667 pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
668 * dev_cnt, GFP_KERNEL);
669 if (!pdata->devices) {
670 pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
671 kfree(pdata);
672 return;
673 }
674
675 for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
676 pdata->devices[i] = ocp2scp_dev;
677
678 pdata->dev_cnt = dev_cnt;
679
680 pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL,
681 0, false);
682 if (IS_ERR(pdev)) {
683 pr_err("Could not build omap_device for %s %s\n",
684 name, oh_name);
685 kfree(pdata->devices);
686 kfree(pdata);
687 return;
688 }
689}
690#else
691static inline void omap_init_ocp2scp(void) { }
692#endif
693
616/*-------------------------------------------------------------------------*/ 694/*-------------------------------------------------------------------------*/
617 695
618static int __init omap2_init_devices(void) 696static int __init omap2_init_devices(void)
@@ -640,6 +718,7 @@ static int __init omap2_init_devices(void)
640 omap_init_sham(); 718 omap_init_sham();
641 omap_init_aes(); 719 omap_init_aes();
642 omap_init_vout(); 720 omap_init_vout();
721 omap_init_ocp2scp();
643 722
644 return 0; 723 return 0;
645} 724}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1d258b..87cc6d058de2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -422,6 +422,38 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
422} 422}
423 423
424/** 424/**
425 * _wait_softreset_complete - wait for an OCP softreset to complete
426 * @oh: struct omap_hwmod * to wait on
427 *
428 * Wait until the IP block represented by @oh reports that its OCP
429 * softreset is complete. This can be triggered by software (see
430 * _ocp_softreset()) or by hardware upon returning from off-mode (one
431 * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT
432 * microseconds. Returns the number of microseconds waited.
433 */
434static int _wait_softreset_complete(struct omap_hwmod *oh)
435{
436 struct omap_hwmod_class_sysconfig *sysc;
437 u32 softrst_mask;
438 int c = 0;
439
440 sysc = oh->class->sysc;
441
442 if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
443 omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
444 & SYSS_RESETDONE_MASK),
445 MAX_MODULE_SOFTRESET_WAIT, c);
446 else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
447 softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
448 omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
449 & softrst_mask),
450 MAX_MODULE_SOFTRESET_WAIT, c);
451 }
452
453 return c;
454}
455
456/**
425 * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v 457 * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
426 * @oh: struct omap_hwmod * 458 * @oh: struct omap_hwmod *
427 * 459 *
@@ -1282,6 +1314,18 @@ static void _enable_sysc(struct omap_hwmod *oh)
1282 if (!oh->class->sysc) 1314 if (!oh->class->sysc)
1283 return; 1315 return;
1284 1316
1317 /*
1318 * Wait until reset has completed, this is needed as the IP
1319 * block is reset automatically by hardware in some cases
1320 * (off-mode for example), and the drivers require the
1321 * IP to be ready when they access it
1322 */
1323 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1324 _enable_optional_clocks(oh);
1325 _wait_softreset_complete(oh);
1326 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1327 _disable_optional_clocks(oh);
1328
1285 v = oh->_sysc_cache; 1329 v = oh->_sysc_cache;
1286 sf = oh->class->sysc->sysc_flags; 1330 sf = oh->class->sysc->sysc_flags;
1287 1331
@@ -1804,7 +1848,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
1804 */ 1848 */
1805static int _ocp_softreset(struct omap_hwmod *oh) 1849static int _ocp_softreset(struct omap_hwmod *oh)
1806{ 1850{
1807 u32 v, softrst_mask; 1851 u32 v;
1808 int c = 0; 1852 int c = 0;
1809 int ret = 0; 1853 int ret = 0;
1810 1854
@@ -1834,19 +1878,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1834 if (oh->class->sysc->srst_udelay) 1878 if (oh->class->sysc->srst_udelay)
1835 udelay(oh->class->sysc->srst_udelay); 1879 udelay(oh->class->sysc->srst_udelay);
1836 1880
1837 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) 1881 c = _wait_softreset_complete(oh);
1838 omap_test_timeout((omap_hwmod_read(oh,
1839 oh->class->sysc->syss_offs)
1840 & SYSS_RESETDONE_MASK),
1841 MAX_MODULE_SOFTRESET_WAIT, c);
1842 else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
1843 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
1844 omap_test_timeout(!(omap_hwmod_read(oh,
1845 oh->class->sysc->sysc_offs)
1846 & softrst_mask),
1847 MAX_MODULE_SOFTRESET_WAIT, c);
1848 }
1849
1850 if (c == MAX_MODULE_SOFTRESET_WAIT) 1882 if (c == MAX_MODULE_SOFTRESET_WAIT)
1851 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", 1883 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1852 oh->name, MAX_MODULE_SOFTRESET_WAIT); 1884 oh->name, MAX_MODULE_SOFTRESET_WAIT);
@@ -2352,6 +2384,9 @@ static int __init _setup_reset(struct omap_hwmod *oh)
2352 if (oh->_state != _HWMOD_STATE_INITIALIZED) 2384 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2353 return -EINVAL; 2385 return -EINVAL;
2354 2386
2387 if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK)
2388 return -EPERM;
2389
2355 if (oh->rst_lines_cnt == 0) { 2390 if (oh->rst_lines_cnt == 0) {
2356 r = _enable(oh); 2391 r = _enable(oh);
2357 if (r) { 2392 if (r) {
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 652d0285bd6d..0b1249e00398 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/platform_data/gpio-omap.h> 22#include <linux/platform_data/gpio-omap.h>
23#include <linux/power/smartreflex.h> 23#include <linux/power/smartreflex.h>
24#include <linux/platform_data/omap_ocp2scp.h>
24 25
25#include <plat/omap_hwmod.h> 26#include <plat/omap_hwmod.h>
26#include <plat/i2c.h> 27#include <plat/i2c.h>
@@ -2125,6 +2126,14 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2125 .name = "mcpdm", 2126 .name = "mcpdm",
2126 .class = &omap44xx_mcpdm_hwmod_class, 2127 .class = &omap44xx_mcpdm_hwmod_class,
2127 .clkdm_name = "abe_clkdm", 2128 .clkdm_name = "abe_clkdm",
2129 /*
2130 * It's suspected that the McPDM requires an off-chip main
2131 * functional clock, controlled via I2C. This IP block is
2132 * currently reset very early during boot, before I2C is
2133 * available, so it doesn't seem that we have any choice in
2134 * the kernel other than to avoid resetting it.
2135 */
2136 .flags = HWMOD_EXT_OPT_MAIN_CLK,
2128 .mpu_irqs = omap44xx_mcpdm_irqs, 2137 .mpu_irqs = omap44xx_mcpdm_irqs,
2129 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 2138 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2130 .main_clk = "mcpdm_fck", 2139 .main_clk = "mcpdm_fck",
@@ -2681,6 +2690,32 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2681 .sysc = &omap44xx_ocp2scp_sysc, 2690 .sysc = &omap44xx_ocp2scp_sysc,
2682}; 2691};
2683 2692
2693/* ocp2scp dev_attr */
2694static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2695 {
2696 .name = "usb_phy",
2697 .start = 0x4a0ad080,
2698 .end = 0x4a0ae000,
2699 .flags = IORESOURCE_MEM,
2700 },
2701 {
2702 /* XXX: Remove this once control module driver is in place */
2703 .name = "ctrl_dev",
2704 .start = 0x4a002300,
2705 .end = 0x4a002303,
2706 .flags = IORESOURCE_MEM,
2707 },
2708 { }
2709};
2710
2711static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2712 {
2713 .drv_name = "omap-usb2",
2714 .res = omap44xx_usb_phy_and_pll_addrs,
2715 },
2716 { }
2717};
2718
2684/* ocp2scp_usb_phy */ 2719/* ocp2scp_usb_phy */
2685static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { 2720static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2686 .name = "ocp2scp_usb_phy", 2721 .name = "ocp2scp_usb_phy",
@@ -2694,6 +2729,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2694 .modulemode = MODULEMODE_HWCTRL, 2729 .modulemode = MODULEMODE_HWCTRL,
2695 }, 2730 },
2696 }, 2731 },
2732 .dev_attr = ocp2scp_dev_attr,
2697}; 2733};
2698 2734
2699/* 2735/*
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 635e109f5ad3..44c42057b61c 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -366,7 +366,7 @@ static struct regulator_init_data omap4_clk32kg_idata = {
366}; 366};
367 367
368static struct regulator_consumer_supply omap4_vdd1_supply[] = { 368static struct regulator_consumer_supply omap4_vdd1_supply[] = {
369 REGULATOR_SUPPLY("vcc", "mpu.0"), 369 REGULATOR_SUPPLY("vcc", "cpu0"),
370}; 370};
371 371
372static struct regulator_consumer_supply omap4_vdd2_supply[] = { 372static struct regulator_consumer_supply omap4_vdd2_supply[] = {
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 880249b17012..75878c37959b 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -264,7 +264,7 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
264 264
265 if (initialized) { 265 if (initialized) {
266 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 266 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
267 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).", 267 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
268 __func__, voltdm->name, i2c_high_speed); 268 __func__, voltdm->name, i2c_high_speed);
269 return; 269 return;
270 } 270 }
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 5ecbd17b5641..e2c6391863fe 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -28,6 +28,7 @@
28#include <linux/mfd/asic3.h> 28#include <linux/mfd/asic3.h>
29#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/pda_power.h> 30#include <linux/pda_power.h>
31#include <linux/pwm.h>
31#include <linux/pwm_backlight.h> 32#include <linux/pwm_backlight.h>
32#include <linux/regulator/driver.h> 33#include <linux/regulator/driver.h>
33#include <linux/regulator/gpio-regulator.h> 34#include <linux/regulator/gpio-regulator.h>
@@ -556,7 +557,7 @@ static struct platform_device hx4700_lcd = {
556 */ 557 */
557 558
558static struct platform_pwm_backlight_data backlight_data = { 559static struct platform_pwm_backlight_data backlight_data = {
559 .pwm_id = 1, 560 .pwm_id = -1, /* Superseded by pwm_lookup */
560 .max_brightness = 200, 561 .max_brightness = 200,
561 .dft_brightness = 100, 562 .dft_brightness = 100,
562 .pwm_period_ns = 30923, 563 .pwm_period_ns = 30923,
@@ -571,6 +572,10 @@ static struct platform_device backlight = {
571 }, 572 },
572}; 573};
573 574
575static struct pwm_lookup hx4700_pwm_lookup[] = {
576 PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight", NULL),
577};
578
574/* 579/*
575 * USB "Transceiver" 580 * USB "Transceiver"
576 */ 581 */
@@ -872,6 +877,7 @@ static void __init hx4700_init(void)
872 pxa_set_stuart_info(NULL); 877 pxa_set_stuart_info(NULL);
873 878
874 platform_add_devices(devices, ARRAY_SIZE(devices)); 879 platform_add_devices(devices, ARRAY_SIZE(devices));
880 pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));
875 881
876 pxa_set_ficp_info(&ficp_info); 882 pxa_set_ficp_info(&ficp_info);
877 pxa27x_set_i2c_power_info(NULL); 883 pxa27x_set_i2c_power_info(NULL);
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 438f02fe122a..842596d4d31e 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -86,10 +86,7 @@ static void spitz_discharge1(int on)
86 gpio_set_value(SPITZ_GPIO_LED_GREEN, on); 86 gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
87} 87}
88 88
89static unsigned long gpio18_config[] = { 89static unsigned long gpio18_config = GPIO18_GPIO;
90 GPIO18_RDY,
91 GPIO18_GPIO,
92};
93 90
94static void spitz_presuspend(void) 91static void spitz_presuspend(void)
95{ 92{
@@ -112,7 +109,7 @@ static void spitz_presuspend(void)
112 PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT; 109 PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
113 PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0); 110 PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
114 111
115 pxa2xx_mfp_config(&gpio18_config[0], 1); 112 pxa2xx_mfp_config(&gpio18_config, 1);
116 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown"); 113 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
117 gpio_free(18); 114 gpio_free(18);
118 115
@@ -131,7 +128,6 @@ static void spitz_presuspend(void)
131 128
132static void spitz_postsuspend(void) 129static void spitz_postsuspend(void)
133{ 130{
134 pxa2xx_mfp_config(&gpio18_config[1], 1);
135} 131}
136 132
137static int spitz_should_wakeup(unsigned int resume_on_alarm) 133static int spitz_should_wakeup(unsigned int resume_on_alarm)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 023f443784ec..b820edaf3184 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -745,7 +745,7 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
745static int 745static int
746do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 746do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
747{ 747{
748 union offset_union offset; 748 union offset_union uninitialized_var(offset);
749 unsigned long instr = 0, instrptr; 749 unsigned long instr = 0, instrptr;
750 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs); 750 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
751 unsigned int type; 751 unsigned int type;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index b3349f7b1a2c..1db029438022 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -443,6 +443,11 @@ struct omap_hwmod_omap4_prcm {
443 * in order to complete the reset. Optional clocks will be disabled 443 * in order to complete the reset. Optional clocks will be disabled
444 * again after the reset. 444 * again after the reset.
445 * HWMOD_16BIT_REG: Module has 16bit registers 445 * HWMOD_16BIT_REG: Module has 16bit registers
446 * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
447 * this IP block comes from an off-chip source and is not always
448 * enabled. This prevents the hwmod code from being able to
449 * enable and reset the IP block early. XXX Eventually it should
450 * be possible to query the clock framework for this information.
446 */ 451 */
447#define HWMOD_SWSUP_SIDLE (1 << 0) 452#define HWMOD_SWSUP_SIDLE (1 << 0)
448#define HWMOD_SWSUP_MSTANDBY (1 << 1) 453#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -453,6 +458,7 @@ struct omap_hwmod_omap4_prcm {
453#define HWMOD_NO_IDLEST (1 << 6) 458#define HWMOD_NO_IDLEST (1 << 6)
454#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) 459#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
455#define HWMOD_16BIT_REG (1 << 8) 460#define HWMOD_16BIT_REG (1 << 8)
461#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
456 462
457/* 463/*
458 * omap_hwmod._int_flags definitions 464 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index cd60a81163e9..32d05c8219dc 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -5,6 +5,6 @@
5# 5#
6 6
7include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types 7include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
8 $(kecho) ' Generating $@' 8 @$(kecho) ' Generating $@'
9 @mkdir -p $(dir $@) 9 @mkdir -p $(dir $@)
10 $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; } 10 $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index c834b32af275..3b44e0dd0a93 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -701,11 +701,14 @@ static int __init vfp_init(void)
701 elf_hwcap |= HWCAP_VFPv3; 701 elf_hwcap |= HWCAP_VFPv3;
702 702
703 /* 703 /*
704 * Check for VFPv3 D16. CPUs in this configuration 704 * Check for VFPv3 D16 and VFPv4 D16. CPUs in
705 * only have 16 x 64bit registers. 705 * this configuration only have 16 x 64bit
706 * registers.
706 */ 707 */
707 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1) 708 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
708 elf_hwcap |= HWCAP_VFPv3D16; 709 elf_hwcap |= HWCAP_VFPv3D16; /* also v4-D16 */
710 else
711 elf_hwcap |= HWCAP_VFPD32;
709 } 712 }
710#endif 713#endif
711 /* 714 /*
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 59bcb96ac369..f57609275449 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -166,3 +166,14 @@ void free_xenballooned_pages(int nr_pages, struct page **pages)
166 *pages = NULL; 166 *pages = NULL;
167} 167}
168EXPORT_SYMBOL_GPL(free_xenballooned_pages); 168EXPORT_SYMBOL_GPL(free_xenballooned_pages);
169
170/* In the hypervisor.S file. */
171EXPORT_SYMBOL_GPL(HYPERVISOR_event_channel_op);
172EXPORT_SYMBOL_GPL(HYPERVISOR_grant_table_op);
173EXPORT_SYMBOL_GPL(HYPERVISOR_xen_version);
174EXPORT_SYMBOL_GPL(HYPERVISOR_console_io);
175EXPORT_SYMBOL_GPL(HYPERVISOR_sched_op);
176EXPORT_SYMBOL_GPL(HYPERVISOR_hvm_op);
177EXPORT_SYMBOL_GPL(HYPERVISOR_memory_op);
178EXPORT_SYMBOL_GPL(HYPERVISOR_physdev_op);
179EXPORT_SYMBOL_GPL(privcmd_call);
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ef54a59a9e89..15ac18a56c93 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,6 +1,7 @@
1config ARM64 1config ARM64
2 def_bool y 2 def_bool y
3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
4 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
4 select GENERIC_CLOCKEVENTS 5 select GENERIC_CLOCKEVENTS
5 select GENERIC_HARDIRQS_NO_DEPRECATED 6 select GENERIC_HARDIRQS_NO_DEPRECATED
6 select GENERIC_IOMAP 7 select GENERIC_IOMAP
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index cf284649dfcb..07fea290d7c1 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -25,12 +25,10 @@
25#include <asm/user.h> 25#include <asm/user.h>
26 26
27typedef unsigned long elf_greg_t; 27typedef unsigned long elf_greg_t;
28typedef unsigned long elf_freg_t[3];
29 28
30#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) 29#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
31typedef elf_greg_t elf_gregset_t[ELF_NGREG]; 30typedef elf_greg_t elf_gregset_t[ELF_NGREG];
32 31typedef struct user_fpsimd_state elf_fpregset_t;
33typedef struct user_fp elf_fpregset_t;
34 32
35#define EM_AARCH64 183 33#define EM_AARCH64 183
36 34
@@ -87,7 +85,6 @@ typedef struct user_fp elf_fpregset_t;
87#define R_AARCH64_MOVW_PREL_G2_NC 292 85#define R_AARCH64_MOVW_PREL_G2_NC 292
88#define R_AARCH64_MOVW_PREL_G3 293 86#define R_AARCH64_MOVW_PREL_G3 293
89 87
90
91/* 88/*
92 * These are used to set parameters in the core dumps. 89 * These are used to set parameters in the core dumps.
93 */ 90 */
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index b42fab9f62a9..c43b4ac13008 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -25,9 +25,8 @@
25 * - FPSR and FPCR 25 * - FPSR and FPCR
26 * - 32 128-bit data registers 26 * - 32 128-bit data registers
27 * 27 *
28 * Note that user_fp forms a prefix of this structure, which is relied 28 * Note that user_fpsimd forms a prefix of this structure, which is
29 * upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must 29 * relied upon in the ptrace FP/SIMD accessors.
30 * form a prefix of struct fpsimd_state.
31 */ 30 */
32struct fpsimd_state { 31struct fpsimd_state {
33 union { 32 union {
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 74a2a7d304a9..d2f05a608274 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -114,7 +114,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
114 * I/O port access primitives. 114 * I/O port access primitives.
115 */ 115 */
116#define IO_SPACE_LIMIT 0xffff 116#define IO_SPACE_LIMIT 0xffff
117#define PCI_IOBASE ((void __iomem *)0xffffffbbfffe0000UL) 117#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_2M))
118 118
119static inline u8 inb(unsigned long addr) 119static inline u8 inb(unsigned long addr)
120{ 120{
@@ -222,12 +222,12 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot
222extern void __iounmap(volatile void __iomem *addr); 222extern void __iounmap(volatile void __iomem *addr);
223 223
224#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY) 224#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
225#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 225#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
226#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) 226#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
227 227
228#define ioremap(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE) 228#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
229#define ioremap_nocache(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE) 229#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
230#define ioremap_wc(addr, size) __ioremap((addr), (size), PROT_NORMAL_NC) 230#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
231#define iounmap __iounmap 231#define iounmap __iounmap
232 232
233#define ARCH_HAS_IOREMAP_WC 233#define ARCH_HAS_IOREMAP_WC
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 0f3b4581d925..75fd13d289b9 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -38,7 +38,8 @@
38#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 38#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
39#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 39#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
40#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 40#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
41#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 41#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
42#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
42 43
43/* 44/*
44 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 45 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
@@ -57,7 +58,8 @@
57#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 58#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
58#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 59#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
59#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 60#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
60#define PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 61#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
62#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
61 63
62/* 64/*
63 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 65 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 8960239be722..14aba2db6776 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -62,23 +62,23 @@ extern pgprot_t pgprot_default;
62 62
63#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b)) 63#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
64 64
65#define PAGE_NONE _MOD_PROT(pgprot_default, PTE_NG | PTE_XN | PTE_RDONLY) 65#define PAGE_NONE _MOD_PROT(pgprot_default, PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
66#define PAGE_SHARED _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN) 66#define PAGE_SHARED _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
67#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG) 67#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
68#define PAGE_COPY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY) 68#define PAGE_COPY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
69#define PAGE_COPY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY) 69#define PAGE_COPY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
70#define PAGE_READONLY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY) 70#define PAGE_READONLY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
71#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY) 71#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
72#define PAGE_KERNEL _MOD_PROT(pgprot_default, PTE_XN | PTE_DIRTY) 72#define PAGE_KERNEL _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
73#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_default, PTE_DIRTY) 73#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
74 74
75#define __PAGE_NONE __pgprot(_PAGE_DEFAULT | PTE_NG | PTE_XN | PTE_RDONLY) 75#define __PAGE_NONE __pgprot(_PAGE_DEFAULT | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
76#define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN) 76#define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
77#define __PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG) 77#define __PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
78#define __PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY) 78#define __PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
79#define __PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY) 79#define __PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
80#define __PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY) 80#define __PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
81#define __PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY) 81#define __PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
82 82
83#endif /* __ASSEMBLY__ */ 83#endif /* __ASSEMBLY__ */
84 84
@@ -130,10 +130,10 @@ extern struct page *empty_zero_page;
130#define pte_young(pte) (pte_val(pte) & PTE_AF) 130#define pte_young(pte) (pte_val(pte) & PTE_AF)
131#define pte_special(pte) (pte_val(pte) & PTE_SPECIAL) 131#define pte_special(pte) (pte_val(pte) & PTE_SPECIAL)
132#define pte_write(pte) (!(pte_val(pte) & PTE_RDONLY)) 132#define pte_write(pte) (!(pte_val(pte) & PTE_RDONLY))
133#define pte_exec(pte) (!(pte_val(pte) & PTE_XN)) 133#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
134 134
135#define pte_present_exec_user(pte) \ 135#define pte_present_exec_user(pte) \
136 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_XN)) == \ 136 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == \
137 (PTE_VALID | PTE_USER)) 137 (PTE_VALID | PTE_USER))
138 138
139#define PTE_BIT_FUNC(fn,op) \ 139#define PTE_BIT_FUNC(fn,op) \
@@ -262,7 +262,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
262 262
263static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 263static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
264{ 264{
265 const pteval_t mask = PTE_USER | PTE_XN | PTE_RDONLY; 265 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY;
266 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 266 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
267 return pte; 267 return pte;
268} 268}
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 5d810044feda..77f696c14339 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -43,6 +43,8 @@
43#else 43#else
44#define STACK_TOP STACK_TOP_MAX 44#define STACK_TOP STACK_TOP_MAX
45#endif /* CONFIG_COMPAT */ 45#endif /* CONFIG_COMPAT */
46
47#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK
46#endif /* __KERNEL__ */ 48#endif /* __KERNEL__ */
47 49
48struct debug_info { 50struct debug_info {
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 63f853f8b718..68aff2816e86 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -14,7 +14,6 @@
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16#ifdef CONFIG_COMPAT 16#ifdef CONFIG_COMPAT
17#define __ARCH_WANT_COMPAT_IPC_PARSE_VERSION
18#define __ARCH_WANT_COMPAT_STAT64 17#define __ARCH_WANT_COMPAT_STAT64
19#define __ARCH_WANT_SYS_GETHOSTNAME 18#define __ARCH_WANT_SYS_GETHOSTNAME
20#define __ARCH_WANT_SYS_PAUSE 19#define __ARCH_WANT_SYS_PAUSE
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index ecbf2d81ec5c..c76c7241125b 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -613,17 +613,11 @@ enum armv8_pmuv3_perf_types {
613 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19, 613 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
614 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A, 614 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
615 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D, 615 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
616
617 /*
618 * This isn't an architected event.
619 * We detect this event number and use the cycle counter instead.
620 */
621 ARMV8_PMUV3_PERFCTR_CPU_CYCLES = 0xFF,
622}; 616};
623 617
624/* PMUv3 HW events mapping. */ 618/* PMUv3 HW events mapping. */
625static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 619static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
626 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 620 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
627 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED, 621 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
628 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS, 622 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
629 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL, 623 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
@@ -1106,7 +1100,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1106 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT; 1100 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1107 1101
1108 /* Always place a cycle counter into the cycle counter. */ 1102 /* Always place a cycle counter into the cycle counter. */
1109 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { 1103 if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1110 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) 1104 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1111 return -EAGAIN; 1105 return -EAGAIN;
1112 1106
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index f22965ea1cfc..e04cebdbb47f 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -310,24 +310,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
310} 310}
311 311
312/* 312/*
313 * Fill in the task's elfregs structure for a core dump.
314 */
315int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
316{
317 elf_core_copy_regs(elfregs, task_pt_regs(t));
318 return 1;
319}
320
321/*
322 * fill in the fpe structure for a core dump...
323 */
324int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
325{
326 return 0;
327}
328EXPORT_SYMBOL(dump_fpu);
329
330/*
331 * Shuffle the argument into the correct register before calling the 313 * Shuffle the argument into the correct register before calling the
332 * thread function. x1 is the thread argument, x2 is the pointer to 314 * thread function. x1 is the thread argument, x2 is the pointer to
333 * the thread function, and x3 points to the exit function. 315 * the thread function, and x3 points to the exit function.
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 226b6bf6e9c2..538300f2273d 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -211,8 +211,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
211 * before we continue. 211 * before we continue.
212 */ 212 */
213 set_cpu_online(cpu, true); 213 set_cpu_online(cpu, true);
214 while (!cpu_active(cpu)) 214 complete(&cpu_running);
215 cpu_relax();
216 215
217 /* 216 /*
218 * OK, it's off to the idle thread for us 217 * OK, it's off to the idle thread for us
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index efbf7df05d3f..4cd28931dba9 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -80,7 +80,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
80#ifdef CONFIG_ZONE_DMA32 80#ifdef CONFIG_ZONE_DMA32
81 /* 4GB maximum for 32-bit only capable devices */ 81 /* 4GB maximum for 32-bit only capable devices */
82 max_dma32 = min(max, MAX_DMA32_PFN); 82 max_dma32 = min(max, MAX_DMA32_PFN);
83 zone_size[ZONE_DMA32] = max_dma32 - min; 83 zone_size[ZONE_DMA32] = max(min, max_dma32) - min;
84#endif 84#endif
85 zone_size[ZONE_NORMAL] = max - max_dma32; 85 zone_size[ZONE_NORMAL] = max - max_dma32;
86 86
diff --git a/arch/h8300/include/asm/cache.h b/arch/h8300/include/asm/cache.h
index c6350283649d..05887a1d80e5 100644
--- a/arch/h8300/include/asm/cache.h
+++ b/arch/h8300/include/asm/cache.h
@@ -2,7 +2,8 @@
2#define __ARCH_H8300_CACHE_H 2#define __ARCH_H8300_CACHE_H
3 3
4/* bytes per L1 cache line */ 4/* bytes per L1 cache line */
5#define L1_CACHE_BYTES 4 5#define L1_CACHE_SHIFT 2
6#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
6 7
7/* m68k-elf-gcc 2.95.2 doesn't like these */ 8/* m68k-elf-gcc 2.95.2 doesn't like these */
8 9
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index acd5b68e8871..082e383c1b6f 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -637,7 +637,6 @@ mem_init (void)
637 637
638 high_memory = __va(max_low_pfn * PAGE_SIZE); 638 high_memory = __va(max_low_pfn * PAGE_SIZE);
639 639
640 reset_zone_present_pages();
641 for_each_online_pgdat(pgdat) 640 for_each_online_pgdat(pgdat)
642 if (pgdat->bdata->node_bootmem_map) 641 if (pgdat->bdata->node_bootmem_map)
643 totalram_pages += free_all_bootmem_node(pgdat); 642 totalram_pages += free_all_bootmem_node(pgdat);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index d38246e33ddb..9f883bf76953 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -30,6 +30,7 @@
30 * measurement, and debugging facilities. 30 * measurement, and debugging facilities.
31 */ 31 */
32 32
33#include <linux/irqflags.h>
33#include <asm/octeon/cvmx.h> 34#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-l2c.h> 35#include <asm/octeon/cvmx-l2c.h>
35#include <asm/octeon/cvmx-spinlock.h> 36#include <asm/octeon/cvmx-spinlock.h>
diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c
index 7cf80ca2c1d2..f9f5307434c2 100644
--- a/arch/mips/fw/arc/misc.c
+++ b/arch/mips/fw/arc/misc.c
@@ -11,6 +11,7 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irqflags.h>
14 15
15#include <asm/bcache.h> 16#include <asm/bcache.h>
16 17
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 82ad35ce2b45..46ac73abd5ee 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -14,7 +14,6 @@
14#endif 14#endif
15 15
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/irqflags.h>
18#include <linux/types.h> 17#include <linux/types.h>
19#include <asm/barrier.h> 18#include <asm/barrier.h>
20#include <asm/byteorder.h> /* sigh ... */ 19#include <asm/byteorder.h> /* sigh ... */
@@ -44,6 +43,24 @@
44#define smp_mb__before_clear_bit() smp_mb__before_llsc() 43#define smp_mb__before_clear_bit() smp_mb__before_llsc()
45#define smp_mb__after_clear_bit() smp_llsc_mb() 44#define smp_mb__after_clear_bit() smp_llsc_mb()
46 45
46
47/*
48 * These are the "slower" versions of the functions and are in bitops.c.
49 * These functions call raw_local_irq_{save,restore}().
50 */
51void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
52void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
53void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
54int __mips_test_and_set_bit(unsigned long nr,
55 volatile unsigned long *addr);
56int __mips_test_and_set_bit_lock(unsigned long nr,
57 volatile unsigned long *addr);
58int __mips_test_and_clear_bit(unsigned long nr,
59 volatile unsigned long *addr);
60int __mips_test_and_change_bit(unsigned long nr,
61 volatile unsigned long *addr);
62
63
47/* 64/*
48 * set_bit - Atomically set a bit in memory 65 * set_bit - Atomically set a bit in memory
49 * @nr: the bit to set 66 * @nr: the bit to set
@@ -57,7 +74,7 @@
57static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 74static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
58{ 75{
59 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 76 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
60 unsigned short bit = nr & SZLONG_MASK; 77 int bit = nr & SZLONG_MASK;
61 unsigned long temp; 78 unsigned long temp;
62 79
63 if (kernel_uses_llsc && R10000_LLSC_WAR) { 80 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
92 : "=&r" (temp), "+m" (*m) 109 : "=&r" (temp), "+m" (*m)
93 : "ir" (1UL << bit)); 110 : "ir" (1UL << bit));
94 } while (unlikely(!temp)); 111 } while (unlikely(!temp));
95 } else { 112 } else
96 volatile unsigned long *a = addr; 113 __mips_set_bit(nr, addr);
97 unsigned long mask;
98 unsigned long flags;
99
100 a += nr >> SZLONG_LOG;
101 mask = 1UL << bit;
102 raw_local_irq_save(flags);
103 *a |= mask;
104 raw_local_irq_restore(flags);
105 }
106} 114}
107 115
108/* 116/*
@@ -118,7 +126,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
118static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 126static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
119{ 127{
120 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 128 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
121 unsigned short bit = nr & SZLONG_MASK; 129 int bit = nr & SZLONG_MASK;
122 unsigned long temp; 130 unsigned long temp;
123 131
124 if (kernel_uses_llsc && R10000_LLSC_WAR) { 132 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
153 : "=&r" (temp), "+m" (*m) 161 : "=&r" (temp), "+m" (*m)
154 : "ir" (~(1UL << bit))); 162 : "ir" (~(1UL << bit)));
155 } while (unlikely(!temp)); 163 } while (unlikely(!temp));
156 } else { 164 } else
157 volatile unsigned long *a = addr; 165 __mips_clear_bit(nr, addr);
158 unsigned long mask;
159 unsigned long flags;
160
161 a += nr >> SZLONG_LOG;
162 mask = 1UL << bit;
163 raw_local_irq_save(flags);
164 *a &= ~mask;
165 raw_local_irq_restore(flags);
166 }
167} 166}
168 167
169/* 168/*
@@ -191,7 +190,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
191 */ 190 */
192static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 191static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
193{ 192{
194 unsigned short bit = nr & SZLONG_MASK; 193 int bit = nr & SZLONG_MASK;
195 194
196 if (kernel_uses_llsc && R10000_LLSC_WAR) { 195 if (kernel_uses_llsc && R10000_LLSC_WAR) {
197 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 196 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
220 : "=&r" (temp), "+m" (*m) 219 : "=&r" (temp), "+m" (*m)
221 : "ir" (1UL << bit)); 220 : "ir" (1UL << bit));
222 } while (unlikely(!temp)); 221 } while (unlikely(!temp));
223 } else { 222 } else
224 volatile unsigned long *a = addr; 223 __mips_change_bit(nr, addr);
225 unsigned long mask;
226 unsigned long flags;
227
228 a += nr >> SZLONG_LOG;
229 mask = 1UL << bit;
230 raw_local_irq_save(flags);
231 *a ^= mask;
232 raw_local_irq_restore(flags);
233 }
234} 224}
235 225
236/* 226/*
@@ -244,7 +234,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
244static inline int test_and_set_bit(unsigned long nr, 234static inline int test_and_set_bit(unsigned long nr,
245 volatile unsigned long *addr) 235 volatile unsigned long *addr)
246{ 236{
247 unsigned short bit = nr & SZLONG_MASK; 237 int bit = nr & SZLONG_MASK;
248 unsigned long res; 238 unsigned long res;
249 239
250 smp_mb__before_llsc(); 240 smp_mb__before_llsc();
@@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr,
281 } while (unlikely(!res)); 271 } while (unlikely(!res));
282 272
283 res = temp & (1UL << bit); 273 res = temp & (1UL << bit);
284 } else { 274 } else
285 volatile unsigned long *a = addr; 275 res = __mips_test_and_set_bit(nr, addr);
286 unsigned long mask;
287 unsigned long flags;
288
289 a += nr >> SZLONG_LOG;
290 mask = 1UL << bit;
291 raw_local_irq_save(flags);
292 res = (mask & *a);
293 *a |= mask;
294 raw_local_irq_restore(flags);
295 }
296 276
297 smp_llsc_mb(); 277 smp_llsc_mb();
298 278
@@ -310,7 +290,7 @@ static inline int test_and_set_bit(unsigned long nr,
310static inline int test_and_set_bit_lock(unsigned long nr, 290static inline int test_and_set_bit_lock(unsigned long nr,
311 volatile unsigned long *addr) 291 volatile unsigned long *addr)
312{ 292{
313 unsigned short bit = nr & SZLONG_MASK; 293 int bit = nr & SZLONG_MASK;
314 unsigned long res; 294 unsigned long res;
315 295
316 if (kernel_uses_llsc && R10000_LLSC_WAR) { 296 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
345 } while (unlikely(!res)); 325 } while (unlikely(!res));
346 326
347 res = temp & (1UL << bit); 327 res = temp & (1UL << bit);
348 } else { 328 } else
349 volatile unsigned long *a = addr; 329 res = __mips_test_and_set_bit_lock(nr, addr);
350 unsigned long mask;
351 unsigned long flags;
352
353 a += nr >> SZLONG_LOG;
354 mask = 1UL << bit;
355 raw_local_irq_save(flags);
356 res = (mask & *a);
357 *a |= mask;
358 raw_local_irq_restore(flags);
359 }
360 330
361 smp_llsc_mb(); 331 smp_llsc_mb();
362 332
@@ -373,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
373static inline int test_and_clear_bit(unsigned long nr, 343static inline int test_and_clear_bit(unsigned long nr,
374 volatile unsigned long *addr) 344 volatile unsigned long *addr)
375{ 345{
376 unsigned short bit = nr & SZLONG_MASK; 346 int bit = nr & SZLONG_MASK;
377 unsigned long res; 347 unsigned long res;
378 348
379 smp_mb__before_llsc(); 349 smp_mb__before_llsc();
@@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr,
428 } while (unlikely(!res)); 398 } while (unlikely(!res));
429 399
430 res = temp & (1UL << bit); 400 res = temp & (1UL << bit);
431 } else { 401 } else
432 volatile unsigned long *a = addr; 402 res = __mips_test_and_clear_bit(nr, addr);
433 unsigned long mask;
434 unsigned long flags;
435
436 a += nr >> SZLONG_LOG;
437 mask = 1UL << bit;
438 raw_local_irq_save(flags);
439 res = (mask & *a);
440 *a &= ~mask;
441 raw_local_irq_restore(flags);
442 }
443 403
444 smp_llsc_mb(); 404 smp_llsc_mb();
445 405
@@ -457,7 +417,7 @@ static inline int test_and_clear_bit(unsigned long nr,
457static inline int test_and_change_bit(unsigned long nr, 417static inline int test_and_change_bit(unsigned long nr,
458 volatile unsigned long *addr) 418 volatile unsigned long *addr)
459{ 419{
460 unsigned short bit = nr & SZLONG_MASK; 420 int bit = nr & SZLONG_MASK;
461 unsigned long res; 421 unsigned long res;
462 422
463 smp_mb__before_llsc(); 423 smp_mb__before_llsc();
@@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr,
494 } while (unlikely(!res)); 454 } while (unlikely(!res));
495 455
496 res = temp & (1UL << bit); 456 res = temp & (1UL << bit);
497 } else { 457 } else
498 volatile unsigned long *a = addr; 458 res = __mips_test_and_change_bit(nr, addr);
499 unsigned long mask;
500 unsigned long flags;
501
502 a += nr >> SZLONG_LOG;
503 mask = 1UL << bit;
504 raw_local_irq_save(flags);
505 res = (mask & *a);
506 *a ^= mask;
507 raw_local_irq_restore(flags);
508 }
509 459
510 smp_llsc_mb(); 460 smp_llsc_mb();
511 461
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 58277e0e9cd4..3c5d1464b7bd 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -290,7 +290,7 @@ struct compat_shmid64_ds {
290 290
291static inline int is_compat_task(void) 291static inline int is_compat_task(void)
292{ 292{
293 return test_thread_flag(TIF_32BIT); 293 return test_thread_flag(TIF_32BIT_ADDR);
294} 294}
295 295
296#endif /* _ASM_COMPAT_H */ 296#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 29d9c23c20c7..ff2e0345e013 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,6 +15,7 @@
15#include <linux/compiler.h> 15#include <linux/compiler.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/irqflags.h>
18 19
19#include <asm/addrspace.h> 20#include <asm/addrspace.h>
20#include <asm/bug.h> 21#include <asm/bug.h>
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 309cbcd6909c..9f3384c789d7 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -16,83 +16,13 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18 18
19__asm__( 19#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
20 " .macro arch_local_irq_enable \n"
21 " .set push \n"
22 " .set reorder \n"
23 " .set noat \n"
24#ifdef CONFIG_MIPS_MT_SMTC
25 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
26 " ori $1, 0x400 \n"
27 " xori $1, 0x400 \n"
28 " mtc0 $1, $2, 1 \n"
29#elif defined(CONFIG_CPU_MIPSR2)
30 " ei \n"
31#else
32 " mfc0 $1,$12 \n"
33 " ori $1,0x1f \n"
34 " xori $1,0x1e \n"
35 " mtc0 $1,$12 \n"
36#endif
37 " irq_enable_hazard \n"
38 " .set pop \n"
39 " .endm");
40 20
41extern void smtc_ipi_replay(void);
42
43static inline void arch_local_irq_enable(void)
44{
45#ifdef CONFIG_MIPS_MT_SMTC
46 /*
47 * SMTC kernel needs to do a software replay of queued
48 * IPIs, at the cost of call overhead on each local_irq_enable()
49 */
50 smtc_ipi_replay();
51#endif
52 __asm__ __volatile__(
53 "arch_local_irq_enable"
54 : /* no outputs */
55 : /* no inputs */
56 : "memory");
57}
58
59
60/*
61 * For cli() we have to insert nops to make sure that the new value
62 * has actually arrived in the status register before the end of this
63 * macro.
64 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
65 * no nops at all.
66 */
67/*
68 * For TX49, operating only IE bit is not enough.
69 *
70 * If mfc0 $12 follows store and the mfc0 is last instruction of a
71 * page and fetching the next instruction causes TLB miss, the result
72 * of the mfc0 might wrongly contain EXL bit.
73 *
74 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
75 *
76 * Workaround: mask EXL bit of the result or place a nop before mfc0.
77 */
78__asm__( 21__asm__(
79 " .macro arch_local_irq_disable\n" 22 " .macro arch_local_irq_disable\n"
80 " .set push \n" 23 " .set push \n"
81 " .set noat \n" 24 " .set noat \n"
82#ifdef CONFIG_MIPS_MT_SMTC
83 " mfc0 $1, $2, 1 \n"
84 " ori $1, 0x400 \n"
85 " .set noreorder \n"
86 " mtc0 $1, $2, 1 \n"
87#elif defined(CONFIG_CPU_MIPSR2)
88 " di \n" 25 " di \n"
89#else
90 " mfc0 $1,$12 \n"
91 " ori $1,0x1f \n"
92 " xori $1,0x1f \n"
93 " .set noreorder \n"
94 " mtc0 $1,$12 \n"
95#endif
96 " irq_disable_hazard \n" 26 " irq_disable_hazard \n"
97 " .set pop \n" 27 " .set pop \n"
98 " .endm \n"); 28 " .endm \n");
@@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void)
106 : "memory"); 36 : "memory");
107} 37}
108 38
109__asm__(
110 " .macro arch_local_save_flags flags \n"
111 " .set push \n"
112 " .set reorder \n"
113#ifdef CONFIG_MIPS_MT_SMTC
114 " mfc0 \\flags, $2, 1 \n"
115#else
116 " mfc0 \\flags, $12 \n"
117#endif
118 " .set pop \n"
119 " .endm \n");
120
121static inline unsigned long arch_local_save_flags(void)
122{
123 unsigned long flags;
124 asm volatile("arch_local_save_flags %0" : "=r" (flags));
125 return flags;
126}
127 39
128__asm__( 40__asm__(
129 " .macro arch_local_irq_save result \n" 41 " .macro arch_local_irq_save result \n"
130 " .set push \n" 42 " .set push \n"
131 " .set reorder \n" 43 " .set reorder \n"
132 " .set noat \n" 44 " .set noat \n"
133#ifdef CONFIG_MIPS_MT_SMTC
134 " mfc0 \\result, $2, 1 \n"
135 " ori $1, \\result, 0x400 \n"
136 " .set noreorder \n"
137 " mtc0 $1, $2, 1 \n"
138 " andi \\result, \\result, 0x400 \n"
139#elif defined(CONFIG_CPU_MIPSR2)
140 " di \\result \n" 45 " di \\result \n"
141 " andi \\result, 1 \n" 46 " andi \\result, 1 \n"
142#else
143 " mfc0 \\result, $12 \n"
144 " ori $1, \\result, 0x1f \n"
145 " xori $1, 0x1f \n"
146 " .set noreorder \n"
147 " mtc0 $1, $12 \n"
148#endif
149 " irq_disable_hazard \n" 47 " irq_disable_hazard \n"
150 " .set pop \n" 48 " .set pop \n"
151 " .endm \n"); 49 " .endm \n");
@@ -160,61 +58,37 @@ static inline unsigned long arch_local_irq_save(void)
160 return flags; 58 return flags;
161} 59}
162 60
61
163__asm__( 62__asm__(
164 " .macro arch_local_irq_restore flags \n" 63 " .macro arch_local_irq_restore flags \n"
165 " .set push \n" 64 " .set push \n"
166 " .set noreorder \n" 65 " .set noreorder \n"
167 " .set noat \n" 66 " .set noat \n"
168#ifdef CONFIG_MIPS_MT_SMTC 67#if defined(CONFIG_IRQ_CPU)
169 "mfc0 $1, $2, 1 \n"
170 "andi \\flags, 0x400 \n"
171 "ori $1, 0x400 \n"
172 "xori $1, 0x400 \n"
173 "or \\flags, $1 \n"
174 "mtc0 \\flags, $2, 1 \n"
175#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
176 /* 68 /*
177 * Slow, but doesn't suffer from a relatively unlikely race 69 * Slow, but doesn't suffer from a relatively unlikely race
178 * condition we're having since days 1. 70 * condition we're having since days 1.
179 */ 71 */
180 " beqz \\flags, 1f \n" 72 " beqz \\flags, 1f \n"
181 " di \n" 73 " di \n"
182 " ei \n" 74 " ei \n"
183 "1: \n" 75 "1: \n"
184#elif defined(CONFIG_CPU_MIPSR2) 76#else
185 /* 77 /*
186 * Fast, dangerous. Life is fun, life is good. 78 * Fast, dangerous. Life is fun, life is good.
187 */ 79 */
188 " mfc0 $1, $12 \n" 80 " mfc0 $1, $12 \n"
189 " ins $1, \\flags, 0, 1 \n" 81 " ins $1, \\flags, 0, 1 \n"
190 " mtc0 $1, $12 \n" 82 " mtc0 $1, $12 \n"
191#else
192 " mfc0 $1, $12 \n"
193 " andi \\flags, 1 \n"
194 " ori $1, 0x1f \n"
195 " xori $1, 0x1f \n"
196 " or \\flags, $1 \n"
197 " mtc0 \\flags, $12 \n"
198#endif 83#endif
199 " irq_disable_hazard \n" 84 " irq_disable_hazard \n"
200 " .set pop \n" 85 " .set pop \n"
201 " .endm \n"); 86 " .endm \n");
202 87
203
204static inline void arch_local_irq_restore(unsigned long flags) 88static inline void arch_local_irq_restore(unsigned long flags)
205{ 89{
206 unsigned long __tmp1; 90 unsigned long __tmp1;
207 91
208#ifdef CONFIG_MIPS_MT_SMTC
209 /*
210 * SMTC kernel needs to do a software replay of queued
211 * IPIs, at the cost of branch and call overhead on each
212 * local_irq_restore()
213 */
214 if (unlikely(!(flags & 0x0400)))
215 smtc_ipi_replay();
216#endif
217
218 __asm__ __volatile__( 92 __asm__ __volatile__(
219 "arch_local_irq_restore\t%0" 93 "arch_local_irq_restore\t%0"
220 : "=r" (__tmp1) 94 : "=r" (__tmp1)
@@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags)
232 : "0" (flags) 106 : "0" (flags)
233 : "memory"); 107 : "memory");
234} 108}
109#else
110/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
111void arch_local_irq_disable(void);
112unsigned long arch_local_irq_save(void);
113void arch_local_irq_restore(unsigned long flags);
114void __arch_local_irq_restore(unsigned long flags);
115#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
116
117
118__asm__(
119 " .macro arch_local_irq_enable \n"
120 " .set push \n"
121 " .set reorder \n"
122 " .set noat \n"
123#ifdef CONFIG_MIPS_MT_SMTC
124 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
125 " ori $1, 0x400 \n"
126 " xori $1, 0x400 \n"
127 " mtc0 $1, $2, 1 \n"
128#elif defined(CONFIG_CPU_MIPSR2)
129 " ei \n"
130#else
131 " mfc0 $1,$12 \n"
132 " ori $1,0x1f \n"
133 " xori $1,0x1e \n"
134 " mtc0 $1,$12 \n"
135#endif
136 " irq_enable_hazard \n"
137 " .set pop \n"
138 " .endm");
139
140extern void smtc_ipi_replay(void);
141
142static inline void arch_local_irq_enable(void)
143{
144#ifdef CONFIG_MIPS_MT_SMTC
145 /*
146 * SMTC kernel needs to do a software replay of queued
147 * IPIs, at the cost of call overhead on each local_irq_enable()
148 */
149 smtc_ipi_replay();
150#endif
151 __asm__ __volatile__(
152 "arch_local_irq_enable"
153 : /* no outputs */
154 : /* no inputs */
155 : "memory");
156}
157
158
159__asm__(
160 " .macro arch_local_save_flags flags \n"
161 " .set push \n"
162 " .set reorder \n"
163#ifdef CONFIG_MIPS_MT_SMTC
164 " mfc0 \\flags, $2, 1 \n"
165#else
166 " mfc0 \\flags, $12 \n"
167#endif
168 " .set pop \n"
169 " .endm \n");
170
171static inline unsigned long arch_local_save_flags(void)
172{
173 unsigned long flags;
174 asm volatile("arch_local_save_flags %0" : "=r" (flags));
175 return flags;
176}
177
235 178
236static inline int arch_irqs_disabled_flags(unsigned long flags) 179static inline int arch_irqs_disabled_flags(unsigned long flags)
237{ 180{
@@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
245#endif 188#endif
246} 189}
247 190
248#endif 191#endif /* #ifndef __ASSEMBLY__ */
249 192
250/* 193/*
251 * Do the CPU's IRQ-state tracing from assembly code. 194 * Do the CPU's IRQ-state tracing from assembly code.
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 8debe9e91754..18806a52061c 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -112,12 +112,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
112#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 112#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
113#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 113#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
114 114
115#ifdef CONFIG_MIPS32_O32
116#define TIF_32BIT TIF_32BIT_REGS
117#elif defined(CONFIG_MIPS32_N32)
118#define TIF_32BIT _TIF_32BIT_ADDR
119#endif /* CONFIG_MIPS32_O32 */
120
121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 115#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
122#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 116#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
123#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 117#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index c4a82e841c73..eeddc58802e1 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,9 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o delay.o memcpy.o memset.o \ 5lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \
6 strlen_user.o strncpy_user.o strnlen_user.o uncached.o 6 mips-atomic.o strlen_user.o strncpy_user.o \
7 strnlen_user.o uncached.o
7 8
8obj-y += iomap.o 9obj-y += iomap.o
9obj-$(CONFIG_PCI) += iomap-pci.o 10obj-$(CONFIG_PCI) += iomap-pci.o
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
new file mode 100644
index 000000000000..239a9c957b02
--- /dev/null
+++ b/arch/mips/lib/bitops.c
@@ -0,0 +1,179 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
8 */
9#include <linux/bitops.h>
10#include <linux/irqflags.h>
11#include <linux/export.h>
12
13
14/**
15 * __mips_set_bit - Atomically set a bit in memory. This is called by
16 * set_bit() if it cannot find a faster solution.
17 * @nr: the bit to set
18 * @addr: the address to start counting from
19 */
20void __mips_set_bit(unsigned long nr, volatile unsigned long *addr)
21{
22 volatile unsigned long *a = addr;
23 unsigned bit = nr & SZLONG_MASK;
24 unsigned long mask;
25 unsigned long flags;
26
27 a += nr >> SZLONG_LOG;
28 mask = 1UL << bit;
29 raw_local_irq_save(flags);
30 *a |= mask;
31 raw_local_irq_restore(flags);
32}
33EXPORT_SYMBOL(__mips_set_bit);
34
35
36/**
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
38 * it cannot find a faster solution.
39 * @nr: Bit to clear
40 * @addr: Address to start counting from
41 */
42void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr)
43{
44 volatile unsigned long *a = addr;
45 unsigned bit = nr & SZLONG_MASK;
46 unsigned long mask;
47 unsigned long flags;
48
49 a += nr >> SZLONG_LOG;
50 mask = 1UL << bit;
51 raw_local_irq_save(flags);
52 *a &= ~mask;
53 raw_local_irq_restore(flags);
54}
55EXPORT_SYMBOL(__mips_clear_bit);
56
57
58/**
59 * __mips_change_bit - Toggle a bit in memory. This is called by change_bit()
60 * if it cannot find a faster solution.
61 * @nr: Bit to change
62 * @addr: Address to start counting from
63 */
64void __mips_change_bit(unsigned long nr, volatile unsigned long *addr)
65{
66 volatile unsigned long *a = addr;
67 unsigned bit = nr & SZLONG_MASK;
68 unsigned long mask;
69 unsigned long flags;
70
71 a += nr >> SZLONG_LOG;
72 mask = 1UL << bit;
73 raw_local_irq_save(flags);
74 *a ^= mask;
75 raw_local_irq_restore(flags);
76}
77EXPORT_SYMBOL(__mips_change_bit);
78
79
80/**
81 * __mips_test_and_set_bit - Set a bit and return its old value. This is
82 * called by test_and_set_bit() if it cannot find a faster solution.
83 * @nr: Bit to set
84 * @addr: Address to count from
85 */
86int __mips_test_and_set_bit(unsigned long nr,
87 volatile unsigned long *addr)
88{
89 volatile unsigned long *a = addr;
90 unsigned bit = nr & SZLONG_MASK;
91 unsigned long mask;
92 unsigned long flags;
93 unsigned long res;
94
95 a += nr >> SZLONG_LOG;
96 mask = 1UL << bit;
97 raw_local_irq_save(flags);
98 res = (mask & *a);
99 *a |= mask;
100 raw_local_irq_restore(flags);
101 return res;
102}
103EXPORT_SYMBOL(__mips_test_and_set_bit);
104
105
106/**
107 * __mips_test_and_set_bit_lock - Set a bit and return its old value. This is
108 * called by test_and_set_bit_lock() if it cannot find a faster solution.
109 * @nr: Bit to set
110 * @addr: Address to count from
111 */
112int __mips_test_and_set_bit_lock(unsigned long nr,
113 volatile unsigned long *addr)
114{
115 volatile unsigned long *a = addr;
116 unsigned bit = nr & SZLONG_MASK;
117 unsigned long mask;
118 unsigned long flags;
119 unsigned long res;
120
121 a += nr >> SZLONG_LOG;
122 mask = 1UL << bit;
123 raw_local_irq_save(flags);
124 res = (mask & *a);
125 *a |= mask;
126 raw_local_irq_restore(flags);
127 return res;
128}
129EXPORT_SYMBOL(__mips_test_and_set_bit_lock);
130
131
132/**
133 * __mips_test_and_clear_bit - Clear a bit and return its old value. This is
134 * called by test_and_clear_bit() if it cannot find a faster solution.
135 * @nr: Bit to clear
136 * @addr: Address to count from
137 */
138int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
139{
140 volatile unsigned long *a = addr;
141 unsigned bit = nr & SZLONG_MASK;
142 unsigned long mask;
143 unsigned long flags;
144 unsigned long res;
145
146 a += nr >> SZLONG_LOG;
147 mask = 1UL << bit;
148 raw_local_irq_save(flags);
149 res = (mask & *a);
150 *a &= ~mask;
151 raw_local_irq_restore(flags);
152 return res;
153}
154EXPORT_SYMBOL(__mips_test_and_clear_bit);
155
156
157/**
158 * __mips_test_and_change_bit - Change a bit and return its old value. This is
159 * called by test_and_change_bit() if it cannot find a faster solution.
160 * @nr: Bit to change
161 * @addr: Address to count from
162 */
163int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
164{
165 volatile unsigned long *a = addr;
166 unsigned bit = nr & SZLONG_MASK;
167 unsigned long mask;
168 unsigned long flags;
169 unsigned long res;
170
171 a += nr >> SZLONG_LOG;
172 mask = 1UL << bit;
173 raw_local_irq_save(flags);
174 res = (mask & *a);
175 *a ^= mask;
176 raw_local_irq_restore(flags);
177 return res;
178}
179EXPORT_SYMBOL(__mips_test_and_change_bit);
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
new file mode 100644
index 000000000000..e091430dbeb1
--- /dev/null
+++ b/arch/mips/lib/mips-atomic.c
@@ -0,0 +1,176 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */
11#include <asm/irqflags.h>
12#include <asm/hazards.h>
13#include <linux/compiler.h>
14#include <linux/preempt.h>
15#include <linux/export.h>
16
17#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC)
18
19/*
20 * For cli() we have to insert nops to make sure that the new value
21 * has actually arrived in the status register before the end of this
22 * macro.
23 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
24 * no nops at all.
25 */
26/*
27 * For TX49, operating only IE bit is not enough.
28 *
29 * If mfc0 $12 follows store and the mfc0 is last instruction of a
30 * page and fetching the next instruction causes TLB miss, the result
31 * of the mfc0 might wrongly contain EXL bit.
32 *
33 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
34 *
35 * Workaround: mask EXL bit of the result or place a nop before mfc0.
36 */
37__asm__(
38 " .macro arch_local_irq_disable\n"
39 " .set push \n"
40 " .set noat \n"
41#ifdef CONFIG_MIPS_MT_SMTC
42 " mfc0 $1, $2, 1 \n"
43 " ori $1, 0x400 \n"
44 " .set noreorder \n"
45 " mtc0 $1, $2, 1 \n"
46#elif defined(CONFIG_CPU_MIPSR2)
47 /* see irqflags.h for inline function */
48#else
49 " mfc0 $1,$12 \n"
50 " ori $1,0x1f \n"
51 " xori $1,0x1f \n"
52 " .set noreorder \n"
53 " mtc0 $1,$12 \n"
54#endif
55 " irq_disable_hazard \n"
56 " .set pop \n"
57 " .endm \n");
58
59void arch_local_irq_disable(void)
60{
61 preempt_disable();
62 __asm__ __volatile__(
63 "arch_local_irq_disable"
64 : /* no outputs */
65 : /* no inputs */
66 : "memory");
67 preempt_enable();
68}
69EXPORT_SYMBOL(arch_local_irq_disable);
70
71
72__asm__(
73 " .macro arch_local_irq_save result \n"
74 " .set push \n"
75 " .set reorder \n"
76 " .set noat \n"
77#ifdef CONFIG_MIPS_MT_SMTC
78 " mfc0 \\result, $2, 1 \n"
79 " ori $1, \\result, 0x400 \n"
80 " .set noreorder \n"
81 " mtc0 $1, $2, 1 \n"
82 " andi \\result, \\result, 0x400 \n"
83#elif defined(CONFIG_CPU_MIPSR2)
84 /* see irqflags.h for inline function */
85#else
86 " mfc0 \\result, $12 \n"
87 " ori $1, \\result, 0x1f \n"
88 " xori $1, 0x1f \n"
89 " .set noreorder \n"
90 " mtc0 $1, $12 \n"
91#endif
92 " irq_disable_hazard \n"
93 " .set pop \n"
94 " .endm \n");
95
96unsigned long arch_local_irq_save(void)
97{
98 unsigned long flags;
99 preempt_disable();
100 asm volatile("arch_local_irq_save\t%0"
101 : "=r" (flags)
102 : /* no inputs */
103 : "memory");
104 preempt_enable();
105 return flags;
106}
107EXPORT_SYMBOL(arch_local_irq_save);
108
109
110__asm__(
111 " .macro arch_local_irq_restore flags \n"
112 " .set push \n"
113 " .set noreorder \n"
114 " .set noat \n"
115#ifdef CONFIG_MIPS_MT_SMTC
116 "mfc0 $1, $2, 1 \n"
117 "andi \\flags, 0x400 \n"
118 "ori $1, 0x400 \n"
119 "xori $1, 0x400 \n"
120 "or \\flags, $1 \n"
121 "mtc0 \\flags, $2, 1 \n"
122#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
123 /* see irqflags.h for inline function */
124#elif defined(CONFIG_CPU_MIPSR2)
125 /* see irqflags.h for inline function */
126#else
127 " mfc0 $1, $12 \n"
128 " andi \\flags, 1 \n"
129 " ori $1, 0x1f \n"
130 " xori $1, 0x1f \n"
131 " or \\flags, $1 \n"
132 " mtc0 \\flags, $12 \n"
133#endif
134 " irq_disable_hazard \n"
135 " .set pop \n"
136 " .endm \n");
137
138void arch_local_irq_restore(unsigned long flags)
139{
140 unsigned long __tmp1;
141
142#ifdef CONFIG_MIPS_MT_SMTC
143 /*
144 * SMTC kernel needs to do a software replay of queued
145 * IPIs, at the cost of branch and call overhead on each
146 * local_irq_restore()
147 */
148 if (unlikely(!(flags & 0x0400)))
149 smtc_ipi_replay();
150#endif
151 preempt_disable();
152 __asm__ __volatile__(
153 "arch_local_irq_restore\t%0"
154 : "=r" (__tmp1)
155 : "0" (flags)
156 : "memory");
157 preempt_enable();
158}
159EXPORT_SYMBOL(arch_local_irq_restore);
160
161
162void __arch_local_irq_restore(unsigned long flags)
163{
164 unsigned long __tmp1;
165
166 preempt_disable();
167 __asm__ __volatile__(
168 "arch_local_irq_restore\t%0"
169 : "=r" (__tmp1)
170 : "0" (flags)
171 : "memory");
172 preempt_enable();
173}
174EXPORT_SYMBOL(__arch_local_irq_restore);
175
176#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 80562b81f0f2..74732177851c 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -29,6 +29,7 @@
29#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
30#include <linux/mtd/physmap.h> 30#include <linux/mtd/physmap.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <asm/mips-boards/maltaint.h>
32#include <mtd/mtd-abi.h> 33#include <mtd/mtd-abi.h>
33 34
34#define SMC_PORT(base, int) \ 35#define SMC_PORT(base, int) \
@@ -48,7 +49,7 @@ static struct plat_serial8250_port uart8250_data[] = {
48 SMC_PORT(0x2F8, 3), 49 SMC_PORT(0x2F8, 3),
49 { 50 {
50 .mapbase = 0x1f000900, /* The CBUS UART */ 51 .mapbase = 0x1f000900, /* The CBUS UART */
51 .irq = MIPS_CPU_IRQ_BASE + 2, 52 .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
52 .uartclk = 3686400, /* Twice the usual clk! */ 53 .uartclk = 3686400, /* Twice the usual clk! */
53 .iotype = UPIO_MEM32, 54 .iotype = UPIO_MEM32,
54 .flags = CBUS_UART_FLAGS, 55 .flags = CBUS_UART_FLAGS,
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 5dba755a43e6..d385f396dfee 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -96,6 +96,7 @@ config S390
96 select HAVE_MEMBLOCK_NODE_MAP 96 select HAVE_MEMBLOCK_NODE_MAP
97 select HAVE_CMPXCHG_LOCAL 97 select HAVE_CMPXCHG_LOCAL
98 select HAVE_CMPXCHG_DOUBLE 98 select HAVE_CMPXCHG_DOUBLE
99 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
99 select HAVE_VIRT_CPU_ACCOUNTING 100 select HAVE_VIRT_CPU_ACCOUNTING
100 select VIRT_CPU_ACCOUNTING 101 select VIRT_CPU_ACCOUNTING
101 select ARCH_DISCARD_MEMBLOCK 102 select ARCH_DISCARD_MEMBLOCK
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index 55bde6035216..ad2b924167d7 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -9,6 +9,8 @@
9 9
10#define LPM_ANYPATH 0xff 10#define LPM_ANYPATH 0xff
11#define __MAX_CSSID 0 11#define __MAX_CSSID 0
12#define __MAX_SUBCHANNEL 65535
13#define __MAX_SSID 3
12 14
13#include <asm/scsw.h> 15#include <asm/scsw.h>
14 16
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index a34a9d612fc0..18cd6b592650 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -20,7 +20,7 @@
20#define PSW32_MASK_CC 0x00003000UL 20#define PSW32_MASK_CC 0x00003000UL
21#define PSW32_MASK_PM 0x00000f00UL 21#define PSW32_MASK_PM 0x00000f00UL
22 22
23#define PSW32_MASK_USER 0x00003F00UL 23#define PSW32_MASK_USER 0x0000FF00UL
24 24
25#define PSW32_ADDR_AMODE 0x80000000UL 25#define PSW32_ADDR_AMODE 0x80000000UL
26#define PSW32_ADDR_INSN 0x7FFFFFFFUL 26#define PSW32_ADDR_INSN 0x7FFFFFFFUL
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index dd647c919a66..2d3b7cb26005 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -506,12 +506,15 @@ static inline int pud_bad(pud_t pud)
506 506
507static inline int pmd_present(pmd_t pmd) 507static inline int pmd_present(pmd_t pmd)
508{ 508{
509 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; 509 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO;
510 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE ||
511 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV);
510} 512}
511 513
512static inline int pmd_none(pmd_t pmd) 514static inline int pmd_none(pmd_t pmd)
513{ 515{
514 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; 516 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) &&
517 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO);
515} 518}
516 519
517static inline int pmd_large(pmd_t pmd) 520static inline int pmd_large(pmd_t pmd)
@@ -1223,6 +1226,11 @@ static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1223} 1226}
1224 1227
1225#ifdef CONFIG_TRANSPARENT_HUGEPAGE 1228#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1229
1230#define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE)
1231#define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO)
1232#define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW)
1233
1226#define __HAVE_ARCH_PGTABLE_DEPOSIT 1234#define __HAVE_ARCH_PGTABLE_DEPOSIT
1227extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable); 1235extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
1228 1236
@@ -1242,16 +1250,15 @@ static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1242 1250
1243static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1251static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1244{ 1252{
1245 unsigned long pgprot_pmd = 0; 1253 /*
1246 1254 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
1247 if (pgprot_val(pgprot) & _PAGE_INVALID) { 1255 * Convert to segment table entry format.
1248 if (pgprot_val(pgprot) & _PAGE_SWT) 1256 */
1249 pgprot_pmd |= _HPAGE_TYPE_NONE; 1257 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1250 pgprot_pmd |= _SEGMENT_ENTRY_INV; 1258 return pgprot_val(SEGMENT_NONE);
1251 } 1259 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1252 if (pgprot_val(pgprot) & _PAGE_RO) 1260 return pgprot_val(SEGMENT_RO);
1253 pgprot_pmd |= _SEGMENT_ENTRY_RO; 1261 return pgprot_val(SEGMENT_RW);
1254 return pgprot_pmd;
1255} 1262}
1256 1263
1257static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1264static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
@@ -1269,7 +1276,9 @@ static inline pmd_t pmd_mkhuge(pmd_t pmd)
1269 1276
1270static inline pmd_t pmd_mkwrite(pmd_t pmd) 1277static inline pmd_t pmd_mkwrite(pmd_t pmd)
1271{ 1278{
1272 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; 1279 /* Do not clobber _HPAGE_TYPE_NONE pages! */
1280 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV))
1281 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
1273 return pmd; 1282 return pmd;
1274} 1283}
1275 1284
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h
index 9ca305383760..9935cbd6a46f 100644
--- a/arch/s390/include/asm/topology.h
+++ b/arch/s390/include/asm/topology.h
@@ -8,6 +8,9 @@ struct cpu;
8 8
9#ifdef CONFIG_SCHED_BOOK 9#ifdef CONFIG_SCHED_BOOK
10 10
11extern unsigned char cpu_socket_id[NR_CPUS];
12#define topology_physical_package_id(cpu) (cpu_socket_id[cpu])
13
11extern unsigned char cpu_core_id[NR_CPUS]; 14extern unsigned char cpu_core_id[NR_CPUS];
12extern cpumask_t cpu_core_map[NR_CPUS]; 15extern cpumask_t cpu_core_map[NR_CPUS];
13 16
diff --git a/arch/s390/include/uapi/asm/ptrace.h b/arch/s390/include/uapi/asm/ptrace.h
index 705588a16d70..a5ca214b34fd 100644
--- a/arch/s390/include/uapi/asm/ptrace.h
+++ b/arch/s390/include/uapi/asm/ptrace.h
@@ -239,7 +239,7 @@ typedef struct
239#define PSW_MASK_EA 0x00000000UL 239#define PSW_MASK_EA 0x00000000UL
240#define PSW_MASK_BA 0x00000000UL 240#define PSW_MASK_BA 0x00000000UL
241 241
242#define PSW_MASK_USER 0x00003F00UL 242#define PSW_MASK_USER 0x0000FF00UL
243 243
244#define PSW_ADDR_AMODE 0x80000000UL 244#define PSW_ADDR_AMODE 0x80000000UL
245#define PSW_ADDR_INSN 0x7FFFFFFFUL 245#define PSW_ADDR_INSN 0x7FFFFFFFUL
@@ -269,7 +269,7 @@ typedef struct
269#define PSW_MASK_EA 0x0000000100000000UL 269#define PSW_MASK_EA 0x0000000100000000UL
270#define PSW_MASK_BA 0x0000000080000000UL 270#define PSW_MASK_BA 0x0000000080000000UL
271 271
272#define PSW_MASK_USER 0x00003F8180000000UL 272#define PSW_MASK_USER 0x0000FF8180000000UL
273 273
274#define PSW_ADDR_AMODE 0x0000000000000000UL 274#define PSW_ADDR_AMODE 0x0000000000000000UL
275#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL 275#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index a1e8a8694bb7..593fcc9253fc 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -309,6 +309,10 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs)
309 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | 309 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) |
310 (__u64)(regs32.psw.mask & PSW32_MASK_USER) << 32 | 310 (__u64)(regs32.psw.mask & PSW32_MASK_USER) << 32 |
311 (__u64)(regs32.psw.addr & PSW32_ADDR_AMODE); 311 (__u64)(regs32.psw.addr & PSW32_ADDR_AMODE);
312 /* Check for invalid user address space control. */
313 if ((regs->psw.mask & PSW_MASK_ASC) >= (psw_kernel_bits & PSW_MASK_ASC))
314 regs->psw.mask = (psw_user_bits & PSW_MASK_ASC) |
315 (regs->psw.mask & ~PSW_MASK_ASC);
312 regs->psw.addr = (__u64)(regs32.psw.addr & PSW32_ADDR_INSN); 316 regs->psw.addr = (__u64)(regs32.psw.addr & PSW32_ADDR_INSN);
313 for (i = 0; i < NUM_GPRS; i++) 317 for (i = 0; i < NUM_GPRS; i++)
314 regs->gprs[i] = (__u64) regs32.gprs[i]; 318 regs->gprs[i] = (__u64) regs32.gprs[i];
@@ -481,7 +485,10 @@ static int setup_frame32(int sig, struct k_sigaction *ka,
481 485
482 /* Set up registers for signal handler */ 486 /* Set up registers for signal handler */
483 regs->gprs[15] = (__force __u64) frame; 487 regs->gprs[15] = (__force __u64) frame;
484 regs->psw.mask |= PSW_MASK_BA; /* force amode 31 */ 488 /* Force 31 bit amode and default user address space control. */
489 regs->psw.mask = PSW_MASK_BA |
490 (psw_user_bits & PSW_MASK_ASC) |
491 (regs->psw.mask & ~PSW_MASK_ASC);
485 regs->psw.addr = (__force __u64) ka->sa.sa_handler; 492 regs->psw.addr = (__force __u64) ka->sa.sa_handler;
486 493
487 regs->gprs[2] = map_signal(sig); 494 regs->gprs[2] = map_signal(sig);
@@ -549,7 +556,10 @@ static int setup_rt_frame32(int sig, struct k_sigaction *ka, siginfo_t *info,
549 556
550 /* Set up registers for signal handler */ 557 /* Set up registers for signal handler */
551 regs->gprs[15] = (__force __u64) frame; 558 regs->gprs[15] = (__force __u64) frame;
552 regs->psw.mask |= PSW_MASK_BA; /* force amode 31 */ 559 /* Force 31 bit amode and default user address space control. */
560 regs->psw.mask = PSW_MASK_BA |
561 (psw_user_bits & PSW_MASK_ASC) |
562 (regs->psw.mask & ~PSW_MASK_ASC);
553 regs->psw.addr = (__u64) ka->sa.sa_handler; 563 regs->psw.addr = (__u64) ka->sa.sa_handler;
554 564
555 regs->gprs[2] = map_signal(sig); 565 regs->gprs[2] = map_signal(sig);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index bf053898630d..b6506ee32a36 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -44,6 +44,12 @@ _sclp_wait_int:
44#endif 44#endif
45 mvc .LoldpswS1-.LbaseS1(16,%r13),0(%r8) 45 mvc .LoldpswS1-.LbaseS1(16,%r13),0(%r8)
46 mvc 0(16,%r8),0(%r9) 46 mvc 0(16,%r8),0(%r9)
47#ifdef CONFIG_64BIT
48 epsw %r6,%r7 # set current addressing mode
49 nill %r6,0x1 # in new psw (31 or 64 bit mode)
50 nilh %r7,0x8000
51 stm %r6,%r7,0(%r8)
52#endif
47 lhi %r6,0x0200 # cr mask for ext int (cr0.54) 53 lhi %r6,0x0200 # cr mask for ext int (cr0.54)
48 ltr %r2,%r2 54 ltr %r2,%r2
49 jz .LsetctS1 55 jz .LsetctS1
@@ -87,7 +93,7 @@ _sclp_wait_int:
87 .long 0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int 93 .long 0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int
88#ifdef CONFIG_64BIT 94#ifdef CONFIG_64BIT
89.LextpswS1_64: 95.LextpswS1_64:
90 .quad 0x0000000180000000, .LwaitS1 # PSW to handle ext int, 64 bit 96 .quad 0, .LwaitS1 # PSW to handle ext int, 64 bit
91#endif 97#endif
92.LwaitpswS1: 98.LwaitpswS1:
93 .long 0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int 99 .long 0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index c13a2a37ef00..d1259d875074 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -136,6 +136,10 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs)
136 /* Use regs->psw.mask instead of psw_user_bits to preserve PER bit. */ 136 /* Use regs->psw.mask instead of psw_user_bits to preserve PER bit. */
137 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | 137 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) |
138 (user_sregs.regs.psw.mask & PSW_MASK_USER); 138 (user_sregs.regs.psw.mask & PSW_MASK_USER);
139 /* Check for invalid user address space control. */
140 if ((regs->psw.mask & PSW_MASK_ASC) >= (psw_kernel_bits & PSW_MASK_ASC))
141 regs->psw.mask = (psw_user_bits & PSW_MASK_ASC) |
142 (regs->psw.mask & ~PSW_MASK_ASC);
139 /* Check for invalid amode */ 143 /* Check for invalid amode */
140 if (regs->psw.mask & PSW_MASK_EA) 144 if (regs->psw.mask & PSW_MASK_EA)
141 regs->psw.mask |= PSW_MASK_BA; 145 regs->psw.mask |= PSW_MASK_BA;
@@ -273,7 +277,10 @@ static int setup_frame(int sig, struct k_sigaction *ka,
273 277
274 /* Set up registers for signal handler */ 278 /* Set up registers for signal handler */
275 regs->gprs[15] = (unsigned long) frame; 279 regs->gprs[15] = (unsigned long) frame;
276 regs->psw.mask |= PSW_MASK_EA | PSW_MASK_BA; /* 64 bit amode */ 280 /* Force default amode and default user address space control. */
281 regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA |
282 (psw_user_bits & PSW_MASK_ASC) |
283 (regs->psw.mask & ~PSW_MASK_ASC);
277 regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE; 284 regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE;
278 285
279 regs->gprs[2] = map_signal(sig); 286 regs->gprs[2] = map_signal(sig);
@@ -346,7 +353,10 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
346 353
347 /* Set up registers for signal handler */ 354 /* Set up registers for signal handler */
348 regs->gprs[15] = (unsigned long) frame; 355 regs->gprs[15] = (unsigned long) frame;
349 regs->psw.mask |= PSW_MASK_EA | PSW_MASK_BA; /* 64 bit amode */ 356 /* Force default amode and default user address space control. */
357 regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA |
358 (psw_user_bits & PSW_MASK_ASC) |
359 (regs->psw.mask & ~PSW_MASK_ASC);
350 regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE; 360 regs->psw.addr = (unsigned long) ka->sa.sa_handler | PSW_ADDR_AMODE;
351 361
352 regs->gprs[2] = map_signal(sig); 362 regs->gprs[2] = map_signal(sig);
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 54d93f4b6818..dd55f7c20104 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -40,6 +40,7 @@ static DEFINE_SPINLOCK(topology_lock);
40static struct mask_info core_info; 40static struct mask_info core_info;
41cpumask_t cpu_core_map[NR_CPUS]; 41cpumask_t cpu_core_map[NR_CPUS];
42unsigned char cpu_core_id[NR_CPUS]; 42unsigned char cpu_core_id[NR_CPUS];
43unsigned char cpu_socket_id[NR_CPUS];
43 44
44static struct mask_info book_info; 45static struct mask_info book_info;
45cpumask_t cpu_book_map[NR_CPUS]; 46cpumask_t cpu_book_map[NR_CPUS];
@@ -83,11 +84,12 @@ static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu,
83 cpumask_set_cpu(lcpu, &book->mask); 84 cpumask_set_cpu(lcpu, &book->mask);
84 cpu_book_id[lcpu] = book->id; 85 cpu_book_id[lcpu] = book->id;
85 cpumask_set_cpu(lcpu, &core->mask); 86 cpumask_set_cpu(lcpu, &core->mask);
87 cpu_core_id[lcpu] = rcpu;
86 if (one_core_per_cpu) { 88 if (one_core_per_cpu) {
87 cpu_core_id[lcpu] = rcpu; 89 cpu_socket_id[lcpu] = rcpu;
88 core = core->next; 90 core = core->next;
89 } else { 91 } else {
90 cpu_core_id[lcpu] = core->id; 92 cpu_socket_id[lcpu] = core->id;
91 } 93 }
92 smp_cpu_set_polarization(lcpu, tl_cpu->pp); 94 smp_cpu_set_polarization(lcpu, tl_cpu->pp);
93 } 95 }
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 2d37bb861faf..9017a63dda3d 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -39,7 +39,7 @@ static __always_inline unsigned long follow_table(struct mm_struct *mm,
39 pmd = pmd_offset(pud, addr); 39 pmd = pmd_offset(pud, addr);
40 if (pmd_none(*pmd)) 40 if (pmd_none(*pmd))
41 return -0x10UL; 41 return -0x10UL;
42 if (pmd_huge(*pmd)) { 42 if (pmd_large(*pmd)) {
43 if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO)) 43 if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO))
44 return -0x04UL; 44 return -0x04UL;
45 return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK); 45 return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
diff --git a/arch/s390/mm/gup.c b/arch/s390/mm/gup.c
index 60acb93a4680..1f5315d1215c 100644
--- a/arch/s390/mm/gup.c
+++ b/arch/s390/mm/gup.c
@@ -126,7 +126,7 @@ static inline int gup_pmd_range(pud_t *pudp, pud_t pud, unsigned long addr,
126 */ 126 */
127 if (pmd_none(pmd) || pmd_trans_splitting(pmd)) 127 if (pmd_none(pmd) || pmd_trans_splitting(pmd))
128 return 0; 128 return 0;
129 if (unlikely(pmd_huge(pmd))) { 129 if (unlikely(pmd_large(pmd))) {
130 if (!gup_huge_pmd(pmdp, pmd, addr, next, 130 if (!gup_huge_pmd(pmdp, pmd, addr, next,
131 write, pages, nr)) 131 write, pages, nr))
132 return 0; 132 return 0;
@@ -180,8 +180,7 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
180 addr = start; 180 addr = start;
181 len = (unsigned long) nr_pages << PAGE_SHIFT; 181 len = (unsigned long) nr_pages << PAGE_SHIFT;
182 end = start + len; 182 end = start + len;
183 if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, 183 if ((end < start) || (end > TASK_SIZE))
184 (void __user *)start, len)))
185 return 0; 184 return 0;
186 185
187 local_irq_save(flags); 186 local_irq_save(flags);
@@ -229,7 +228,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
229 addr = start; 228 addr = start;
230 len = (unsigned long) nr_pages << PAGE_SHIFT; 229 len = (unsigned long) nr_pages << PAGE_SHIFT;
231 end = start + len; 230 end = start + len;
232 if (end < start) 231 if ((end < start) || (end > TASK_SIZE))
233 goto slow_irqon; 232 goto slow_irqon;
234 233
235 /* 234 /*
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index b6b442b0d793..9f2edb5c5551 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -20,6 +20,7 @@ config SPARC
20 select HAVE_ARCH_TRACEHOOK 20 select HAVE_ARCH_TRACEHOOK
21 select SYSCTL_EXCEPTION_TRACE 21 select SYSCTL_EXCEPTION_TRACE
22 select ARCH_WANT_OPTIONAL_GPIOLIB 22 select ARCH_WANT_OPTIONAL_GPIOLIB
23 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
23 select RTC_CLASS 24 select RTC_CLASS
24 select RTC_DRV_M48T59 25 select RTC_DRV_M48T59
25 select HAVE_IRQ_WORK 26 select HAVE_IRQ_WORK
diff --git a/arch/sparc/crypto/Makefile b/arch/sparc/crypto/Makefile
index 6ae1ad5e502b..5d469d81761f 100644
--- a/arch/sparc/crypto/Makefile
+++ b/arch/sparc/crypto/Makefile
@@ -13,13 +13,13 @@ obj-$(CONFIG_CRYPTO_DES_SPARC64) += camellia-sparc64.o
13 13
14obj-$(CONFIG_CRYPTO_CRC32C_SPARC64) += crc32c-sparc64.o 14obj-$(CONFIG_CRYPTO_CRC32C_SPARC64) += crc32c-sparc64.o
15 15
16sha1-sparc64-y := sha1_asm.o sha1_glue.o crop_devid.o 16sha1-sparc64-y := sha1_asm.o sha1_glue.o
17sha256-sparc64-y := sha256_asm.o sha256_glue.o crop_devid.o 17sha256-sparc64-y := sha256_asm.o sha256_glue.o
18sha512-sparc64-y := sha512_asm.o sha512_glue.o crop_devid.o 18sha512-sparc64-y := sha512_asm.o sha512_glue.o
19md5-sparc64-y := md5_asm.o md5_glue.o crop_devid.o 19md5-sparc64-y := md5_asm.o md5_glue.o
20 20
21aes-sparc64-y := aes_asm.o aes_glue.o crop_devid.o 21aes-sparc64-y := aes_asm.o aes_glue.o
22des-sparc64-y := des_asm.o des_glue.o crop_devid.o 22des-sparc64-y := des_asm.o des_glue.o
23camellia-sparc64-y := camellia_asm.o camellia_glue.o crop_devid.o 23camellia-sparc64-y := camellia_asm.o camellia_glue.o
24 24
25crc32c-sparc64-y := crc32c_asm.o crc32c_glue.o crop_devid.o 25crc32c-sparc64-y := crc32c_asm.o crc32c_glue.o
diff --git a/arch/sparc/crypto/aes_glue.c b/arch/sparc/crypto/aes_glue.c
index 8f1c9980f637..3965d1d36dfa 100644
--- a/arch/sparc/crypto/aes_glue.c
+++ b/arch/sparc/crypto/aes_glue.c
@@ -475,3 +475,5 @@ MODULE_LICENSE("GPL");
475MODULE_DESCRIPTION("AES Secure Hash Algorithm, sparc64 aes opcode accelerated"); 475MODULE_DESCRIPTION("AES Secure Hash Algorithm, sparc64 aes opcode accelerated");
476 476
477MODULE_ALIAS("aes"); 477MODULE_ALIAS("aes");
478
479#include "crop_devid.c"
diff --git a/arch/sparc/crypto/camellia_glue.c b/arch/sparc/crypto/camellia_glue.c
index 42905c084299..62c89af3fd3f 100644
--- a/arch/sparc/crypto/camellia_glue.c
+++ b/arch/sparc/crypto/camellia_glue.c
@@ -320,3 +320,5 @@ MODULE_LICENSE("GPL");
320MODULE_DESCRIPTION("Camellia Cipher Algorithm, sparc64 camellia opcode accelerated"); 320MODULE_DESCRIPTION("Camellia Cipher Algorithm, sparc64 camellia opcode accelerated");
321 321
322MODULE_ALIAS("aes"); 322MODULE_ALIAS("aes");
323
324#include "crop_devid.c"
diff --git a/arch/sparc/crypto/crc32c_glue.c b/arch/sparc/crypto/crc32c_glue.c
index 0bd89cea8d8e..5162fad912ce 100644
--- a/arch/sparc/crypto/crc32c_glue.c
+++ b/arch/sparc/crypto/crc32c_glue.c
@@ -177,3 +177,5 @@ MODULE_LICENSE("GPL");
177MODULE_DESCRIPTION("CRC32c (Castagnoli), sparc64 crc32c opcode accelerated"); 177MODULE_DESCRIPTION("CRC32c (Castagnoli), sparc64 crc32c opcode accelerated");
178 178
179MODULE_ALIAS("crc32c"); 179MODULE_ALIAS("crc32c");
180
181#include "crop_devid.c"
diff --git a/arch/sparc/crypto/des_glue.c b/arch/sparc/crypto/des_glue.c
index c4940c2d3073..41524cebcc49 100644
--- a/arch/sparc/crypto/des_glue.c
+++ b/arch/sparc/crypto/des_glue.c
@@ -527,3 +527,5 @@ MODULE_LICENSE("GPL");
527MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms, sparc64 des opcode accelerated"); 527MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms, sparc64 des opcode accelerated");
528 528
529MODULE_ALIAS("des"); 529MODULE_ALIAS("des");
530
531#include "crop_devid.c"
diff --git a/arch/sparc/crypto/md5_glue.c b/arch/sparc/crypto/md5_glue.c
index 603d723038ce..09a9ea1dfb69 100644
--- a/arch/sparc/crypto/md5_glue.c
+++ b/arch/sparc/crypto/md5_glue.c
@@ -186,3 +186,5 @@ MODULE_LICENSE("GPL");
186MODULE_DESCRIPTION("MD5 Secure Hash Algorithm, sparc64 md5 opcode accelerated"); 186MODULE_DESCRIPTION("MD5 Secure Hash Algorithm, sparc64 md5 opcode accelerated");
187 187
188MODULE_ALIAS("md5"); 188MODULE_ALIAS("md5");
189
190#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha1_glue.c b/arch/sparc/crypto/sha1_glue.c
index 2bbb20bee9f1..6cd5f29e1e0d 100644
--- a/arch/sparc/crypto/sha1_glue.c
+++ b/arch/sparc/crypto/sha1_glue.c
@@ -181,3 +181,5 @@ MODULE_LICENSE("GPL");
181MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, sparc64 sha1 opcode accelerated"); 181MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, sparc64 sha1 opcode accelerated");
182 182
183MODULE_ALIAS("sha1"); 183MODULE_ALIAS("sha1");
184
185#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha256_glue.c b/arch/sparc/crypto/sha256_glue.c
index 591e656bd891..04f555ab2680 100644
--- a/arch/sparc/crypto/sha256_glue.c
+++ b/arch/sparc/crypto/sha256_glue.c
@@ -239,3 +239,5 @@ MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm, sparc64 sha256 op
239 239
240MODULE_ALIAS("sha224"); 240MODULE_ALIAS("sha224");
241MODULE_ALIAS("sha256"); 241MODULE_ALIAS("sha256");
242
243#include "crop_devid.c"
diff --git a/arch/sparc/crypto/sha512_glue.c b/arch/sparc/crypto/sha512_glue.c
index 486f0a2b7001..f04d1994d19a 100644
--- a/arch/sparc/crypto/sha512_glue.c
+++ b/arch/sparc/crypto/sha512_glue.c
@@ -224,3 +224,5 @@ MODULE_DESCRIPTION("SHA-384 and SHA-512 Secure Hash Algorithm, sparc64 sha512 op
224 224
225MODULE_ALIAS("sha384"); 225MODULE_ALIAS("sha384");
226MODULE_ALIAS("sha512"); 226MODULE_ALIAS("sha512");
227
228#include "crop_devid.c"
diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
index ce35a1cf1a20..be56a244c9cf 100644
--- a/arch/sparc/include/asm/atomic_64.h
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -1,7 +1,7 @@
1/* atomic.h: Thankfully the V9 is at least reasonable for this 1/* atomic.h: Thankfully the V9 is at least reasonable for this
2 * stuff. 2 * stuff.
3 * 3 *
4 * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1996, 1997, 2000, 2012 David S. Miller (davem@redhat.com)
5 */ 5 */
6 6
7#ifndef __ARCH_SPARC64_ATOMIC__ 7#ifndef __ARCH_SPARC64_ATOMIC__
@@ -106,6 +106,8 @@ static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
106 106
107#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) 107#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
108 108
109extern long atomic64_dec_if_positive(atomic64_t *v);
110
109/* Atomic operations are already serializing */ 111/* Atomic operations are already serializing */
110#define smp_mb__before_atomic_dec() barrier() 112#define smp_mb__before_atomic_dec() barrier()
111#define smp_mb__after_atomic_dec() barrier() 113#define smp_mb__after_atomic_dec() barrier()
diff --git a/arch/sparc/include/asm/backoff.h b/arch/sparc/include/asm/backoff.h
index db3af0d30fb1..4e02086b839c 100644
--- a/arch/sparc/include/asm/backoff.h
+++ b/arch/sparc/include/asm/backoff.h
@@ -1,6 +1,46 @@
1#ifndef _SPARC64_BACKOFF_H 1#ifndef _SPARC64_BACKOFF_H
2#define _SPARC64_BACKOFF_H 2#define _SPARC64_BACKOFF_H
3 3
4/* The macros in this file implement an exponential backoff facility
5 * for atomic operations.
6 *
7 * When multiple threads compete on an atomic operation, it is
8 * possible for one thread to be continually denied a successful
9 * completion of the compare-and-swap instruction. Heavily
10 * threaded cpu implementations like Niagara can compound this
11 * problem even further.
12 *
13 * When an atomic operation fails and needs to be retried, we spin a
14 * certain number of times. At each subsequent failure of the same
15 * operation we double the spin count, realizing an exponential
16 * backoff.
17 *
18 * When we spin, we try to use an operation that will cause the
19 * current cpu strand to block, and therefore make the core fully
20 * available to any other other runnable strands. There are two
21 * options, based upon cpu capabilities.
22 *
23 * On all cpus prior to SPARC-T4 we do three dummy reads of the
24 * condition code register. Each read blocks the strand for something
25 * between 40 and 50 cpu cycles.
26 *
27 * For SPARC-T4 and later we have a special "pause" instruction
28 * available. This is implemented using writes to register %asr27.
29 * The cpu will block the number of cycles written into the register,
30 * unless a disrupting trap happens first. SPARC-T4 specifically
31 * implements pause with a granularity of 8 cycles. Each strand has
32 * an internal pause counter which decrements every 8 cycles. So the
33 * chip shifts the %asr27 value down by 3 bits, and writes the result
34 * into the pause counter. If a value smaller than 8 is written, the
35 * chip blocks for 1 cycle.
36 *
37 * To achieve the same amount of backoff as the three %ccr reads give
38 * on earlier chips, we shift the backoff value up by 7 bits. (Three
39 * %ccr reads block for about 128 cycles, 1 << 7 == 128) We write the
40 * whole amount we want to block into the pause register, rather than
41 * loop writing 128 each time.
42 */
43
4#define BACKOFF_LIMIT (4 * 1024) 44#define BACKOFF_LIMIT (4 * 1024)
5 45
6#ifdef CONFIG_SMP 46#ifdef CONFIG_SMP
@@ -11,16 +51,25 @@
11#define BACKOFF_LABEL(spin_label, continue_label) \ 51#define BACKOFF_LABEL(spin_label, continue_label) \
12 spin_label 52 spin_label
13 53
14#define BACKOFF_SPIN(reg, tmp, label) \ 54#define BACKOFF_SPIN(reg, tmp, label) \
15 mov reg, tmp; \ 55 mov reg, tmp; \
1688: brnz,pt tmp, 88b; \ 5688: rd %ccr, %g0; \
17 sub tmp, 1, tmp; \ 57 rd %ccr, %g0; \
18 set BACKOFF_LIMIT, tmp; \ 58 rd %ccr, %g0; \
19 cmp reg, tmp; \ 59 .section .pause_3insn_patch,"ax";\
20 bg,pn %xcc, label; \ 60 .word 88b; \
21 nop; \ 61 sllx tmp, 7, tmp; \
22 ba,pt %xcc, label; \ 62 wr tmp, 0, %asr27; \
23 sllx reg, 1, reg; 63 clr tmp; \
64 .previous; \
65 brnz,pt tmp, 88b; \
66 sub tmp, 1, tmp; \
67 set BACKOFF_LIMIT, tmp; \
68 cmp reg, tmp; \
69 bg,pn %xcc, label; \
70 nop; \
71 ba,pt %xcc, label; \
72 sllx reg, 1, reg;
24 73
25#else 74#else
26 75
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
index cef99fbc0a21..830502fe62b4 100644
--- a/arch/sparc/include/asm/compat.h
+++ b/arch/sparc/include/asm/compat.h
@@ -232,9 +232,10 @@ static inline void __user *arch_compat_alloc_user_space(long len)
232 struct pt_regs *regs = current_thread_info()->kregs; 232 struct pt_regs *regs = current_thread_info()->kregs;
233 unsigned long usp = regs->u_regs[UREG_I6]; 233 unsigned long usp = regs->u_regs[UREG_I6];
234 234
235 if (!(test_thread_flag(TIF_32BIT))) 235 if (test_thread_64bit_stack(usp))
236 usp += STACK_BIAS; 236 usp += STACK_BIAS;
237 else 237
238 if (test_thread_flag(TIF_32BIT))
238 usp &= 0xffffffffUL; 239 usp &= 0xffffffffUL;
239 240
240 usp -= len; 241 usp -= len;
diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h
index 4e5a483122a0..721e25f0e2ea 100644
--- a/arch/sparc/include/asm/processor_64.h
+++ b/arch/sparc/include/asm/processor_64.h
@@ -196,7 +196,22 @@ extern unsigned long get_wchan(struct task_struct *task);
196#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc) 196#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
197#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP]) 197#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
198 198
199#define cpu_relax() barrier() 199/* Please see the commentary in asm/backoff.h for a description of
200 * what these instructions are doing and how they have been choosen.
201 * To make a long story short, we are trying to yield the current cpu
202 * strand during busy loops.
203 */
204#define cpu_relax() asm volatile("\n99:\n\t" \
205 "rd %%ccr, %%g0\n\t" \
206 "rd %%ccr, %%g0\n\t" \
207 "rd %%ccr, %%g0\n\t" \
208 ".section .pause_3insn_patch,\"ax\"\n\t"\
209 ".word 99b\n\t" \
210 "wr %%g0, 128, %%asr27\n\t" \
211 "nop\n\t" \
212 "nop\n\t" \
213 ".previous" \
214 ::: "memory")
200 215
201/* Prefetch support. This is tuned for UltraSPARC-III and later. 216/* Prefetch support. This is tuned for UltraSPARC-III and later.
202 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has 217 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index c28765110706..f93003123bce 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -63,5 +63,10 @@ extern char *of_console_options;
63extern void irq_trans_init(struct device_node *dp); 63extern void irq_trans_init(struct device_node *dp);
64extern char *build_path_component(struct device_node *dp); 64extern char *build_path_component(struct device_node *dp);
65 65
66/* SPARC has a local implementation */
67extern int of_address_to_resource(struct device_node *dev, int index,
68 struct resource *r);
69#define of_address_to_resource of_address_to_resource
70
66#endif /* __KERNEL__ */ 71#endif /* __KERNEL__ */
67#endif /* _SPARC_PROM_H */ 72#endif /* _SPARC_PROM_H */
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 4e2276631081..a3fe4dcc0aa6 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -259,6 +259,11 @@ static inline bool test_and_clear_restore_sigmask(void)
259 259
260#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG) 260#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
261 261
262#define thread32_stack_is_64bit(__SP) (((__SP) & 0x1) != 0)
263#define test_thread_64bit_stack(__SP) \
264 ((test_thread_flag(TIF_32BIT) && !thread32_stack_is_64bit(__SP)) ? \
265 false : true)
266
262#endif /* !__ASSEMBLY__ */ 267#endif /* !__ASSEMBLY__ */
263 268
264#endif /* __KERNEL__ */ 269#endif /* __KERNEL__ */
diff --git a/arch/sparc/include/asm/ttable.h b/arch/sparc/include/asm/ttable.h
index 48f2807d3265..71b5a67522ab 100644
--- a/arch/sparc/include/asm/ttable.h
+++ b/arch/sparc/include/asm/ttable.h
@@ -372,7 +372,9 @@ etrap_spill_fixup_64bit: \
372 372
373/* Normal 32bit spill */ 373/* Normal 32bit spill */
374#define SPILL_2_GENERIC(ASI) \ 374#define SPILL_2_GENERIC(ASI) \
375 srl %sp, 0, %sp; \ 375 and %sp, 1, %g3; \
376 brnz,pn %g3, (. - (128 + 4)); \
377 srl %sp, 0, %sp; \
376 stwa %l0, [%sp + %g0] ASI; \ 378 stwa %l0, [%sp + %g0] ASI; \
377 mov 0x04, %g3; \ 379 mov 0x04, %g3; \
378 stwa %l1, [%sp + %g3] ASI; \ 380 stwa %l1, [%sp + %g3] ASI; \
@@ -398,14 +400,16 @@ etrap_spill_fixup_64bit: \
398 stwa %i6, [%g1 + %g0] ASI; \ 400 stwa %i6, [%g1 + %g0] ASI; \
399 stwa %i7, [%g1 + %g3] ASI; \ 401 stwa %i7, [%g1 + %g3] ASI; \
400 saved; \ 402 saved; \
401 retry; nop; nop; \ 403 retry; \
402 b,a,pt %xcc, spill_fixup_dax; \ 404 b,a,pt %xcc, spill_fixup_dax; \
403 b,a,pt %xcc, spill_fixup_mna; \ 405 b,a,pt %xcc, spill_fixup_mna; \
404 b,a,pt %xcc, spill_fixup; 406 b,a,pt %xcc, spill_fixup;
405 407
406#define SPILL_2_GENERIC_ETRAP \ 408#define SPILL_2_GENERIC_ETRAP \
407etrap_user_spill_32bit: \ 409etrap_user_spill_32bit: \
408 srl %sp, 0, %sp; \ 410 and %sp, 1, %g3; \
411 brnz,pn %g3, etrap_user_spill_64bit; \
412 srl %sp, 0, %sp; \
409 stwa %l0, [%sp + 0x00] %asi; \ 413 stwa %l0, [%sp + 0x00] %asi; \
410 stwa %l1, [%sp + 0x04] %asi; \ 414 stwa %l1, [%sp + 0x04] %asi; \
411 stwa %l2, [%sp + 0x08] %asi; \ 415 stwa %l2, [%sp + 0x08] %asi; \
@@ -427,7 +431,7 @@ etrap_user_spill_32bit: \
427 ba,pt %xcc, etrap_save; \ 431 ba,pt %xcc, etrap_save; \
428 wrpr %g1, %cwp; \ 432 wrpr %g1, %cwp; \
429 nop; nop; nop; nop; \ 433 nop; nop; nop; nop; \
430 nop; nop; nop; nop; \ 434 nop; nop; \
431 ba,a,pt %xcc, etrap_spill_fixup_32bit; \ 435 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
432 ba,a,pt %xcc, etrap_spill_fixup_32bit; \ 436 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
433 ba,a,pt %xcc, etrap_spill_fixup_32bit; 437 ba,a,pt %xcc, etrap_spill_fixup_32bit;
@@ -592,7 +596,9 @@ user_rtt_fill_64bit: \
592 596
593/* Normal 32bit fill */ 597/* Normal 32bit fill */
594#define FILL_2_GENERIC(ASI) \ 598#define FILL_2_GENERIC(ASI) \
595 srl %sp, 0, %sp; \ 599 and %sp, 1, %g3; \
600 brnz,pn %g3, (. - (128 + 4)); \
601 srl %sp, 0, %sp; \
596 lduwa [%sp + %g0] ASI, %l0; \ 602 lduwa [%sp + %g0] ASI, %l0; \
597 mov 0x04, %g2; \ 603 mov 0x04, %g2; \
598 mov 0x08, %g3; \ 604 mov 0x08, %g3; \
@@ -616,14 +622,16 @@ user_rtt_fill_64bit: \
616 lduwa [%g1 + %g3] ASI, %i6; \ 622 lduwa [%g1 + %g3] ASI, %i6; \
617 lduwa [%g1 + %g5] ASI, %i7; \ 623 lduwa [%g1 + %g5] ASI, %i7; \
618 restored; \ 624 restored; \
619 retry; nop; nop; nop; nop; \ 625 retry; nop; nop; \
620 b,a,pt %xcc, fill_fixup_dax; \ 626 b,a,pt %xcc, fill_fixup_dax; \
621 b,a,pt %xcc, fill_fixup_mna; \ 627 b,a,pt %xcc, fill_fixup_mna; \
622 b,a,pt %xcc, fill_fixup; 628 b,a,pt %xcc, fill_fixup;
623 629
624#define FILL_2_GENERIC_RTRAP \ 630#define FILL_2_GENERIC_RTRAP \
625user_rtt_fill_32bit: \ 631user_rtt_fill_32bit: \
626 srl %sp, 0, %sp; \ 632 and %sp, 1, %g3; \
633 brnz,pn %g3, user_rtt_fill_64bit; \
634 srl %sp, 0, %sp; \
627 lduwa [%sp + 0x00] %asi, %l0; \ 635 lduwa [%sp + 0x00] %asi, %l0; \
628 lduwa [%sp + 0x04] %asi, %l1; \ 636 lduwa [%sp + 0x04] %asi, %l1; \
629 lduwa [%sp + 0x08] %asi, %l2; \ 637 lduwa [%sp + 0x08] %asi, %l2; \
@@ -643,7 +651,7 @@ user_rtt_fill_32bit: \
643 ba,pt %xcc, user_rtt_pre_restore; \ 651 ba,pt %xcc, user_rtt_pre_restore; \
644 restored; \ 652 restored; \
645 nop; nop; nop; nop; nop; \ 653 nop; nop; nop; nop; nop; \
646 nop; nop; nop; nop; nop; \ 654 nop; nop; nop; \
647 ba,a,pt %xcc, user_rtt_fill_fixup; \ 655 ba,a,pt %xcc, user_rtt_fill_fixup; \
648 ba,a,pt %xcc, user_rtt_fill_fixup; \ 656 ba,a,pt %xcc, user_rtt_fill_fixup; \
649 ba,a,pt %xcc, user_rtt_fill_fixup; 657 ba,a,pt %xcc, user_rtt_fill_fixup;
diff --git a/arch/sparc/include/uapi/asm/unistd.h b/arch/sparc/include/uapi/asm/unistd.h
index 8974ef7ae920..cac719d1bc5c 100644
--- a/arch/sparc/include/uapi/asm/unistd.h
+++ b/arch/sparc/include/uapi/asm/unistd.h
@@ -405,8 +405,13 @@
405#define __NR_setns 337 405#define __NR_setns 337
406#define __NR_process_vm_readv 338 406#define __NR_process_vm_readv 338
407#define __NR_process_vm_writev 339 407#define __NR_process_vm_writev 339
408#define __NR_kern_features 340
409#define __NR_kcmp 341
408 410
409#define NR_syscalls 340 411#define NR_syscalls 342
412
413/* Bitmask values returned from kern_features system call. */
414#define KERN_FEATURE_MIXED_MODE_STACK 0x00000001
410 415
411#ifdef __32bit_syscall_numbers__ 416#ifdef __32bit_syscall_numbers__
412/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, 417/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h
index 0c218e4c0881..cc3c5cb47cda 100644
--- a/arch/sparc/kernel/entry.h
+++ b/arch/sparc/kernel/entry.h
@@ -59,6 +59,13 @@ struct popc_6insn_patch_entry {
59extern struct popc_6insn_patch_entry __popc_6insn_patch, 59extern struct popc_6insn_patch_entry __popc_6insn_patch,
60 __popc_6insn_patch_end; 60 __popc_6insn_patch_end;
61 61
62struct pause_patch_entry {
63 unsigned int addr;
64 unsigned int insns[3];
65};
66extern struct pause_patch_entry __pause_3insn_patch,
67 __pause_3insn_patch_end;
68
62extern void __init per_cpu_patch(void); 69extern void __init per_cpu_patch(void);
63extern void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *, 70extern void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *,
64 struct sun4v_1insn_patch_entry *); 71 struct sun4v_1insn_patch_entry *);
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index f8b6eee40bde..87f60ee65433 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -56,11 +56,13 @@ static inline unsigned int leon_eirq_get(int cpu)
56static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc) 56static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc)
57{ 57{
58 unsigned int eirq; 58 unsigned int eirq;
59 struct irq_bucket *p;
59 int cpu = sparc_leon3_cpuid(); 60 int cpu = sparc_leon3_cpuid();
60 61
61 eirq = leon_eirq_get(cpu); 62 eirq = leon_eirq_get(cpu);
62 if ((eirq & 0x10) && irq_map[eirq]->irq) /* bit4 tells if IRQ happened */ 63 p = irq_map[eirq];
63 generic_handle_irq(irq_map[eirq]->irq); 64 if ((eirq & 0x10) && p && p->irq) /* bit4 tells if IRQ happened */
65 generic_handle_irq(p->irq);
64} 66}
65 67
66/* The extended IRQ controller has been found, this function registers it */ 68/* The extended IRQ controller has been found, this function registers it */
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 885a8af74064..b5c38faa4ead 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1762,15 +1762,25 @@ static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1762 1762
1763 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; 1763 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1764 do { 1764 do {
1765 struct sparc_stackf32 *usf, sf;
1766 unsigned long pc; 1765 unsigned long pc;
1767 1766
1768 usf = (struct sparc_stackf32 *) ufp; 1767 if (thread32_stack_is_64bit(ufp)) {
1769 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1768 struct sparc_stackf *usf, sf;
1770 break;
1771 1769
1772 pc = sf.callers_pc; 1770 ufp += STACK_BIAS;
1773 ufp = (unsigned long)sf.fp; 1771 usf = (struct sparc_stackf *) ufp;
1772 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1773 break;
1774 pc = sf.callers_pc & 0xffffffff;
1775 ufp = ((unsigned long) sf.fp) & 0xffffffff;
1776 } else {
1777 struct sparc_stackf32 *usf, sf;
1778 usf = (struct sparc_stackf32 *) ufp;
1779 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1780 break;
1781 pc = sf.callers_pc;
1782 ufp = (unsigned long)sf.fp;
1783 }
1774 perf_callchain_store(entry, pc); 1784 perf_callchain_store(entry, pc);
1775 } while (entry->nr < PERF_MAX_STACK_DEPTH); 1785 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1776} 1786}
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index d778248ef3f8..c6e0c2910043 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -452,13 +452,16 @@ void flush_thread(void)
452/* It's a bit more tricky when 64-bit tasks are involved... */ 452/* It's a bit more tricky when 64-bit tasks are involved... */
453static unsigned long clone_stackframe(unsigned long csp, unsigned long psp) 453static unsigned long clone_stackframe(unsigned long csp, unsigned long psp)
454{ 454{
455 bool stack_64bit = test_thread_64bit_stack(psp);
455 unsigned long fp, distance, rval; 456 unsigned long fp, distance, rval;
456 457
457 if (!(test_thread_flag(TIF_32BIT))) { 458 if (stack_64bit) {
458 csp += STACK_BIAS; 459 csp += STACK_BIAS;
459 psp += STACK_BIAS; 460 psp += STACK_BIAS;
460 __get_user(fp, &(((struct reg_window __user *)psp)->ins[6])); 461 __get_user(fp, &(((struct reg_window __user *)psp)->ins[6]));
461 fp += STACK_BIAS; 462 fp += STACK_BIAS;
463 if (test_thread_flag(TIF_32BIT))
464 fp &= 0xffffffff;
462 } else 465 } else
463 __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6])); 466 __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6]));
464 467
@@ -472,7 +475,7 @@ static unsigned long clone_stackframe(unsigned long csp, unsigned long psp)
472 rval = (csp - distance); 475 rval = (csp - distance);
473 if (copy_in_user((void __user *) rval, (void __user *) psp, distance)) 476 if (copy_in_user((void __user *) rval, (void __user *) psp, distance))
474 rval = 0; 477 rval = 0;
475 else if (test_thread_flag(TIF_32BIT)) { 478 else if (!stack_64bit) {
476 if (put_user(((u32)csp), 479 if (put_user(((u32)csp),
477 &(((struct reg_window32 __user *)rval)->ins[6]))) 480 &(((struct reg_window32 __user *)rval)->ins[6])))
478 rval = 0; 481 rval = 0;
@@ -507,18 +510,18 @@ void synchronize_user_stack(void)
507 510
508 flush_user_windows(); 511 flush_user_windows();
509 if ((window = get_thread_wsaved()) != 0) { 512 if ((window = get_thread_wsaved()) != 0) {
510 int winsize = sizeof(struct reg_window);
511 int bias = 0;
512
513 if (test_thread_flag(TIF_32BIT))
514 winsize = sizeof(struct reg_window32);
515 else
516 bias = STACK_BIAS;
517
518 window -= 1; 513 window -= 1;
519 do { 514 do {
520 unsigned long sp = (t->rwbuf_stkptrs[window] + bias);
521 struct reg_window *rwin = &t->reg_window[window]; 515 struct reg_window *rwin = &t->reg_window[window];
516 int winsize = sizeof(struct reg_window);
517 unsigned long sp;
518
519 sp = t->rwbuf_stkptrs[window];
520
521 if (test_thread_64bit_stack(sp))
522 sp += STACK_BIAS;
523 else
524 winsize = sizeof(struct reg_window32);
522 525
523 if (!copy_to_user((char __user *)sp, rwin, winsize)) { 526 if (!copy_to_user((char __user *)sp, rwin, winsize)) {
524 shift_window_buffer(window, get_thread_wsaved() - 1, t); 527 shift_window_buffer(window, get_thread_wsaved() - 1, t);
@@ -544,13 +547,6 @@ void fault_in_user_windows(void)
544{ 547{
545 struct thread_info *t = current_thread_info(); 548 struct thread_info *t = current_thread_info();
546 unsigned long window; 549 unsigned long window;
547 int winsize = sizeof(struct reg_window);
548 int bias = 0;
549
550 if (test_thread_flag(TIF_32BIT))
551 winsize = sizeof(struct reg_window32);
552 else
553 bias = STACK_BIAS;
554 550
555 flush_user_windows(); 551 flush_user_windows();
556 window = get_thread_wsaved(); 552 window = get_thread_wsaved();
@@ -558,8 +554,16 @@ void fault_in_user_windows(void)
558 if (likely(window != 0)) { 554 if (likely(window != 0)) {
559 window -= 1; 555 window -= 1;
560 do { 556 do {
561 unsigned long sp = (t->rwbuf_stkptrs[window] + bias);
562 struct reg_window *rwin = &t->reg_window[window]; 557 struct reg_window *rwin = &t->reg_window[window];
558 int winsize = sizeof(struct reg_window);
559 unsigned long sp;
560
561 sp = t->rwbuf_stkptrs[window];
562
563 if (test_thread_64bit_stack(sp))
564 sp += STACK_BIAS;
565 else
566 winsize = sizeof(struct reg_window32);
563 567
564 if (unlikely(sp & 0x7UL)) 568 if (unlikely(sp & 0x7UL))
565 stack_unaligned(sp); 569 stack_unaligned(sp);
diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
index 484dabac7045..7ff45e4ba681 100644
--- a/arch/sparc/kernel/ptrace_64.c
+++ b/arch/sparc/kernel/ptrace_64.c
@@ -151,7 +151,7 @@ static int regwindow64_get(struct task_struct *target,
151{ 151{
152 unsigned long rw_addr = regs->u_regs[UREG_I6]; 152 unsigned long rw_addr = regs->u_regs[UREG_I6];
153 153
154 if (test_tsk_thread_flag(current, TIF_32BIT)) { 154 if (!test_thread_64bit_stack(rw_addr)) {
155 struct reg_window32 win32; 155 struct reg_window32 win32;
156 int i; 156 int i;
157 157
@@ -176,7 +176,7 @@ static int regwindow64_set(struct task_struct *target,
176{ 176{
177 unsigned long rw_addr = regs->u_regs[UREG_I6]; 177 unsigned long rw_addr = regs->u_regs[UREG_I6];
178 178
179 if (test_tsk_thread_flag(current, TIF_32BIT)) { 179 if (!test_thread_64bit_stack(rw_addr)) {
180 struct reg_window32 win32; 180 struct reg_window32 win32;
181 int i; 181 int i;
182 182
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 0800e71d8a88..0eaf0059aaef 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -316,6 +316,25 @@ static void __init popc_patch(void)
316 } 316 }
317} 317}
318 318
319static void __init pause_patch(void)
320{
321 struct pause_patch_entry *p;
322
323 p = &__pause_3insn_patch;
324 while (p < &__pause_3insn_patch_end) {
325 unsigned long i, addr = p->addr;
326
327 for (i = 0; i < 3; i++) {
328 *(unsigned int *) (addr + (i * 4)) = p->insns[i];
329 wmb();
330 __asm__ __volatile__("flush %0"
331 : : "r" (addr + (i * 4)));
332 }
333
334 p++;
335 }
336}
337
319#ifdef CONFIG_SMP 338#ifdef CONFIG_SMP
320void __init boot_cpu_id_too_large(int cpu) 339void __init boot_cpu_id_too_large(int cpu)
321{ 340{
@@ -528,6 +547,8 @@ static void __init init_sparc64_elf_hwcap(void)
528 547
529 if (sparc64_elf_hwcap & AV_SPARC_POPC) 548 if (sparc64_elf_hwcap & AV_SPARC_POPC)
530 popc_patch(); 549 popc_patch();
550 if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
551 pause_patch();
531} 552}
532 553
533void __init setup_arch(char **cmdline_p) 554void __init setup_arch(char **cmdline_p)
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 11c6c9603e71..878ef3d5fec5 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -751,3 +751,8 @@ int kernel_execve(const char *filename,
751 : "cc"); 751 : "cc");
752 return __res; 752 return __res;
753} 753}
754
755asmlinkage long sys_kern_features(void)
756{
757 return KERN_FEATURE_MIXED_MODE_STACK;
758}
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 63402f9e9f51..5147f574f125 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -85,3 +85,4 @@ sys_call_table:
85/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init 85/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
86/*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime 86/*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
87/*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev 87/*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
88/*340*/ .long sys_ni_syscall, sys_kcmp
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 3a58e0d66f51..1c9af9fa38e9 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -86,6 +86,7 @@ sys_call_table32:
86 .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init 86 .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init
87/*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime 87/*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime
88 .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev 88 .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev
89/*340*/ .word sys_kern_features, sys_kcmp
89 90
90#endif /* CONFIG_COMPAT */ 91#endif /* CONFIG_COMPAT */
91 92
@@ -163,3 +164,4 @@ sys_call_table:
163 .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init 164 .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
164/*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime 165/*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
165 .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev 166 .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
167/*340*/ .word sys_kern_features, sys_kcmp
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index f81d038f7340..8201c25e7669 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -113,21 +113,24 @@ static inline long sign_extend_imm13(long imm)
113 113
114static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) 114static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
115{ 115{
116 unsigned long value; 116 unsigned long value, fp;
117 117
118 if (reg < 16) 118 if (reg < 16)
119 return (!reg ? 0 : regs->u_regs[reg]); 119 return (!reg ? 0 : regs->u_regs[reg]);
120
121 fp = regs->u_regs[UREG_FP];
122
120 if (regs->tstate & TSTATE_PRIV) { 123 if (regs->tstate & TSTATE_PRIV) {
121 struct reg_window *win; 124 struct reg_window *win;
122 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS); 125 win = (struct reg_window *)(fp + STACK_BIAS);
123 value = win->locals[reg - 16]; 126 value = win->locals[reg - 16];
124 } else if (test_thread_flag(TIF_32BIT)) { 127 } else if (!test_thread_64bit_stack(fp)) {
125 struct reg_window32 __user *win32; 128 struct reg_window32 __user *win32;
126 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 129 win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
127 get_user(value, &win32->locals[reg - 16]); 130 get_user(value, &win32->locals[reg - 16]);
128 } else { 131 } else {
129 struct reg_window __user *win; 132 struct reg_window __user *win;
130 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); 133 win = (struct reg_window __user *)(fp + STACK_BIAS);
131 get_user(value, &win->locals[reg - 16]); 134 get_user(value, &win->locals[reg - 16]);
132 } 135 }
133 return value; 136 return value;
@@ -135,19 +138,24 @@ static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
135 138
136static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs) 139static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
137{ 140{
141 unsigned long fp;
142
138 if (reg < 16) 143 if (reg < 16)
139 return &regs->u_regs[reg]; 144 return &regs->u_regs[reg];
145
146 fp = regs->u_regs[UREG_FP];
147
140 if (regs->tstate & TSTATE_PRIV) { 148 if (regs->tstate & TSTATE_PRIV) {
141 struct reg_window *win; 149 struct reg_window *win;
142 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS); 150 win = (struct reg_window *)(fp + STACK_BIAS);
143 return &win->locals[reg - 16]; 151 return &win->locals[reg - 16];
144 } else if (test_thread_flag(TIF_32BIT)) { 152 } else if (!test_thread_64bit_stack(fp)) {
145 struct reg_window32 *win32; 153 struct reg_window32 *win32;
146 win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 154 win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
147 return (unsigned long *)&win32->locals[reg - 16]; 155 return (unsigned long *)&win32->locals[reg - 16];
148 } else { 156 } else {
149 struct reg_window *win; 157 struct reg_window *win;
150 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS); 158 win = (struct reg_window *)(fp + STACK_BIAS);
151 return &win->locals[reg - 16]; 159 return &win->locals[reg - 16];
152 } 160 }
153} 161}
@@ -392,13 +400,15 @@ int handle_popc(u32 insn, struct pt_regs *regs)
392 if (rd) 400 if (rd)
393 regs->u_regs[rd] = ret; 401 regs->u_regs[rd] = ret;
394 } else { 402 } else {
395 if (test_thread_flag(TIF_32BIT)) { 403 unsigned long fp = regs->u_regs[UREG_FP];
404
405 if (!test_thread_64bit_stack(fp)) {
396 struct reg_window32 __user *win32; 406 struct reg_window32 __user *win32;
397 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 407 win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
398 put_user(ret, &win32->locals[rd - 16]); 408 put_user(ret, &win32->locals[rd - 16]);
399 } else { 409 } else {
400 struct reg_window __user *win; 410 struct reg_window __user *win;
401 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); 411 win = (struct reg_window __user *)(fp + STACK_BIAS);
402 put_user(ret, &win->locals[rd - 16]); 412 put_user(ret, &win->locals[rd - 16]);
403 } 413 }
404 } 414 }
@@ -554,7 +564,7 @@ void handle_ld_nf(u32 insn, struct pt_regs *regs)
554 reg[0] = 0; 564 reg[0] = 0;
555 if ((insn & 0x780000) == 0x180000) 565 if ((insn & 0x780000) == 0x180000)
556 reg[1] = 0; 566 reg[1] = 0;
557 } else if (test_thread_flag(TIF_32BIT)) { 567 } else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
558 put_user(0, (int __user *) reg); 568 put_user(0, (int __user *) reg);
559 if ((insn & 0x780000) == 0x180000) 569 if ((insn & 0x780000) == 0x180000)
560 put_user(0, ((int __user *) reg) + 1); 570 put_user(0, ((int __user *) reg) + 1);
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index 08e074b7eb6a..c096c624ac4d 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -149,21 +149,24 @@ static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
149 149
150static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) 150static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
151{ 151{
152 unsigned long value; 152 unsigned long value, fp;
153 153
154 if (reg < 16) 154 if (reg < 16)
155 return (!reg ? 0 : regs->u_regs[reg]); 155 return (!reg ? 0 : regs->u_regs[reg]);
156
157 fp = regs->u_regs[UREG_FP];
158
156 if (regs->tstate & TSTATE_PRIV) { 159 if (regs->tstate & TSTATE_PRIV) {
157 struct reg_window *win; 160 struct reg_window *win;
158 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS); 161 win = (struct reg_window *)(fp + STACK_BIAS);
159 value = win->locals[reg - 16]; 162 value = win->locals[reg - 16];
160 } else if (test_thread_flag(TIF_32BIT)) { 163 } else if (!test_thread_64bit_stack(fp)) {
161 struct reg_window32 __user *win32; 164 struct reg_window32 __user *win32;
162 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 165 win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
163 get_user(value, &win32->locals[reg - 16]); 166 get_user(value, &win32->locals[reg - 16]);
164 } else { 167 } else {
165 struct reg_window __user *win; 168 struct reg_window __user *win;
166 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); 169 win = (struct reg_window __user *)(fp + STACK_BIAS);
167 get_user(value, &win->locals[reg - 16]); 170 get_user(value, &win->locals[reg - 16]);
168 } 171 }
169 return value; 172 return value;
@@ -172,16 +175,18 @@ static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
172static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg, 175static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg,
173 struct pt_regs *regs) 176 struct pt_regs *regs)
174{ 177{
178 unsigned long fp = regs->u_regs[UREG_FP];
179
175 BUG_ON(reg < 16); 180 BUG_ON(reg < 16);
176 BUG_ON(regs->tstate & TSTATE_PRIV); 181 BUG_ON(regs->tstate & TSTATE_PRIV);
177 182
178 if (test_thread_flag(TIF_32BIT)) { 183 if (!test_thread_64bit_stack(fp)) {
179 struct reg_window32 __user *win32; 184 struct reg_window32 __user *win32;
180 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 185 win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
181 return (unsigned long __user *)&win32->locals[reg - 16]; 186 return (unsigned long __user *)&win32->locals[reg - 16];
182 } else { 187 } else {
183 struct reg_window __user *win; 188 struct reg_window __user *win;
184 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); 189 win = (struct reg_window __user *)(fp + STACK_BIAS);
185 return &win->locals[reg - 16]; 190 return &win->locals[reg - 16];
186 } 191 }
187} 192}
@@ -204,7 +209,7 @@ static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd)
204 } else { 209 } else {
205 unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs); 210 unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs);
206 211
207 if (test_thread_flag(TIF_32BIT)) 212 if (!test_thread_64bit_stack(regs->u_regs[UREG_FP]))
208 __put_user((u32)val, (u32 __user *)rd_user); 213 __put_user((u32)val, (u32 __user *)rd_user);
209 else 214 else
210 __put_user(val, rd_user); 215 __put_user(val, rd_user);
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index 89c2c29f154b..0bacceb19150 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -132,6 +132,11 @@ SECTIONS
132 *(.popc_6insn_patch) 132 *(.popc_6insn_patch)
133 __popc_6insn_patch_end = .; 133 __popc_6insn_patch_end = .;
134 } 134 }
135 .pause_3insn_patch : {
136 __pause_3insn_patch = .;
137 *(.pause_3insn_patch)
138 __pause_3insn_patch_end = .;
139 }
135 PERCPU_SECTION(SMP_CACHE_BYTES) 140 PERCPU_SECTION(SMP_CACHE_BYTES)
136 141
137 . = ALIGN(PAGE_SIZE); 142 . = ALIGN(PAGE_SIZE);
diff --git a/arch/sparc/kernel/winfixup.S b/arch/sparc/kernel/winfixup.S
index a6b0863c27df..1e67ce958369 100644
--- a/arch/sparc/kernel/winfixup.S
+++ b/arch/sparc/kernel/winfixup.S
@@ -43,6 +43,8 @@ spill_fixup_mna:
43spill_fixup_dax: 43spill_fixup_dax:
44 TRAP_LOAD_THREAD_REG(%g6, %g1) 44 TRAP_LOAD_THREAD_REG(%g6, %g1)
45 ldx [%g6 + TI_FLAGS], %g1 45 ldx [%g6 + TI_FLAGS], %g1
46 andcc %sp, 0x1, %g0
47 movne %icc, 0, %g1
46 andcc %g1, _TIF_32BIT, %g0 48 andcc %g1, _TIF_32BIT, %g0
47 ldub [%g6 + TI_WSAVED], %g1 49 ldub [%g6 + TI_WSAVED], %g1
48 sll %g1, 3, %g3 50 sll %g1, 3, %g3
diff --git a/arch/sparc/lib/atomic_64.S b/arch/sparc/lib/atomic_64.S
index 4d502da3de78..85c233d0a340 100644
--- a/arch/sparc/lib/atomic_64.S
+++ b/arch/sparc/lib/atomic_64.S
@@ -1,6 +1,6 @@
1/* atomic.S: These things are too big to do inline. 1/* atomic.S: These things are too big to do inline.
2 * 2 *
3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1999, 2007 2012 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/linkage.h> 6#include <linux/linkage.h>
@@ -117,3 +117,17 @@ ENTRY(atomic64_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
117 sub %g1, %o0, %o0 117 sub %g1, %o0, %o0
1182: BACKOFF_SPIN(%o2, %o3, 1b) 1182: BACKOFF_SPIN(%o2, %o3, 1b)
119ENDPROC(atomic64_sub_ret) 119ENDPROC(atomic64_sub_ret)
120
121ENTRY(atomic64_dec_if_positive) /* %o0 = atomic_ptr */
122 BACKOFF_SETUP(%o2)
1231: ldx [%o0], %g1
124 brlez,pn %g1, 3f
125 sub %g1, 1, %g7
126 casx [%o0], %g1, %g7
127 cmp %g1, %g7
128 bne,pn %xcc, BACKOFF_LABEL(2f, 1b)
129 nop
1303: retl
131 sub %g1, 1, %o0
1322: BACKOFF_SPIN(%o2, %o3, 1b)
133ENDPROC(atomic64_dec_if_positive)
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
index ee31b884c61b..0c4e35e522fa 100644
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -116,6 +116,7 @@ EXPORT_SYMBOL(atomic64_add);
116EXPORT_SYMBOL(atomic64_add_ret); 116EXPORT_SYMBOL(atomic64_add_ret);
117EXPORT_SYMBOL(atomic64_sub); 117EXPORT_SYMBOL(atomic64_sub);
118EXPORT_SYMBOL(atomic64_sub_ret); 118EXPORT_SYMBOL(atomic64_sub_ret);
119EXPORT_SYMBOL(atomic64_dec_if_positive);
119 120
120/* Atomic bit operations. */ 121/* Atomic bit operations. */
121EXPORT_SYMBOL(test_and_set_bit); 122EXPORT_SYMBOL(test_and_set_bit);
diff --git a/arch/sparc/math-emu/math_64.c b/arch/sparc/math-emu/math_64.c
index 1704068da928..034aadbff036 100644
--- a/arch/sparc/math-emu/math_64.c
+++ b/arch/sparc/math-emu/math_64.c
@@ -320,7 +320,7 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap)
320 XR = 0; 320 XR = 0;
321 else if (freg < 16) 321 else if (freg < 16)
322 XR = regs->u_regs[freg]; 322 XR = regs->u_regs[freg];
323 else if (test_thread_flag(TIF_32BIT)) { 323 else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
324 struct reg_window32 __user *win32; 324 struct reg_window32 __user *win32;
325 flushw_user (); 325 flushw_user ();
326 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 326 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index e5c5473e69ce..c4fbb21e802b 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -16,6 +16,8 @@ config UNICORE32
16 select ARCH_WANT_FRAME_POINTERS 16 select ARCH_WANT_FRAME_POINTERS
17 select GENERIC_IOMAP 17 select GENERIC_IOMAP
18 select MODULES_USE_ELF_REL 18 select MODULES_USE_ELF_REL
19 select GENERIC_KERNEL_THREAD
20 select GENERIC_KERNEL_EXECVE
19 help 21 help
20 UniCore-32 is 32-bit Instruction Set Architecture, 22 UniCore-32 is 32-bit Instruction Set Architecture,
21 including a series of low-power-consumption RISC chip 23 including a series of low-power-consumption RISC chip
@@ -64,6 +66,9 @@ config GENERIC_CALIBRATE_DELAY
64config ARCH_MAY_HAVE_PC_FDC 66config ARCH_MAY_HAVE_PC_FDC
65 bool 67 bool
66 68
69config ZONE_DMA
70 def_bool y
71
67config NEED_DMA_MAP_STATE 72config NEED_DMA_MAP_STATE
68 def_bool y 73 def_bool y
69 74
@@ -216,7 +221,7 @@ config PUV3_GPIO
216 bool 221 bool
217 depends on !ARCH_FPGA 222 depends on !ARCH_FPGA
218 select GENERIC_GPIO 223 select GENERIC_GPIO
219 select GPIO_SYSFS if EXPERIMENTAL 224 select GPIO_SYSFS
220 default y 225 default y
221 226
222if PUV3_NB0916 227if PUV3_NB0916
diff --git a/arch/unicore32/include/asm/Kbuild b/arch/unicore32/include/asm/Kbuild
index c910c9857e11..601e92f18af6 100644
--- a/arch/unicore32/include/asm/Kbuild
+++ b/arch/unicore32/include/asm/Kbuild
@@ -1,4 +1,3 @@
1include include/asm-generic/Kbuild.asm
2 1
3generic-y += atomic.h 2generic-y += atomic.h
4generic-y += auxvec.h 3generic-y += auxvec.h
diff --git a/arch/unicore32/include/asm/bug.h b/arch/unicore32/include/asm/bug.h
index b1ff8cadb086..93a56f3e2344 100644
--- a/arch/unicore32/include/asm/bug.h
+++ b/arch/unicore32/include/asm/bug.h
@@ -19,9 +19,4 @@ extern void die(const char *msg, struct pt_regs *regs, int err);
19extern void uc32_notify_die(const char *str, struct pt_regs *regs, 19extern void uc32_notify_die(const char *str, struct pt_regs *regs,
20 struct siginfo *info, unsigned long err, unsigned long trap); 20 struct siginfo *info, unsigned long err, unsigned long trap);
21 21
22extern asmlinkage void __backtrace(void);
23extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
24
25extern void __show_regs(struct pt_regs *);
26
27#endif /* __UNICORE_BUG_H__ */ 22#endif /* __UNICORE_BUG_H__ */
diff --git a/arch/unicore32/include/asm/cmpxchg.h b/arch/unicore32/include/asm/cmpxchg.h
index df4d5acfd19f..8e797ad4fa24 100644
--- a/arch/unicore32/include/asm/cmpxchg.h
+++ b/arch/unicore32/include/asm/cmpxchg.h
@@ -35,7 +35,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
35 : "memory", "cc"); 35 : "memory", "cc");
36 break; 36 break;
37 default: 37 default:
38 ret = __xchg_bad_pointer(); 38 __xchg_bad_pointer();
39 } 39 }
40 40
41 return ret; 41 return ret;
diff --git a/arch/unicore32/include/asm/kvm_para.h b/arch/unicore32/include/asm/kvm_para.h
deleted file mode 100644
index 14fab8f0b957..000000000000
--- a/arch/unicore32/include/asm/kvm_para.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/kvm_para.h>
diff --git a/arch/unicore32/include/asm/processor.h b/arch/unicore32/include/asm/processor.h
index 14382cb09657..4eaa42167667 100644
--- a/arch/unicore32/include/asm/processor.h
+++ b/arch/unicore32/include/asm/processor.h
@@ -72,11 +72,6 @@ unsigned long get_wchan(struct task_struct *p);
72 72
73#define cpu_relax() barrier() 73#define cpu_relax() barrier()
74 74
75/*
76 * Create a new kernel thread
77 */
78extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
79
80#define task_pt_regs(p) \ 75#define task_pt_regs(p) \
81 ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1) 76 ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
82 77
diff --git a/arch/unicore32/include/asm/ptrace.h b/arch/unicore32/include/asm/ptrace.h
index b9caf9b0997b..726749dab52f 100644
--- a/arch/unicore32/include/asm/ptrace.h
+++ b/arch/unicore32/include/asm/ptrace.h
@@ -12,80 +12,10 @@
12#ifndef __UNICORE_PTRACE_H__ 12#ifndef __UNICORE_PTRACE_H__
13#define __UNICORE_PTRACE_H__ 13#define __UNICORE_PTRACE_H__
14 14
15#define PTRACE_GET_THREAD_AREA 22 15#include <uapi/asm/ptrace.h>
16
17/*
18 * PSR bits
19 */
20#define USER_MODE 0x00000010
21#define REAL_MODE 0x00000011
22#define INTR_MODE 0x00000012
23#define PRIV_MODE 0x00000013
24#define ABRT_MODE 0x00000017
25#define EXTN_MODE 0x0000001b
26#define SUSR_MODE 0x0000001f
27#define MODE_MASK 0x0000001f
28#define PSR_R_BIT 0x00000040
29#define PSR_I_BIT 0x00000080
30#define PSR_V_BIT 0x10000000
31#define PSR_C_BIT 0x20000000
32#define PSR_Z_BIT 0x40000000
33#define PSR_S_BIT 0x80000000
34
35/*
36 * Groups of PSR bits
37 */
38#define PSR_f 0xff000000 /* Flags */
39#define PSR_c 0x000000ff /* Control */
40 16
41#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
42 18
43/*
44 * This struct defines the way the registers are stored on the
45 * stack during a system call. Note that sizeof(struct pt_regs)
46 * has to be a multiple of 8.
47 */
48struct pt_regs {
49 unsigned long uregs[34];
50};
51
52#define UCreg_asr uregs[32]
53#define UCreg_pc uregs[31]
54#define UCreg_lr uregs[30]
55#define UCreg_sp uregs[29]
56#define UCreg_ip uregs[28]
57#define UCreg_fp uregs[27]
58#define UCreg_26 uregs[26]
59#define UCreg_25 uregs[25]
60#define UCreg_24 uregs[24]
61#define UCreg_23 uregs[23]
62#define UCreg_22 uregs[22]
63#define UCreg_21 uregs[21]
64#define UCreg_20 uregs[20]
65#define UCreg_19 uregs[19]
66#define UCreg_18 uregs[18]
67#define UCreg_17 uregs[17]
68#define UCreg_16 uregs[16]
69#define UCreg_15 uregs[15]
70#define UCreg_14 uregs[14]
71#define UCreg_13 uregs[13]
72#define UCreg_12 uregs[12]
73#define UCreg_11 uregs[11]
74#define UCreg_10 uregs[10]
75#define UCreg_09 uregs[9]
76#define UCreg_08 uregs[8]
77#define UCreg_07 uregs[7]
78#define UCreg_06 uregs[6]
79#define UCreg_05 uregs[5]
80#define UCreg_04 uregs[4]
81#define UCreg_03 uregs[3]
82#define UCreg_02 uregs[2]
83#define UCreg_01 uregs[1]
84#define UCreg_00 uregs[0]
85#define UCreg_ORIG_00 uregs[33]
86
87#ifdef __KERNEL__
88
89#define user_mode(regs) \ 19#define user_mode(regs) \
90 (processor_mode(regs) == USER_MODE) 20 (processor_mode(regs) == USER_MODE)
91 21
@@ -125,9 +55,5 @@ static inline int valid_user_regs(struct pt_regs *regs)
125 55
126#define instruction_pointer(regs) ((regs)->UCreg_pc) 56#define instruction_pointer(regs) ((regs)->UCreg_pc)
127 57
128#endif /* __KERNEL__ */
129
130#endif /* __ASSEMBLY__ */ 58#endif /* __ASSEMBLY__ */
131
132#endif 59#endif
133
diff --git a/arch/unicore32/include/uapi/asm/Kbuild b/arch/unicore32/include/uapi/asm/Kbuild
index baebb3da1d44..0514d7ad6855 100644
--- a/arch/unicore32/include/uapi/asm/Kbuild
+++ b/arch/unicore32/include/uapi/asm/Kbuild
@@ -1,3 +1,10 @@
1# UAPI Header export list 1# UAPI Header export list
2include include/uapi/asm-generic/Kbuild.asm 2include include/uapi/asm-generic/Kbuild.asm
3 3
4header-y += byteorder.h
5header-y += kvm_para.h
6header-y += ptrace.h
7header-y += sigcontext.h
8header-y += unistd.h
9
10generic-y += kvm_para.h
diff --git a/arch/unicore32/include/asm/byteorder.h b/arch/unicore32/include/uapi/asm/byteorder.h
index ebe1b3fef3e3..ebe1b3fef3e3 100644
--- a/arch/unicore32/include/asm/byteorder.h
+++ b/arch/unicore32/include/uapi/asm/byteorder.h
diff --git a/arch/unicore32/include/uapi/asm/ptrace.h b/arch/unicore32/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000000..187aa2e98a53
--- /dev/null
+++ b/arch/unicore32/include/uapi/asm/ptrace.h
@@ -0,0 +1,90 @@
1/*
2 * linux/arch/unicore32/include/asm/ptrace.h
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef _UAPI__UNICORE_PTRACE_H__
13#define _UAPI__UNICORE_PTRACE_H__
14
15#define PTRACE_GET_THREAD_AREA 22
16
17/*
18 * PSR bits
19 */
20#define USER_MODE 0x00000010
21#define REAL_MODE 0x00000011
22#define INTR_MODE 0x00000012
23#define PRIV_MODE 0x00000013
24#define ABRT_MODE 0x00000017
25#define EXTN_MODE 0x0000001b
26#define SUSR_MODE 0x0000001f
27#define MODE_MASK 0x0000001f
28#define PSR_R_BIT 0x00000040
29#define PSR_I_BIT 0x00000080
30#define PSR_V_BIT 0x10000000
31#define PSR_C_BIT 0x20000000
32#define PSR_Z_BIT 0x40000000
33#define PSR_S_BIT 0x80000000
34
35/*
36 * Groups of PSR bits
37 */
38#define PSR_f 0xff000000 /* Flags */
39#define PSR_c 0x000000ff /* Control */
40
41#ifndef __ASSEMBLY__
42
43/*
44 * This struct defines the way the registers are stored on the
45 * stack during a system call. Note that sizeof(struct pt_regs)
46 * has to be a multiple of 8.
47 */
48struct pt_regs {
49 unsigned long uregs[34];
50};
51
52#define UCreg_asr uregs[32]
53#define UCreg_pc uregs[31]
54#define UCreg_lr uregs[30]
55#define UCreg_sp uregs[29]
56#define UCreg_ip uregs[28]
57#define UCreg_fp uregs[27]
58#define UCreg_26 uregs[26]
59#define UCreg_25 uregs[25]
60#define UCreg_24 uregs[24]
61#define UCreg_23 uregs[23]
62#define UCreg_22 uregs[22]
63#define UCreg_21 uregs[21]
64#define UCreg_20 uregs[20]
65#define UCreg_19 uregs[19]
66#define UCreg_18 uregs[18]
67#define UCreg_17 uregs[17]
68#define UCreg_16 uregs[16]
69#define UCreg_15 uregs[15]
70#define UCreg_14 uregs[14]
71#define UCreg_13 uregs[13]
72#define UCreg_12 uregs[12]
73#define UCreg_11 uregs[11]
74#define UCreg_10 uregs[10]
75#define UCreg_09 uregs[9]
76#define UCreg_08 uregs[8]
77#define UCreg_07 uregs[7]
78#define UCreg_06 uregs[6]
79#define UCreg_05 uregs[5]
80#define UCreg_04 uregs[4]
81#define UCreg_03 uregs[3]
82#define UCreg_02 uregs[2]
83#define UCreg_01 uregs[1]
84#define UCreg_00 uregs[0]
85#define UCreg_ORIG_00 uregs[33]
86
87
88#endif /* __ASSEMBLY__ */
89
90#endif /* _UAPI__UNICORE_PTRACE_H__ */
diff --git a/arch/unicore32/include/asm/sigcontext.h b/arch/unicore32/include/uapi/asm/sigcontext.h
index 6a2d7671c052..6a2d7671c052 100644
--- a/arch/unicore32/include/asm/sigcontext.h
+++ b/arch/unicore32/include/uapi/asm/sigcontext.h
diff --git a/arch/unicore32/include/asm/unistd.h b/arch/unicore32/include/uapi/asm/unistd.h
index 2abcf61c615d..d18a3be89b38 100644
--- a/arch/unicore32/include/asm/unistd.h
+++ b/arch/unicore32/include/uapi/asm/unistd.h
@@ -12,3 +12,4 @@
12 12
13/* Use the standard ABI for syscalls. */ 13/* Use the standard ABI for syscalls. */
14#include <asm-generic/unistd.h> 14#include <asm-generic/unistd.h>
15#define __ARCH_WANT_SYS_EXECVE
diff --git a/arch/unicore32/kernel/entry.S b/arch/unicore32/kernel/entry.S
index dcb87ab19ddd..7049350c790f 100644
--- a/arch/unicore32/kernel/entry.S
+++ b/arch/unicore32/kernel/entry.S
@@ -573,17 +573,16 @@ ENDPROC(ret_to_user)
573 */ 573 */
574ENTRY(ret_from_fork) 574ENTRY(ret_from_fork)
575 b.l schedule_tail 575 b.l schedule_tail
576 get_thread_info tsk
577 ldw r1, [tsk+], #TI_FLAGS @ check for syscall tracing
578 mov why, #1
579 cand.a r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
580 beq ret_slow_syscall
581 mov r1, sp
582 mov r0, #1 @ trace exit [IP = 1]
583 b.l syscall_trace
584 b ret_slow_syscall 576 b ret_slow_syscall
585ENDPROC(ret_from_fork) 577ENDPROC(ret_from_fork)
586 578
579ENTRY(ret_from_kernel_thread)
580 b.l schedule_tail
581 mov r0, r5
582 adr lr, ret_slow_syscall
583 mov pc, r4
584ENDPROC(ret_from_kernel_thread)
585
587/*============================================================================= 586/*=============================================================================
588 * SWI handler 587 * SWI handler
589 *----------------------------------------------------------------------------- 588 *-----------------------------------------------------------------------------
@@ -669,11 +668,6 @@ __cr_alignment:
669#endif 668#endif
670 .ltorg 669 .ltorg
671 670
672ENTRY(sys_execve)
673 add r3, sp, #S_OFF
674 b __sys_execve
675ENDPROC(sys_execve)
676
677ENTRY(sys_clone) 671ENTRY(sys_clone)
678 add ip, sp, #S_OFF 672 add ip, sp, #S_OFF
679 stw ip, [sp+], #4 673 stw ip, [sp+], #4
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index b008586dad75..a8fe265ce2c0 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -258,6 +258,7 @@ void release_thread(struct task_struct *dead_task)
258} 258}
259 259
260asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); 260asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
261asmlinkage void ret_from_kernel_thread(void) __asm__("ret_from_kernel_thread");
261 262
262int 263int
263copy_thread(unsigned long clone_flags, unsigned long stack_start, 264copy_thread(unsigned long clone_flags, unsigned long stack_start,
@@ -266,17 +267,22 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
266 struct thread_info *thread = task_thread_info(p); 267 struct thread_info *thread = task_thread_info(p);
267 struct pt_regs *childregs = task_pt_regs(p); 268 struct pt_regs *childregs = task_pt_regs(p);
268 269
269 *childregs = *regs;
270 childregs->UCreg_00 = 0;
271 childregs->UCreg_sp = stack_start;
272
273 memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save)); 270 memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
274 thread->cpu_context.sp = (unsigned long)childregs; 271 thread->cpu_context.sp = (unsigned long)childregs;
275 thread->cpu_context.pc = (unsigned long)ret_from_fork; 272 if (unlikely(!regs)) {
276 273 thread->cpu_context.pc = (unsigned long)ret_from_kernel_thread;
277 if (clone_flags & CLONE_SETTLS) 274 thread->cpu_context.r4 = stack_start;
278 childregs->UCreg_16 = regs->UCreg_03; 275 thread->cpu_context.r5 = stk_sz;
276 memset(childregs, 0, sizeof(struct pt_regs));
277 } else {
278 thread->cpu_context.pc = (unsigned long)ret_from_fork;
279 *childregs = *regs;
280 childregs->UCreg_00 = 0;
281 childregs->UCreg_sp = stack_start;
279 282
283 if (clone_flags & CLONE_SETTLS)
284 childregs->UCreg_16 = regs->UCreg_03;
285 }
280 return 0; 286 return 0;
281} 287}
282 288
@@ -305,42 +311,6 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fp)
305} 311}
306EXPORT_SYMBOL(dump_fpu); 312EXPORT_SYMBOL(dump_fpu);
307 313
308/*
309 * Shuffle the argument into the correct register before calling the
310 * thread function. r1 is the thread argument, r2 is the pointer to
311 * the thread function, and r3 points to the exit function.
312 */
313asm(".pushsection .text\n"
314" .align\n"
315" .type kernel_thread_helper, #function\n"
316"kernel_thread_helper:\n"
317" mov.a asr, r7\n"
318" mov r0, r4\n"
319" mov lr, r6\n"
320" mov pc, r5\n"
321" .size kernel_thread_helper, . - kernel_thread_helper\n"
322" .popsection");
323
324/*
325 * Create a kernel thread.
326 */
327pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
328{
329 struct pt_regs regs;
330
331 memset(&regs, 0, sizeof(regs));
332
333 regs.UCreg_04 = (unsigned long)arg;
334 regs.UCreg_05 = (unsigned long)fn;
335 regs.UCreg_06 = (unsigned long)do_exit;
336 regs.UCreg_07 = PRIV_MODE;
337 regs.UCreg_pc = (unsigned long)kernel_thread_helper;
338 regs.UCreg_asr = regs.UCreg_07 | PSR_I_BIT;
339
340 return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
341}
342EXPORT_SYMBOL(kernel_thread);
343
344unsigned long get_wchan(struct task_struct *p) 314unsigned long get_wchan(struct task_struct *p)
345{ 315{
346 struct stackframe frame; 316 struct stackframe frame;
diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h
index f23955028a18..30f749da8f73 100644
--- a/arch/unicore32/kernel/setup.h
+++ b/arch/unicore32/kernel/setup.h
@@ -30,4 +30,10 @@ extern char __vectors_start[], __vectors_end[];
30extern void kernel_thread_helper(void); 30extern void kernel_thread_helper(void);
31 31
32extern void __init early_signal_init(void); 32extern void __init early_signal_init(void);
33
34extern asmlinkage void __backtrace(void);
35extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
36
37extern void __show_regs(struct pt_regs *);
38
33#endif 39#endif
diff --git a/arch/unicore32/kernel/sys.c b/arch/unicore32/kernel/sys.c
index fabdee96110b..9680134b31f0 100644
--- a/arch/unicore32/kernel/sys.c
+++ b/arch/unicore32/kernel/sys.c
@@ -42,69 +42,6 @@ asmlinkage long __sys_clone(unsigned long clone_flags, unsigned long newsp,
42 parent_tid, child_tid); 42 parent_tid, child_tid);
43} 43}
44 44
45/* sys_execve() executes a new program.
46 * This is called indirectly via a small wrapper
47 */
48asmlinkage long __sys_execve(const char __user *filename,
49 const char __user *const __user *argv,
50 const char __user *const __user *envp,
51 struct pt_regs *regs)
52{
53 int error;
54 struct filename *fn;
55
56 fn = getname(filename);
57 error = PTR_ERR(fn);
58 if (IS_ERR(fn))
59 goto out;
60 error = do_execve(fn->name, argv, envp, regs);
61 putname(fn);
62out:
63 return error;
64}
65
66int kernel_execve(const char *filename,
67 const char *const argv[],
68 const char *const envp[])
69{
70 struct pt_regs regs;
71 int ret;
72
73 memset(&regs, 0, sizeof(struct pt_regs));
74 ret = do_execve(filename,
75 (const char __user *const __user *)argv,
76 (const char __user *const __user *)envp, &regs);
77 if (ret < 0)
78 goto out;
79
80 /*
81 * Save argc to the register structure for userspace.
82 */
83 regs.UCreg_00 = ret;
84
85 /*
86 * We were successful. We won't be returning to our caller, but
87 * instead to user space by manipulating the kernel stack.
88 */
89 asm("add r0, %0, %1\n\t"
90 "mov r1, %2\n\t"
91 "mov r2, %3\n\t"
92 "mov r22, #0\n\t" /* not a syscall */
93 "mov r23, %0\n\t" /* thread structure */
94 "b.l memmove\n\t" /* copy regs to top of stack */
95 "mov sp, r0\n\t" /* reposition stack pointer */
96 "b ret_to_user"
97 :
98 : "r" (current_thread_info()),
99 "Ir" (THREAD_START_SP - sizeof(regs)),
100 "r" (&regs),
101 "Ir" (sizeof(regs))
102 : "r0", "r1", "r2", "r3", "ip", "lr", "memory");
103
104 out:
105 return ret;
106}
107
108/* Note: used by the compat code even in 64-bit Linux. */ 45/* Note: used by the compat code even in 64-bit Linux. */
109SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 46SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
110 unsigned long, prot, unsigned long, flags, 47 unsigned long, prot, unsigned long, flags,
diff --git a/arch/unicore32/mm/fault.c b/arch/unicore32/mm/fault.c
index 2eeb9c04cab0..f9b5c10bccee 100644
--- a/arch/unicore32/mm/fault.c
+++ b/arch/unicore32/mm/fault.c
@@ -168,7 +168,7 @@ static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma)
168} 168}
169 169
170static int __do_pf(struct mm_struct *mm, unsigned long addr, unsigned int fsr, 170static int __do_pf(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
171 struct task_struct *tsk) 171 unsigned int flags, struct task_struct *tsk)
172{ 172{
173 struct vm_area_struct *vma; 173 struct vm_area_struct *vma;
174 int fault; 174 int fault;
@@ -194,14 +194,7 @@ good_area:
194 * If for any reason at all we couldn't handle the fault, make 194 * If for any reason at all we couldn't handle the fault, make
195 * sure we exit gracefully rather than endlessly redo the fault. 195 * sure we exit gracefully rather than endlessly redo the fault.
196 */ 196 */
197 fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, 197 fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, flags);
198 (!(fsr ^ 0x12)) ? FAULT_FLAG_WRITE : 0);
199 if (unlikely(fault & VM_FAULT_ERROR))
200 return fault;
201 if (fault & VM_FAULT_MAJOR)
202 tsk->maj_flt++;
203 else
204 tsk->min_flt++;
205 return fault; 198 return fault;
206 199
207check_stack: 200check_stack:
@@ -216,6 +209,8 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
216 struct task_struct *tsk; 209 struct task_struct *tsk;
217 struct mm_struct *mm; 210 struct mm_struct *mm;
218 int fault, sig, code; 211 int fault, sig, code;
212 unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
213 ((!(fsr ^ 0x12)) ? FAULT_FLAG_WRITE : 0);
219 214
220 tsk = current; 215 tsk = current;
221 mm = tsk->mm; 216 mm = tsk->mm;
@@ -236,6 +231,7 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
236 if (!user_mode(regs) 231 if (!user_mode(regs)
237 && !search_exception_tables(regs->UCreg_pc)) 232 && !search_exception_tables(regs->UCreg_pc))
238 goto no_context; 233 goto no_context;
234retry:
239 down_read(&mm->mmap_sem); 235 down_read(&mm->mmap_sem);
240 } else { 236 } else {
241 /* 237 /*
@@ -251,7 +247,28 @@ static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
251#endif 247#endif
252 } 248 }
253 249
254 fault = __do_pf(mm, addr, fsr, tsk); 250 fault = __do_pf(mm, addr, fsr, flags, tsk);
251
252 /* If we need to retry but a fatal signal is pending, handle the
253 * signal first. We do not need to release the mmap_sem because
254 * it would already be released in __lock_page_or_retry in
255 * mm/filemap.c. */
256 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
257 return 0;
258
259 if (!(fault & VM_FAULT_ERROR) && (flags & FAULT_FLAG_ALLOW_RETRY)) {
260 if (fault & VM_FAULT_MAJOR)
261 tsk->maj_flt++;
262 else
263 tsk->min_flt++;
264 if (fault & VM_FAULT_RETRY) {
265 /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
266 * of starvation. */
267 flags &= ~FAULT_FLAG_ALLOW_RETRY;
268 goto retry;
269 }
270 }
271
255 up_read(&mm->mmap_sem); 272 up_read(&mm->mmap_sem);
256 273
257 /* 274 /*
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 59c226d120cd..c20d1ce62dc6 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -359,18 +359,14 @@ HYPERVISOR_update_va_mapping(unsigned long va, pte_t new_val,
359 return _hypercall4(int, update_va_mapping, va, 359 return _hypercall4(int, update_va_mapping, va,
360 new_val.pte, new_val.pte >> 32, flags); 360 new_val.pte, new_val.pte >> 32, flags);
361} 361}
362extern int __must_check xen_event_channel_op_compat(int, void *);
362 363
363static inline int 364static inline int
364HYPERVISOR_event_channel_op(int cmd, void *arg) 365HYPERVISOR_event_channel_op(int cmd, void *arg)
365{ 366{
366 int rc = _hypercall2(int, event_channel_op, cmd, arg); 367 int rc = _hypercall2(int, event_channel_op, cmd, arg);
367 if (unlikely(rc == -ENOSYS)) { 368 if (unlikely(rc == -ENOSYS))
368 struct evtchn_op op; 369 rc = xen_event_channel_op_compat(cmd, arg);
369 op.cmd = cmd;
370 memcpy(&op.u, arg, sizeof(op.u));
371 rc = _hypercall1(int, event_channel_op_compat, &op);
372 memcpy(arg, &op.u, sizeof(op.u));
373 }
374 return rc; 370 return rc;
375} 371}
376 372
@@ -386,17 +382,14 @@ HYPERVISOR_console_io(int cmd, int count, char *str)
386 return _hypercall3(int, console_io, cmd, count, str); 382 return _hypercall3(int, console_io, cmd, count, str);
387} 383}
388 384
385extern int __must_check HYPERVISOR_physdev_op_compat(int, void *);
386
389static inline int 387static inline int
390HYPERVISOR_physdev_op(int cmd, void *arg) 388HYPERVISOR_physdev_op(int cmd, void *arg)
391{ 389{
392 int rc = _hypercall2(int, physdev_op, cmd, arg); 390 int rc = _hypercall2(int, physdev_op, cmd, arg);
393 if (unlikely(rc == -ENOSYS)) { 391 if (unlikely(rc == -ENOSYS))
394 struct physdev_op op; 392 rc = HYPERVISOR_physdev_op_compat(cmd, arg);
395 op.cmd = cmd;
396 memcpy(&op.u, arg, sizeof(op.u));
397 rc = _hypercall1(int, physdev_op_compat, &op);
398 memcpy(arg, &op.u, sizeof(op.u));
399 }
400 return rc; 393 return rc;
401} 394}
402 395
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index a10e46016851..58fc51488828 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -24,6 +24,9 @@ static inline bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
24{ 24{
25 struct kvm_cpuid_entry2 *best; 25 struct kvm_cpuid_entry2 *best;
26 26
27 if (!static_cpu_has(X86_FEATURE_XSAVE))
28 return 0;
29
27 best = kvm_find_cpuid_entry(vcpu, 1, 0); 30 best = kvm_find_cpuid_entry(vcpu, 1, 0);
28 return best && (best->ecx & bit(X86_FEATURE_XSAVE)); 31 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
29} 32}
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ad6b1dd06f8b..f85815945fc6 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -6549,19 +6549,22 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6549 } 6549 }
6550 } 6550 }
6551 6551
6552 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6553 /* Exposing INVPCID only when PCID is exposed */ 6552 /* Exposing INVPCID only when PCID is exposed */
6554 best = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6553 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6555 if (vmx_invpcid_supported() && 6554 if (vmx_invpcid_supported() &&
6556 best && (best->ebx & bit(X86_FEATURE_INVPCID)) && 6555 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6557 guest_cpuid_has_pcid(vcpu)) { 6556 guest_cpuid_has_pcid(vcpu)) {
6557 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6558 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID; 6558 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6559 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, 6559 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6560 exec_control); 6560 exec_control);
6561 } else { 6561 } else {
6562 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 6562 if (cpu_has_secondary_exec_ctrls()) {
6563 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, 6563 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6564 exec_control); 6564 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6565 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6566 exec_control);
6567 }
6565 if (best) 6568 if (best)
6566 best->ebx &= ~bit(X86_FEATURE_INVPCID); 6569 best->ebx &= ~bit(X86_FEATURE_INVPCID);
6567 } 6570 }
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 224a7e78cb6c..4f7641756be2 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5781,6 +5781,9 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5781 int pending_vec, max_bits, idx; 5781 int pending_vec, max_bits, idx;
5782 struct desc_ptr dt; 5782 struct desc_ptr dt;
5783 5783
5784 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
5785 return -EINVAL;
5786
5784 dt.size = sregs->idt.limit; 5787 dt.size = sregs->idt.limit;
5785 dt.address = sregs->idt.base; 5788 dt.address = sregs->idt.base;
5786 kvm_x86_ops->set_idt(vcpu, &dt); 5789 kvm_x86_ops->set_idt(vcpu, &dt);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 13:06:17 -0400