14 files changed, 55 insertions, 30 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db524e75c4a2..f1d9297b1050 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -9,7 +9,7 @@ config ARM
         select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
         select HAVE_ARCH_KGDB
-        select HAVE_KPROBES if (!XIP_KERNEL)
+        select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
         select HAVE_KRETPROBES if (HAVE_KPROBES)
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2..4d26f2c52a75 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -70,12 +70,7 @@ else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
 
-ifeq ($(CONFIG_THUMB2_KERNEL),y)
-# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
-$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
-else
 $(obj)/uImage: STARTADDR=$(LOADADDR)
-endif
 
 $(obj)/uImage:  $(obj)/zImage FORCE
         $(call if_changed,uimage)
diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
index 8b0de41c3dcb..78b508075161 100644
--- a/arch/arm/boot/bootp/init.S
+++ b/arch/arm/boot/bootp/init.S
@@ -73,6 +73,8 @@ move:		ldmia	r4!, {r7 - r10}		@ move 32-bytes at a time
 
                 .size   _start, . - _start
 
+                .align
+
                 .type   data,#object
 data:           .word   initrd_start            @ source initrd address
                 .word   initrd_phys             @ destination initrd address
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9be21ba648cd..7193884ed8b0 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -125,9 +125,13 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
  * sort out different calling conventions
  */
                 .align
+                .arm                            @ Always enter in ARM state
 start:
                 .type   start,#function
-                .rept   8
+ THUMB(         adr     r12, BSYM(1f)   )
+ THUMB(         bx      r12             )
+ THUMB(         .rept   6               )
+ ARM(           .rept   8               )
                 mov     r0, r0
                 .endr
 
@@ -135,6 +139,7 @@ start:
                 .word   0x016f2818              @ Magic numbers to help the loader
                 .word   start                   @ absolute load/run zImage address
                 .word   _edata                  @ zImage end address
+ THUMB(         .thumb                  )
 1:              mov     r7, r1                  @ save architecture ID
                 mov     r8, r2                  @ save atags pointer
 
@@ -174,7 +179,8 @@ not_angel:
                 ldr     sp, [r0, #28]
 #ifdef CONFIG_AUTO_ZRELADDR
                 @ determine final kernel image address
-                and     r4, pc, #0xf8000000
+                mov     r4, pc
+                and     r4, r4, #0xf8000000
                 add     r4, r4, #TEXT_OFFSET
 #else
                 ldr     r4, =zreladdr
@@ -445,7 +451,8 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
  */
                 mov     r1, #0x1e
                 orr     r1, r1, #3 << 10
-                mov     r2, pc, lsr #20
+                mov     r2, pc
+                mov     r2, r2, lsr #20
                 orr     r1, r1, r2, lsl #20
                 add     r0, r3, r2, lsl #2
                 str     r1, [r0], #4
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 772f95f1aecd..e6388dcd8cfa 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
         unsigned int shift = (irq % 4) * 8;
         unsigned int cpu = cpumask_first(mask_val);
         u32 val;
+        struct irq_desc *desc;
 
         spin_lock(&irq_controller_lock);
-        irq_desc[irq].node = cpu;
+        desc = irq_to_desc(irq);
+        if (desc == NULL) {
+                spin_unlock(&irq_controller_lock);
+                return -EINVAL;
+        }
+        desc->node = cpu;
         val = readl(reg) & ~(0xff << shift);
         val |= 1 << (cpu + shift);
         writel(val, reg);
@@ -210,7 +216,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
                           unsigned int irq_start)
 {
-        unsigned int max_irq, i;
+        unsigned int gic_irqs, irq_limit, i;
         u32 cpumask = 1 << smp_processor_id();
 
         if (gic_nr >= MAX_GIC_NR)
@@ -226,47 +232,49 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
 
         /*
          * Find out how many interrupts are supported.
-         */
-        max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
-        max_irq = (max_irq + 1) * 32;
-
-        /*
          * The GIC only supports up to 1020 interrupt sources.
-         * Limit this to either the architected maximum, or the
-         * platform maximum.
          */
-        if (max_irq > max(1020, NR_IRQS))
-                max_irq = max(1020, NR_IRQS);
+        gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = (gic_irqs + 1) * 32;
+        if (gic_irqs > 1020)
+                gic_irqs = 1020;
 
         /*
          * Set all global interrupts to be level triggered, active low.
          */
-        for (i = 32; i < max_irq; i += 16)
+        for (i = 32; i < gic_irqs; i += 16)
                 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 
         /*
          * Set all global interrupts to this CPU only.
          */
-        for (i = 32; i < max_irq; i += 4)
+        for (i = 32; i < gic_irqs; i += 4)
                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
         /*
          * Set priority on all global interrupts.
          */
-        for (i = 32; i < max_irq; i += 4)
+        for (i = 32; i < gic_irqs; i += 4)
                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 
         /*
          * Disable all interrupts.  Leave the PPI and SGIs alone
          * as these enables are banked registers.
          */
-        for (i = 32; i < max_irq; i += 32)
+        for (i = 32; i < gic_irqs; i += 32)
                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
         /*
+         * Limit number of interrupts registered to the platform maximum
+         */
+        irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
+        if (WARN_ON(irq_limit > NR_IRQS))
+                irq_limit = NR_IRQS;
+
+        /*
          * Setup the Linux IRQ subsystem.
          */
-        for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
+        for (i = irq_start; i < irq_limit; i++) {
                 set_irq_chip(i, &gic_chip);
                 set_irq_chip_data(i, &gic_data[gic_nr]);
                 set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c09e3573c5de..bb96a7d4bbf5 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -911,7 +911,7 @@ __kuser_cmpxchg:				@ 0xffff0fc0
          * A special ghost syscall is used for that (see traps.c).
          */
         stmfd   sp!, {r7, lr}
-        ldr     r7, =1f                 @ it's 20 bits
+        ldr     r7, 1f                  @ it's 20 bits
         swi     __ARM_NR_cmpxchg
         ldmfd   sp!, {r7, pc}
 1:      .word   __ARM_NR_cmpxchg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index dd6b369ac69c..6bd82d25683c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -85,9 +85,11 @@ ENTRY(stext)
         mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?
+ THUMB( it      eq )            @ force fixup-able long branch encoding
         beq     __error_p                       @ yes, error 'p'
         bl      __lookup_machine_type           @ r5=machinfo
         movs    r8, r5                          @ invalid machine (r5=0)?
+ THUMB( it      eq )            @ force fixup-able long branch encoding
         beq     __error_a                       @ yes, error 'a'
         bl      __vet_atags
 #ifdef CONFIG_SMP_ON_UP
@@ -262,6 +264,7 @@ __create_page_tables:
         mov     pc, lr
 ENDPROC(__create_page_tables)
         .ltorg
+        .align
 __enable_mmu_loc:
         .long   .
         .long   __enable_mmu
@@ -282,6 +285,7 @@ ENTRY(secondary_startup)
         bl      __lookup_processor_type
         movs    r10, r5                         @ invalid processor?
         moveq   r0, #'p'                        @ yes, error 'p'
+ THUMB( it      eq )            @ force fixup-able long branch encoding
         beq     __error_p
 
         /*
@@ -308,6 +312,8 @@ ENTRY(__secondary_switched)
         b       secondary_start_kernel
 ENDPROC(__secondary_switched)
 
+        .align
+
         .type   __secondary_data, %object
 __secondary_data:
         .long   .
@@ -413,6 +419,7 @@ __fixup_smp_on_up:
         mov     pc, lr
 ENDPROC(__fixup_smp)
 
+        .align
 1:      .word   .
         .word   __smpalt_begin
         .word   __smpalt_end
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index fd26f8d65151..9cf4cbf8f95b 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -59,6 +59,8 @@ relocate_new_kernel:
         ldr r2,kexec_boot_atags
         mov pc,lr
 
+        .align
+
         .globl kexec_start_address
 kexec_start_address:
         .long   0x0
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 38088c36936c..78defd71a829 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -369,7 +369,7 @@ static int __init cns3xxx_pcie_init(void)
 {
         int i;
 
-        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
                         "imprecise external abort");
 
         for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
index 4075473cf68a..b34be4554d40 100644
--- a/arch/arm/mach-realview/headsmp.S
+++ b/arch/arm/mach-realview/headsmp.S
@@ -35,5 +35,6 @@ pen:	ldr	r7, [r6]
          */
         b       secondary_startup
 
+        .align
 1:      .long   .
         .long   pen_release
diff --git a/arch/arm/mach-vexpress/headsmp.S b/arch/arm/mach-vexpress/headsmp.S
index 8a78ff68e1ee..7a3f0632947c 100644
--- a/arch/arm/mach-vexpress/headsmp.S
+++ b/arch/arm/mach-vexpress/headsmp.S
@@ -35,5 +35,6 @@ pen:	ldr	r7, [r6]
          */
         b       secondary_startup
 
+        .align
 1:      .long   .
         .long   pen_release
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 53cbe2225153..9b9ff5d949fd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -381,7 +381,7 @@ __v7_ca9mp_proc_info:
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        b       __v7_ca9mp_setup
+        W(b)    __v7_ca9mp_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
@@ -413,7 +413,7 @@ __v7_proc_info:
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        b       __v7_setup
+        W(b)    __v7_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 85d3e55ca4a9..558cdfaf76b6 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -18,6 +18,7 @@
 #include <linux/time.h>
 #include <linux/init.h>
 #include <linux/timex.h>
+#include <linux/sched.h>
 #include <linux/io.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
@@ -36,7 +37,7 @@
 /*
  * IOP clocksource (free-running timer 1).
  */
-static cycle_t iop_clocksource_read(struct clocksource *unused)
+static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
 {
         return 0xffffffffu - read_tcr1();
 }
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index d66cead97d28..9897dcfc16d6 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -206,6 +206,7 @@ ENTRY(vfp_save_state)
         mov     pc, lr
 ENDPROC(vfp_save_state)
 
+        .align
 last_VFP_context_address:
         .word   last_VFP_context