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-rw-r--r--arch/arm/boot/dts/highbank.dts12
-rw-r--r--arch/arm/configs/omap1_defconfig1
-rw-r--r--arch/arm/mach-davinci/clock.c13
-rw-r--r--arch/arm/mach-davinci/clock.h10
-rw-r--r--arch/arm/mach-davinci/dm644x.c4
-rw-r--r--arch/arm/mach-dove/addr-map.c121
-rw-r--r--arch/arm/mach-dove/common.c16
-rw-r--r--arch/arm/mach-dove/common.h1
-rw-r--r--arch/arm/mach-dove/pcie.c4
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c137
-rw-r--r--arch/arm/mach-kirkwood/common.c19
-rw-r--r--arch/arm/mach-kirkwood/common.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h1
-rw-r--r--arch/arm/mach-kirkwood/mpp.c1
-rw-r--r--arch/arm/mach-kirkwood/mpp.h1
-rw-r--r--arch/arm/mach-kirkwood/pcie.c4
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c102
-rw-r--r--arch/arm/mach-mv78xx0/common.c22
-rw-r--r--arch/arm/mach-mv78xx0/common.h1
-rw-r--r--arch/arm/mach-mv78xx0/mpp.c1
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c4
-rw-r--r--arch/arm/mach-omap1/Kconfig64
-rw-r--r--arch/arm/mach-omap1/clock.c14
-rw-r--r--arch/arm/mach-omap1/clock.h3
-rw-r--r--arch/arm/mach-omap1/clock_data.c19
-rw-r--r--arch/arm/mach-omap1/opp.h1
-rw-r--r--arch/arm/mach-omap1/opp_data.c63
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c11
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c374
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c217
-rw-r--r--arch/arm/mach-omap2/prcm-common.h2
-rw-r--r--arch/arm/mach-orion5x/addr-map.c146
-rw-r--r--arch/arm/mach-orion5x/common.c23
-rw-r--r--arch/arm/mach-orion5x/common.h3
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h2
-rw-r--r--arch/arm/mach-orion5x/mpp.c1
-rw-r--r--arch/arm/mach-orion5x/pci.c5
-rw-r--r--arch/arm/mach-picoxcell/common.c37
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c88
-rw-r--r--arch/arm/mach-ux500/board-mop500.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500.h63
-rw-r--r--arch/arm/mach-ux500/clock.c207
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c41
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c30
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c10
-rw-r--r--arch/arm/mach-ux500/id.c6
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h4
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h20
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h2
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h10
-rw-r--r--arch/arm/mach-ux500/include/mach/id.h24
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h1
-rw-r--r--arch/arm/plat-omap/sram.c9
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/addr-map.c174
-rw-r--r--arch/arm/plat-orion/common.c43
-rw-r--r--arch/arm/plat-orion/include/plat/addr-map.h53
-rw-r--r--arch/arm/plat-orion/include/plat/audio.h3
-rw-r--r--arch/arm/plat-orion/include/plat/common.h17
-rw-r--r--arch/arm/plat-orion/include/plat/ehci-orion.h1
-rw-r--r--arch/arm/plat-orion/include/plat/mv_xor.h6
-rw-r--r--arch/arm/plat-orion/include/plat/mvsdio.h1
-rw-r--r--arch/arm/plat-orion/include/plat/pcie.h3
-rw-r--r--arch/arm/plat-orion/pcie.c6
66 files changed, 1370 insertions, 920 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index aeb1a7578fad..305635bd45c0 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -194,5 +194,17 @@
194 reg = <0xfff3d000 0x1000>; 194 reg = <0xfff3d000 0x1000>;
195 interrupts = <0 92 4>; 195 interrupts = <0 92 4>;
196 }; 196 };
197
198 ethernet@fff50000 {
199 compatible = "calxeda,hb-xgmac";
200 reg = <0xfff50000 0x1000>;
201 interrupts = <0 77 4 0 78 4 0 79 4>;
202 };
203
204 ethernet@fff51000 {
205 compatible = "calxeda,hb-xgmac";
206 reg = <0xfff51000 0x1000>;
207 interrupts = <0 80 4 0 81 4 0 82 4>;
208 };
197 }; 209 };
198}; 210};
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 945a34f2a34d..dde2a1af7b39 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y
48CONFIG_MACH_NOKIA770=y 48CONFIG_MACH_NOKIA770=y
49CONFIG_MACH_AMS_DELTA=y 49CONFIG_MACH_AMS_DELTA=y
50CONFIG_MACH_OMAP_GENERIC=y 50CONFIG_MACH_OMAP_GENERIC=y
51CONFIG_OMAP_ARM_182MHZ=y
52# CONFIG_ARM_THUMB is not set 51# CONFIG_ARM_THUMB is not set
53CONFIG_PCCARD=y 52CONFIG_PCCARD=y
54CONFIG_OMAP_CF=y 53CONFIG_OMAP_CF=y
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 00861139101d..008772e3b843 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -31,19 +31,12 @@ static LIST_HEAD(clocks);
31static DEFINE_MUTEX(clocks_mutex); 31static DEFINE_MUTEX(clocks_mutex);
32static DEFINE_SPINLOCK(clockfw_lock); 32static DEFINE_SPINLOCK(clockfw_lock);
33 33
34static unsigned psc_domain(struct clk *clk)
35{
36 return (clk->flags & PSC_DSP)
37 ? DAVINCI_GPSC_DSPDOMAIN
38 : DAVINCI_GPSC_ARMDOMAIN;
39}
40
41static void __clk_enable(struct clk *clk) 34static void __clk_enable(struct clk *clk)
42{ 35{
43 if (clk->parent) 36 if (clk->parent)
44 __clk_enable(clk->parent); 37 __clk_enable(clk->parent);
45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 38 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 39 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
47 true, clk->flags); 40 true, clk->flags);
48} 41}
49 42
@@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk)
53 return; 46 return;
54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && 47 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
55 (clk->flags & CLK_PSC)) 48 (clk->flags & CLK_PSC))
56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 49 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
57 false, clk->flags); 50 false, clk->flags);
58 if (clk->parent) 51 if (clk->parent)
59 __clk_disable(clk->parent); 52 __clk_disable(clk->parent);
@@ -237,7 +230,7 @@ static int __init clk_disable_unused(void)
237 230
238 pr_debug("Clocks: disable unused %s\n", ck->name); 231 pr_debug("Clocks: disable unused %s\n", ck->name);
239 232
240 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 233 davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
241 false, ck->flags); 234 false, ck->flags);
242 } 235 }
243 spin_unlock_irq(&clockfw_lock); 236 spin_unlock_irq(&clockfw_lock);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a705f367a84d..46f0f1bf1a4c 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -93,6 +93,7 @@ struct clk {
93 u8 usecount; 93 u8 usecount;
94 u8 lpsc; 94 u8 lpsc;
95 u8 gpsc; 95 u8 gpsc;
96 u8 domain;
96 u32 flags; 97 u32 flags;
97 struct clk *parent; 98 struct clk *parent;
98 struct list_head children; /* list of children */ 99 struct list_head children; /* list of children */
@@ -107,11 +108,10 @@ struct clk {
107/* Clock flags: SoC-specific flags start at BIT(16) */ 108/* Clock flags: SoC-specific flags start at BIT(16) */
108#define ALWAYS_ENABLED BIT(1) 109#define ALWAYS_ENABLED BIT(1)
109#define CLK_PSC BIT(2) 110#define CLK_PSC BIT(2)
110#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 111#define CLK_PLL BIT(3) /* PLL-derived clock */
111#define CLK_PLL BIT(4) /* PLL-derived clock */ 112#define PRE_PLL BIT(4) /* source is before PLL mult/div */
112#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 113#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ 114#define PSC_FORCE BIT(6) /* Force module state transtition */
114#define PSC_FORCE BIT(7) /* Force module state transtition */
115 115
116#define CLK(dev, con, ck) \ 116#define CLK(dev, con, ck) \
117 { \ 117 { \
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 0800f9cf33bb..43a48ee1917b 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -130,7 +130,7 @@ static struct clk dsp_clk = {
130 .name = "dsp", 130 .name = "dsp",
131 .parent = &pll1_sysclk1, 131 .parent = &pll1_sysclk1,
132 .lpsc = DAVINCI_LPSC_GEM, 132 .lpsc = DAVINCI_LPSC_GEM,
133 .flags = PSC_DSP, 133 .domain = DAVINCI_GPSC_DSPDOMAIN,
134 .usecount = 1, /* REVISIT how to disable? */ 134 .usecount = 1, /* REVISIT how to disable? */
135}; 135};
136 136
@@ -145,7 +145,7 @@ static struct clk vicp_clk = {
145 .name = "vicp", 145 .name = "vicp",
146 .parent = &pll1_sysclk2, 146 .parent = &pll1_sysclk2,
147 .lpsc = DAVINCI_LPSC_IMCOP, 147 .lpsc = DAVINCI_LPSC_IMCOP,
148 .flags = PSC_DSP, 148 .domain = DAVINCI_GPSC_DSPDOMAIN,
149 .usecount = 1, /* REVISIT how to disable? */ 149 .usecount = 1, /* REVISIT how to disable? */
150}; 150};
151 151
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 00be4fc26dd7..98b8c83b09ab 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/setup.h> 16#include <asm/setup.h>
17#include <plat/addr-map.h>
17#include "common.h" 18#include "common.h"
18 19
19/* 20/*
@@ -34,98 +35,72 @@
34#define ATTR_PCIE_MEM 0xe8 35#define ATTR_PCIE_MEM 0xe8
35#define ATTR_SCRATCHPAD 0x0 36#define ATTR_SCRATCHPAD 0x0
36 37
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45struct mbus_dram_target_info dove_mbus_dram_info;
46
47static inline void __iomem *ddr_map_sc(int i) 38static inline void __iomem *ddr_map_sc(int i)
48{ 39{
49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); 40 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
50} 41}
51 42
52static int cpu_win_can_remap(int win) 43/*
53{ 44 * Description of the windows needed by the platform code
54 if (win < 4) 45 */
55 return 1; 46static struct __initdata orion_addr_map_cfg addr_map_cfg = {
56 47 .num_wins = 8,
57 return 0; 48 .remappable_wins = 4,
58} 49 .bridge_virt_base = BRIDGE_VIRT_BASE,
59 50};
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76}
77
78void __init dove_setup_cpu_mbus(void)
79{
80 int i;
81 int cs;
82 51
52static const struct __initdata orion_addr_map_info addr_map_info[] = {
83 /* 53 /*
84 * First, disable and clear windows. 54 * Windows for PCIe IO+MEM space.
85 */ 55 */
86 for (i = 0; i < 8; i++) { 56 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
87 writel(0, WIN_BASE(i)); 57 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
88 writel(0, WIN_CTRL(i)); 58 },
89 if (cpu_win_can_remap(i)) { 59 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
90 writel(0, WIN_REMAP_LO(i)); 60 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
91 writel(0, WIN_REMAP_HI(i)); 61 },
92 } 62 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
93 } 63 TARGET_PCIE0, ATTR_PCIE_MEM, -1
94 64 },
65 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
66 TARGET_PCIE1, ATTR_PCIE_MEM, -1
67 },
95 /* 68 /*
96 * Setup windows for PCIe IO+MEM space. 69 * Window for CESA engine.
97 */ 70 */
98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, 71 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); 72 TARGET_CESA, ATTR_CESA, -1
100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, 73 },
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
107 /* 74 /*
108 * Setup window for CESA engine. 75 * Window to the BootROM for Standby and Sleep Resume
109 */ 76 */
110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, 77 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
111 TARGET_CESA, ATTR_CESA, -1); 78 TARGET_BOOTROM, ATTR_BOOTROM, -1
112 79 },
113 /* 80 /*
114 * Setup the Window to the BootROM for Standby and Sleep Resume 81 * Window to the PMU Scratch Pad space
115 */ 82 */
116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, 83 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
117 TARGET_BOOTROM, ATTR_BOOTROM, -1); 84 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
85 },
86 /* End marker */
87 { -1, 0, 0, 0, 0, 0 }
88};
89
90void __init dove_setup_cpu_mbus(void)
91{
92 int i;
93 int cs;
118 94
119 /* 95 /*
120 * Setup the Window to the PMU Scratch Pad space 96 * Disable, clear and configure windows.
121 */ 97 */
122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, 98 orion_config_wins(&addr_map_cfg, addr_map_info);
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
124 99
125 /* 100 /*
126 * Setup MBUS dram target info. 101 * Setup MBUS dram target info.
127 */ 102 */
128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 103 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
129 104
130 for (i = 0, cs = 0; i < 2; i++) { 105 for (i = 0, cs = 0; i < 2; i++) {
131 u32 map = readl(ddr_map_sc(i)); 106 u32 map = readl(ddr_map_sc(i));
@@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
136 if (map & 1) { 111 if (map & 1) {
137 struct mbus_dram_window *w; 112 struct mbus_dram_window *w;
138 113
139 w = &dove_mbus_dram_info.cs[cs++]; 114 w = &orion_mbus_dram_info.cs[cs++];
140 w->cs_index = i; 115 w->cs_index = i;
141 w->mbus_attr = 0; /* CS address decoding done inside */ 116 w->mbus_attr = 0; /* CS address decoding done inside */
142 /* the DDR controller, no need to */ 117 /* the DDR controller, no need to */
@@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 120 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
146 } 121 }
147 } 122 }
148 dove_mbus_dram_info.num_cs = cs; 123 orion_mbus_dram_info.num_cs = cs;
149} 124}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 13bb236cd0cd..dd1429ae6405 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -14,7 +14,6 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/mbus.h>
18#include <linux/ata_platform.h> 17#include <linux/ata_platform.h>
19#include <linux/gpio.h> 18#include <linux/gpio.h>
20#include <asm/page.h> 19#include <asm/page.h>
@@ -30,6 +29,7 @@
30#include <linux/irq.h> 29#include <linux/irq.h>
31#include <plat/time.h> 30#include <plat/time.h>
32#include <plat/common.h> 31#include <plat/common.h>
32#include <plat/addr-map.h>
33#include "common.h" 33#include "common.h"
34 34
35static int get_tclk(void); 35static int get_tclk(void);
@@ -71,8 +71,7 @@ void __init dove_map_io(void)
71 ****************************************************************************/ 71 ****************************************************************************/
72void __init dove_ehci0_init(void) 72void __init dove_ehci0_init(void)
73{ 73{
74 orion_ehci_init(&dove_mbus_dram_info, 74 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
75 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
76} 75}
77 76
78/***************************************************************************** 77/*****************************************************************************
@@ -80,8 +79,7 @@ void __init dove_ehci0_init(void)
80 ****************************************************************************/ 79 ****************************************************************************/
81void __init dove_ehci1_init(void) 80void __init dove_ehci1_init(void)
82{ 81{
83 orion_ehci_1_init(&dove_mbus_dram_info, 82 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
84 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
85} 83}
86 84
87/***************************************************************************** 85/*****************************************************************************
@@ -89,7 +87,7 @@ void __init dove_ehci1_init(void)
89 ****************************************************************************/ 87 ****************************************************************************/
90void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 88void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
91{ 89{
92 orion_ge00_init(eth_data, &dove_mbus_dram_info, 90 orion_ge00_init(eth_data,
93 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 91 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
94 0, get_tclk()); 92 0, get_tclk());
95} 93}
@@ -107,8 +105,7 @@ void __init dove_rtc_init(void)
107 ****************************************************************************/ 105 ****************************************************************************/
108void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 106void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
109{ 107{
110 orion_sata_init(sata_data, &dove_mbus_dram_info, 108 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
111 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
112 109
113} 110}
114 111
@@ -198,8 +195,7 @@ struct sys_timer dove_timer = {
198 ****************************************************************************/ 195 ****************************************************************************/
199void __init dove_xor0_init(void) 196void __init dove_xor0_init(void)
200{ 197{
201 orion_xor0_init(&dove_mbus_dram_info, 198 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
202 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
203 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 199 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
204} 200}
205 201
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 42027305c107..6432a3ba864b 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data; 15struct mv_sata_platform_data;
16 16
17extern struct sys_timer dove_timer; 17extern struct sys_timer dove_timer;
18extern struct mbus_dram_target_info dove_mbus_dram_info;
19 18
20/* 19/*
21 * Basic Dove init functions used early by machine-setup. 20 * Basic Dove init functions used early by machine-setup.
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index aa2b3a09a51d..6c11a4df7178 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,7 +10,6 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <video/vga.h> 13#include <video/vga.h>
15#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
16#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
@@ -19,6 +18,7 @@
19#include <plat/pcie.h> 18#include <plat/pcie.h>
20#include <mach/irqs.h> 19#include <mach/irqs.h>
21#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/addr-map.h>
22#include "common.h" 22#include "common.h"
23 23
24struct pcie_port { 24struct pcie_port {
@@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
50 */ 50 */
51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
52 52
53 orion_pcie_setup(pp->base, &dove_mbus_dram_info); 53 orion_pcie_setup(pp->base);
54 54
55 /* 55 /*
56 * IORESOURCE_IO 56 * IORESOURCE_IO
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8d03bcef5182..e9a7180863d9 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -13,12 +13,12 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/hardware.h> 15#include <mach/hardware.h>
16#include <plat/addr-map.h>
16#include "common.h" 17#include "common.h"
17 18
18/* 19/*
19 * Generic Address Decode Windows bit settings 20 * Generic Address Decode Windows bit settings
20 */ 21 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1 22#define TARGET_DEV_BUS 1
23#define TARGET_SRAM 3 23#define TARGET_SRAM 3
24#define TARGET_PCIE 4 24#define TARGET_PCIE 4
@@ -36,118 +36,55 @@
36#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
37 37
38/* 38/*
39 * Helpers to get DDR bank info 39 * Description of the windows needed by the platform code
40 */ 40 */
41#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 41static struct __initdata orion_addr_map_cfg addr_map_cfg = {
42#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 42 .num_wins = 8,
43 43 .remappable_wins = 4,
44/* 44 .bridge_virt_base = BRIDGE_VIRT_BASE,
45 * CPU Address Decode Windows registers 45};
46 */
47#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
48#define WIN_CTRL_OFF 0x0000
49#define WIN_BASE_OFF 0x0004
50#define WIN_REMAP_LO_OFF 0x0008
51#define WIN_REMAP_HI_OFF 0x000c
52
53
54struct mbus_dram_target_info kirkwood_mbus_dram_info;
55
56static int __init cpu_win_can_remap(int win)
57{
58 if (win < 4)
59 return 1;
60
61 return 0;
62}
63
64static void __init setup_cpu_win(int win, u32 base, u32 size,
65 u8 target, u8 attr, int remap)
66{
67 void __iomem *addr = (void __iomem *)WIN_OFF(win);
68 u32 ctrl;
69
70 base &= 0xffff0000;
71 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
72
73 writel(base, addr + WIN_BASE_OFF);
74 writel(ctrl, addr + WIN_CTRL_OFF);
75 if (cpu_win_can_remap(win)) {
76 if (remap < 0)
77 remap = base;
78
79 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
80 writel(0, addr + WIN_REMAP_HI_OFF);
81 }
82}
83
84void __init kirkwood_setup_cpu_mbus(void)
85{
86 void __iomem *addr;
87 int i;
88 int cs;
89 46
47static const struct __initdata orion_addr_map_info addr_map_info[] = {
90 /* 48 /*
91 * First, disable and clear windows. 49 * Windows for PCIe IO+MEM space.
92 */ 50 */
93 for (i = 0; i < 8; i++) { 51 { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
94 addr = (void __iomem *)WIN_OFF(i); 52 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
95 53 },
96 writel(0, addr + WIN_BASE_OFF); 54 { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
97 writel(0, addr + WIN_CTRL_OFF); 55 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
98 if (cpu_win_can_remap(i)) { 56 },
99 writel(0, addr + WIN_REMAP_LO_OFF); 57 { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
100 writel(0, addr + WIN_REMAP_HI_OFF); 58 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
101 } 59 },
102 } 60 { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
103 61 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
62 },
104 /* 63 /*
105 * Setup windows for PCIe IO+MEM space. 64 * Window for NAND controller.
106 */ 65 */
107 setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, 66 { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 67 TARGET_DEV_BUS, ATTR_DEV_NAND, -1
109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 68 },
110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
115
116 /* 69 /*
117 * Setup window for NAND controller. 70 * Window for SRAM.
118 */ 71 */
119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 72 { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 73 TARGET_SRAM, ATTR_SRAM, -1
74 },
75 /* End marker */
76 { -1, 0, 0, 0, 0, 0 }
77};
121 78
79void __init kirkwood_setup_cpu_mbus(void)
80{
122 /* 81 /*
123 * Setup window for SRAM. 82 * Disable, clear and configure windows.
124 */ 83 */
125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 84 orion_config_wins(&addr_map_cfg, addr_map_info);
126 TARGET_SRAM, ATTR_SRAM, -1);
127 85
128 /* 86 /*
129 * Setup MBUS dram target info. 87 * Setup MBUS dram target info.
130 */ 88 */
131 kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 89 orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
132
133 addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
134
135 for (i = 0, cs = 0; i < 4; i++) {
136 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
137 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
138
139 /*
140 * Chip select enabled?
141 */
142 if (size & 1) {
143 struct mbus_dram_window *w;
144
145 w = &kirkwood_mbus_dram_info.cs[cs++];
146 w->cs_index = i;
147 w->mbus_attr = 0xf & ~(1 << i);
148 w->base = base & 0xffff0000;
149 w->size = (size | 0x0000ffff) + 1;
150 }
151 }
152 kirkwood_mbus_dram_info.num_cs = cs;
153} 90}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0bff4a916231..cc15426787b1 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -12,7 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
17#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
18#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
@@ -30,6 +29,7 @@
30#include <plat/orion_nand.h> 29#include <plat/orion_nand.h>
31#include <plat/common.h> 30#include <plat/common.h>
32#include <plat/time.h> 31#include <plat/time.h>
32#include <plat/addr-map.h>
33#include "common.h" 33#include "common.h"
34 34
35/***************************************************************************** 35/*****************************************************************************
@@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73void __init kirkwood_ehci_init(void) 73void __init kirkwood_ehci_init(void)
74{ 74{
75 kirkwood_clk_ctrl |= CGC_USB0; 75 kirkwood_clk_ctrl |= CGC_USB0;
76 orion_ehci_init(&kirkwood_mbus_dram_info, 76 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
77 USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
78} 77}
79 78
80 79
@@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
85{ 84{
86 kirkwood_clk_ctrl |= CGC_GE0; 85 kirkwood_clk_ctrl |= CGC_GE0;
87 86
88 orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, 87 orion_ge00_init(eth_data,
89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, 88 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); 89 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
91} 90}
@@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
99 98
100 kirkwood_clk_ctrl |= CGC_GE1; 99 kirkwood_clk_ctrl |= CGC_GE1;
101 100
102 orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, 101 orion_ge01_init(eth_data,
103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, 102 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); 103 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
105} 104}
@@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
178 if (sata_data->n_ports > 1) 177 if (sata_data->n_ports > 1)
179 kirkwood_clk_ctrl |= CGC_SATA1; 178 kirkwood_clk_ctrl |= CGC_SATA1;
180 179
181 orion_sata_init(sata_data, &kirkwood_mbus_dram_info, 180 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
182 SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
183} 181}
184 182
185 183
@@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
221 mvsdio_data->clock = 100000000; 219 mvsdio_data->clock = 100000000;
222 else 220 else
223 mvsdio_data->clock = 200000000; 221 mvsdio_data->clock = 200000000;
224 mvsdio_data->dram = &kirkwood_mbus_dram_info;
225 kirkwood_clk_ctrl |= CGC_SDIO; 222 kirkwood_clk_ctrl |= CGC_SDIO;
226 kirkwood_sdio.dev.platform_data = mvsdio_data; 223 kirkwood_sdio.dev.platform_data = mvsdio_data;
227 platform_device_register(&kirkwood_sdio); 224 platform_device_register(&kirkwood_sdio);
@@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void)
285{ 282{
286 kirkwood_clk_ctrl |= CGC_XOR0; 283 kirkwood_clk_ctrl |= CGC_XOR0;
287 284
288 orion_xor0_init(&kirkwood_mbus_dram_info, 285 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
289 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
290 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); 286 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
291} 287}
292 288
@@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = {
364}; 360};
365 361
366static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { 362static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
367 .dram = &kirkwood_mbus_dram_info,
368 .burst = 128, 363 .burst = 128,
369}; 364};
370 365
@@ -430,6 +425,8 @@ static char * __init kirkwood_id(void)
430 } else if (dev == MV88F6282_DEV_ID) { 425 } else if (dev == MV88F6282_DEV_ID) {
431 if (rev == MV88F6282_REV_A0) 426 if (rev == MV88F6282_REV_A0)
432 return "MV88F6282-Rev-A0"; 427 return "MV88F6282-Rev-A0";
428 else if (rev == MV88F6282_REV_A1)
429 return "MV88F6282-Rev-A1";
433 else 430 else
434 return "MV88F6282-Rev-Unsupported"; 431 return "MV88F6282-Rev-Unsupported";
435 } else { 432 } else {
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 1529280246d6..9071a397136d 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,6 @@ void kirkwood_init(void);
30void kirkwood_init_early(void); 30void kirkwood_init_early(void);
31void kirkwood_init_irq(void); 31void kirkwood_init_irq(void);
32 32
33extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
34void kirkwood_setup_cpu_mbus(void); 33void kirkwood_setup_cpu_mbus(void);
35 34
36void kirkwood_enable_pcie(void); 35void kirkwood_enable_pcie(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 010bdeb4ac5f..fede3d503efa 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -135,4 +135,5 @@
135 135
136#define MV88F6282_DEV_ID 0x6282 136#define MV88F6282_DEV_ID 0x6282
137#define MV88F6282_REV_A0 0 137#define MV88F6282_REV_A0 0
138#define MV88F6282_REV_A1 1
138#endif 139#endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index cc431fa22ccb..0c6ad63f10c7 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -10,7 +10,6 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <mach/hardware.h> 14#include <mach/hardware.h>
16#include <plat/mpp.h> 15#include <plat/mpp.h>
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index ac787957e2d9..e8fda45c0736 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -102,6 +102,7 @@
102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
103 103
104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
105#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
106#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
107#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 74b992d810ea..fb451bfe478b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,12 +11,12 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/mbus.h>
15#include <video/vga.h> 14#include <video/vga.h>
16#include <asm/irq.h> 15#include <asm/irq.h>
17#include <asm/mach/pci.h> 16#include <asm/mach/pci.h>
18#include <plat/pcie.h> 17#include <plat/pcie.h>
19#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include <plat/addr-map.h>
20#include "common.h" 20#include "common.h"
21 21
22void kirkwood_enable_pcie(void) 22void kirkwood_enable_pcie(void)
@@ -208,7 +208,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
208 */ 208 */
209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
210 210
211 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); 211 orion_pcie_setup(pp->base);
212 212
213 return 1; 213 return 1;
214} 214}
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc7..62b53d710efd 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/addr-map.h>
15#include "common.h" 16#include "common.h"
16 17
17/* 18/*
18 * Generic Address Decode Windows bit settings 19 * Generic Address Decode Windows bit settings
19 */ 20 */
20#define TARGET_DDR 0
21#define TARGET_DEV_BUS 1 21#define TARGET_DEV_BUS 1
22#define TARGET_PCIE0 4 22#define TARGET_PCIE0 4
23#define TARGET_PCIE1 8 23#define TARGET_PCIE1 8
@@ -32,23 +32,10 @@
32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) 32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
33 33
34/* 34/*
35 * Helpers to get DDR bank info
36 */
37#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
38#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
39
40/*
41 * CPU Address Decode Windows registers 35 * CPU Address Decode Windows registers
42 */ 36 */
43#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) 37#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
44#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) 38#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
45#define WIN_CTRL_OFF 0x0000
46#define WIN_BASE_OFF 0x0004
47#define WIN_REMAP_LO_OFF 0x0008
48#define WIN_REMAP_HI_OFF 0x000c
49
50
51struct mbus_dram_target_info mv78xx0_mbus_dram_info;
52 39
53static void __init __iomem *win_cfg_base(int win) 40static void __init __iomem *win_cfg_base(int win)
54{ 41{
@@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win)
63 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); 50 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
64} 51}
65 52
66static int __init cpu_win_can_remap(int win) 53/*
67{ 54 * Description of the windows needed by the platform code
68 if (win < 8) 55 */
69 return 1; 56static struct __initdata orion_addr_map_cfg addr_map_cfg = {
70 57 .num_wins = 14,
71 return 0; 58 .remappable_wins = 8,
72} 59 .win_cfg_base = win_cfg_base,
73 60};
74static void __init setup_cpu_win(int win, u32 base, u32 size,
75 u8 target, u8 attr, int remap)
76{
77 void __iomem *addr = win_cfg_base(win);
78 u32 ctrl;
79
80 base &= 0xffff0000;
81 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
82
83 writel(base, addr + WIN_BASE_OFF);
84 writel(ctrl, addr + WIN_CTRL_OFF);
85 if (cpu_win_can_remap(win)) {
86 if (remap < 0)
87 remap = base;
88
89 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93 61
94void __init mv78xx0_setup_cpu_mbus(void) 62void __init mv78xx0_setup_cpu_mbus(void)
95{ 63{
96 void __iomem *addr;
97 int i;
98 int cs;
99
100 /* 64 /*
101 * First, disable and clear windows. 65 * Disable, clear and configure windows.
102 */ 66 */
103 for (i = 0; i < 14; i++) { 67 orion_config_wins(&addr_map_cfg, NULL);
104 addr = win_cfg_base(i);
105
106 writel(0, addr + WIN_BASE_OFF);
107 writel(0, addr + WIN_CTRL_OFF);
108 if (cpu_win_can_remap(i)) {
109 writel(0, addr + WIN_REMAP_LO_OFF);
110 writel(0, addr + WIN_REMAP_HI_OFF);
111 }
112 }
113 68
114 /* 69 /*
115 * Setup MBUS dram target info. 70 * Setup MBUS dram target info.
116 */ 71 */
117 mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
118
119 if (mv78xx0_core_index() == 0) 72 if (mv78xx0_core_index() == 0)
120 addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; 73 orion_setup_cpu_mbus_target(&addr_map_cfg,
74 DDR_WINDOW_CPU0_BASE);
121 else 75 else
122 addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; 76 orion_setup_cpu_mbus_target(&addr_map_cfg,
123 77 DDR_WINDOW_CPU1_BASE);
124 for (i = 0, cs = 0; i < 4; i++) {
125 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
126 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
127
128 /*
129 * Chip select enabled?
130 */
131 if (size & 1) {
132 struct mbus_dram_window *w;
133
134 w = &mv78xx0_mbus_dram_info.cs[cs++];
135 w->cs_index = i;
136 w->mbus_attr = 0xf & ~(1 << i);
137 w->base = base & 0xffff0000;
138 w->size = (size | 0x0000ffff) + 1;
139 }
140 }
141 mv78xx0_mbus_dram_info.num_cs = cs;
142} 78}
143 79
144void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 80void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
145 int maj, int min) 81 int maj, int min)
146{ 82{
147 setup_cpu_win(window, base, size, TARGET_PCIE(maj), 83 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
148 ATTR_PCIE_IO(min), -1); 84 TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
149} 85}
150 86
151void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, 87void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
152 int maj, int min) 88 int maj, int min)
153{ 89{
154 setup_cpu_win(window, base, size, TARGET_PCIE(maj), 90 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
155 ATTR_PCIE_MEM(min), -1); 91 TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
156} 92}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 5b9632b01169..0cdd41004ad0 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -12,7 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
17#include <linux/ethtool.h> 16#include <linux/ethtool.h>
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
@@ -23,6 +22,7 @@
23#include <plat/orion_nand.h> 22#include <plat/orion_nand.h>
24#include <plat/time.h> 23#include <plat/time.h>
25#include <plat/common.h> 24#include <plat/common.h>
25#include <plat/addr-map.h>
26#include "common.h" 26#include "common.h"
27 27
28static int get_tclk(void); 28static int get_tclk(void);
@@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void)
169 ****************************************************************************/ 169 ****************************************************************************/
170void __init mv78xx0_ehci0_init(void) 170void __init mv78xx0_ehci0_init(void)
171{ 171{
172 orion_ehci_init(&mv78xx0_mbus_dram_info, 172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
173 USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
174} 173}
175 174
176 175
@@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void)
179 ****************************************************************************/ 178 ****************************************************************************/
180void __init mv78xx0_ehci1_init(void) 179void __init mv78xx0_ehci1_init(void)
181{ 180{
182 orion_ehci_1_init(&mv78xx0_mbus_dram_info, 181 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
183 USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
184} 182}
185 183
186 184
@@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void)
189 ****************************************************************************/ 187 ****************************************************************************/
190void __init mv78xx0_ehci2_init(void) 188void __init mv78xx0_ehci2_init(void)
191{ 189{
192 orion_ehci_2_init(&mv78xx0_mbus_dram_info, 190 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
193 USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
194} 191}
195 192
196 193
@@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void)
199 ****************************************************************************/ 196 ****************************************************************************/
200void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 197void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
201{ 198{
202 orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, 199 orion_ge00_init(eth_data,
203 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 200 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
204 IRQ_MV78XX0_GE_ERR, get_tclk()); 201 IRQ_MV78XX0_GE_ERR, get_tclk());
205} 202}
@@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
210 ****************************************************************************/ 207 ****************************************************************************/
211void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 208void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
212{ 209{
213 orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, 210 orion_ge01_init(eth_data,
214 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 211 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
215 NO_IRQ, get_tclk()); 212 NO_IRQ, get_tclk());
216} 213}
@@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
234 eth_data->duplex = DUPLEX_FULL; 231 eth_data->duplex = DUPLEX_FULL;
235 } 232 }
236 233
237 orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, 234 orion_ge10_init(eth_data,
238 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 235 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
239 NO_IRQ, get_tclk()); 236 NO_IRQ, get_tclk());
240} 237}
@@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
258 eth_data->duplex = DUPLEX_FULL; 255 eth_data->duplex = DUPLEX_FULL;
259 } 256 }
260 257
261 orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, 258 orion_ge11_init(eth_data,
262 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 259 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
263 NO_IRQ, get_tclk()); 260 NO_IRQ, get_tclk());
264} 261}
@@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void)
277 ****************************************************************************/ 274 ****************************************************************************/
278void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 275void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
279{ 276{
280 orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, 277 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
281 SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
282} 278}
283 279
284 280
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 07d5f8f6be7d..507c767d49e0 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -23,7 +23,6 @@ void mv78xx0_init(void);
23void mv78xx0_init_early(void); 23void mv78xx0_init_early(void);
24void mv78xx0_init_irq(void); 24void mv78xx0_init_irq(void);
25 25
26extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
27void mv78xx0_setup_cpu_mbus(void); 26void mv78xx0_setup_cpu_mbus(void);
28void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 27void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
29 int maj, int min); 28 int maj, int min);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index cf4e494d44bf..df50342179e2 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -10,7 +10,6 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <plat/mpp.h> 14#include <plat/mpp.h>
16#include <mach/hardware.h> 15#include <mach/hardware.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index c51af1cac300..12fcb108b0e1 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <video/vga.h> 13#include <video/vga.h>
15#include <asm/irq.h> 14#include <asm/irq.h>
16#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
17#include <plat/pcie.h> 16#include <plat/pcie.h>
17#include <plat/addr-map.h>
18#include "common.h" 18#include "common.h"
19 19
20struct pcie_port { 20struct pcie_port {
@@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
153 * Generic PCIe unit setup. 153 * Generic PCIe unit setup.
154 */ 154 */
155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
156 orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); 156 orion_pcie_setup(pp->base);
157 157
158 sys->resource[0] = &pp->res[0]; 158 sys->resource[0] = &pp->res[0];
159 sys->resource[1] = &pp->res[1]; 159 sys->resource[1] = &pp->res[1];
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 73f287d6429b..4f8d66f044e7 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC
168 custom OMAP boards. Say Y here if you have a custom 168 custom OMAP boards. Say Y here if you have a custom
169 board. 169 board.
170 170
171comment "OMAP CPU Speed"
172 depends on ARCH_OMAP1
173
174config OMAP_ARM_216MHZ
175 bool "OMAP ARM 216 MHz CPU (1710 only)"
176 depends on ARCH_OMAP1 && ARCH_OMAP16XX
177 help
178 Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
179
180config OMAP_ARM_195MHZ
181 bool "OMAP ARM 195 MHz CPU"
182 depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
183 help
184 Enable 195MHz clock for OMAP CPU. If unsure, say N.
185
186config OMAP_ARM_192MHZ
187 bool "OMAP ARM 192 MHz CPU"
188 depends on ARCH_OMAP1 && ARCH_OMAP16XX
189 help
190 Enable 192MHz clock for OMAP CPU. If unsure, say N.
191
192config OMAP_ARM_182MHZ
193 bool "OMAP ARM 182 MHz CPU"
194 depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
195 help
196 Enable 182MHz clock for OMAP CPU. If unsure, say N.
197
198config OMAP_ARM_168MHZ
199 bool "OMAP ARM 168 MHz CPU"
200 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
201 help
202 Enable 168MHz clock for OMAP CPU. If unsure, say N.
203
204config OMAP_ARM_150MHZ
205 bool "OMAP ARM 150 MHz CPU"
206 depends on ARCH_OMAP1 && ARCH_OMAP15XX
207 help
208 Enable 150MHz clock for OMAP CPU. If unsure, say N.
209
210config OMAP_ARM_120MHZ
211 bool "OMAP ARM 120 MHz CPU"
212 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
213 help
214 Enable 120MHz clock for OMAP CPU. If unsure, say N.
215
216config OMAP_ARM_96MHZ
217 bool "OMAP ARM 96 MHz CPU"
218 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
219 help
220 Enable 96MHz clock for OMAP CPU. If unsure, say N.
221
222config OMAP_ARM_60MHZ
223 bool "OMAP ARM 60 MHz CPU"
224 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
225 default y
226 help
227 Enable 60MHz clock for OMAP CPU. If unsure, say Y.
228
229config OMAP_ARM_30MHZ
230 bool "OMAP ARM 30 MHz CPU"
231 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
232 help
233 Enable 30MHz clock for OMAP CPU. If unsure, say N.
234
235endmenu 171endmenu
236 172
237endif 173endif
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 84ef70476b51..0c50df05d135 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
197 ref_rate = ck_ref_p->rate; 197 ref_rate = ck_ref_p->rate;
198 198
199 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 199 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
200 if (ptr->xtal != ref_rate) 200 if (!(ptr->flags & cpu_mask))
201 continue; 201 continue;
202 202
203 /* DPLL1 cannot be reprogrammed without risking system crash */ 203 if (ptr->xtal != ref_rate)
204 if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
205 continue; 204 continue;
206 205
207 /* Can check only after xtal frequency check */ 206 /* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
215 /* 214 /*
216 * In most cases we should not need to reprogram DPLL. 215 * In most cases we should not need to reprogram DPLL.
217 * Reprogramming the DPLL is tricky, it must be done from SRAM. 216 * Reprogramming the DPLL is tricky, it must be done from SRAM.
218 * (on 730, bit 13 must always be 1)
219 */ 217 */
220 if (cpu_is_omap7xx()) 218 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
221 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
222 else
223 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
224 219
225 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ 220 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
226 ck_dpll1_p->rate = ptr->pll_rate; 221 ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
290 highest_rate = -EINVAL; 285 highest_rate = -EINVAL;
291 286
292 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 287 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
288 if (!(ptr->flags & cpu_mask))
289 continue;
290
293 if (ptr->xtal != ref_rate) 291 if (ptr->xtal != ref_rate)
294 continue; 292 continue;
295 293
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 16b1423b454a..3d04f4f67676 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy;
111extern const struct clkops clkops_uart_16xx; 111extern const struct clkops clkops_uart_16xx;
112extern const struct clkops clkops_generic; 112extern const struct clkops clkops_generic;
113 113
114/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
115extern u32 cpu_mask;
116
114#endif 117#endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9ff90a744a21..94699a82a734 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,6 +25,7 @@
25#include <plat/clock.h> 25#include <plat/clock.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27#include <plat/clkdev_omap.h> 27#include <plat/clkdev_omap.h>
28#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
28#include <plat/usb.h> /* for OTG_BASE */ 29#include <plat/usb.h> /* for OTG_BASE */
29 30
30#include "clock.h" 31#include "clock.h"
@@ -778,12 +779,14 @@ static void __init omap1_show_rates(void)
778 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 779 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
779} 780}
780 781
782u32 cpu_mask;
783
781int __init omap1_clk_init(void) 784int __init omap1_clk_init(void)
782{ 785{
783 struct omap_clk *c; 786 struct omap_clk *c;
784 const struct omap_clock_config *info; 787 const struct omap_clock_config *info;
785 int crystal_type = 0; /* Default 12 MHz */ 788 int crystal_type = 0; /* Default 12 MHz */
786 u32 reg, cpu_mask; 789 u32 reg;
787 790
788#ifdef CONFIG_DEBUG_LL 791#ifdef CONFIG_DEBUG_LL
789 /* 792 /*
@@ -808,6 +811,8 @@ int __init omap1_clk_init(void)
808 clk_preinit(c->lk.clk); 811 clk_preinit(c->lk.clk);
809 812
810 cpu_mask = 0; 813 cpu_mask = 0;
814 if (cpu_is_omap1710())
815 cpu_mask |= CK_1710;
811 if (cpu_is_omap16xx()) 816 if (cpu_is_omap16xx())
812 cpu_mask |= CK_16XX; 817 cpu_mask |= CK_16XX;
813 if (cpu_is_omap1510()) 818 if (cpu_is_omap1510())
@@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void)
931{ 936{
932 unsigned long rate = ck_dpll1.rate; 937 unsigned long rate = ck_dpll1.rate;
933 938
934 if (rate >= OMAP1_DPLL1_SANE_VALUE)
935 return;
936
937 /* System booting at unusable rate, force reprogramming of DPLL1 */
938 ck_dpll1_p->rate = 0;
939
940 /* Find the highest supported frequency and enable it */ 939 /* Find the highest supported frequency and enable it */
941 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 940 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
942 pr_err("System frequencies not set, using default. Check your config.\n"); 941 pr_err("System frequencies not set, using default. Check your config.\n");
943 omap_writew(0x2290, DPLL_CTL); 942 /*
944 omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); 943 * Reprogramming the DPLL is tricky, it must be done from SRAM.
944 */
945 omap_sram_reprogram_clock(0x2290, 0x0005);
945 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; 946 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
946 } 947 }
947 propagate_rate(&ck_dpll1); 948 propagate_rate(&ck_dpll1);
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
index 07074d79adce..79a683864a5c 100644
--- a/arch/arm/mach-omap1/opp.h
+++ b/arch/arm/mach-omap1/opp.h
@@ -21,6 +21,7 @@ struct mpu_rate {
21 unsigned long pll_rate; 21 unsigned long pll_rate;
22 __u16 ckctl_val; 22 __u16 ckctl_val;
23 __u16 dpllctl_val; 23 __u16 dpllctl_val;
24 u32 flags;
24}; 25};
25 26
26extern struct mpu_rate omap1_rate_table[]; 27extern struct mpu_rate omap1_rate_table[];
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 75a546514994..9cd4ddb51397 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#include <plat/clkdev_omap.h>
13#include "opp.h" 14#include "opp.h"
14 15
15/*------------------------------------------------------------------------- 16/*-------------------------------------------------------------------------
@@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = {
20 * NOTE: Comment order here is different from bits in CKCTL value: 21 * NOTE: Comment order here is different from bits in CKCTL value:
21 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv 22 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
22 */ 23 */
23#if defined(CONFIG_OMAP_ARM_216MHZ) 24 { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
24 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ 25 CK_1710 },
25#endif 26 { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
26#if defined(CONFIG_OMAP_ARM_195MHZ) 27 CK_7XX },
27 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ 28 { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
28#endif 29 CK_16XX },
29#if defined(CONFIG_OMAP_ARM_192MHZ) 30 { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
30 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ 31 CK_16XX },
31 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ 32 { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
32 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ 33 CK_16XX },
33 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ 34 { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
34 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ 35 CK_16XX },
35#endif 36 { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
36#if defined(CONFIG_OMAP_ARM_182MHZ) 37 CK_16XX },
37 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ 38 { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
38#endif 39 CK_7XX },
39#if defined(CONFIG_OMAP_ARM_168MHZ) 40 { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
40 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ 41 CK_16XX|CK_7XX },
41#endif 42 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
42#if defined(CONFIG_OMAP_ARM_150MHZ) 43 CK_1510 },
43 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ 44 { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
44#endif 45 CK_16XX|CK_1510|CK_310|CK_7XX },
45#if defined(CONFIG_OMAP_ARM_120MHZ) 46 { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
46 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ 47 CK_16XX|CK_1510|CK_310|CK_7XX },
47#endif 48 { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
48#if defined(CONFIG_OMAP_ARM_96MHZ) 49 CK_16XX|CK_1510|CK_310|CK_7XX },
49 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ 50 { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
50#endif 51 CK_16XX|CK_1510|CK_310|CK_7XX },
51#if defined(CONFIG_OMAP_ARM_60MHZ)
52 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
53#endif
54#if defined(CONFIG_OMAP_ARM_30MHZ)
55 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
56#endif
57 { 0, 0, 0, 0, 0 }, 52 { 0, 0, 0, 0, 0 },
58}; 53};
59 54
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 60424f41156b..039cadf84c11 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2480,6 +2480,16 @@ static struct clk uart4_fck = {
2480 .recalc = &followparent_recalc, 2480 .recalc = &followparent_recalc,
2481}; 2481};
2482 2482
2483static struct clk uart4_fck_am35xx = {
2484 .name = "uart4_fck",
2485 .ops = &clkops_omap2_dflt_wait,
2486 .parent = &per_48m_fck,
2487 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2488 .enable_bit = OMAP3430_EN_UART4_SHIFT,
2489 .clkdm_name = "core_l4_clkdm",
2490 .recalc = &followparent_recalc,
2491};
2492
2483static struct clk gpt2_fck = { 2493static struct clk gpt2_fck = {
2484 .name = "gpt2_fck", 2494 .name = "gpt2_fck",
2485 .ops = &clkops_omap2_dflt_wait, 2495 .ops = &clkops_omap2_dflt_wait,
@@ -3403,6 +3413,7 @@ static struct omap_clk omap3xxx_clks[] = {
3403 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3413 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3404 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3414 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3405 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), 3415 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3416 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517),
3406 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), 3417 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3407 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), 3418 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3408 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), 3419 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 126cb49c0de7..5324e8d93bc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp5_hwmod; 84static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; 85static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; 86static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
88static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
87 89
88/* L3 -> L4_CORE interface */ 90/* L3 -> L4_CORE interface */
89static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 91static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
164static struct omap_hwmod omap3xxx_uart2_hwmod; 166static struct omap_hwmod omap3xxx_uart2_hwmod;
165static struct omap_hwmod omap3xxx_uart3_hwmod; 167static struct omap_hwmod omap3xxx_uart3_hwmod;
166static struct omap_hwmod omap3xxx_uart4_hwmod; 168static struct omap_hwmod omap3xxx_uart4_hwmod;
169static struct omap_hwmod am35xx_uart4_hwmod;
167static struct omap_hwmod omap3xxx_usbhsotg_hwmod; 170static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
168 171
169/* l3_core -> usbhsotg interface */ 172/* l3_core -> usbhsotg interface */
@@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .user = OCP_USER_MPU | OCP_USER_SDMA, 302 .user = OCP_USER_MPU | OCP_USER_SDMA,
300}; 303};
301 304
305/* AM35xx: L4 CORE -> UART4 interface */
306static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
307 {
308 .pa_start = OMAP3_UART4_AM35XX_BASE,
309 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
310 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
311 },
312};
313
314static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
315 .master = &omap3xxx_l4_core_hwmod,
316 .slave = &am35xx_uart4_hwmod,
317 .clk = "uart4_ick",
318 .addr = am35xx_uart4_addr_space,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
320};
321
302/* L4 CORE -> I2C1 interface */ 322/* L4 CORE -> I2C1 interface */
303static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 323static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
304 .master = &omap3xxx_l4_core_hwmod, 324 .master = &omap3xxx_l4_core_hwmod,
@@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1162 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1182 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1183 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1185 .clockact = CLOCKACT_TEST_ICLK,
1165 .sysc_fields = &omap_hwmod_sysc_type1, 1186 .sysc_fields = &omap_hwmod_sysc_type1,
1166}; 1187};
1167 1188
@@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1309 .class = &omap2_uart_class, 1330 .class = &omap2_uart_class,
1310}; 1331};
1311 1332
1333static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
1334 { .irq = INT_35XX_UART4_IRQ, },
1335};
1336
1337static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1338 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
1339 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1340};
1341
1342static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1343 &am35xx_l4_core__uart4,
1344};
1345
1346static struct omap_hwmod am35xx_uart4_hwmod = {
1347 .name = "uart4",
1348 .mpu_irqs = am35xx_uart4_mpu_irqs,
1349 .sdma_reqs = am35xx_uart4_sdma_reqs,
1350 .main_clk = "uart4_fck",
1351 .prcm = {
1352 .omap2 = {
1353 .module_offs = CORE_MOD,
1354 .prcm_reg_id = 1,
1355 .module_bit = OMAP3430_EN_UART4_SHIFT,
1356 .idlest_reg_id = 1,
1357 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1358 },
1359 },
1360 .slaves = am35xx_uart4_slaves,
1361 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1362 .class = &omap2_uart_class,
1363};
1364
1365
1312static struct omap_hwmod_class i2c_class = { 1366static struct omap_hwmod_class i2c_class = {
1313 .name = "i2c", 1367 .name = "i2c",
1314 .sysc = &i2c_sysc, 1368 .sysc = &i2c_sysc,
@@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1636 1690
1637static struct omap_hwmod omap3xxx_i2c1_hwmod = { 1691static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1638 .name = "i2c1", 1692 .name = "i2c1",
1639 .flags = HWMOD_16BIT_REG, 1693 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1640 .mpu_irqs = omap2_i2c1_mpu_irqs, 1694 .mpu_irqs = omap2_i2c1_mpu_irqs,
1641 .sdma_reqs = omap2_i2c1_sdma_reqs, 1695 .sdma_reqs = omap2_i2c1_sdma_reqs,
1642 .main_clk = "i2c1_fck", 1696 .main_clk = "i2c1_fck",
@@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1670 1724
1671static struct omap_hwmod omap3xxx_i2c2_hwmod = { 1725static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1672 .name = "i2c2", 1726 .name = "i2c2",
1673 .flags = HWMOD_16BIT_REG, 1727 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1674 .mpu_irqs = omap2_i2c2_mpu_irqs, 1728 .mpu_irqs = omap2_i2c2_mpu_irqs,
1675 .sdma_reqs = omap2_i2c2_sdma_reqs, 1729 .sdma_reqs = omap2_i2c2_sdma_reqs,
1676 .main_clk = "i2c2_fck", 1730 .main_clk = "i2c2_fck",
@@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1715 1769
1716static struct omap_hwmod omap3xxx_i2c3_hwmod = { 1770static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1717 .name = "i2c3", 1771 .name = "i2c3",
1718 .flags = HWMOD_16BIT_REG, 1772 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1719 .mpu_irqs = i2c3_mpu_irqs, 1773 .mpu_irqs = i2c3_mpu_irqs,
1720 .sdma_reqs = i2c3_sdma_reqs, 1774 .sdma_reqs = i2c3_sdma_reqs,
1721 .main_clk = "i2c3_fck", 1775 .main_clk = "i2c3_fck",
@@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
3072 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 3126 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3073}; 3127};
3074 3128
3075static struct omap_hwmod omap3xxx_mmc1_hwmod = { 3129/* See 35xx errata 2.1.1.128 in SPRZ278F */
3130static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3131 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3132 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3133};
3134
3135static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3136 .name = "mmc1",
3137 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3138 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3139 .opt_clks = omap34xx_mmc1_opt_clks,
3140 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3141 .main_clk = "mmchs1_fck",
3142 .prcm = {
3143 .omap2 = {
3144 .module_offs = CORE_MOD,
3145 .prcm_reg_id = 1,
3146 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3147 .idlest_reg_id = 1,
3148 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3149 },
3150 },
3151 .dev_attr = &mmc1_pre_es3_dev_attr,
3152 .slaves = omap3xxx_mmc1_slaves,
3153 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3154 .class = &omap34xx_mmc_class,
3155};
3156
3157static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3076 .name = "mmc1", 3158 .name = "mmc1",
3077 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3159 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3078 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3160 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
@@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3115 &omap3xxx_l4_core__mmc2, 3197 &omap3xxx_l4_core__mmc2,
3116}; 3198};
3117 3199
3118static struct omap_hwmod omap3xxx_mmc2_hwmod = { 3200/* See 35xx errata 2.1.1.128 in SPRZ278F */
3201static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3202 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3203};
3204
3205static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3206 .name = "mmc2",
3207 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3208 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3209 .opt_clks = omap34xx_mmc2_opt_clks,
3210 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3211 .main_clk = "mmchs2_fck",
3212 .prcm = {
3213 .omap2 = {
3214 .module_offs = CORE_MOD,
3215 .prcm_reg_id = 1,
3216 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3217 .idlest_reg_id = 1,
3218 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3219 },
3220 },
3221 .dev_attr = &mmc2_pre_es3_dev_attr,
3222 .slaves = omap3xxx_mmc2_slaves,
3223 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3224 .class = &omap34xx_mmc_class,
3225};
3226
3227static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3119 .name = "mmc2", 3228 .name = "mmc2",
3120 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3229 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3121 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3230 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
@@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3177 .class = &omap34xx_mmc_class, 3286 .class = &omap34xx_mmc_class,
3178}; 3287};
3179 3288
3289/*
3290 * 'usb_host_hs' class
3291 * high-speed multi-port usb host controller
3292 */
3293static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3294 .master = &omap3xxx_usb_host_hs_hwmod,
3295 .slave = &omap3xxx_l3_main_hwmod,
3296 .clk = "core_l3_ick",
3297 .user = OCP_USER_MPU,
3298};
3299
3300static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3301 .rev_offs = 0x0000,
3302 .sysc_offs = 0x0010,
3303 .syss_offs = 0x0014,
3304 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
3305 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
3306 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3308 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3309 .sysc_fields = &omap_hwmod_sysc_type1,
3310};
3311
3312static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3313 .name = "usb_host_hs",
3314 .sysc = &omap3xxx_usb_host_hs_sysc,
3315};
3316
3317static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3318 &omap3xxx_usb_host_hs__l3_main_2,
3319};
3320
3321static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3322 {
3323 .name = "uhh",
3324 .pa_start = 0x48064000,
3325 .pa_end = 0x480643ff,
3326 .flags = ADDR_TYPE_RT
3327 },
3328 {
3329 .name = "ohci",
3330 .pa_start = 0x48064400,
3331 .pa_end = 0x480647ff,
3332 },
3333 {
3334 .name = "ehci",
3335 .pa_start = 0x48064800,
3336 .pa_end = 0x48064cff,
3337 },
3338 {}
3339};
3340
3341static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3342 .master = &omap3xxx_l4_core_hwmod,
3343 .slave = &omap3xxx_usb_host_hs_hwmod,
3344 .clk = "usbhost_ick",
3345 .addr = omap3xxx_usb_host_hs_addrs,
3346 .user = OCP_USER_MPU | OCP_USER_SDMA,
3347};
3348
3349static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3350 &omap3xxx_l4_core__usb_host_hs,
3351};
3352
3353static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3354 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3355};
3356
3357static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
3358 { .name = "ohci-irq", .irq = 76 },
3359 { .name = "ehci-irq", .irq = 77 },
3360 { .irq = -1 }
3361};
3362
3363static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3364 .name = "usb_host_hs",
3365 .class = &omap3xxx_usb_host_hs_hwmod_class,
3366 .clkdm_name = "l3_init_clkdm",
3367 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
3368 .main_clk = "usbhost_48m_fck",
3369 .prcm = {
3370 .omap2 = {
3371 .module_offs = OMAP3430ES2_USBHOST_MOD,
3372 .prcm_reg_id = 1,
3373 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3374 .idlest_reg_id = 1,
3375 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
3376 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
3377 },
3378 },
3379 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3380 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3381 .slaves = omap3xxx_usb_host_hs_slaves,
3382 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3383 .masters = omap3xxx_usb_host_hs_masters,
3384 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3385
3386 /*
3387 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3388 * id: i660
3389 *
3390 * Description:
3391 * In the following configuration :
3392 * - USBHOST module is set to smart-idle mode
3393 * - PRCM asserts idle_req to the USBHOST module ( This typically
3394 * happens when the system is going to a low power mode : all ports
3395 * have been suspended, the master part of the USBHOST module has
3396 * entered the standby state, and SW has cut the functional clocks)
3397 * - an USBHOST interrupt occurs before the module is able to answer
3398 * idle_ack, typically a remote wakeup IRQ.
3399 * Then the USB HOST module will enter a deadlock situation where it
3400 * is no more accessible nor functional.
3401 *
3402 * Workaround:
3403 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3404 */
3405
3406 /*
3407 * Errata: USB host EHCI may stall when entering smart-standby mode
3408 * Id: i571
3409 *
3410 * Description:
3411 * When the USBHOST module is set to smart-standby mode, and when it is
3412 * ready to enter the standby state (i.e. all ports are suspended and
3413 * all attached devices are in suspend mode), then it can wrongly assert
3414 * the Mstandby signal too early while there are still some residual OCP
3415 * transactions ongoing. If this condition occurs, the internal state
3416 * machine may go to an undefined state and the USB link may be stuck
3417 * upon the next resume.
3418 *
3419 * Workaround:
3420 * Don't use smart standby; use only force standby,
3421 * hence HWMOD_SWSUP_MSTANDBY
3422 */
3423
3424 /*
3425 * During system boot; If the hwmod framework resets the module
3426 * the module will have smart idle settings; which can lead to deadlock
3427 * (above Errata Id:i660); so, dont reset the module during boot;
3428 * Use HWMOD_INIT_NO_RESET.
3429 */
3430
3431 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3432 HWMOD_INIT_NO_RESET,
3433};
3434
3435/*
3436 * 'usb_tll_hs' class
3437 * usb_tll_hs module is the adapter on the usb_host_hs ports
3438 */
3439static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
3440 .rev_offs = 0x0000,
3441 .sysc_offs = 0x0010,
3442 .syss_offs = 0x0014,
3443 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3444 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3445 SYSC_HAS_AUTOIDLE),
3446 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3447 .sysc_fields = &omap_hwmod_sysc_type1,
3448};
3449
3450static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
3451 .name = "usb_tll_hs",
3452 .sysc = &omap3xxx_usb_tll_hs_sysc,
3453};
3454
3455static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3456 { .name = "tll-irq", .irq = 78 },
3457 { .irq = -1 }
3458};
3459
3460static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3461 {
3462 .name = "tll",
3463 .pa_start = 0x48062000,
3464 .pa_end = 0x48062fff,
3465 .flags = ADDR_TYPE_RT
3466 },
3467 {}
3468};
3469
3470static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3471 .master = &omap3xxx_l4_core_hwmod,
3472 .slave = &omap3xxx_usb_tll_hs_hwmod,
3473 .clk = "usbtll_ick",
3474 .addr = omap3xxx_usb_tll_hs_addrs,
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3476};
3477
3478static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
3479 &omap3xxx_l4_core__usb_tll_hs,
3480};
3481
3482static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3483 .name = "usb_tll_hs",
3484 .class = &omap3xxx_usb_tll_hs_hwmod_class,
3485 .clkdm_name = "l3_init_clkdm",
3486 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
3487 .main_clk = "usbtll_fck",
3488 .prcm = {
3489 .omap2 = {
3490 .module_offs = CORE_MOD,
3491 .prcm_reg_id = 3,
3492 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3493 .idlest_reg_id = 3,
3494 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3495 },
3496 },
3497 .slaves = omap3xxx_usb_tll_hs_slaves,
3498 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
3499};
3500
3180static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 3501static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3181 &omap3xxx_l3_main_hwmod, 3502 &omap3xxx_l3_main_hwmod,
3182 &omap3xxx_l4_core_hwmod, 3503 &omap3xxx_l4_core_hwmod,
3183 &omap3xxx_l4_per_hwmod, 3504 &omap3xxx_l4_per_hwmod,
3184 &omap3xxx_l4_wkup_hwmod, 3505 &omap3xxx_l4_wkup_hwmod,
3185 &omap3xxx_mmc1_hwmod,
3186 &omap3xxx_mmc2_hwmod,
3187 &omap3xxx_mmc3_hwmod, 3506 &omap3xxx_mmc3_hwmod,
3188 &omap3xxx_mpu_hwmod, 3507 &omap3xxx_mpu_hwmod,
3189 3508
@@ -3203,6 +3522,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3203 &omap3xxx_uart1_hwmod, 3522 &omap3xxx_uart1_hwmod,
3204 &omap3xxx_uart2_hwmod, 3523 &omap3xxx_uart2_hwmod,
3205 &omap3xxx_uart3_hwmod, 3524 &omap3xxx_uart3_hwmod,
3525
3206 /* dss class */ 3526 /* dss class */
3207 &omap3xxx_dss_dispc_hwmod, 3527 &omap3xxx_dss_dispc_hwmod,
3208 &omap3xxx_dss_dsi1_hwmod, 3528 &omap3xxx_dss_dsi1_hwmod,
@@ -3260,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3260static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { 3580static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3261 &omap3xxx_dss_core_hwmod, 3581 &omap3xxx_dss_core_hwmod,
3262 &omap3xxx_usbhsotg_hwmod, 3582 &omap3xxx_usbhsotg_hwmod,
3583 &omap3xxx_usb_host_hs_hwmod,
3584 &omap3xxx_usb_tll_hs_hwmod,
3585 NULL
3586};
3587
3588/* <= 3430ES3-only hwmods */
3589static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3590 &omap3xxx_pre_es3_mmc1_hwmod,
3591 &omap3xxx_pre_es3_mmc2_hwmod,
3592 NULL
3593};
3594
3595/* 3430ES3+-only hwmods */
3596static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3597 &omap3xxx_es3plus_mmc1_hwmod,
3598 &omap3xxx_es3plus_mmc2_hwmod,
3263 NULL 3599 NULL
3264}; 3600};
3265 3601
@@ -3281,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3281 &omap36xx_sr2_hwmod, 3617 &omap36xx_sr2_hwmod,
3282 &omap3xxx_usbhsotg_hwmod, 3618 &omap3xxx_usbhsotg_hwmod,
3283 &omap3xxx_mailbox_hwmod, 3619 &omap3xxx_mailbox_hwmod,
3620 &omap3xxx_usb_host_hs_hwmod,
3621 &omap3xxx_usb_tll_hs_hwmod,
3622 &omap3xxx_es3plus_mmc1_hwmod,
3623 &omap3xxx_es3plus_mmc2_hwmod,
3284 NULL 3624 NULL
3285}; 3625};
3286 3626
3287static __initdata struct omap_hwmod *am35xx_hwmods[] = { 3627static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3288 &omap3xxx_dss_core_hwmod, /* XXX ??? */ 3628 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3289 &am35xx_usbhsotg_hwmod, 3629 &am35xx_usbhsotg_hwmod,
3630 &am35xx_uart4_hwmod,
3631 &omap3xxx_usb_host_hs_hwmod,
3632 &omap3xxx_usb_tll_hs_hwmod,
3633 &omap3xxx_es3plus_mmc1_hwmod,
3634 &omap3xxx_es3plus_mmc2_hwmod,
3290 NULL 3635 NULL
3291}; 3636};
3292 3637
@@ -3346,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void)
3346 h = omap3430es2plus_hwmods; 3691 h = omap3430es2plus_hwmods;
3347 }; 3692 };
3348 3693
3694 if (h) {
3695 r = omap_hwmod_register(h);
3696 if (r < 0)
3697 return r;
3698 }
3699
3700 h = NULL;
3701 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3702 rev == OMAP3430_REV_ES2_1) {
3703 h = omap3430_pre_es3_hwmods;
3704 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3705 rev == OMAP3430_REV_ES3_1_2) {
3706 h = omap3430_es3plus_hwmods;
3707 };
3708
3349 if (h) 3709 if (h)
3350 r = omap_hwmod_register(h); 3710 r = omap_hwmod_register(h);
3351 3711
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index daaf165af696..f9f151081760 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -70,6 +70,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod;
70static struct omap_hwmod omap44xx_mpu_hwmod; 70static struct omap_hwmod omap44xx_mpu_hwmod;
71static struct omap_hwmod omap44xx_mpu_private_hwmod; 71static struct omap_hwmod omap44xx_mpu_private_hwmod;
72static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; 72static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
73 75
74/* 76/*
75 * Interconnects omap_hwmod structures 77 * Interconnects omap_hwmod structures
@@ -2246,6 +2248,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2246 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2248 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2247 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2249 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2248 SIDLE_SMART_WKUP), 2250 SIDLE_SMART_WKUP),
2251 .clockact = CLOCKACT_TEST_ICLK,
2249 .sysc_fields = &omap_hwmod_sysc_type1, 2252 .sysc_fields = &omap_hwmod_sysc_type1,
2250}; 2253};
2251 2254
@@ -2300,7 +2303,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2300 .name = "i2c1", 2303 .name = "i2c1",
2301 .class = &omap44xx_i2c_hwmod_class, 2304 .class = &omap44xx_i2c_hwmod_class,
2302 .clkdm_name = "l4_per_clkdm", 2305 .clkdm_name = "l4_per_clkdm",
2303 .flags = HWMOD_16BIT_REG, 2306 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2304 .mpu_irqs = omap44xx_i2c1_irqs, 2307 .mpu_irqs = omap44xx_i2c1_irqs,
2305 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 2308 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2306 .main_clk = "i2c1_fck", 2309 .main_clk = "i2c1_fck",
@@ -2356,7 +2359,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2356 .name = "i2c2", 2359 .name = "i2c2",
2357 .class = &omap44xx_i2c_hwmod_class, 2360 .class = &omap44xx_i2c_hwmod_class,
2358 .clkdm_name = "l4_per_clkdm", 2361 .clkdm_name = "l4_per_clkdm",
2359 .flags = HWMOD_16BIT_REG, 2362 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2360 .mpu_irqs = omap44xx_i2c2_irqs, 2363 .mpu_irqs = omap44xx_i2c2_irqs,
2361 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 2364 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2362 .main_clk = "i2c2_fck", 2365 .main_clk = "i2c2_fck",
@@ -2412,7 +2415,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2412 .name = "i2c3", 2415 .name = "i2c3",
2413 .class = &omap44xx_i2c_hwmod_class, 2416 .class = &omap44xx_i2c_hwmod_class,
2414 .clkdm_name = "l4_per_clkdm", 2417 .clkdm_name = "l4_per_clkdm",
2415 .flags = HWMOD_16BIT_REG, 2418 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2416 .mpu_irqs = omap44xx_i2c3_irqs, 2419 .mpu_irqs = omap44xx_i2c3_irqs,
2417 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 2420 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2418 .main_clk = "i2c3_fck", 2421 .main_clk = "i2c3_fck",
@@ -2468,7 +2471,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
2468 .name = "i2c4", 2471 .name = "i2c4",
2469 .class = &omap44xx_i2c_hwmod_class, 2472 .class = &omap44xx_i2c_hwmod_class,
2470 .clkdm_name = "l4_per_clkdm", 2473 .clkdm_name = "l4_per_clkdm",
2471 .flags = HWMOD_16BIT_REG, 2474 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2472 .mpu_irqs = omap44xx_i2c4_irqs, 2475 .mpu_irqs = omap44xx_i2c4_irqs,
2473 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 2476 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2474 .main_clk = "i2c4_fck", 2477 .main_clk = "i2c4_fck",
@@ -5276,6 +5279,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5276 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), 5279 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5277}; 5280};
5278 5281
5282/*
5283 * 'usb_host_hs' class
5284 * high-speed multi-port usb host controller
5285 */
5286static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5287 .master = &omap44xx_usb_host_hs_hwmod,
5288 .slave = &omap44xx_l3_main_2_hwmod,
5289 .clk = "l3_div_ck",
5290 .user = OCP_USER_MPU | OCP_USER_SDMA,
5291};
5292
5293static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5294 .rev_offs = 0x0000,
5295 .sysc_offs = 0x0010,
5296 .syss_offs = 0x0014,
5297 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5298 SYSC_HAS_SOFTRESET),
5299 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5300 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5301 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5302 .sysc_fields = &omap_hwmod_sysc_type2,
5303};
5304
5305static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5306 .name = "usb_host_hs",
5307 .sysc = &omap44xx_usb_host_hs_sysc,
5308};
5309
5310static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5311 &omap44xx_usb_host_hs__l3_main_2,
5312};
5313
5314static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5315 {
5316 .name = "uhh",
5317 .pa_start = 0x4a064000,
5318 .pa_end = 0x4a0647ff,
5319 .flags = ADDR_TYPE_RT
5320 },
5321 {
5322 .name = "ohci",
5323 .pa_start = 0x4a064800,
5324 .pa_end = 0x4a064bff,
5325 },
5326 {
5327 .name = "ehci",
5328 .pa_start = 0x4a064c00,
5329 .pa_end = 0x4a064fff,
5330 },
5331 {}
5332};
5333
5334static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5335 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5336 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5337 { .irq = -1 }
5338};
5339
5340static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5341 .master = &omap44xx_l4_cfg_hwmod,
5342 .slave = &omap44xx_usb_host_hs_hwmod,
5343 .clk = "l4_div_ck",
5344 .addr = omap44xx_usb_host_hs_addrs,
5345 .user = OCP_USER_MPU | OCP_USER_SDMA,
5346};
5347
5348static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5349 &omap44xx_l4_cfg__usb_host_hs,
5350};
5351
5352static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5353 .name = "usb_host_hs",
5354 .class = &omap44xx_usb_host_hs_hwmod_class,
5355 .clkdm_name = "l3_init_clkdm",
5356 .main_clk = "usb_host_hs_fck",
5357 .prcm = {
5358 .omap4 = {
5359 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5360 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5361 .modulemode = MODULEMODE_SWCTRL,
5362 },
5363 },
5364 .mpu_irqs = omap44xx_usb_host_hs_irqs,
5365 .slaves = omap44xx_usb_host_hs_slaves,
5366 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5367 .masters = omap44xx_usb_host_hs_masters,
5368 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5369
5370 /*
5371 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5372 * id: i660
5373 *
5374 * Description:
5375 * In the following configuration :
5376 * - USBHOST module is set to smart-idle mode
5377 * - PRCM asserts idle_req to the USBHOST module ( This typically
5378 * happens when the system is going to a low power mode : all ports
5379 * have been suspended, the master part of the USBHOST module has
5380 * entered the standby state, and SW has cut the functional clocks)
5381 * - an USBHOST interrupt occurs before the module is able to answer
5382 * idle_ack, typically a remote wakeup IRQ.
5383 * Then the USB HOST module will enter a deadlock situation where it
5384 * is no more accessible nor functional.
5385 *
5386 * Workaround:
5387 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5388 */
5389
5390 /*
5391 * Errata: USB host EHCI may stall when entering smart-standby mode
5392 * Id: i571
5393 *
5394 * Description:
5395 * When the USBHOST module is set to smart-standby mode, and when it is
5396 * ready to enter the standby state (i.e. all ports are suspended and
5397 * all attached devices are in suspend mode), then it can wrongly assert
5398 * the Mstandby signal too early while there are still some residual OCP
5399 * transactions ongoing. If this condition occurs, the internal state
5400 * machine may go to an undefined state and the USB link may be stuck
5401 * upon the next resume.
5402 *
5403 * Workaround:
5404 * Don't use smart standby; use only force standby,
5405 * hence HWMOD_SWSUP_MSTANDBY
5406 */
5407
5408 /*
5409 * During system boot; If the hwmod framework resets the module
5410 * the module will have smart idle settings; which can lead to deadlock
5411 * (above Errata Id:i660); so, dont reset the module during boot;
5412 * Use HWMOD_INIT_NO_RESET.
5413 */
5414
5415 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5416 HWMOD_INIT_NO_RESET,
5417};
5418
5419/*
5420 * 'usb_tll_hs' class
5421 * usb_tll_hs module is the adapter on the usb_host_hs ports
5422 */
5423static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5424 .rev_offs = 0x0000,
5425 .sysc_offs = 0x0010,
5426 .syss_offs = 0x0014,
5427 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5428 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5429 SYSC_HAS_AUTOIDLE),
5430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5431 .sysc_fields = &omap_hwmod_sysc_type1,
5432};
5433
5434static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5435 .name = "usb_tll_hs",
5436 .sysc = &omap44xx_usb_tll_hs_sysc,
5437};
5438
5439static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5440 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5441 { .irq = -1 }
5442};
5443
5444static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5445 {
5446 .name = "tll",
5447 .pa_start = 0x4a062000,
5448 .pa_end = 0x4a063fff,
5449 .flags = ADDR_TYPE_RT
5450 },
5451 {}
5452};
5453
5454static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5455 .master = &omap44xx_l4_cfg_hwmod,
5456 .slave = &omap44xx_usb_tll_hs_hwmod,
5457 .clk = "l4_div_ck",
5458 .addr = omap44xx_usb_tll_hs_addrs,
5459 .user = OCP_USER_MPU | OCP_USER_SDMA,
5460};
5461
5462static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5463 &omap44xx_l4_cfg__usb_tll_hs,
5464};
5465
5466static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5467 .name = "usb_tll_hs",
5468 .class = &omap44xx_usb_tll_hs_hwmod_class,
5469 .clkdm_name = "l3_init_clkdm",
5470 .main_clk = "usb_tll_hs_ick",
5471 .prcm = {
5472 .omap4 = {
5473 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5474 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5475 .modulemode = MODULEMODE_HWCTRL,
5476 },
5477 },
5478 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
5479 .slaves = omap44xx_usb_tll_hs_slaves,
5480 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5481};
5482
5279static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 5483static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5280 5484
5281 /* dmm class */ 5485 /* dmm class */
@@ -5415,13 +5619,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5415 &omap44xx_uart3_hwmod, 5619 &omap44xx_uart3_hwmod,
5416 &omap44xx_uart4_hwmod, 5620 &omap44xx_uart4_hwmod,
5417 5621
5622 /* usb host class */
5623 &omap44xx_usb_host_hs_hwmod,
5624 &omap44xx_usb_tll_hs_hwmod,
5625
5418 /* usb_otg_hs class */ 5626 /* usb_otg_hs class */
5419 &omap44xx_usb_otg_hs_hwmod, 5627 &omap44xx_usb_otg_hs_hwmod,
5420 5628
5421 /* wd_timer class */ 5629 /* wd_timer class */
5422 &omap44xx_wd_timer2_hwmod, 5630 &omap44xx_wd_timer2_hwmod,
5423 &omap44xx_wd_timer3_hwmod, 5631 &omap44xx_wd_timer3_hwmod,
5424
5425 NULL, 5632 NULL,
5426}; 5633};
5427 5634
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0363dcb0ef93..da2d80f5fcbd 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -201,6 +201,8 @@
201#define OMAP3430_EN_MMC2_SHIFT 25 201#define OMAP3430_EN_MMC2_SHIFT 25
202#define OMAP3430_EN_MMC1_MASK (1 << 24) 202#define OMAP3430_EN_MMC1_MASK (1 << 24)
203#define OMAP3430_EN_MMC1_SHIFT 24 203#define OMAP3430_EN_MMC1_SHIFT 24
204#define OMAP3430_EN_UART4_MASK (1 << 23)
205#define OMAP3430_EN_UART4_SHIFT 23
204#define OMAP3430_EN_MCSPI4_MASK (1 << 21) 206#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
205#define OMAP3430_EN_MCSPI4_SHIFT 21 207#define OMAP3430_EN_MCSPI4_SHIFT 21
206#define OMAP3430_EN_MCSPI3_MASK (1 << 20) 208#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 5ceafdccc456..3638e5c12b7e 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,8 +14,8 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/errno.h>
18#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <plat/addr-map.h>
19#include "common.h" 19#include "common.h"
20 20
21/* 21/*
@@ -41,7 +41,6 @@
41/* 41/*
42 * Generic Address Decode Windows bit settings 42 * Generic Address Decode Windows bit settings
43 */ 43 */
44#define TARGET_DDR 0
45#define TARGET_DEV_BUS 1 44#define TARGET_DEV_BUS 1
46#define TARGET_PCI 3 45#define TARGET_PCI 3
47#define TARGET_PCIE 4 46#define TARGET_PCIE 4
@@ -57,27 +56,10 @@
57#define ATTR_DEV_BOOT 0xf 56#define ATTR_DEV_BOOT 0xf
58#define ATTR_SRAM 0x0 57#define ATTR_SRAM 0x0
59 58
60/*
61 * Helpers to get DDR bank info
62 */
63#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
64#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
65#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
66
67/*
68 * CPU Address Decode Windows registers
69 */
70#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
71#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
72#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
73#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
74#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
75
76
77struct mbus_dram_target_info orion5x_mbus_dram_info;
78static int __initdata win_alloc_count; 59static int __initdata win_alloc_count;
79 60
80static int __init orion5x_cpu_win_can_remap(int win) 61static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
62 const int win)
81{ 63{
82 u32 dev, rev; 64 u32 dev, rev;
83 65
@@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win)
91 return 0; 73 return 0;
92} 74}
93 75
94static int __init setup_cpu_win(int win, u32 base, u32 size, 76/*
95 u8 target, u8 attr, int remap) 77 * Description of the windows needed by the platform code
96{ 78 */
97 if (win >= 8) { 79static struct __initdata orion_addr_map_cfg addr_map_cfg = {
98 printk(KERN_ERR "setup_cpu_win: trying to allocate " 80 .num_wins = 8,
99 "window %d\n", win); 81 .cpu_win_can_remap = cpu_win_can_remap,
100 return -ENOSPC; 82 .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
101 } 83};
102
103 writel(base & 0xffff0000, CPU_WIN_BASE(win));
104 writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
105 CPU_WIN_CTRL(win));
106
107 if (orion5x_cpu_win_can_remap(win)) {
108 if (remap < 0)
109 remap = base;
110
111 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
112 writel(0, CPU_WIN_REMAP_HI(win));
113 }
114 return 0;
115}
116
117void __init orion5x_setup_cpu_mbus_bridge(void)
118{
119 int i;
120 int cs;
121 84
85static const struct __initdata orion_addr_map_info addr_map_info[] = {
122 /* 86 /*
123 * First, disable and clear windows. 87 * Setup windows for PCI+PCIe IO+MEM space.
124 */ 88 */
125 for (i = 0; i < 8; i++) { 89 { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
126 writel(0, CPU_WIN_BASE(i)); 90 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
127 writel(0, CPU_WIN_CTRL(i)); 91 },
128 if (orion5x_cpu_win_can_remap(i)) { 92 { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
129 writel(0, CPU_WIN_REMAP_LO(i)); 93 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
130 writel(0, CPU_WIN_REMAP_HI(i)); 94 },
131 } 95 { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
132 } 96 TARGET_PCIE, ATTR_PCIE_MEM, -1
97 },
98 { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
99 TARGET_PCI, ATTR_PCI_MEM, -1
100 },
101 /* End marker */
102 { -1, 0, 0, 0, 0, 0 }
103};
133 104
105void __init orion5x_setup_cpu_mbus_bridge(void)
106{
134 /* 107 /*
135 * Setup windows for PCI+PCIe IO+MEM space. 108 * Disable, clear and configure windows.
136 */ 109 */
137 setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, 110 orion_config_wins(&addr_map_cfg, addr_map_info);
138 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
139 setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
140 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
141 setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
142 TARGET_PCIE, ATTR_PCIE_MEM, -1);
143 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
144 TARGET_PCI, ATTR_PCI_MEM, -1);
145 win_alloc_count = 4; 111 win_alloc_count = 4;
146 112
147 /* 113 /*
148 * Setup MBUS dram target info. 114 * Setup MBUS dram target info.
149 */ 115 */
150 orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 116 orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
151
152 for (i = 0, cs = 0; i < 4; i++) {
153 u32 base = readl(DDR_BASE_CS(i));
154 u32 size = readl(DDR_SIZE_CS(i));
155
156 /*
157 * Chip select enabled?
158 */
159 if (size & 1) {
160 struct mbus_dram_window *w;
161
162 w = &orion5x_mbus_dram_info.cs[cs++];
163 w->cs_index = i;
164 w->mbus_attr = 0xf & ~(1 << i);
165 w->base = base & 0xffff0000;
166 w->size = (size | 0x0000ffff) + 1;
167 }
168 }
169 orion5x_mbus_dram_info.num_cs = cs;
170} 117}
171 118
172void __init orion5x_setup_dev_boot_win(u32 base, u32 size) 119void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
173{ 120{
174 setup_cpu_win(win_alloc_count++, base, size, 121 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
175 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); 122 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
176} 123}
177 124
178void __init orion5x_setup_dev0_win(u32 base, u32 size) 125void __init orion5x_setup_dev0_win(u32 base, u32 size)
179{ 126{
180 setup_cpu_win(win_alloc_count++, base, size, 127 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
181 TARGET_DEV_BUS, ATTR_DEV_CS0, -1); 128 TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
182} 129}
183 130
184void __init orion5x_setup_dev1_win(u32 base, u32 size) 131void __init orion5x_setup_dev1_win(u32 base, u32 size)
185{ 132{
186 setup_cpu_win(win_alloc_count++, base, size, 133 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
187 TARGET_DEV_BUS, ATTR_DEV_CS1, -1); 134 TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
188} 135}
189 136
190void __init orion5x_setup_dev2_win(u32 base, u32 size) 137void __init orion5x_setup_dev2_win(u32 base, u32 size)
191{ 138{
192 setup_cpu_win(win_alloc_count++, base, size, 139 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
193 TARGET_DEV_BUS, ATTR_DEV_CS2, -1); 140 TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
194} 141}
195 142
196void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) 143void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
197{ 144{
198 setup_cpu_win(win_alloc_count++, base, size, 145 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
199 TARGET_PCIE, ATTR_PCIE_WA, -1); 146 TARGET_PCIE, ATTR_PCIE_WA, -1);
200} 147}
201 148
202int __init orion5x_setup_sram_win(void) 149void __init orion5x_setup_sram_win(void)
203{ 150{
204 return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, 151 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
205 ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); 152 ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
153 TARGET_SRAM, ATTR_SRAM, -1);
206} 154}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 41127e80cc1e..0e28bae20bd4 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -15,7 +15,6 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
17#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
18#include <linux/mbus.h>
19#include <linux/mv643xx_i2c.h> 18#include <linux/mv643xx_i2c.h>
20#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
21#include <linux/delay.h> 20#include <linux/delay.h>
@@ -32,6 +31,7 @@
32#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
33#include <plat/time.h> 32#include <plat/time.h>
34#include <plat/common.h> 33#include <plat/common.h>
34#include <plat/addr-map.h>
35#include "common.h" 35#include "common.h"
36 36
37/***************************************************************************** 37/*****************************************************************************
@@ -72,8 +72,7 @@ void __init orion5x_map_io(void)
72 ****************************************************************************/ 72 ****************************************************************************/
73void __init orion5x_ehci0_init(void) 73void __init orion5x_ehci0_init(void)
74{ 74{
75 orion_ehci_init(&orion5x_mbus_dram_info, 75 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
76 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
77} 76}
78 77
79 78
@@ -82,8 +81,7 @@ void __init orion5x_ehci0_init(void)
82 ****************************************************************************/ 81 ****************************************************************************/
83void __init orion5x_ehci1_init(void) 82void __init orion5x_ehci1_init(void)
84{ 83{
85 orion_ehci_1_init(&orion5x_mbus_dram_info, 84 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
86 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
87} 85}
88 86
89 87
@@ -92,7 +90,7 @@ void __init orion5x_ehci1_init(void)
92 ****************************************************************************/ 90 ****************************************************************************/
93void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 91void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
94{ 92{
95 orion_ge00_init(eth_data, &orion5x_mbus_dram_info, 93 orion_ge00_init(eth_data,
96 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 94 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
97 IRQ_ORION5X_ETH_ERR, orion5x_tclk); 95 IRQ_ORION5X_ETH_ERR, orion5x_tclk);
98} 96}
@@ -122,8 +120,7 @@ void __init orion5x_i2c_init(void)
122 ****************************************************************************/ 120 ****************************************************************************/
123void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 121void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
124{ 122{
125 orion_sata_init(sata_data, &orion5x_mbus_dram_info, 123 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
126 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
127} 124}
128 125
129 126
@@ -159,8 +156,7 @@ void __init orion5x_uart1_init(void)
159 ****************************************************************************/ 156 ****************************************************************************/
160void __init orion5x_xor_init(void) 157void __init orion5x_xor_init(void)
161{ 158{
162 orion_xor0_init(&orion5x_mbus_dram_info, 159 orion_xor0_init(ORION5X_XOR_PHYS_BASE,
163 ORION5X_XOR_PHYS_BASE,
164 ORION5X_XOR_PHYS_BASE + 0x200, 160 ORION5X_XOR_PHYS_BASE + 0x200,
165 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 161 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
166} 162}
@@ -170,12 +166,7 @@ void __init orion5x_xor_init(void)
170 ****************************************************************************/ 166 ****************************************************************************/
171static void __init orion5x_crypto_init(void) 167static void __init orion5x_crypto_init(void)
172{ 168{
173 int ret; 169 orion5x_setup_sram_win();
174
175 ret = orion5x_setup_sram_win();
176 if (ret)
177 return;
178
179 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 170 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 SZ_8K, IRQ_ORION5X_CESA); 171 SZ_8K, IRQ_ORION5X_CESA);
181} 172}
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 37ef18de61b7..d2513ac79ff5 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer;
20 * functions to map its interfaces and by the machine-setup to map its on- 20 * functions to map its interfaces and by the machine-setup to map its on-
21 * board devices. Details in /mach-orion/addr-map.c 21 * board devices. Details in /mach-orion/addr-map.c
22 */ 22 */
23extern struct mbus_dram_target_info orion5x_mbus_dram_info;
24void orion5x_setup_cpu_mbus_bridge(void); 23void orion5x_setup_cpu_mbus_bridge(void);
25void orion5x_setup_dev_boot_win(u32 base, u32 size); 24void orion5x_setup_dev_boot_win(u32 base, u32 size);
26void orion5x_setup_dev0_win(u32 base, u32 size); 25void orion5x_setup_dev0_win(u32 base, u32 size);
27void orion5x_setup_dev1_win(u32 base, u32 size); 26void orion5x_setup_dev1_win(u32 base, u32 size);
28void orion5x_setup_dev2_win(u32 base, u32 size); 27void orion5x_setup_dev2_win(u32 base, u32 size);
29void orion5x_setup_pcie_wa_win(u32 base, u32 size); 28void orion5x_setup_pcie_wa_win(u32 base, u32 size);
30int orion5x_setup_sram_win(void); 29void orion5x_setup_sram_win(void);
31 30
32void orion5x_ehci0_init(void); 31void orion5x_ehci0_init(void);
33void orion5x_ehci1_init(void); 32void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 0a28bbc76891..2745f5d95b3f 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -69,7 +69,7 @@
69 ******************************************************************************/ 69 ******************************************************************************/
70 70
71#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) 71#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
72 72#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500)
73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) 73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) 74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) 75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index b6ddd7a5db6a..5b70026f478c 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -10,7 +10,6 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <mach/hardware.h> 14#include <mach/hardware.h>
16#include <plat/mpp.h> 15#include <plat/mpp.h>
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index bc4a920e26ee..a494c470e3e4 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -18,6 +18,7 @@
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/mach/pci.h> 19#include <asm/mach/pci.h>
20#include <plat/pcie.h> 20#include <plat/pcie.h>
21#include <plat/addr-map.h>
21#include "common.h" 22#include "common.h"
22 23
23/***************************************************************************** 24/*****************************************************************************
@@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
145 /* 146 /*
146 * Generic PCIe unit setup. 147 * Generic PCIe unit setup.
147 */ 148 */
148 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 149 orion_pcie_setup(PCIE_BASE);
149 150
150 /* 151 /*
151 * Check whether to apply Orion-1/Orion-NAS PCIe config 152 * Check whether to apply Orion-1/Orion-NAS PCIe config
@@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
477 /* 478 /*
478 * Point PCI unit MBUS decode windows to DRAM space. 479 * Point PCI unit MBUS decode windows to DRAM space.
479 */ 480 */
480 orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 481 orion5x_setup_pci_wins(&orion_mbus_dram_info);
481 482
482 /* 483 /*
483 * Master + Slave enable 484 * Master + Slave enable
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index febee47bc116..a2e8ae8b5821 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -7,6 +7,7 @@
7 * 7 *
8 * All enquiries to support@picochip.com 8 * All enquiries to support@picochip.com
9 */ 9 */
10#include <linux/delay.h>
10#include <linux/irq.h> 11#include <linux/irq.h>
11#include <linux/irqdomain.h> 12#include <linux/irqdomain.h>
12#include <linux/of.h> 13#include <linux/of.h>
@@ -23,6 +24,26 @@
23 24
24#include "common.h" 25#include "common.h"
25 26
27#define WDT_CTRL_REG_EN_MASK (1 << 0)
28#define WDT_CTRL_REG_OFFS (0x00)
29#define WDT_TIMEOUT_REG_OFFS (0x04)
30static void __iomem *wdt_regs;
31
32/*
33 * The machine restart method can be called from an atomic context so we won't
34 * be able to ioremap the regs then.
35 */
36static void picoxcell_setup_restart(void)
37{
38 struct device_node *np = of_find_compatible_node(NULL, NULL,
39 "snps,dw-apb-wdg");
40 if (WARN(!np, "unable to setup watchdog restart"))
41 return;
42
43 wdt_regs = of_iomap(np, 0);
44 WARN(!wdt_regs, "failed to remap watchdog regs");
45}
46
26static struct map_desc io_map __initdata = { 47static struct map_desc io_map __initdata = {
27 .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE), 48 .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
28 .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE), 49 .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
@@ -38,6 +59,7 @@ static void __init picoxcell_map_io(void)
38static void __init picoxcell_init_machine(void) 59static void __init picoxcell_init_machine(void)
39{ 60{
40 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 61 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
62 picoxcell_setup_restart();
41} 63}
42 64
43static const char *picoxcell_dt_match[] = { 65static const char *picoxcell_dt_match[] = {
@@ -56,6 +78,20 @@ static void __init picoxcell_init_irq(void)
56 of_irq_init(vic_of_match); 78 of_irq_init(vic_of_match);
57} 79}
58 80
81static void picoxcell_wdt_restart(char mode, const char *cmd)
82{
83 /*
84 * Configure the watchdog to reset with the shortest possible timeout
85 * and give it chance to do the reset.
86 */
87 if (wdt_regs) {
88 writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS);
89 writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS);
90 /* No sleeping, possibly atomic. */
91 mdelay(500);
92 }
93}
94
59DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") 95DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
60 .map_io = picoxcell_map_io, 96 .map_io = picoxcell_map_io,
61 .nr_irqs = NR_IRQS_LEGACY, 97 .nr_irqs = NR_IRQS_LEGACY,
@@ -64,4 +100,5 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
64 .timer = &picoxcell_timer, 100 .timer = &picoxcell_timer,
65 .init_machine = picoxcell_init_machine, 101 .init_machine = picoxcell_init_machine,
66 .dt_compat = picoxcell_dt_match, 102 .dt_compat = picoxcell_dt_match,
103 .restart = picoxcell_wdt_restart,
67MACHINE_END 104MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 6826faeecc68..23be34b3bb6e 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -22,6 +22,12 @@
22#include "ste-dma40-db8500.h" 22#include "ste-dma40-db8500.h"
23 23
24/* 24/*
25 * v2 has a new version of this block that need to be forced, the number found
26 * in hardware is incorrect
27 */
28#define U8500_SDI_V2_PERIPHID 0x10480180
29
30/*
25 * SDI 0 (MicroSD slot) 31 * SDI 0 (MicroSD slot)
26 */ 32 */
27 33
@@ -117,10 +123,7 @@ static void sdi0_configure(void)
117 gpio_direction_output(sdi0_en, 1); 123 gpio_direction_output(sdi0_en, 1);
118 124
119 /* Add the device, force v2 to subrevision 1 */ 125 /* Add the device, force v2 to subrevision 1 */
120 if (cpu_is_u8500v2()) 126 db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
121 db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
122 else
123 db8500_add_sdi0(&mop500_sdi0_data, 0);
124} 127}
125 128
126void mop500_sdi_tc35892_init(void) 129void mop500_sdi_tc35892_init(void)
@@ -132,6 +135,42 @@ void mop500_sdi_tc35892_init(void)
132} 135}
133 136
134/* 137/*
138 * SDI1 (SDIO WLAN)
139 */
140#ifdef CONFIG_STE_DMA40
141static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
142 .mode = STEDMA40_MODE_LOGICAL,
143 .dir = STEDMA40_PERIPH_TO_MEM,
144 .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
145 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
146 .src_info.data_width = STEDMA40_WORD_WIDTH,
147 .dst_info.data_width = STEDMA40_WORD_WIDTH,
148};
149
150static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
151 .mode = STEDMA40_MODE_LOGICAL,
152 .dir = STEDMA40_MEM_TO_PERIPH,
153 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
154 .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
155 .src_info.data_width = STEDMA40_WORD_WIDTH,
156 .dst_info.data_width = STEDMA40_WORD_WIDTH,
157};
158#endif
159
160static struct mmci_platform_data mop500_sdi1_data = {
161 .ocr_mask = MMC_VDD_29_30,
162 .f_max = 50000000,
163 .capabilities = MMC_CAP_4_BIT_DATA,
164 .gpio_cd = -1,
165 .gpio_wp = -1,
166#ifdef CONFIG_STE_DMA40
167 .dma_filter = stedma40_filter,
168 .dma_rx_param = &sdi1_dma_cfg_rx,
169 .dma_tx_param = &sdi1_dma_cfg_tx,
170#endif
171};
172
173/*
135 * SDI 2 (POP eMMC, not on DB8500ed) 174 * SDI 2 (POP eMMC, not on DB8500ed)
136 */ 175 */
137 176
@@ -158,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
158static struct mmci_platform_data mop500_sdi2_data = { 197static struct mmci_platform_data mop500_sdi2_data = {
159 .ocr_mask = MMC_VDD_165_195, 198 .ocr_mask = MMC_VDD_165_195,
160 .f_max = 50000000, 199 .f_max = 50000000,
161 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 200 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
201 MMC_CAP_MMC_HIGHSPEED,
162 .gpio_cd = -1, 202 .gpio_cd = -1,
163 .gpio_wp = -1, 203 .gpio_wp = -1,
164#ifdef CONFIG_STE_DMA40 204#ifdef CONFIG_STE_DMA40
@@ -208,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = {
208 248
209void __init mop500_sdi_init(void) 249void __init mop500_sdi_init(void)
210{ 250{
211 u32 periphid = 0; 251 /* PoP:ed eMMC */
212 252 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
213 /* v2 has a new version of this block that need to be forced */
214 if (cpu_is_u8500v2())
215 periphid = 0x10480180;
216 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
217 if (!cpu_is_u8500v10())
218 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
219
220 db8500_add_sdi2(&mop500_sdi2_data, periphid);
221
222 /* On-board eMMC */ 253 /* On-board eMMC */
223 db8500_add_sdi4(&mop500_sdi4_data, periphid); 254 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
224
225 /* 255 /*
226 * On boards with the TC35892 GPIO expander, sdi0 will finally 256 * On boards with the TC35892 GPIO expander, sdi0 will finally
227 * be added when the TC35892 initializes and calls 257 * be added when the TC35892 initializes and calls
@@ -231,13 +261,9 @@ void __init mop500_sdi_init(void)
231 261
232void __init snowball_sdi_init(void) 262void __init snowball_sdi_init(void)
233{ 263{
234 u32 periphid = 0x10480180;
235
236 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
237
238 /* On-board eMMC */ 264 /* On-board eMMC */
239 db8500_add_sdi4(&mop500_sdi4_data, periphid); 265 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
240 266 /* External Micro SD slot */
241 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; 267 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
242 mop500_sdi0_data.cd_invert = true; 268 mop500_sdi0_data.cd_invert = true;
243 sdi0_en = SNOWBALL_SDMMC_EN_GPIO; 269 sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
@@ -247,17 +273,15 @@ void __init snowball_sdi_init(void)
247 273
248void __init hrefv60_sdi_init(void) 274void __init hrefv60_sdi_init(void)
249{ 275{
250 u32 periphid = 0x10480180; 276 /* PoP:ed eMMC */
251 277 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
252 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
253
254 db8500_add_sdi2(&mop500_sdi2_data, periphid);
255
256 /* On-board eMMC */ 278 /* On-board eMMC */
257 db8500_add_sdi4(&mop500_sdi4_data, periphid); 279 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
258 280 /* External Micro SD slot */
259 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; 281 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
260 sdi0_en = HREFV60_SDMMC_EN_GPIO; 282 sdi0_en = HREFV60_SDMMC_EN_GPIO;
261 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; 283 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
262 sdi0_configure(); 284 sdi0_configure();
285 /* WLAN SDIO channel */
286 db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
263} 287}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index de1f5f8f7330..9361a5290177 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
673 ARRAY_SIZE(mop500_platform_devs)); 673 ARRAY_SIZE(mop500_platform_devs));
674 674
675 mop500_i2c_init(); 675 mop500_i2c_init();
676 mop500_sdi_init(); 676 hrefv60_sdi_init();
677 mop500_spi_init(); 677 mop500_spi_init();
678 mop500_uart_init(); 678 mop500_uart_init();
679 679
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index de18a2a23e6e..f926d3db6207 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,40 +7,77 @@
7#ifndef __BOARD_MOP500_H 7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H 8#define __BOARD_MOP500_H
9 9
10/* snowball GPIO for MMC card */ 10/* Snowball specific GPIO assignments, this board has no GPIO expander */
11#define SNOWBALL_SDMMC_EN_GPIO 217 11#define SNOWBALL_ACCEL_INT1_GPIO 163
12#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 12#define SNOWBALL_ACCEL_INT2_GPIO 164
13#define SNOWBALL_SDMMC_CD_GPIO 218 13#define SNOWBALL_MAGNET_DRDY_GPIO 165
14#define SNOWBALL_SDMMC_EN_GPIO 217
15#define SNOWBALL_SDMMC_1V8_3V_GPIO 228
16#define SNOWBALL_SDMMC_CD_GPIO 218
14 17
15/* HREFv60-specific GPIO assignments, this board has no GPIO expander */ 18/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
16#define HREFV60_TOUCH_RST_GPIO 143
17#define HREFV60_PROX_SENSE_GPIO 217
18#define HREFV60_HAL_SW_GPIO 145
19#define HREFV60_SDMMC_EN_GPIO 169
20#define HREFV60_SDMMC_1V8_3V_GPIO 5 19#define HREFV60_SDMMC_1V8_3V_GPIO 5
21#define HREFV60_SDMMC_CD_GPIO 95 20#define HREFV60_CAMERA_FLASH_ENABLE 21
22#define HREFV60_ACCEL_INT1_GPIO 82
23#define HREFV60_ACCEL_INT2_GPIO 83
24#define HREFV60_MAGNET_DRDY_GPIO 32 21#define HREFV60_MAGNET_DRDY_GPIO 32
25#define HREFV60_DISP1_RST_GPIO 65 22#define HREFV60_DISP1_RST_GPIO 65
26#define HREFV60_DISP2_RST_GPIO 66 23#define HREFV60_DISP2_RST_GPIO 66
24#define HREFV60_ACCEL_INT1_GPIO 82
25#define HREFV60_ACCEL_INT2_GPIO 83
26#define HREFV60_SDMMC_CD_GPIO 95
27#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140
28#define HREFV60_TOUCH_RST_GPIO 143
29#define HREFV60_HAL_SW_GPIO 145
30#define HREFV60_SDMMC_EN_GPIO 169
31#define HREFV60_MMIO_XENON_CHARGE 170
32#define HREFV60_PROX_SENSE_GPIO 217
33
34/* MOP500 generic GPIOs */
35#define CAMERA_FLASH_INT_PIN 7
36#define CYPRESS_TOUCH_INT_PIN 84
37#define XSHUTDOWN_PRIMARY_SENSOR 141
38#define XSHUTDOWN_SECONDARY_SENSOR 142
39#define CYPRESS_TOUCH_RST_GPIO 143
40#define MOP500_HDMI_RST_GPIO 196
41#define CYPRESS_SLAVE_SELECT_GPIO 216
27 42
28/* GPIOs on the TC35892 expander */ 43/* GPIOs on the TC35892 expander */
29#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) 44#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x))
45#define GPIO_MAGNET_DRDY MOP500_EGPIO(1)
30#define GPIO_SDMMC_CD MOP500_EGPIO(3) 46#define GPIO_SDMMC_CD MOP500_EGPIO(3)
47#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4)
48#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5)
31#define GPIO_PROX_SENSOR MOP500_EGPIO(7) 49#define GPIO_PROX_SENSOR MOP500_EGPIO(7)
50#define GPIO_HAL_SENSOR MOP500_EGPIO(8)
51#define GPIO_ACCEL_INT1 MOP500_EGPIO(10)
52#define GPIO_ACCEL_INT2 MOP500_EGPIO(11)
32#define GPIO_BU21013_CS MOP500_EGPIO(13) 53#define GPIO_BU21013_CS MOP500_EGPIO(13)
54#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14)
55#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15)
33#define GPIO_SDMMC_EN MOP500_EGPIO(17) 56#define GPIO_SDMMC_EN MOP500_EGPIO(17)
34#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) 57#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18)
35#define MOP500_EGPIO_END MOP500_EGPIO(24) 58#define MOP500_EGPIO_END MOP500_EGPIO(24)
36 59
37/* GPIOs on the AB8500 mixed-signals circuit */ 60/*
38#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) 61 * GPIOs on the AB8500 mixed-signals circuit
62 * Notice that we subtract 1 from the number passed into the macro, this is
63 * because the AB8500 GPIO pins are enumbered starting from 1, so the value in
64 * parens matches the GPIO pin number in the data sheet.
65 */
66#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x) - 1)
67/*Snowball AB8500 GPIO */
68#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */
69#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */
70#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */
71#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */
72#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */
73#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */
74#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
39 75
40struct i2c_board_info; 76struct i2c_board_info;
41 77
42extern void mop500_sdi_init(void); 78extern void mop500_sdi_init(void);
43extern void snowball_sdi_init(void); 79extern void snowball_sdi_init(void);
80extern void hrefv60_sdi_init(void);
44extern void mop500_sdi_tc35892_init(void); 81extern void mop500_sdi_tc35892_init(void);
45void __init mop500_u8500uib_init(void); 82void __init mop500_u8500uib_init(void);
46void __init mop500_stuib_init(void); 83void __init mop500_stuib_init(void);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index e832664d1bd9..737907537004 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk)
239 writel(1 << clk->prcmu_cg_bit, cg_clr_reg); 239 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
240} 240}
241 241
242/* ED doesn't have the combined set/clr registers */
243static void clk_prcmu_ed_enable(struct clk *clk)
244{
245 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
246 + clk->prcmu_cg_mgt;
247
248 writel(readl(addr) | PRCM_MGT_ENABLE, addr);
249}
250
251static void clk_prcmu_ed_disable(struct clk *clk)
252{
253 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
254 + clk->prcmu_cg_mgt;
255
256 writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
257}
258
259static struct clkops clk_prcmu_ops = { 242static struct clkops clk_prcmu_ops = {
260 .enable = clk_prcmu_enable, 243 .enable = clk_prcmu_enable,
261 .disable = clk_prcmu_disable, 244 .disable = clk_prcmu_disable,
@@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = {
267 [3] = U8500_CLKRST3_BASE, 250 [3] = U8500_CLKRST3_BASE,
268 [5] = U8500_CLKRST5_BASE, 251 [5] = U8500_CLKRST5_BASE,
269 [6] = U8500_CLKRST6_BASE, 252 [6] = U8500_CLKRST6_BASE,
270 [7] = U8500_CLKRST7_BASE_ED,
271}; 253};
272 254
273static void clk_prcc_enable(struct clk *clk) 255static void clk_prcc_enable(struct clk *clk)
@@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
321static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); 303static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
322static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); 304static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
323static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); 305static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
324static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
325static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); 306static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
326static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); 307static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
327static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); 308static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
@@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
351static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); 332static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
352static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); 333static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
353static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); 334static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
354static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); 335static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
355static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
356static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); 336static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
357static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); 337static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
358static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); 338static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
359static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
360static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); 339static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
361static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); 340static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
362static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); 341static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
363static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); 342static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
364 343
365/* Peripheral Cluster #2 */ 344/* Peripheral Cluster #2 */
366 345static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
367static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); 346static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
368static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); 347static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
369static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); 348static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
370static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); 349static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
371static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); 350static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
372static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); 351static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
373static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); 352static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
374static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); 353static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
375static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); 354static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
376static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); 355static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
377static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); 356static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
378static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
379
380static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
381static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
382static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
383static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
384static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
385static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
386static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
387static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
388static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
389static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
390static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
391static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
392 357
393/* Peripheral Cluster #3 */ 358/* Peripheral Cluster #3 */
394static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); 359static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
@@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
397static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); 362static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
398static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); 363static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
399static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); 364static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
400static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); 365static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
401static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); 366static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
402static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
403static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
404static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); 367static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
405 368
406/* Peripheral Cluster #4 is in the always on domain */ 369/* Peripheral Cluster #4 is in the always on domain */
407 370
408/* Peripheral Cluster #5 */ 371/* Peripheral Cluster #5 */
409static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); 372static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
410static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); 373static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
411static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
412 374
413/* Peripheral Cluster #6 */ 375/* Peripheral Cluster #6 */
414 376
415/* MTU ID in data */ 377/* MTU ID in data */
416static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); 378static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
417static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); 379static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
418static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); 380static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL);
419static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
420static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); 381static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
421static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); 382static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk);
422static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
423static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); 383static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
424static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); 384static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
425static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); 385static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
426static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); 386static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
427static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
428
429/* Peripheral Cluster #7 */
430
431static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
432/* MTU ID in data */
433static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
434static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
435static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
436static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
437 387
438static struct clk clk_dummy_apb_pclk = { 388static struct clk clk_dummy_apb_pclk = {
439 .name = "apb_pclk", 389 .name = "apb_pclk",
440}; 390};
441 391
442static struct clk_lookup u8500_common_clks[] = { 392static struct clk_lookup u8500_clks[] = {
443 CLK(dummy_apb_pclk, NULL, "apb_pclk"), 393 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
444 394
445 /* Peripheral Cluster #1 */ 395 /* Peripheral Cluster #1 */
@@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = {
494 CLK(dmaclk, "dma40.0", NULL), 444 CLK(dmaclk, "dma40.0", NULL),
495 CLK(b2r2clk, "b2r2", NULL), 445 CLK(b2r2clk, "b2r2", NULL),
496 CLK(tvclk, "tv", NULL), 446 CLK(tvclk, "tv", NULL),
497};
498 447
499static struct clk_lookup u8500_ed_clks[] = {
500 /* Peripheral Cluster #1 */
501 CLK(spi3_ed, "spi3", NULL),
502 CLK(msp1_ed, "msp1", NULL),
503
504 /* Peripheral Cluster #2 */
505 CLK(gpio1_ed, "gpio.6", NULL),
506 CLK(gpio1_ed, "gpio.7", NULL),
507 CLK(ssitx_ed, "ssitx", NULL),
508 CLK(ssirx_ed, "ssirx", NULL),
509 CLK(spi0_ed, "spi0", NULL),
510 CLK(sdi3_ed, "sdi3", NULL),
511 CLK(sdi1_ed, "sdi1", NULL),
512 CLK(msp2_ed, "msp2", NULL),
513 CLK(sdi4_ed, "sdi4", NULL),
514 CLK(pwl_ed, "pwl", NULL),
515 CLK(spi1_ed, "spi1", NULL),
516 CLK(spi2_ed, "spi2", NULL),
517 CLK(i2c3_ed, "nmk-i2c.3", NULL),
518
519 /* Peripheral Cluster #3 */
520 CLK(ssp1_ed, "ssp1", NULL),
521 CLK(ssp0_ed, "ssp0", NULL),
522
523 /* Peripheral Cluster #5 */
524 CLK(usb_ed, "musb-ux500.0", "usb"),
525
526 /* Peripheral Cluster #6 */
527 CLK(dmc_ed, "dmc", NULL),
528 CLK(cryp1_ed, "cryp1", NULL),
529 CLK(rng_ed, "rng", NULL),
530
531 /* Peripheral Cluster #7 */
532 CLK(tzpc0_ed, "tzpc0", NULL),
533 CLK(mtu1_ed, "mtu1", NULL),
534 CLK(mtu0_ed, "mtu0", NULL),
535 CLK(wdg_ed, "wdg", NULL),
536 CLK(cfgreg_ed, "cfgreg", NULL),
537};
538
539static struct clk_lookup u8500_v1_clks[] = {
540 /* Peripheral Cluster #1 */ 448 /* Peripheral Cluster #1 */
541 CLK(i2c4, "nmk-i2c.4", NULL), 449 CLK(i2c4, "nmk-i2c.4", NULL),
542 CLK(spi3_v1, "spi3", NULL), 450 CLK(spi3, "spi3", NULL),
543 CLK(msp1_v1, "msp1", NULL), 451 CLK(msp1, "msp1", NULL),
544 452
545 /* Peripheral Cluster #2 */ 453 /* Peripheral Cluster #2 */
546 CLK(gpio1_v1, "gpio.6", NULL), 454 CLK(gpio1, "gpio.6", NULL),
547 CLK(gpio1_v1, "gpio.7", NULL), 455 CLK(gpio1, "gpio.7", NULL),
548 CLK(ssitx_v1, "ssitx", NULL), 456 CLK(ssitx, "ssitx", NULL),
549 CLK(ssirx_v1, "ssirx", NULL), 457 CLK(ssirx, "ssirx", NULL),
550 CLK(spi0_v1, "spi0", NULL), 458 CLK(spi0, "spi0", NULL),
551 CLK(sdi3_v1, "sdi3", NULL), 459 CLK(sdi3, "sdi3", NULL),
552 CLK(sdi1_v1, "sdi1", NULL), 460 CLK(sdi1, "sdi1", NULL),
553 CLK(msp2_v1, "msp2", NULL), 461 CLK(msp2, "msp2", NULL),
554 CLK(sdi4_v1, "sdi4", NULL), 462 CLK(sdi4, "sdi4", NULL),
555 CLK(pwl_v1, "pwl", NULL), 463 CLK(pwl, "pwl", NULL),
556 CLK(spi1_v1, "spi1", NULL), 464 CLK(spi1, "spi1", NULL),
557 CLK(spi2_v1, "spi2", NULL), 465 CLK(spi2, "spi2", NULL),
558 CLK(i2c3_v1, "nmk-i2c.3", NULL), 466 CLK(i2c3, "nmk-i2c.3", NULL),
559 467
560 /* Peripheral Cluster #3 */ 468 /* Peripheral Cluster #3 */
561 CLK(ssp1_v1, "ssp1", NULL), 469 CLK(ssp1, "ssp1", NULL),
562 CLK(ssp0_v1, "ssp0", NULL), 470 CLK(ssp0, "ssp0", NULL),
563 471
564 /* Peripheral Cluster #5 */ 472 /* Peripheral Cluster #5 */
565 CLK(usb_v1, "musb-ux500.0", "usb"), 473 CLK(usb, "musb-ux500.0", "usb"),
566 474
567 /* Peripheral Cluster #6 */ 475 /* Peripheral Cluster #6 */
568 CLK(mtu1_v1, "mtu1", NULL), 476 CLK(mtu1, "mtu1", NULL),
569 CLK(mtu0_v1, "mtu0", NULL), 477 CLK(mtu0, "mtu0", NULL),
570 CLK(cfgreg_v1, "cfgreg", NULL), 478 CLK(cfgreg, "cfgreg", NULL),
571 CLK(hash1, "hash1", NULL), 479 CLK(hash1, "hash1", NULL),
572 CLK(unipro_v1, "unipro", NULL), 480 CLK(unipro, "unipro", NULL),
573 CLK(rng_v1, "rng", NULL), 481 CLK(rng, "rng", NULL),
574 482
575 /* PRCMU level clock gating */ 483 /* PRCMU level clock gating */
576 484
@@ -743,7 +651,7 @@ err_out:
743late_initcall(clk_debugfs_init); 651late_initcall(clk_debugfs_init);
744#endif /* defined(CONFIG_DEBUG_FS) */ 652#endif /* defined(CONFIG_DEBUG_FS) */
745 653
746unsigned long clk_smp_twd_rate = 400000000; 654unsigned long clk_smp_twd_rate = 500000000;
747 655
748unsigned long clk_smp_twd_get_rate(struct clk *clk) 656unsigned long clk_smp_twd_get_rate(struct clk *clk)
749{ 657{
@@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb,
769 677
770 if (state == CPUFREQ_PRECHANGE) { 678 if (state == CPUFREQ_PRECHANGE) {
771 /* Save frequency in simple Hz */ 679 /* Save frequency in simple Hz */
772 clk_smp_twd_rate = f->new * 1000; 680 clk_smp_twd_rate = (f->new * 1000) / 2;
773 } 681 }
774 682
775 return NOTIFY_OK; 683 return NOTIFY_OK;
@@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq);
790 698
791int __init clk_init(void) 699int __init clk_init(void)
792{ 700{
793 if (cpu_is_u8500ed()) { 701 if (cpu_is_u5500()) {
794 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
795 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
796 clk_per6clk.rate = 100000000;
797 } else if (cpu_is_u5500()) {
798 /* Clock tree for U5500 not implemented yet */ 702 /* Clock tree for U5500 not implemented yet */
799 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; 703 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
800 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; 704 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
@@ -802,20 +706,11 @@ int __init clk_init(void)
802 clk_sdmmcclk.rate = 99900000; 706 clk_sdmmcclk.rate = 99900000;
803 } 707 }
804 708
805 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); 709 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
806 if (cpu_is_u8500ed())
807 clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
808 else
809 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
810
811 clkdev_add(&clk_smp_twd_lookup); 710 clkdev_add(&clk_smp_twd_lookup);
812 711
813#ifdef CONFIG_DEBUG_FS 712#ifdef CONFIG_DEBUG_FS
814 clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); 713 clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
815 if (cpu_is_u8500ed())
816 clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
817 else
818 clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
819#endif 714#endif
820 return 0; 715 return 0;
821} 716}
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 5323286b265e..18aa5c05c69e 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -46,26 +46,6 @@ static struct map_desc u5500_io_desc[] __initdata = {
46 __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), 46 __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
47}; 47};
48 48
49static struct resource db5500_pmu_resources[] = {
50 [0] = {
51 .start = IRQ_DB5500_PMU0,
52 .end = IRQ_DB5500_PMU0,
53 .flags = IORESOURCE_IRQ,
54 },
55 [1] = {
56 .start = IRQ_DB5500_PMU1,
57 .end = IRQ_DB5500_PMU1,
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static struct platform_device db5500_pmu_device = {
63 .name = "arm-pmu",
64 .id = ARM_PMU_DEVICE_CPU,
65 .num_resources = ARRAY_SIZE(db5500_pmu_resources),
66 .resource = db5500_pmu_resources,
67};
68
69static struct resource mbox0_resources[] = { 49static struct resource mbox0_resources[] = {
70 { 50 {
71 .name = "mbox_peer", 51 .name = "mbox_peer",
@@ -151,7 +131,6 @@ static struct platform_device mbox2_device = {
151}; 131};
152 132
153static struct platform_device *db5500_platform_devs[] __initdata = { 133static struct platform_device *db5500_platform_devs[] __initdata = {
154 &db5500_pmu_device,
155 &mbox0_device, 134 &mbox0_device,
156 &mbox1_device, 135 &mbox1_device,
157 &mbox2_device, 136 &mbox2_device,
@@ -192,6 +171,25 @@ void __init u5500_map_io(void)
192 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); 171 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
193} 172}
194 173
174static void __init db5500_pmu_init(void)
175{
176 struct resource res[] = {
177 [0] = {
178 .start = IRQ_DB5500_PMU0,
179 .end = IRQ_DB5500_PMU0,
180 .flags = IORESOURCE_IRQ,
181 },
182 [1] = {
183 .start = IRQ_DB5500_PMU1,
184 .end = IRQ_DB5500_PMU1,
185 .flags = IORESOURCE_IRQ,
186 },
187 };
188
189 platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
190 res, ARRAY_SIZE(res));
191}
192
195static int usb_db5500_rx_dma_cfg[] = { 193static int usb_db5500_rx_dma_cfg[] = {
196 DB5500_DMA_DEV4_USB_OTG_IEP_1_9, 194 DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
197 DB5500_DMA_DEV5_USB_OTG_IEP_2_10, 195 DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
@@ -217,6 +215,7 @@ static int usb_db5500_tx_dma_cfg[] = {
217void __init u5500_init_devices(void) 215void __init u5500_init_devices(void)
218{ 216{
219 db5500_add_gpios(); 217 db5500_add_gpios();
218 db5500_pmu_init();
220 db5500_dma_init(); 219 db5500_dma_init();
221 db5500_add_rtc(); 220 db5500_add_rtc();
222 db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); 221 db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7f2729c05db3..7176ee7491ab 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008-2009 ST-Ericsson 2 * Copyright (C) 2008-2009 ST-Ericsson SA
3 * 3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 * 5 *
@@ -53,19 +53,6 @@ static struct map_desc u8500_io_desc[] __initdata = {
53 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 53 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
54 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
55 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
56};
57
58static struct map_desc u8500_ed_io_desc[] __initdata = {
59 __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
60 __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
61};
62
63static struct map_desc u8500_v1_io_desc[] __initdata = {
64 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
65 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
66};
67
68static struct map_desc u8500_v2_io_desc[] __initdata = {
69 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
70}; 57};
71 58
@@ -80,13 +67,6 @@ void __init u8500_map_io(void)
80 67
81 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 68 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
82 69
83 if (cpu_is_u8500ed())
84 iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
85 else if (cpu_is_u8500v1())
86 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
87 else if (cpu_is_u8500v2())
88 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
89
90 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 70 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
91} 71}
92 72
@@ -155,12 +135,9 @@ static resource_size_t __initdata db8500_gpio_base[] = {
155static void __init db8500_add_gpios(void) 135static void __init db8500_add_gpios(void)
156{ 136{
157 struct nmk_gpio_platform_data pdata = { 137 struct nmk_gpio_platform_data pdata = {
158 /* No custom data yet */ 138 .supports_sleepmode = true,
159 }; 139 };
160 140
161 if (cpu_is_u8500v2())
162 pdata.supports_sleepmode = true;
163
164 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 141 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
165 IRQ_DB8500_GPIO0, &pdata); 142 IRQ_DB8500_GPIO0, &pdata);
166} 143}
@@ -192,9 +169,6 @@ static int usb_db8500_tx_dma_cfg[] = {
192 */ 169 */
193void __init u8500_init_devices(void) 170void __init u8500_init_devices(void)
194{ 171{
195 if (cpu_is_u8500ed())
196 dma40_u8500ed_fixup();
197
198 db8500_add_rtc(); 172 db8500_add_rtc();
199 db8500_add_gpios(); 173 db8500_add_gpios();
200 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 174 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 73b17404b194..a7c6cdc9b11e 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = {
166 .resource = dma40_resources 166 .resource = dma40_resources
167}; 167};
168 168
169void dma40_u8500ed_fixup(void)
170{
171 dma40_plat_data.memcpy = NULL;
172 dma40_plat_data.memcpy_len = 0;
173 dma40_resources[0].start = U8500_DMA_BASE_ED;
174 dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
175 dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
176 dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
177}
178
179struct resource keypad_resources[] = { 169struct resource keypad_resources[] = {
180 [0] = { 170 [0] = {
181 .start = U8500_SKE_BASE, 171 .start = U8500_SKE_BASE,
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index d35122ebc67b..15a0f63b2e2b 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid)
65 * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 65 * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
66 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 66 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
67 * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 67 * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0
68 * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2
68 * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 69 * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0
69 */ 70 */
70 71
@@ -80,9 +81,10 @@ void __init ux500_map_io(void)
80 addr = 0x9001FFF4; 81 addr = 0x9001FFF4;
81 break; 82 break;
82 83
83 case 0x412fc091: /* DB8500v2 / DB5500v1 */ 84 case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
84 asicid = ux500_read_asicid(0x9001DBF4); 85 asicid = ux500_read_asicid(0x9001DBF4);
85 if (partnumber(asicid) == 0x8500) 86 if (partnumber(asicid) == 0x8500 ||
87 partnumber(asicid) == 0x8520)
86 /* DB8500v2 */ 88 /* DB8500v2 */
87 break; 89 break;
88 90
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 994b5fe6f85a..8e714bcb099f 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -65,8 +65,11 @@
65#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) 65#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
66#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) 66#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
67#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) 67#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
68#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000)
68#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) 69#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
69#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) 70#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
71#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000)
72#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000)
70 73
71#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) 74#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
72#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) 75#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
@@ -125,6 +128,7 @@
125#define U5500_ACCCON_BASE (0xBFFF1000) 128#define U5500_ACCCON_BASE (0xBFFF1000)
126#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) 129#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
127#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) 130#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
131#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4)
128 132
129#define U5500_ESRAM_BASE 0x40000000 133#define U5500_ESRAM_BASE 0x40000000
130#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 134#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 751b0e6938d4..80e10f50282e 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -22,7 +22,9 @@
22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
23 23
24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) 24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
25#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) 25
26/* This address fulfills the 256k alignment requirement of the lcla base */
27#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
26 28
27#define U8500_PER3_BASE 0x80000000 29#define U8500_PER3_BASE 0x80000000
28#define U8500_STM_BASE 0x80100000 30#define U8500_STM_BASE 0x80100000
@@ -40,15 +42,14 @@
40#define U8500_ASIC_ID_BASE 0x9001D000 42#define U8500_ASIC_ID_BASE 0x9001D000
41 43
42#define U8500_PER6_BASE 0xa03c0000 44#define U8500_PER6_BASE 0xa03c0000
45#define U8500_PER7_BASE 0xa03d0000
43#define U8500_PER5_BASE 0xa03e0000 46#define U8500_PER5_BASE 0xa03e0000
44#define U8500_PER7_BASE_ED 0xa03d0000
45 47
46#define U8500_SVA_BASE 0xa0100000 48#define U8500_SVA_BASE 0xa0100000
47#define U8500_SIA_BASE 0xa0200000 49#define U8500_SIA_BASE 0xa0200000
48 50
49#define U8500_SGA_BASE 0xa0300000 51#define U8500_SGA_BASE 0xa0300000
50#define U8500_MCDE_BASE 0xa0350000 52#define U8500_MCDE_BASE 0xa0350000
51#define U8500_DMA_BASE_ED 0xa0362000
52#define U8500_DMA_BASE 0x801C0000 /* v1 */ 53#define U8500_DMA_BASE 0x801C0000 /* v1 */
53 54
54#define U8500_SBAG_BASE 0xa0390000 55#define U8500_SBAG_BASE 0xa0390000
@@ -66,13 +67,6 @@
66#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) 67#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
67#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) 68#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
68 69
69/* per7 base addresses */
70#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
71#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
72#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
73#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
74#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
75
76#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) 70#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
77#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) 71#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
78 72
@@ -102,12 +96,10 @@
102#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) 96#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
103#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 97#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
104#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 98#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
105#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
106#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
107#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
108#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) 99#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
109#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) 100#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
110 101#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
102#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
111 103
112/* per3 base addresses */ 104/* per3 base addresses */
113#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 105#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 020b6369a30a..5f6cb71fc62d 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device;
18extern struct platform_device u8500_dma40_device; 18extern struct platform_device u8500_dma40_device;
19extern struct platform_device ux500_ske_keypad_device; 19extern struct platform_device ux500_ske_keypad_device;
20 20
21void dma40_u8500ed_fixup(void);
22
23#endif 21#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 470ac52663d6..b6ba26a1367d 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -10,20 +10,21 @@
10#ifndef __MACH_HARDWARE_H 10#ifndef __MACH_HARDWARE_H
11#define __MACH_HARDWARE_H 11#define __MACH_HARDWARE_H
12 12
13/* macros to get at IO space when running virtually 13/*
14 * Macros to get at IO space when running virtually
14 * We dont map all the peripherals, let ioremap do 15 * We dont map all the peripherals, let ioremap do
15 * this for us. We map only very basic peripherals here. 16 * this for us. We map only very basic peripherals here.
16 */ 17 */
17#define U8500_IO_VIRTUAL 0xf0000000 18#define U8500_IO_VIRTUAL 0xf0000000
18#define U8500_IO_PHYSICAL 0xa0000000 19#define U8500_IO_PHYSICAL 0xa0000000
19 20
20/* this macro is used in assembly, so no cast */ 21/* This macro is used in assembly, so no cast */
21#define IO_ADDRESS(x) \ 22#define IO_ADDRESS(x) \
22 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) 23 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
23 24
24/* typesafe io address */ 25/* typesafe io address */
25#define __io_address(n) __io(IO_ADDRESS(n)) 26#define __io_address(n) __io(IO_ADDRESS(n))
26/* used by some plat-nomadik code */ 27/* Used by some plat-nomadik code */
27#define io_p2v(n) __io_address(n) 28#define io_p2v(n) __io_address(n)
28 29
29#include <mach/db8500-regs.h> 30#include <mach/db8500-regs.h>
@@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE;
36 37
37#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) 38#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
38 39
39#endif 40#endif /* __ASSEMBLY__ */
40
41#endif /* __MACH_HARDWARE_H */ 41#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index 02b541a37ee5..833d6a6edc9b 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void)
47} 47}
48 48
49/* 49/*
50 * 5500 revisions
51 */
52
53static inline bool __attribute_const__ cpu_is_u5500v1(void)
54{
55 return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
56}
57
58static inline bool __attribute_const__ cpu_is_u5500v2(void)
59{
60 return (dbx500_id.revision & 0xf0) == 0xB0;
61}
62
63static inline bool __attribute_const__ cpu_is_u5500v20(void)
64{
65 return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
66}
67
68static inline bool __attribute_const__ cpu_is_u5500v21(void)
69{
70 return cpu_is_u5500() && (dbx500_revision() == 0xB1);
71}
72
73/*
50 * 8500 revisions 74 * 8500 revisions
51 */ 75 */
52 76
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 387a9638991b..b299b8d201c8 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
40#define CK_443X (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_TI816X (1 << 12) 41#define CK_TI816X (1 << 12)
42#define CK_446X (1 << 13) 42#define CK_446X (1 << 13)
43#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
43 44
44 45
45#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 46#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index ebda7382c65b..2efd6454bce0 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -357,7 +357,7 @@
357#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 357#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
358#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 358#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
359#define INT_35XX_USBOTG_IRQ 71 359#define INT_35XX_USBOTG_IRQ 71
360#define INT_35XX_UART4 84 360#define INT_35XX_UART4_IRQ 84
361#define INT_35XX_CCDC_VD0_IRQ 88 361#define INT_35XX_CCDC_VD0_IRQ 88
362#define INT_35XX_CCDC_VD1_IRQ 92 362#define INT_35XX_CCDC_VD1_IRQ 92
363#define INT_35XX_CCDC_VD2_IRQ 93 363#define INT_35XX_CCDC_VD2_IRQ 93
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 581851df1525..80b6d39c31ec 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -44,6 +44,7 @@
44#define OMAP3_UART2_BASE OMAP2_UART2_BASE 44#define OMAP3_UART2_BASE OMAP2_UART2_BASE
45#define OMAP3_UART3_BASE 0x49020000 45#define OMAP3_UART3_BASE 0x49020000
46#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ 46#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
47#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
47 48
48/* OMAP4 serial ports */ 49/* OMAP4 serial ports */
49#define OMAP4_UART1_BASE OMAP2_UART1_BASE 50#define OMAP4_UART1_BASE OMAP2_UART1_BASE
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 8b28664d1c62..6b058a621e8d 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -141,11 +141,9 @@ static void __init omap_detect_sram(void)
141 omap_sram_size = 0x32000; /* 200K */ 141 omap_sram_size = 0x32000; /* 200K */
142 else if (cpu_is_omap15xx()) 142 else if (cpu_is_omap15xx())
143 omap_sram_size = 0x30000; /* 192K */ 143 omap_sram_size = 0x30000; /* 192K */
144 else if (cpu_is_omap1610() || cpu_is_omap1621() || 144 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
145 cpu_is_omap1710()) 145 cpu_is_omap1621() || cpu_is_omap1710())
146 omap_sram_size = 0x4000; /* 16K */ 146 omap_sram_size = 0x4000; /* 16K */
147 else if (cpu_is_omap1611())
148 omap_sram_size = SZ_256K;
149 else { 147 else {
150 pr_err("Could not detect SRAM size\n"); 148 pr_err("Could not detect SRAM size\n");
151 omap_sram_size = 0x4000; 149 omap_sram_size = 0x4000;
@@ -224,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
224void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) 222void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
225{ 223{
226 BUG_ON(!_omap_sram_reprogram_clock); 224 BUG_ON(!_omap_sram_reprogram_clock);
225 /* On 730, bit 13 must always be 1 */
226 if (cpu_is_omap7xx())
227 ckctl |= 0x2000;
227 _omap_sram_reprogram_clock(dpllctl, ckctl); 228 _omap_sram_reprogram_clock(dpllctl, ckctl);
228} 229}
229 230
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 95a5fc53b6db..c20ce0f5ce33 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o time.o common.o mpp.o 5obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
new file mode 100644
index 000000000000..367ca89ac403
--- /dev/null
+++ b/arch/arm/plat-orion/addr-map.c
@@ -0,0 +1,174 @@
1/*
2 * arch/arm/plat-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion based SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/mbus.h>
15#include <linux/io.h>
16#include <plat/addr-map.h>
17
18struct mbus_dram_target_info orion_mbus_dram_info;
19
20const struct mbus_dram_target_info *mv_mbus_dram_info(void)
21{
22 return &orion_mbus_dram_info;
23}
24EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
25
26/*
27 * DDR target is the same on all Orion platforms.
28 */
29#define TARGET_DDR 0
30
31/*
32 * Helpers to get DDR bank info
33 */
34#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
35#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL_OFF 0x0000
41#define WIN_BASE_OFF 0x0004
42#define WIN_REMAP_LO_OFF 0x0008
43#define WIN_REMAP_HI_OFF 0x000c
44
45/*
46 * Default implementation
47 */
48static void __init __iomem *
49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
50{
51 return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
52}
53
54/*
55 * Default implementation
56 */
57static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
58 const int win)
59{
60 if (win < cfg->remappable_wins)
61 return 1;
62
63 return 0;
64}
65
66void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
67 const int win, const u32 base,
68 const u32 size, const u8 target,
69 const u8 attr, const int remap)
70{
71 void __iomem *addr = cfg->win_cfg_base(cfg, win);
72 u32 ctrl, base_high, remap_addr;
73
74 if (win >= cfg->num_wins) {
75 printk(KERN_ERR "setup_cpu_win: trying to allocate window "
76 "%d when only %d allowed\n", win, cfg->num_wins);
77 }
78
79 base_high = base & 0xffff0000;
80 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
81
82 writel(base_high, addr + WIN_BASE_OFF);
83 writel(ctrl, addr + WIN_CTRL_OFF);
84 if (cfg->cpu_win_can_remap(cfg, win)) {
85 if (remap < 0)
86 remap_addr = base;
87 else
88 remap_addr = remap;
89 writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93
94/*
95 * Configure a number of windows.
96 */
97static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
98 const struct orion_addr_map_info *info)
99{
100 while (info->win != -1) {
101 orion_setup_cpu_win(cfg, info->win, info->base, info->size,
102 info->target, info->attr, info->remap);
103 info++;
104 }
105}
106
107static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
108{
109 void __iomem *addr;
110 int i;
111
112 for (i = 0; i < cfg->num_wins; i++) {
113 addr = cfg->win_cfg_base(cfg, i);
114
115 writel(0, addr + WIN_BASE_OFF);
116 writel(0, addr + WIN_CTRL_OFF);
117 if (cfg->cpu_win_can_remap(cfg, i)) {
118 writel(0, addr + WIN_REMAP_LO_OFF);
119 writel(0, addr + WIN_REMAP_HI_OFF);
120 }
121 }
122}
123
124/*
125 * Disable, clear and configure windows.
126 */
127void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
128 const struct orion_addr_map_info *info)
129{
130 if (!cfg->cpu_win_can_remap)
131 cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
132
133 if (!cfg->win_cfg_base)
134 cfg->win_cfg_base = orion_win_cfg_base;
135
136 orion_disable_wins(cfg);
137
138 if (info)
139 orion_setup_cpu_wins(cfg, info);
140}
141
142/*
143 * Setup MBUS dram target info.
144 */
145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
146 const u32 ddr_window_cpu_base)
147{
148 void __iomem *addr;
149 int i;
150 int cs;
151
152 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
153
154 addr = (void __iomem *)ddr_window_cpu_base;
155
156 for (i = 0, cs = 0; i < 4; i++) {
157 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
158 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
159
160 /*
161 * Chip select enabled?
162 */
163 if (size & 1) {
164 struct mbus_dram_window *w;
165
166 w = &orion_mbus_dram_info.cs[cs++];
167 w->cs_index = i;
168 w->mbus_attr = 0xf & ~(1 << i);
169 w->base = base & 0xffff0000;
170 w->size = (size | 0x0000ffff) + 1;
171 }
172 }
173 orion_mbus_dram_info.num_cs = cs;
174}
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 9e5451b3c8e3..e5a2fde29b19 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -13,7 +13,6 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/mbus.h>
17#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
18#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h> 18#include <linux/mv643xx_i2c.h>
@@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase,
203 ****************************************************************************/ 202 ****************************************************************************/
204static __init void ge_complete( 203static __init void ge_complete(
205 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, 204 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
206 struct mbus_dram_target_info *mbus_dram_info, int tclk, 205 int tclk,
207 struct resource *orion_ge_resource, unsigned long irq, 206 struct resource *orion_ge_resource, unsigned long irq,
208 struct platform_device *orion_ge_shared, 207 struct platform_device *orion_ge_shared,
209 struct mv643xx_eth_platform_data *eth_data, 208 struct mv643xx_eth_platform_data *eth_data,
210 struct platform_device *orion_ge) 209 struct platform_device *orion_ge)
211{ 210{
212 orion_ge_shared_data->dram = mbus_dram_info;
213 orion_ge_shared_data->t_clk = tclk; 211 orion_ge_shared_data->t_clk = tclk;
214 orion_ge_resource->start = irq; 212 orion_ge_resource->start = irq;
215 orion_ge_resource->end = irq; 213 orion_ge_resource->end = irq;
@@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = {
259}; 257};
260 258
261void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 259void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
262 struct mbus_dram_target_info *mbus_dram_info,
263 unsigned long mapbase, 260 unsigned long mapbase,
264 unsigned long irq, 261 unsigned long irq,
265 unsigned long irq_err, 262 unsigned long irq_err,
@@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
267{ 264{
268 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, 265 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
269 mapbase + 0x2000, SZ_16K - 1, irq_err); 266 mapbase + 0x2000, SZ_16K - 1, irq_err);
270 ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, 267 ge_complete(&orion_ge00_shared_data, tclk,
271 orion_ge00_resources, irq, &orion_ge00_shared, 268 orion_ge00_resources, irq, &orion_ge00_shared,
272 eth_data, &orion_ge00); 269 eth_data, &orion_ge00);
273} 270}
@@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = {
313}; 310};
314 311
315void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 312void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
316 struct mbus_dram_target_info *mbus_dram_info,
317 unsigned long mapbase, 313 unsigned long mapbase,
318 unsigned long irq, 314 unsigned long irq,
319 unsigned long irq_err, 315 unsigned long irq_err,
@@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
321{ 317{
322 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, 318 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
323 mapbase + 0x2000, SZ_16K - 1, irq_err); 319 mapbase + 0x2000, SZ_16K - 1, irq_err);
324 ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, 320 ge_complete(&orion_ge01_shared_data, tclk,
325 orion_ge01_resources, irq, &orion_ge01_shared, 321 orion_ge01_resources, irq, &orion_ge01_shared,
326 eth_data, &orion_ge01); 322 eth_data, &orion_ge01);
327} 323}
@@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = {
367}; 363};
368 364
369void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 365void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
370 struct mbus_dram_target_info *mbus_dram_info,
371 unsigned long mapbase, 366 unsigned long mapbase,
372 unsigned long irq, 367 unsigned long irq,
373 unsigned long irq_err, 368 unsigned long irq_err,
@@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
375{ 370{
376 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, 371 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
377 mapbase + 0x2000, SZ_16K - 1, irq_err); 372 mapbase + 0x2000, SZ_16K - 1, irq_err);
378 ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, 373 ge_complete(&orion_ge10_shared_data, tclk,
379 orion_ge10_resources, irq, &orion_ge10_shared, 374 orion_ge10_resources, irq, &orion_ge10_shared,
380 eth_data, &orion_ge10); 375 eth_data, &orion_ge10);
381} 376}
@@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = {
421}; 416};
422 417
423void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 418void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
424 struct mbus_dram_target_info *mbus_dram_info,
425 unsigned long mapbase, 419 unsigned long mapbase,
426 unsigned long irq, 420 unsigned long irq,
427 unsigned long irq_err, 421 unsigned long irq_err,
@@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
429{ 423{
430 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, 424 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
431 mapbase + 0x2000, SZ_16K - 1, irq_err); 425 mapbase + 0x2000, SZ_16K - 1, irq_err);
432 ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, 426 ge_complete(&orion_ge11_shared_data, tclk,
433 orion_ge11_resources, irq, &orion_ge11_shared, 427 orion_ge11_resources, irq, &orion_ge11_shared,
434 eth_data, &orion_ge11); 428 eth_data, &orion_ge11);
435} 429}
@@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk)
592/***************************************************************************** 586/*****************************************************************************
593 * XOR 587 * XOR
594 ****************************************************************************/ 588 ****************************************************************************/
595static struct mv_xor_platform_shared_data orion_xor_shared_data;
596
597static u64 orion_xor_dmamask = DMA_BIT_MASK(32); 589static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
598 590
599void __init orion_xor_init_channels( 591void __init orion_xor_init_channels(
@@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = {
632static struct platform_device orion_xor0_shared = { 624static struct platform_device orion_xor0_shared = {
633 .name = MV_XOR_SHARED_NAME, 625 .name = MV_XOR_SHARED_NAME,
634 .id = 0, 626 .id = 0,
635 .dev = {
636 .platform_data = &orion_xor_shared_data,
637 },
638 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), 627 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
639 .resource = orion_xor0_shared_resources, 628 .resource = orion_xor0_shared_resources,
640}; 629};
@@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = {
687 }, 676 },
688}; 677};
689 678
690void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, 679void __init orion_xor0_init(unsigned long mapbase_low,
691 unsigned long mapbase_low,
692 unsigned long mapbase_high, 680 unsigned long mapbase_high,
693 unsigned long irq_0, 681 unsigned long irq_0,
694 unsigned long irq_1) 682 unsigned long irq_1)
695{ 683{
696 orion_xor_shared_data.dram = mbus_dram_info;
697
698 orion_xor0_shared_resources[0].start = mapbase_low; 684 orion_xor0_shared_resources[0].start = mapbase_low;
699 orion_xor0_shared_resources[0].end = mapbase_low + 0xff; 685 orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
700 orion_xor0_shared_resources[1].start = mapbase_high; 686 orion_xor0_shared_resources[1].start = mapbase_high;
@@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = {
727static struct platform_device orion_xor1_shared = { 713static struct platform_device orion_xor1_shared = {
728 .name = MV_XOR_SHARED_NAME, 714 .name = MV_XOR_SHARED_NAME,
729 .id = 1, 715 .id = 1,
730 .dev = {
731 .platform_data = &orion_xor_shared_data,
732 },
733 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), 716 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
734 .resource = orion_xor1_shared_resources, 717 .resource = orion_xor1_shared_resources,
735}; 718};
@@ -828,11 +811,9 @@ static struct platform_device orion_ehci = {
828 }, 811 },
829}; 812};
830 813
831void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, 814void __init orion_ehci_init(unsigned long mapbase,
832 unsigned long mapbase,
833 unsigned long irq) 815 unsigned long irq)
834{ 816{
835 orion_ehci_data.dram = mbus_dram_info;
836 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 817 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
837 irq); 818 irq);
838 819
@@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = {
854 }, 835 },
855}; 836};
856 837
857void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, 838void __init orion_ehci_1_init(unsigned long mapbase,
858 unsigned long mapbase,
859 unsigned long irq) 839 unsigned long irq)
860{ 840{
861 orion_ehci_data.dram = mbus_dram_info;
862 fill_resources(&orion_ehci_1, orion_ehci_1_resources, 841 fill_resources(&orion_ehci_1, orion_ehci_1_resources,
863 mapbase, SZ_4K - 1, irq); 842 mapbase, SZ_4K - 1, irq);
864 843
@@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = {
880 }, 859 },
881}; 860};
882 861
883void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, 862void __init orion_ehci_2_init(unsigned long mapbase,
884 unsigned long mapbase,
885 unsigned long irq) 863 unsigned long irq)
886{ 864{
887 orion_ehci_data.dram = mbus_dram_info;
888 fill_resources(&orion_ehci_2, orion_ehci_2_resources, 865 fill_resources(&orion_ehci_2, orion_ehci_2_resources,
889 mapbase, SZ_4K - 1, irq); 866 mapbase, SZ_4K - 1, irq);
890 867
@@ -911,11 +888,9 @@ static struct platform_device orion_sata = {
911}; 888};
912 889
913void __init orion_sata_init(struct mv_sata_platform_data *sata_data, 890void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
914 struct mbus_dram_target_info *mbus_dram_info,
915 unsigned long mapbase, 891 unsigned long mapbase,
916 unsigned long irq) 892 unsigned long irq)
917{ 893{
918 sata_data->dram = mbus_dram_info;
919 orion_sata.dev.platform_data = sata_data; 894 orion_sata.dev.platform_data = sata_data;
920 fill_resources(&orion_sata, orion_sata_resources, 895 fill_resources(&orion_sata, orion_sata_resources,
921 mapbase, 0x5000 - 1, irq); 896 mapbase, 0x5000 - 1, irq);
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
new file mode 100644
index 000000000000..fd556f77562c
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/plat-orion/include/plat/addr-map.h
3 *
4 * Marvell Orion SoC address map handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_ADDR_MAP_H
12#define __PLAT_ADDR_MAP_H
13
14extern struct mbus_dram_target_info orion_mbus_dram_info;
15
16struct orion_addr_map_cfg {
17 const int num_wins; /* Total number of windows */
18 const int remappable_wins;
19 const u32 bridge_virt_base;
20
21 /* If NULL, the default cpu_win_can_remap will be used, using
22 the value in remappable_wins */
23 int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
24 const int win);
25 /* If NULL, the default win_cfg_base will be used, using the
26 value in bridge_virt_base */
27 void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
28 const int win);
29};
30
31/*
32 * Information needed to setup one address mapping.
33 */
34struct orion_addr_map_info {
35 const int win;
36 const u32 base;
37 const u32 size;
38 const u8 target;
39 const u8 attr;
40 const int remap;
41};
42
43void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
44 const struct orion_addr_map_info *info);
45
46void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
47 const int win, const u32 base,
48 const u32 size, const u8 target,
49 const u8 attr, const int remap);
50
51void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
52 const u32 ddr_window_cpu_base);
53#endif
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 9cf1f781329b..885f8abd927b 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -1,11 +1,8 @@
1#ifndef __PLAT_AUDIO_H 1#ifndef __PLAT_AUDIO_H
2#define __PLAT_AUDIO_H 2#define __PLAT_AUDIO_H
3 3
4#include <linux/mbus.h>
5
6struct kirkwood_asoc_platform_data { 4struct kirkwood_asoc_platform_data {
7 u32 tclk; 5 u32 tclk;
8 struct mbus_dram_target_info *dram;
9 int burst; 6 int burst;
10}; 7};
11#endif 8#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index a63c357e2ab1..0fe08d77e835 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase,
37 unsigned long irq); 37 unsigned long irq);
38 38
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 struct mbus_dram_target_info *mbus_dram_info,
41 unsigned long mapbase, 40 unsigned long mapbase,
42 unsigned long irq, 41 unsigned long irq,
43 unsigned long irq_err, 42 unsigned long irq_err,
44 int tclk); 43 int tclk);
45 44
46void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 45void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
47 struct mbus_dram_target_info *mbus_dram_info,
48 unsigned long mapbase, 46 unsigned long mapbase,
49 unsigned long irq, 47 unsigned long irq,
50 unsigned long irq_err, 48 unsigned long irq_err,
51 int tclk); 49 int tclk);
52 50
53void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 51void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
54 struct mbus_dram_target_info *mbus_dram_info,
55 unsigned long mapbase, 52 unsigned long mapbase,
56 unsigned long irq, 53 unsigned long irq,
57 unsigned long irq_err, 54 unsigned long irq_err,
58 int tclk); 55 int tclk);
59 56
60void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 57void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
61 struct mbus_dram_target_info *mbus_dram_info,
62 unsigned long mapbase, 58 unsigned long mapbase,
63 unsigned long irq, 59 unsigned long irq,
64 unsigned long irq_err, 60 unsigned long irq_err,
@@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase,
82 78
83void __init orion_wdt_init(unsigned long tclk); 79void __init orion_wdt_init(unsigned long tclk);
84 80
85void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, 81void __init orion_xor0_init(unsigned long mapbase_low,
86 unsigned long mapbase_low,
87 unsigned long mapbase_high, 82 unsigned long mapbase_high,
88 unsigned long irq_0, 83 unsigned long irq_0,
89 unsigned long irq_1); 84 unsigned long irq_1);
@@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low,
93 unsigned long irq_0, 88 unsigned long irq_0,
94 unsigned long irq_1); 89 unsigned long irq_1);
95 90
96void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, 91void __init orion_ehci_init(unsigned long mapbase,
97 unsigned long mapbase,
98 unsigned long irq); 92 unsigned long irq);
99 93
100void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, 94void __init orion_ehci_1_init(unsigned long mapbase,
101 unsigned long mapbase,
102 unsigned long irq); 95 unsigned long irq);
103 96
104void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, 97void __init orion_ehci_2_init(unsigned long mapbase,
105 unsigned long mapbase,
106 unsigned long irq); 98 unsigned long irq);
107 99
108void __init orion_sata_init(struct mv_sata_platform_data *sata_data, 100void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
109 struct mbus_dram_target_info *mbus_dram_info,
110 unsigned long mapbase, 101 unsigned long mapbase,
111 unsigned long irq); 102 unsigned long irq);
112 103
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h
index 4ec668e77460..6fc78e430420 100644
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ b/arch/arm/plat-orion/include/plat/ehci-orion.h
@@ -19,7 +19,6 @@ enum orion_ehci_phy_ver {
19}; 19};
20 20
21struct orion_ehci_data { 21struct orion_ehci_data {
22 struct mbus_dram_target_info *dram;
23 enum orion_ehci_phy_ver phy_version; 22 enum orion_ehci_phy_ver phy_version;
24}; 23};
25 24
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h
index bd5f3bdb4ae3..2ba1f7d76eef 100644
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ b/arch/arm/plat-orion/include/plat/mv_xor.h
@@ -13,12 +13,6 @@
13#define MV_XOR_SHARED_NAME "mv_xor_shared" 13#define MV_XOR_SHARED_NAME "mv_xor_shared"
14#define MV_XOR_NAME "mv_xor" 14#define MV_XOR_NAME "mv_xor"
15 15
16struct mbus_dram_target_info;
17
18struct mv_xor_platform_shared_data {
19 struct mbus_dram_target_info *dram;
20};
21
22struct mv_xor_platform_data { 16struct mv_xor_platform_data {
23 struct platform_device *shared; 17 struct platform_device *shared;
24 int hw_id; 18 int hw_id;
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h
index 14ca88676002..1190efedcb94 100644
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ b/arch/arm/plat-orion/include/plat/mvsdio.h
@@ -12,7 +12,6 @@
12#include <linux/mbus.h> 12#include <linux/mbus.h>
13 13
14struct mvsdio_platform_data { 14struct mvsdio_platform_data {
15 struct mbus_dram_target_info *dram;
16 unsigned int clock; 15 unsigned int clock;
17 int gpio_card_detect; 16 int gpio_card_detect;
18 int gpio_write_protect; 17 int gpio_write_protect;
diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
index cc99163e73fd..fe5b9e862747 100644
--- a/arch/arm/plat-orion/include/plat/pcie.h
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base);
20int orion_pcie_get_local_bus_nr(void __iomem *base); 20int orion_pcie_get_local_bus_nr(void __iomem *base);
21void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); 21void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22void orion_pcie_reset(void __iomem *base); 22void orion_pcie_reset(void __iomem *base);
23void orion_pcie_setup(void __iomem *base, 23void orion_pcie_setup(void __iomem *base);
24 struct mbus_dram_target_info *dram);
25int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, 24int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
26 u32 devfn, int where, int size, u32 *val); 25 u32 devfn, int where, int size, u32 *val);
27int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, 26int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index af2d733c50b5..86dbb5bdb172 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
15#include <plat/pcie.h> 15#include <plat/pcie.h>
16#include <plat/addr-map.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
17 18
18/* 19/*
@@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
175 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); 176 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
176} 177}
177 178
178void __init orion_pcie_setup(void __iomem *base, 179void __init orion_pcie_setup(void __iomem *base)
179 struct mbus_dram_target_info *dram)
180{ 180{
181 u16 cmd; 181 u16 cmd;
182 u32 mask; 182 u32 mask;
@@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base,
184 /* 184 /*
185 * Point PCIe unit MBUS decode windows to DRAM space. 185 * Point PCIe unit MBUS decode windows to DRAM space.
186 */ 186 */
187 orion_pcie_setup_wins(base, dram); 187 orion_pcie_setup_wins(base, &orion_mbus_dram_info);
188 188
189 /* 189 /*
190 * Master + slave enable. 190 * Master + slave enable.
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 19:28:07 -0400