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-rw-r--r--arch/arm/mach-s3c24xx/include/mach/irqs.h54
-rw-r--r--arch/arm/mach-s3c24xx/irq.c9
2 files changed, 29 insertions, 34 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index b7a9f4d469e8..ea589e4f0d8b 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,49 @@
59#define IRQ_ADCPARENT S3C2410_IRQ(31) 59#define IRQ_ADCPARENT S3C2410_IRQ(31)
60 60
61/* interrupts generated from the external interrupts sources */ 61/* interrupts generated from the external interrupts sources */
62#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ 62#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
63#define IRQ_EINT5 S3C2410_IRQ(33) 63#define IRQ_EINT5 S3C2410_IRQ(37)
64#define IRQ_EINT6 S3C2410_IRQ(34) 64#define IRQ_EINT6 S3C2410_IRQ(38)
65#define IRQ_EINT7 S3C2410_IRQ(35) 65#define IRQ_EINT7 S3C2410_IRQ(39)
66#define IRQ_EINT8 S3C2410_IRQ(36) 66#define IRQ_EINT8 S3C2410_IRQ(40)
67#define IRQ_EINT9 S3C2410_IRQ(37) 67#define IRQ_EINT9 S3C2410_IRQ(41)
68#define IRQ_EINT10 S3C2410_IRQ(38) 68#define IRQ_EINT10 S3C2410_IRQ(42)
69#define IRQ_EINT11 S3C2410_IRQ(39) 69#define IRQ_EINT11 S3C2410_IRQ(43)
70#define IRQ_EINT12 S3C2410_IRQ(40) 70#define IRQ_EINT12 S3C2410_IRQ(44)
71#define IRQ_EINT13 S3C2410_IRQ(41) 71#define IRQ_EINT13 S3C2410_IRQ(45)
72#define IRQ_EINT14 S3C2410_IRQ(42) 72#define IRQ_EINT14 S3C2410_IRQ(46)
73#define IRQ_EINT15 S3C2410_IRQ(43) 73#define IRQ_EINT15 S3C2410_IRQ(47)
74#define IRQ_EINT16 S3C2410_IRQ(44) 74#define IRQ_EINT16 S3C2410_IRQ(48)
75#define IRQ_EINT17 S3C2410_IRQ(45) 75#define IRQ_EINT17 S3C2410_IRQ(49)
76#define IRQ_EINT18 S3C2410_IRQ(46) 76#define IRQ_EINT18 S3C2410_IRQ(50)
77#define IRQ_EINT19 S3C2410_IRQ(47) 77#define IRQ_EINT19 S3C2410_IRQ(51)
78#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ 78#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
79#define IRQ_EINT21 S3C2410_IRQ(49) 79#define IRQ_EINT21 S3C2410_IRQ(53)
80#define IRQ_EINT22 S3C2410_IRQ(50) 80#define IRQ_EINT22 S3C2410_IRQ(54)
81#define IRQ_EINT23 S3C2410_IRQ(51) 81#define IRQ_EINT23 S3C2410_IRQ(55)
82 82
83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) 83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85 85
86#define IRQ_LCD_FIFO S3C2410_IRQ(52) 86#define IRQ_LCD_FIFO S3C2410_IRQ(56)
87#define IRQ_LCD_FRAME S3C2410_IRQ(53) 87#define IRQ_LCD_FRAME S3C2410_IRQ(57)
88 88
89/* IRQs for the interal UARTs, and ADC 89/* IRQs for the interal UARTs, and ADC
90 * these need to be ordered in number of appearance in the 90 * these need to be ordered in number of appearance in the
91 * SUBSRC mask register 91 * SUBSRC mask register
92*/ 92*/
93 93
94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) 94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
95 95
96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ 96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
99 99
100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ 100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
103 103
104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ 104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
107 107
@@ -136,7 +136,7 @@
136 136
137/* second interrupt-register of s3c2416/s3c2450 */ 137/* second interrupt-register of s3c2416/s3c2450 */
138 138
139#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29) 139#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
140#define IRQ_S3C2416_2D S3C2416_IRQ(0) 140#define IRQ_S3C2416_2D S3C2416_IRQ(0)
141#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) 141#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
142#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) 142#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
index 292f974c5294..c2205eb78dc1 100644
--- a/arch/arm/mach-s3c24xx/irq.c
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -450,7 +450,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
450 void __iomem *base = (void *)0xf6000000; /* static mapping */ 450 void __iomem *base = (void *)0xf6000000; /* static mapping */
451 int irq_num; 451 int irq_num;
452 int irq_start; 452 int irq_start;
453 int irq_offset;
454 int ret; 453 int ret;
455 454
456 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); 455 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
@@ -474,7 +473,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
474 intc->reg_intpnd = base + 0x10; 473 intc->reg_intpnd = base + 0x10;
475 irq_num = 32; 474 irq_num = 32;
476 irq_start = S3C2410_IRQ(0); 475 irq_start = S3C2410_IRQ(0);
477 irq_offset = 0;
478 break; 476 break;
479 case 0x4a000018: 477 case 0x4a000018:
480 pr_debug("irq: found subintc\n"); 478 pr_debug("irq: found subintc\n");
@@ -482,7 +480,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
482 intc->reg_mask = base + 0x1c; 480 intc->reg_mask = base + 0x1c;
483 irq_num = 29; 481 irq_num = 29;
484 irq_start = S3C2410_IRQSUB(0); 482 irq_start = S3C2410_IRQSUB(0);
485 irq_offset = 0;
486 break; 483 break;
487 case 0x4a000040: 484 case 0x4a000040:
488 pr_debug("irq: found intc2\n"); 485 pr_debug("irq: found intc2\n");
@@ -491,7 +488,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
491 intc->reg_intpnd = base + 0x50; 488 intc->reg_intpnd = base + 0x50;
492 irq_num = 8; 489 irq_num = 8;
493 irq_start = S3C2416_IRQ(0); 490 irq_start = S3C2416_IRQ(0);
494 irq_offset = 0;
495 break; 491 break;
496 case 0x560000a4: 492 case 0x560000a4:
497 pr_debug("irq: found eintc\n"); 493 pr_debug("irq: found eintc\n");
@@ -499,9 +495,8 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
499 495
500 intc->reg_mask = base + 0xa4; 496 intc->reg_mask = base + 0xa4;
501 intc->reg_pending = base + 0x08; 497 intc->reg_pending = base + 0x08;
502 irq_num = 20; 498 irq_num = 24;
503 irq_start = S3C2410_IRQ(32); 499 irq_start = S3C2410_IRQ(32);
504 irq_offset = 4;
505 break; 500 break;
506 default: 501 default:
507 pr_err("irq: unsupported controller address\n"); 502 pr_err("irq: unsupported controller address\n");
@@ -512,7 +507,7 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
512 /* now that all the data is complete, init the irq-domain */ 507 /* now that all the data is complete, init the irq-domain */
513 s3c24xx_clear_intc(intc); 508 s3c24xx_clear_intc(intc);
514 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, 509 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
515 irq_offset, &s3c24xx_irq_ops, 510 0, &s3c24xx_irq_ops,
516 intc); 511 intc);
517 if (!intc->domain) { 512 if (!intc->domain) {
518 pr_err("irq: could not create irq-domain\n"); 513 pr_err("irq: could not create irq-domain\n");