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-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c390
1 files changed, 385 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index eea6f8e40289..f53258acd1da 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -18,11 +18,6 @@
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20 20
21/*
22 * To-Do List
23 * -> Populate the Sleep/Wakeup dependencies for the domains
24 */
25
26#include <linux/kernel.h> 21#include <linux/kernel.h>
27#include <linux/io.h> 22#include <linux/io.h>
28 23
@@ -35,6 +30,355 @@
35#include "prcm44xx.h" 30#include "prcm44xx.h"
36#include "prcm_mpu44xx.h" 31#include "prcm_mpu44xx.h"
37 32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep ducati_wkup_sleep_deps[] = {
36 {
37 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
39 },
40 {
41 .clkdm_name = "ivahd_clkdm",
42 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
43 },
44 {
45 .clkdm_name = "l3_1_clkdm",
46 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
47 },
48 {
49 .clkdm_name = "l3_2_clkdm",
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 },
52 {
53 .clkdm_name = "l3_dss_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 },
56 {
57 .clkdm_name = "l3_emif_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 },
60 {
61 .clkdm_name = "l3_gfx_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 },
64 {
65 .clkdm_name = "l3_init_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 },
68 {
69 .clkdm_name = "l4_cfg_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 },
72 {
73 .clkdm_name = "l4_per_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 },
76 {
77 .clkdm_name = "l4_secure_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 },
80 {
81 .clkdm_name = "l4_wkup_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 },
84 {
85 .clkdm_name = "tesla_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 {
93 .clkdm_name = "ivahd_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 },
96 {
97 .clkdm_name = "l3_1_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 },
100 {
101 .clkdm_name = "l3_emif_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 {
109 .clkdm_name = "l3_1_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 },
112 {
113 .clkdm_name = "l3_emif_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 {
121 .clkdm_name = "abe_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 },
124 {
125 .clkdm_name = "ivahd_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 },
128 {
129 .clkdm_name = "l3_1_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 },
132 {
133 .clkdm_name = "l3_2_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 },
136 {
137 .clkdm_name = "l3_emif_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 },
140 {
141 .clkdm_name = "l3_init_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 },
144 {
145 .clkdm_name = "l4_cfg_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 },
148 {
149 .clkdm_name = "l4_per_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 },
152 { NULL },
153};
154
155static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
156 {
157 .clkdm_name = "abe_clkdm",
158 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
159 },
160 {
161 .clkdm_name = "ducati_clkdm",
162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
163 },
164 {
165 .clkdm_name = "ivahd_clkdm",
166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
167 },
168 {
169 .clkdm_name = "l3_1_clkdm",
170 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
171 },
172 {
173 .clkdm_name = "l3_dss_clkdm",
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
175 },
176 {
177 .clkdm_name = "l3_emif_clkdm",
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
179 },
180 {
181 .clkdm_name = "l3_init_clkdm",
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
183 },
184 {
185 .clkdm_name = "l4_cfg_clkdm",
186 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
187 },
188 {
189 .clkdm_name = "l4_per_clkdm",
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
191 },
192 {
193 .clkdm_name = "l4_secure_clkdm",
194 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
195 },
196 {
197 .clkdm_name = "l4_wkup_clkdm",
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
199 },
200 { NULL },
201};
202
203static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
204 {
205 .clkdm_name = "ivahd_clkdm",
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
207 },
208 {
209 .clkdm_name = "l3_2_clkdm",
210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
211 },
212 {
213 .clkdm_name = "l3_emif_clkdm",
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
215 },
216 { NULL },
217};
218
219static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
220 {
221 .clkdm_name = "ivahd_clkdm",
222 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
223 },
224 {
225 .clkdm_name = "l3_1_clkdm",
226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
227 },
228 {
229 .clkdm_name = "l3_emif_clkdm",
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
231 },
232 { NULL },
233};
234
235static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
236 {
237 .clkdm_name = "abe_clkdm",
238 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
239 },
240 {
241 .clkdm_name = "ivahd_clkdm",
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
243 },
244 {
245 .clkdm_name = "l3_emif_clkdm",
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
247 },
248 {
249 .clkdm_name = "l4_cfg_clkdm",
250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
251 },
252 {
253 .clkdm_name = "l4_per_clkdm",
254 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
255 },
256 {
257 .clkdm_name = "l4_secure_clkdm",
258 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
259 },
260 {
261 .clkdm_name = "l4_wkup_clkdm",
262 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
263 },
264 { NULL },
265};
266
267static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
268 {
269 .clkdm_name = "l3_1_clkdm",
270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
271 },
272 {
273 .clkdm_name = "l3_emif_clkdm",
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
275 },
276 {
277 .clkdm_name = "l4_per_clkdm",
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
279 },
280 { NULL },
281};
282
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
284 {
285 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
287 },
288 {
289 .clkdm_name = "ducati_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
291 },
292 {
293 .clkdm_name = "ivahd_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
295 },
296 {
297 .clkdm_name = "l3_1_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
299 },
300 {
301 .clkdm_name = "l3_2_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
303 },
304 {
305 .clkdm_name = "l3_dss_clkdm",
306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
307 },
308 {
309 .clkdm_name = "l3_emif_clkdm",
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
311 },
312 {
313 .clkdm_name = "l3_gfx_clkdm",
314 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
315 },
316 {
317 .clkdm_name = "l3_init_clkdm",
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
319 },
320 {
321 .clkdm_name = "l4_cfg_clkdm",
322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
323 },
324 {
325 .clkdm_name = "l4_per_clkdm",
326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
327 },
328 {
329 .clkdm_name = "l4_secure_clkdm",
330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
331 },
332 {
333 .clkdm_name = "l4_wkup_clkdm",
334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
335 },
336 {
337 .clkdm_name = "tesla_clkdm",
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
339 },
340 { NULL },
341};
342
343static struct clkdm_dep tesla_wkup_sleep_deps[] = {
344 {
345 .clkdm_name = "abe_clkdm",
346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
347 },
348 {
349 .clkdm_name = "ivahd_clkdm",
350 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
351 },
352 {
353 .clkdm_name = "l3_1_clkdm",
354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
355 },
356 {
357 .clkdm_name = "l3_2_clkdm",
358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
359 },
360 {
361 .clkdm_name = "l3_emif_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
363 },
364 {
365 .clkdm_name = "l3_init_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
367 },
368 {
369 .clkdm_name = "l4_cfg_clkdm",
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
371 },
372 {
373 .clkdm_name = "l4_per_clkdm",
374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
375 },
376 {
377 .clkdm_name = "l4_wkup_clkdm",
378 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
379 },
380 { NULL },
381};
38 382
39static struct clockdomain l4_cefuse_44xx_clkdm = { 383static struct clockdomain l4_cefuse_44xx_clkdm = {
40 .name = "l4_cefuse_clkdm", 384 .name = "l4_cefuse_clkdm",
@@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
52 .prcm_partition = OMAP4430_CM2_PARTITION, 396 .prcm_partition = OMAP4430_CM2_PARTITION,
53 .cm_inst = OMAP4430_CM2_CORE_INST, 397 .cm_inst = OMAP4430_CM2_CORE_INST,
54 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, 398 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
399 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
55 .flags = CLKDM_CAN_HWSUP, 400 .flags = CLKDM_CAN_HWSUP,
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
57}; 402};
@@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = {
62 .prcm_partition = OMAP4430_CM1_PARTITION, 407 .prcm_partition = OMAP4430_CM1_PARTITION,
63 .cm_inst = OMAP4430_CM1_TESLA_INST, 408 .cm_inst = OMAP4430_CM1_TESLA_INST,
64 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, 409 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
410 .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
411 .wkdep_srcs = tesla_wkup_sleep_deps,
412 .sleepdep_srcs = tesla_wkup_sleep_deps,
65 .flags = CLKDM_CAN_HWSUP_SWSUP, 413 .flags = CLKDM_CAN_HWSUP_SWSUP,
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
67}; 415};
@@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
72 .prcm_partition = OMAP4430_CM2_PARTITION, 420 .prcm_partition = OMAP4430_CM2_PARTITION,
73 .cm_inst = OMAP4430_CM2_GFX_INST, 421 .cm_inst = OMAP4430_CM2_GFX_INST,
74 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, 422 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
423 .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
424 .wkdep_srcs = l3_gfx_wkup_sleep_deps,
425 .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
75 .flags = CLKDM_CAN_HWSUP_SWSUP, 426 .flags = CLKDM_CAN_HWSUP_SWSUP,
76 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 427 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
77}; 428};
@@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
82 .prcm_partition = OMAP4430_CM2_PARTITION, 433 .prcm_partition = OMAP4430_CM2_PARTITION,
83 .cm_inst = OMAP4430_CM2_IVAHD_INST, 434 .cm_inst = OMAP4430_CM2_IVAHD_INST,
84 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, 435 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
436 .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
437 .wkdep_srcs = ivahd_wkup_sleep_deps,
438 .sleepdep_srcs = ivahd_wkup_sleep_deps,
85 .flags = CLKDM_CAN_HWSUP_SWSUP, 439 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
87}; 441};
@@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
92 .prcm_partition = OMAP4430_CM2_PARTITION, 446 .prcm_partition = OMAP4430_CM2_PARTITION,
93 .cm_inst = OMAP4430_CM2_L4PER_INST, 447 .cm_inst = OMAP4430_CM2_L4PER_INST,
94 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, 448 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
449 .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
450 .wkdep_srcs = l4_secure_wkup_sleep_deps,
451 .sleepdep_srcs = l4_secure_wkup_sleep_deps,
95 .flags = CLKDM_CAN_HWSUP_SWSUP, 452 .flags = CLKDM_CAN_HWSUP_SWSUP,
96 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
97}; 454};
@@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
102 .prcm_partition = OMAP4430_CM2_PARTITION, 459 .prcm_partition = OMAP4430_CM2_PARTITION,
103 .cm_inst = OMAP4430_CM2_L4PER_INST, 460 .cm_inst = OMAP4430_CM2_L4PER_INST,
104 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, 461 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
462 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
105 .flags = CLKDM_CAN_HWSUP_SWSUP, 463 .flags = CLKDM_CAN_HWSUP_SWSUP,
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
107}; 465};
@@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = {
112 .prcm_partition = OMAP4430_CM1_PARTITION, 470 .prcm_partition = OMAP4430_CM1_PARTITION,
113 .cm_inst = OMAP4430_CM1_ABE_INST, 471 .cm_inst = OMAP4430_CM1_ABE_INST,
114 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, 472 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
473 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
115 .flags = CLKDM_CAN_HWSUP_SWSUP, 474 .flags = CLKDM_CAN_HWSUP_SWSUP,
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 475 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
117}; 476};
@@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
131 .prcm_partition = OMAP4430_CM2_PARTITION, 490 .prcm_partition = OMAP4430_CM2_PARTITION,
132 .cm_inst = OMAP4430_CM2_L3INIT_INST, 491 .cm_inst = OMAP4430_CM2_L3INIT_INST,
133 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, 492 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
493 .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
494 .wkdep_srcs = l3_init_wkup_sleep_deps,
495 .sleepdep_srcs = l3_init_wkup_sleep_deps,
134 .flags = CLKDM_CAN_HWSUP_SWSUP, 496 .flags = CLKDM_CAN_HWSUP_SWSUP,
135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
136}; 498};
@@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = {
141 .prcm_partition = OMAP4430_CM1_PARTITION, 503 .prcm_partition = OMAP4430_CM1_PARTITION,
142 .cm_inst = OMAP4430_CM1_MPU_INST, 504 .cm_inst = OMAP4430_CM1_MPU_INST,
143 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps,
144 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
145 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
146}; 510};
@@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
171 .prcm_partition = OMAP4430_CM2_PARTITION, 535 .prcm_partition = OMAP4430_CM2_PARTITION,
172 .cm_inst = OMAP4430_CM2_CORE_INST, 536 .cm_inst = OMAP4430_CM2_CORE_INST,
173 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, 537 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
538 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
174 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 539 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 540 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
176}; 541};
@@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = {
191 .prcm_partition = OMAP4430_CM2_PARTITION, 556 .prcm_partition = OMAP4430_CM2_PARTITION,
192 .cm_inst = OMAP4430_CM2_CORE_INST, 557 .cm_inst = OMAP4430_CM2_CORE_INST,
193 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, 558 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
559 .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
560 .wkdep_srcs = ducati_wkup_sleep_deps,
561 .sleepdep_srcs = ducati_wkup_sleep_deps,
194 .flags = CLKDM_CAN_HWSUP_SWSUP, 562 .flags = CLKDM_CAN_HWSUP_SWSUP,
195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
196}; 564};
@@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
201 .prcm_partition = OMAP4430_CM2_PARTITION, 569 .prcm_partition = OMAP4430_CM2_PARTITION,
202 .cm_inst = OMAP4430_CM2_CORE_INST, 570 .cm_inst = OMAP4430_CM2_CORE_INST,
203 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, 571 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
572 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
204 .flags = CLKDM_CAN_HWSUP, 573 .flags = CLKDM_CAN_HWSUP,
205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
206}; 575};
@@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
211 .prcm_partition = OMAP4430_CM2_PARTITION, 580 .prcm_partition = OMAP4430_CM2_PARTITION,
212 .cm_inst = OMAP4430_CM2_CORE_INST, 581 .cm_inst = OMAP4430_CM2_CORE_INST,
213 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, 582 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
583 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
214 .flags = CLKDM_CAN_HWSUP, 584 .flags = CLKDM_CAN_HWSUP,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216}; 586};
@@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
221 .prcm_partition = OMAP4430_CM2_PARTITION, 591 .prcm_partition = OMAP4430_CM2_PARTITION,
222 .cm_inst = OMAP4430_CM2_CORE_INST, 592 .cm_inst = OMAP4430_CM2_CORE_INST,
223 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, 593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
224 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
225 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
226}; 598};
@@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = {
231 .prcm_partition = OMAP4430_CM2_PARTITION, 603 .prcm_partition = OMAP4430_CM2_PARTITION,
232 .cm_inst = OMAP4430_CM2_CAM_INST, 604 .cm_inst = OMAP4430_CM2_CAM_INST,
233 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, 605 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
606 .wkdep_srcs = iss_wkup_sleep_deps,
607 .sleepdep_srcs = iss_wkup_sleep_deps,
234 .flags = CLKDM_CAN_HWSUP_SWSUP, 608 .flags = CLKDM_CAN_HWSUP_SWSUP,
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
236}; 610};
@@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
241 .prcm_partition = OMAP4430_CM2_PARTITION, 615 .prcm_partition = OMAP4430_CM2_PARTITION,
242 .cm_inst = OMAP4430_CM2_DSS_INST, 616 .cm_inst = OMAP4430_CM2_DSS_INST,
243 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, 617 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
618 .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
619 .wkdep_srcs = l3_dss_wkup_sleep_deps,
620 .sleepdep_srcs = l3_dss_wkup_sleep_deps,
244 .flags = CLKDM_CAN_HWSUP_SWSUP, 621 .flags = CLKDM_CAN_HWSUP_SWSUP,
245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
246}; 623};
@@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
251 .prcm_partition = OMAP4430_PRM_PARTITION, 628 .prcm_partition = OMAP4430_PRM_PARTITION,
252 .cm_inst = OMAP4430_PRM_WKUP_CM_INST, 629 .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
253 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 630 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
631 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
254 .flags = CLKDM_CAN_HWSUP, 632 .flags = CLKDM_CAN_HWSUP,
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256}; 634};
@@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = {
271 .prcm_partition = OMAP4430_CM2_PARTITION, 649 .prcm_partition = OMAP4430_CM2_PARTITION,
272 .cm_inst = OMAP4430_CM2_CORE_INST, 650 .cm_inst = OMAP4430_CM2_CORE_INST,
273 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, 651 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
652 .wkdep_srcs = l3_dma_wkup_sleep_deps,
653 .sleepdep_srcs = l3_dma_wkup_sleep_deps,
274 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 654 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
276}; 656};
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 05:07:59 -0500