10 files changed, 32 insertions, 52 deletions

diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 4553ffd94b1f..361f2e7ccb12 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -642,12 +642,12 @@ void __devinit cpu_init(void)
         asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
 
         /* Clear all 6 debug registers: */
-
-#define CD(register) set_debugreg(0, register)
-
-        CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
-
-#undef CD
+        set_debugreg(0, 0);
+        set_debugreg(0, 1);
+        set_debugreg(0, 2);
+        set_debugreg(0, 3);
+        set_debugreg(0, 6);
+        set_debugreg(0, 7);
 
         /*
          * Force FPU initialization:
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c
index 04e3563da4fe..bf02b5026e62 100644
--- a/arch/i386/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c
@@ -64,8 +64,6 @@ static int dont_scale_voltage;
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
 
 
-#define __hlt()     __asm__ __volatile__("hlt": : :"memory")
-
 /* Clock ratios multiplied by 10 */
 static int clock_ratio[32];
 static int eblcr_table[32];
@@ -168,11 +166,9 @@ static void do_powersaver(union msr_longhaul *longhaul,
         outb(0xFE,0x21);        /* TMR0 only */
         outb(0xFF,0x80);        /* delay */
 
-        local_irq_enable();
-
-        __hlt();
+        safe_halt();
         wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
-        __hlt();
+        halt();
 
         local_irq_disable();
 
@@ -251,9 +247,7 @@ static void longhaul_setstate(unsigned int clock_ratio_index)
                 bcr2.bits.CLOCKMUL = clock_ratio_index;
                 local_irq_disable();
                 wrmsrl (MSR_VIA_BCR2, bcr2.val);
-                local_irq_enable();
-
-                __hlt();
+                safe_halt();
 
                 /* Disable software clock multiplier */
                 rdmsrl (MSR_VIA_BCR2, bcr2.val);
diff --git a/arch/i386/kernel/cpu/cyrix.c b/arch/i386/kernel/cpu/cyrix.c
index ba4b01138c8f..ff87cc22b323 100644
--- a/arch/i386/kernel/cpu/cyrix.c
+++ b/arch/i386/kernel/cpu/cyrix.c
@@ -132,11 +132,7 @@ static void __init set_cx86_memwb(void)
         setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
         /* set 'Not Write-through' */
         cr0 = 0x20000000;
-        __asm__("movl %%cr0,%%eax\n\t"
-                "orl %0,%%eax\n\t"
-                "movl %%eax,%%cr0\n"
-                : : "r" (cr0)
-                :"ax");
+        write_cr0(read_cr0() | cr0);
         /* CCR2 bit 2: lock NW bit and set WT1 */
         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
 }
diff --git a/arch/i386/kernel/efi.c b/arch/i386/kernel/efi.c
index 850648ae8305..921fdb15fc9b 100644
--- a/arch/i386/kernel/efi.c
+++ b/arch/i386/kernel/efi.c
@@ -79,7 +79,7 @@ static void efi_call_phys_prelog(void)
          * directory. If I have PSE, I just need to duplicate one entry in
          * page directory.
          */
-        __asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
+        cr4 = read_cr4();
 
         if (cr4 & X86_CR4_PSE) {
                 efi_bak_pg_dir_pointer[0].pgd =
@@ -115,7 +115,7 @@ static void efi_call_phys_epilog(void)
         cpu_gdt_descr[0].address =
                 (unsigned long) __va(cpu_gdt_descr[0].address);
         __asm__ __volatile__("lgdt %0":"=m"(cpu_gdt_descr));
-        __asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));
+        cr4 = read_cr4();
 
         if (cr4 & X86_CR4_PSE) {
                 swapper_pg_dir[pgd_index(0)].pgd =
diff --git a/arch/i386/kernel/machine_kexec.c b/arch/i386/kernel/machine_kexec.c
index cb699a2aa1f8..f19f6d34bcbf 100644
--- a/arch/i386/kernel/machine_kexec.c
+++ b/arch/i386/kernel/machine_kexec.c
@@ -17,13 +17,7 @@
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
 #include <asm/desc.h>
-
-static inline unsigned long read_cr3(void)
-{
-        unsigned long cr3;
-        asm volatile("movl %%cr3,%0": "=r"(cr3));
-        return cr3;
-}
+#include <asm/system.h>
 
 #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
 
diff --git a/arch/i386/kernel/process.c b/arch/i386/kernel/process.c
index e3f362e8af5b..761d4ed47ef3 100644
--- a/arch/i386/kernel/process.c
+++ b/arch/i386/kernel/process.c
@@ -313,16 +313,12 @@ void show_regs(struct pt_regs * regs)
         printk(" DS: %04x ES: %04x\n",
                 0xffff & regs->xds,0xffff & regs->xes);
 
-        __asm__("movl %%cr0, %0": "=r" (cr0));
-        __asm__("movl %%cr2, %0": "=r" (cr2));
-        __asm__("movl %%cr3, %0": "=r" (cr3));
-        /* This could fault if %cr4 does not exist */
-        __asm__("1: movl %%cr4, %0              \n"
-                "2:                             \n"
-                ".section __ex_table,\"a\"      \n"
-                ".long 1b,2b                    \n"
-                ".previous                      \n"
-                : "=r" (cr4): "0" (0));
+        cr0 = read_cr0();
+        cr2 = read_cr2();
+        cr3 = read_cr3();
+        if (current_cpu_data.x86 > 4) {
+                cr4 = read_cr4();
+        }
         printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);
         show_trace(NULL, &regs->esp);
 }
diff --git a/arch/i386/kernel/smp.c b/arch/i386/kernel/smp.c
index cec4bde67161..48b55db3680f 100644
--- a/arch/i386/kernel/smp.c
+++ b/arch/i386/kernel/smp.c
@@ -576,7 +576,7 @@ static void stop_this_cpu (void * dummy)
         local_irq_disable();
         disable_local_APIC();
         if (cpu_data[smp_processor_id()].hlt_works_ok)
-                for(;;) __asm__("hlt");
+                for(;;) halt();
         for (;;);
 }
 
diff --git a/arch/i386/mm/fault.c b/arch/i386/mm/fault.c
index 61d9e34af5a6..411b8500ad1b 100644
--- a/arch/i386/mm/fault.c
+++ b/arch/i386/mm/fault.c
@@ -233,7 +233,7 @@ fastcall void do_page_fault(struct pt_regs *regs, unsigned long error_code)
         int write, si_code;
 
         /* get the address */
-        __asm__("movl %%cr2,%0":"=r" (address));
+        address = read_cr2();
 
         if (notify_die(DIE_PAGE_FAULT, "page fault", regs, error_code, 14,
                                         SIGSEGV) == NOTIFY_STOP)
@@ -453,7 +453,7 @@ no_context:
         printk(" at virtual address %08lx\n",address);
         printk(KERN_ALERT " printing eip:\n");
         printk("%08lx\n", regs->eip);
-        asm("movl %%cr3,%0":"=r" (page));
+        page = read_cr3();
         page = ((unsigned long *) __va(page))[address >> 22];
         printk(KERN_ALERT "*pde = %08lx\n", page);
         /*
@@ -526,7 +526,7 @@ vmalloc_fault:
                 pmd_t *pmd, *pmd_k;
                 pte_t *pte_k;
 
-                asm("movl %%cr3,%0":"=r" (pgd_paddr));
+                pgd_paddr = read_cr3();
                 pgd = index + (pgd_t *)__va(pgd_paddr);
                 pgd_k = init_mm.pgd + index;
 
diff --git a/arch/i386/mm/pageattr.c b/arch/i386/mm/pageattr.c
index cb3da6baa704..bce06a79eafa 100644
--- a/arch/i386/mm/pageattr.c
+++ b/arch/i386/mm/pageattr.c
@@ -62,7 +62,7 @@ static void flush_kernel_map(void *dummy)
 { 
         /* Could use CLFLUSH here if the CPU supports it (Hammer,P4) */
         if (boot_cpu_data.x86_model >= 4) 
-                asm volatile("wbinvd":::"memory"); 
+                wbinvd();
         /* Flush all to work around Errata in early athlons regarding 
          * large page flushing. 
          */
diff --git a/arch/i386/power/cpu.c b/arch/i386/power/cpu.c
index c547c1af6fa1..4e19c43e0954 100644
--- a/arch/i386/power/cpu.c
+++ b/arch/i386/power/cpu.c
@@ -57,10 +57,10 @@ void __save_processor_state(struct saved_context *ctxt)
         /*
          * control registers 
          */
-        asm volatile ("movl %%cr0, %0" : "=r" (ctxt->cr0));
-        asm volatile ("movl %%cr2, %0" : "=r" (ctxt->cr2));
-        asm volatile ("movl %%cr3, %0" : "=r" (ctxt->cr3));
-        asm volatile ("movl %%cr4, %0" : "=r" (ctxt->cr4));
+        ctxt->cr0 = read_cr0();
+        ctxt->cr2 = read_cr2();
+        ctxt->cr3 = read_cr3();
+        ctxt->cr4 = read_cr4();
 }
 
 void save_processor_state(void)
@@ -109,10 +109,10 @@ void __restore_processor_state(struct saved_context *ctxt)
         /*
          * control registers
          */
-        asm volatile ("movl %0, %%cr4" :: "r" (ctxt->cr4));
-        asm volatile ("movl %0, %%cr3" :: "r" (ctxt->cr3));
-        asm volatile ("movl %0, %%cr2" :: "r" (ctxt->cr2));
-        asm volatile ("movl %0, %%cr0" :: "r" (ctxt->cr0));
+        write_cr4(ctxt->cr4);
+        write_cr3(ctxt->cr3);
+        write_cr2(ctxt->cr2);
+        write_cr2(ctxt->cr0);
 
         /*
          * now restore the descriptor tables to their proper values