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-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/boot/compressed/Makefile5
-rw-r--r--arch/arm/boot/compressed/head.S6
-rw-r--r--arch/arm/include/asm/cputype.h25
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h2
-rw-r--r--arch/arm/include/asm/processor.h1
-rw-r--r--arch/arm/include/asm/ptrace.h17
-rw-r--r--arch/arm/include/asm/tlbflush.h26
-rw-r--r--arch/arm/kernel/entry-armv.S3
-rw-r--r--arch/arm/kernel/entry-common.S3
-rw-r--r--arch/arm/kernel/process.c2
-rw-r--r--arch/arm/kernel/signal.c8
-rw-r--r--arch/arm/kernel/smp.c69
-rw-r--r--arch/arm/kernel/vmlinux.lds.S2
-rw-r--r--arch/arm/mach-realview/Kconfig16
-rw-r--r--arch/arm/mach-realview/Makefile1
-rw-r--r--arch/arm/mach-realview/core.c10
-rw-r--r--arch/arm/mach-realview/include/mach/board-eb.h105
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb1176.h80
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb11mp.h101
-rw-r--r--arch/arm/mach-realview/include/mach/board-pba8.h77
-rw-r--r--arch/arm/mach-realview/include/mach/board-pbx.h108
-rw-r--r--arch/arm/mach-realview/include/mach/debug-macro.S3
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-eb.h129
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pb1176.h99
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pb11mp.h122
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pba8.h98
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pbx.h115
-rw-r--r--arch/arm/mach-realview/include/mach/irqs.h9
-rw-r--r--arch/arm/mach-realview/include/mach/uncompress.h3
-rw-r--r--arch/arm/mach-realview/platsmp.c4
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c23
-rw-r--r--arch/arm/mach-realview/realview_pbx.c335
-rw-r--r--arch/arm/mm/Kconfig20
-rw-r--r--arch/arm/mm/abort-ev6.S3
-rw-r--r--arch/arm/mm/proc-v6.S3
-rw-r--r--arch/arm/mm/proc-v7.S59
-rw-r--r--arch/arm/mm/tlb-v7.S17
-rw-r--r--arch/arm/oprofile/op_model_mpcore.c1
-rw-r--r--arch/arm/vfp/vfphw.S4
-rw-r--r--arch/arm/vfp/vfpmodule.c2
42 files changed, 1298 insertions, 429 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 430d2b756165..c857111ab964 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -849,7 +849,8 @@ source "kernel/time/Kconfig"
849 849
850config SMP 850config SMP
851 bool "Symmetric Multi-Processing (EXPERIMENTAL)" 851 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
852 depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP ||ARCH_OMAP4) 852 depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
853 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
853 depends on GENERIC_CLOCKEVENTS 854 depends on GENERIC_CLOCKEVENTS
854 select USE_GENERIC_SMP_HELPERS 855 select USE_GENERIC_SMP_HELPERS
855 select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4) 856 select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
@@ -920,7 +921,8 @@ config HOTPLUG_CPU
920 921
921config LOCAL_TIMERS 922config LOCAL_TIMERS
922 bool "Use local timer interrupts" 923 bool "Use local timer interrupts"
923 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP || ARCH_OMAP4) 924 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
925 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
924 default y 926 default y
925 select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4) 927 select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
926 help 928 help
@@ -1031,7 +1033,7 @@ config LEDS
1031 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1033 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1032 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1034 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1033 ARCH_AT91 || ARCH_DAVINCI || \ 1035 ARCH_AT91 || ARCH_DAVINCI || \
1034 ARCH_KS8695 || MACH_RD88F5182 1036 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1035 help 1037 help
1036 If you say Y here, the LEDs on your machine will be used 1038 If you say Y here, the LEDs on your machine will be used
1037 to provide useful information about your current system status. 1039 to provide useful information about your current system status.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e8ab87750e9b..0c25f2cb73a1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -11,6 +11,9 @@
11# Copyright (C) 1995-2001 by Russell King 11# Copyright (C) 1995-2001 by Russell King
12 12
13LDFLAGS_vmlinux :=-p --no-undefined -X 13LDFLAGS_vmlinux :=-p --no-undefined -X
14ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
15LDFLAGS_vmlinux += --be8
16endif
14CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) 17CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
15OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S 18OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
16GZFLAGS :=-9 19GZFLAGS :=-9
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index fbe5eef1f6c9..ce39dc540085 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -40,7 +40,7 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
40OBJS += head-sharpsl.o 40OBJS += head-sharpsl.o
41endif 41endif
42 42
43ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 43ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
44ifeq ($(CONFIG_CPU_CP15),y) 44ifeq ($(CONFIG_CPU_CP15),y)
45OBJS += big-endian.o 45OBJS += big-endian.o
46else 46else
@@ -78,6 +78,9 @@ EXTRA_AFLAGS := -Wa,-march=all
78# linker symbols. We only define initrd_phys and params_phys if the 78# linker symbols. We only define initrd_phys and params_phys if the
79# machine class defined the corresponding makefile variable. 79# machine class defined the corresponding makefile variable.
80LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) 80LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
81ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
82LDFLAGS_vmlinux += --be8
83endif
81ifneq ($(INITRD_PHYS),) 84ifneq ($(INITRD_PHYS),)
82LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) 85LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
83endif 86endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b371fba1b954..01d49be3b2ca 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -438,6 +438,9 @@ __armv4_mmu_cache_on:
438 mrc p15, 0, r0, c1, c0, 0 @ read control reg 438 mrc p15, 0, r0, c1, c0, 0 @ read control reg
439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
440 orr r0, r0, #0x0030 440 orr r0, r0, #0x0030
441#ifdef CONFIG_CPU_ENDIAN_BE8
442 orr r0, r0, #1 << 25 @ big-endian page tables
443#endif
441 bl __common_mmu_cache_on 444 bl __common_mmu_cache_on
442 mov r0, #0 445 mov r0, #0
443 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 446 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
@@ -455,6 +458,9 @@ __armv7_mmu_cache_on:
455 mrc p15, 0, r0, c1, c0, 0 @ read control reg 458 mrc p15, 0, r0, c1, c0, 0 @ read control reg
456 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 459 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
457 orr r0, r0, #0x003c @ write buffer 460 orr r0, r0, #0x003c @ write buffer
461#ifdef CONFIG_CPU_ENDIAN_BE8
462 orr r0, r0, #1 << 25 @ big-endian page tables
463#endif
458 orrne r0, r0, #1 @ MMU enabled 464 orrne r0, r0, #1 @ MMU enabled
459 movne r1, #-1 465 movne r1, #-1
460 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 466 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7b9d27e749b8..b3e656c6fb78 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,21 @@
8#define CPUID_TCM 2 8#define CPUID_TCM 2
9#define CPUID_TLBTYPE 3 9#define CPUID_TLBTYPE 3
10 10
11#define CPUID_EXT_PFR0 "c1, 0"
12#define CPUID_EXT_PFR1 "c1, 1"
13#define CPUID_EXT_DFR0 "c1, 2"
14#define CPUID_EXT_AFR0 "c1, 3"
15#define CPUID_EXT_MMFR0 "c1, 4"
16#define CPUID_EXT_MMFR1 "c1, 5"
17#define CPUID_EXT_MMFR2 "c1, 6"
18#define CPUID_EXT_MMFR3 "c1, 7"
19#define CPUID_EXT_ISAR0 "c2, 0"
20#define CPUID_EXT_ISAR1 "c2, 1"
21#define CPUID_EXT_ISAR2 "c2, 2"
22#define CPUID_EXT_ISAR3 "c2, 3"
23#define CPUID_EXT_ISAR4 "c2, 4"
24#define CPUID_EXT_ISAR5 "c2, 5"
25
11#ifdef CONFIG_CPU_CP15 26#ifdef CONFIG_CPU_CP15
12#define read_cpuid(reg) \ 27#define read_cpuid(reg) \
13 ({ \ 28 ({ \
@@ -18,9 +33,19 @@
18 : "cc"); \ 33 : "cc"); \
19 __val; \ 34 __val; \
20 }) 35 })
36#define read_cpuid_ext(ext_reg) \
37 ({ \
38 unsigned int __val; \
39 asm("mrc p15, 0, %0, c0, " ext_reg \
40 : "=r" (__val) \
41 : \
42 : "cc"); \
43 __val; \
44 })
21#else 45#else
22extern unsigned int processor_id; 46extern unsigned int processor_id;
23#define read_cpuid(reg) (processor_id) 47#define read_cpuid(reg) (processor_id)
48#define read_cpuid_ext(reg) 0
24#endif 49#endif
25 50
26/* 51/*
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 64f2252a25cd..cdb9022716fd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -24,6 +24,8 @@
24#define L2X0_CACHE_TYPE 0x004 24#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100 25#define L2X0_CTRL 0x100
26#define L2X0_AUX_CTRL 0x104 26#define L2X0_AUX_CTRL 0x104
27#define L2X0_TAG_LATENCY_CTRL 0x108
28#define L2X0_DATA_LATENCY_CTRL 0x10C
27#define L2X0_EVENT_CNT_CTRL 0x200 29#define L2X0_EVENT_CNT_CTRL 0x200
28#define L2X0_EVENT_CNT1_CFG 0x204 30#define L2X0_EVENT_CNT1_CFG 0x204
29#define L2X0_EVENT_CNT0_CFG 0x208 31#define L2X0_EVENT_CNT0_CFG 0x208
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 1845892260e7..6a89567ffc5b 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -71,6 +71,7 @@ struct thread_struct {
71 regs->ARM_cpsr = USR26_MODE; \ 71 regs->ARM_cpsr = USR26_MODE; \
72 if (elf_hwcap & HWCAP_THUMB && pc & 1) \ 72 if (elf_hwcap & HWCAP_THUMB && pc & 1) \
73 regs->ARM_cpsr |= PSR_T_BIT; \ 73 regs->ARM_cpsr |= PSR_T_BIT; \
74 regs->ARM_cpsr |= PSR_ENDSTATE; \
74 regs->ARM_pc = pc & ~1; /* pc */ \ 75 regs->ARM_pc = pc & ~1; /* pc */ \
75 regs->ARM_sp = sp; /* sp */ \ 76 regs->ARM_sp = sp; /* sp */ \
76 regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ 77 regs->ARM_r2 = stack[2]; /* r2 (envp) */ \
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 236a06b9b7ce..67b833c9b6b9 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -50,6 +50,7 @@
50#define PSR_F_BIT 0x00000040 50#define PSR_F_BIT 0x00000040
51#define PSR_I_BIT 0x00000080 51#define PSR_I_BIT 0x00000080
52#define PSR_A_BIT 0x00000100 52#define PSR_A_BIT 0x00000100
53#define PSR_E_BIT 0x00000200
53#define PSR_J_BIT 0x01000000 54#define PSR_J_BIT 0x01000000
54#define PSR_Q_BIT 0x08000000 55#define PSR_Q_BIT 0x08000000
55#define PSR_V_BIT 0x10000000 56#define PSR_V_BIT 0x10000000
@@ -65,6 +66,22 @@
65#define PSR_x 0x0000ff00 /* Extension */ 66#define PSR_x 0x0000ff00 /* Extension */
66#define PSR_c 0x000000ff /* Control */ 67#define PSR_c 0x000000ff /* Control */
67 68
69/*
70 * ARMv7 groups of APSR bits
71 */
72#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
73#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
74#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
75
76/*
77 * Default endianness state
78 */
79#ifdef CONFIG_CPU_ENDIAN_BE8
80#define PSR_ENDSTATE PSR_E_BIT
81#else
82#define PSR_ENDSTATE 0
83#endif
84
68#ifndef __ASSEMBLY__ 85#ifndef __ASSEMBLY__
69 86
70/* 87/*
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a62218013c78..c964f3fc3bc5 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -40,6 +40,12 @@
40#define TLB_V6_I_ASID (1 << 18) 40#define TLB_V6_I_ASID (1 << 18)
41 41
42#define TLB_BTB (1 << 28) 42#define TLB_BTB (1 << 28)
43
44/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
45#define TLB_V7_UIS_PAGE (1 << 19)
46#define TLB_V7_UIS_FULL (1 << 20)
47#define TLB_V7_UIS_ASID (1 << 21)
48
43#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 49#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
44#define TLB_DCLEAN (1 << 30) 50#define TLB_DCLEAN (1 << 30)
45#define TLB_WB (1 << 31) 51#define TLB_WB (1 << 31)
@@ -176,9 +182,17 @@
176# define v6wbi_always_flags (-1UL) 182# define v6wbi_always_flags (-1UL)
177#endif 183#endif
178 184
185#ifdef CONFIG_SMP
186#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
187 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
188#else
189#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
190 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
191#endif
192
179#ifdef CONFIG_CPU_TLB_V7 193#ifdef CONFIG_CPU_TLB_V7
180# define v7wbi_possible_flags v6wbi_tlb_flags 194# define v7wbi_possible_flags v7wbi_tlb_flags
181# define v7wbi_always_flags v6wbi_tlb_flags 195# define v7wbi_always_flags v7wbi_tlb_flags
182# ifdef _TLB 196# ifdef _TLB
183# define MULTI_TLB 1 197# define MULTI_TLB 1
184# else 198# else
@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
316 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); 330 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
317 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) 331 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
318 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 332 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
333 if (tlb_flag(TLB_V7_UIS_FULL))
334 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
319 335
320 if (tlb_flag(TLB_BTB)) { 336 if (tlb_flag(TLB_BTB)) {
321 /* flush the branch target cache */ 337 /* flush the branch target cache */
@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
351 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); 367 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
352 if (tlb_flag(TLB_V6_I_ASID)) 368 if (tlb_flag(TLB_V6_I_ASID))
353 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); 369 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
370 if (tlb_flag(TLB_V7_UIS_ASID))
371 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
354 372
355 if (tlb_flag(TLB_BTB)) { 373 if (tlb_flag(TLB_BTB)) {
356 /* flush the branch target cache */ 374 /* flush the branch target cache */
@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
389 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); 407 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
390 if (tlb_flag(TLB_V6_I_PAGE)) 408 if (tlb_flag(TLB_V6_I_PAGE))
391 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); 409 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
410 if (tlb_flag(TLB_V7_UIS_PAGE))
411 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
392 412
393 if (tlb_flag(TLB_BTB)) { 413 if (tlb_flag(TLB_BTB)) {
394 /* flush the branch target cache */ 414 /* flush the branch target cache */
@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
424 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); 444 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
425 if (tlb_flag(TLB_V6_I_PAGE)) 445 if (tlb_flag(TLB_V6_I_PAGE))
426 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); 446 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
447 if (tlb_flag(TLB_V7_UIS_PAGE))
448 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
427 449
428 if (tlb_flag(TLB_BTB)) { 450 if (tlb_flag(TLB_BTB)) {
429 /* flush the branch target cache */ 451 /* flush the branch target cache */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 83b1da6b7baa..fc8af43c5000 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -482,6 +482,9 @@ __und_usr:
482 subeq r4, r2, #4 @ ARM instr at LR - 4 482 subeq r4, r2, #4 @ ARM instr at LR - 4
483 subne r4, r2, #2 @ Thumb instr at LR - 2 483 subne r4, r2, #2 @ Thumb instr at LR - 2
4841: ldreqt r0, [r4] 4841: ldreqt r0, [r4]
485#ifdef CONFIG_CPU_ENDIAN_BE8
486 reveq r0, r0 @ little endian instruction
487#endif
485 beq call_fpe 488 beq call_fpe
486 @ Thumb instruction 489 @ Thumb instruction
487#if __LINUX_ARM_ARCH__ >= 7 490#if __LINUX_ARM_ARCH__ >= 7
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index b55cb0331809..366e5097a41a 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -210,6 +210,9 @@ ENTRY(vector_swi)
210 A710( teq ip, #0x0f000000 ) 210 A710( teq ip, #0x0f000000 )
211 A710( bne .Larm710bug ) 211 A710( bne .Larm710bug )
212#endif 212#endif
213#ifdef CONFIG_CPU_ENDIAN_BE8
214 rev r10, r10 @ little endian instruction
215#endif
213 216
214#elif defined(CONFIG_AEABI) 217#elif defined(CONFIG_AEABI)
215 218
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c3265a2e7cd4..1585423699ee 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -365,7 +365,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
365 regs.ARM_r2 = (unsigned long)fn; 365 regs.ARM_r2 = (unsigned long)fn;
366 regs.ARM_r3 = (unsigned long)do_exit; 366 regs.ARM_r3 = (unsigned long)do_exit;
367 regs.ARM_pc = (unsigned long)kernel_thread_helper; 367 regs.ARM_pc = (unsigned long)kernel_thread_helper;
368 regs.ARM_cpsr = SVC_MODE; 368 regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
369 369
370 return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL); 370 return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
371} 371}
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 80b8b5c7e07a..442b87476f97 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -426,9 +426,13 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
426 */ 426 */
427 thumb = handler & 1; 427 thumb = handler & 1;
428 428
429 if (thumb) 429 if (thumb) {
430 cpsr |= PSR_T_BIT; 430 cpsr |= PSR_T_BIT;
431 else 431#if __LINUX_ARM_ARCH__ >= 7
432 /* clear the If-Then Thumb-2 execution state */
433 cpsr &= ~PSR_IT_MASK;
434#endif
435 } else
432 cpsr &= ~PSR_T_BIT; 436 cpsr &= ~PSR_T_BIT;
433 } 437 }
434#endif 438#endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 0d8097fa4ca5..de885fd256c5 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -28,6 +28,7 @@
28#include <asm/atomic.h> 28#include <asm/atomic.h>
29#include <asm/cacheflush.h> 29#include <asm/cacheflush.h>
30#include <asm/cpu.h> 30#include <asm/cpu.h>
31#include <asm/cputype.h>
31#include <asm/mmu_context.h> 32#include <asm/mmu_context.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/pgalloc.h> 34#include <asm/pgalloc.h>
@@ -585,6 +586,12 @@ struct tlb_args {
585 unsigned long ta_end; 586 unsigned long ta_end;
586}; 587};
587 588
589/* all SMP configurations have the extended CPUID registers */
590static inline int tlb_ops_need_broadcast(void)
591{
592 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
593}
594
588static inline void ipi_flush_tlb_all(void *ignored) 595static inline void ipi_flush_tlb_all(void *ignored)
589{ 596{
590 local_flush_tlb_all(); 597 local_flush_tlb_all();
@@ -627,51 +634,61 @@ static inline void ipi_flush_tlb_kernel_range(void *arg)
627 634
628void flush_tlb_all(void) 635void flush_tlb_all(void)
629{ 636{
630 on_each_cpu(ipi_flush_tlb_all, NULL, 1); 637 if (tlb_ops_need_broadcast())
638 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
639 else
640 local_flush_tlb_all();
631} 641}
632 642
633void flush_tlb_mm(struct mm_struct *mm) 643void flush_tlb_mm(struct mm_struct *mm)
634{ 644{
635 on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask); 645 if (tlb_ops_need_broadcast())
646 on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
647 else
648 local_flush_tlb_mm(mm);
636} 649}
637 650
638void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 651void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
639{ 652{
640 struct tlb_args ta; 653 if (tlb_ops_need_broadcast()) {
641 654 struct tlb_args ta;
642 ta.ta_vma = vma; 655 ta.ta_vma = vma;
643 ta.ta_start = uaddr; 656 ta.ta_start = uaddr;
644 657 on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
645 on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask); 658 } else
659 local_flush_tlb_page(vma, uaddr);
646} 660}
647 661
648void flush_tlb_kernel_page(unsigned long kaddr) 662void flush_tlb_kernel_page(unsigned long kaddr)
649{ 663{
650 struct tlb_args ta; 664 if (tlb_ops_need_broadcast()) {
651 665 struct tlb_args ta;
652 ta.ta_start = kaddr; 666 ta.ta_start = kaddr;
653 667 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
654 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); 668 } else
669 local_flush_tlb_kernel_page(kaddr);
655} 670}
656 671
657void flush_tlb_range(struct vm_area_struct *vma, 672void flush_tlb_range(struct vm_area_struct *vma,
658 unsigned long start, unsigned long end) 673 unsigned long start, unsigned long end)
659{ 674{
660 struct tlb_args ta; 675 if (tlb_ops_need_broadcast()) {
661 676 struct tlb_args ta;
662 ta.ta_vma = vma; 677 ta.ta_vma = vma;
663 ta.ta_start = start; 678 ta.ta_start = start;
664 ta.ta_end = end; 679 ta.ta_end = end;
665 680 on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
666 on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask); 681 } else
682 local_flush_tlb_range(vma, start, end);
667} 683}
668 684
669void flush_tlb_kernel_range(unsigned long start, unsigned long end) 685void flush_tlb_kernel_range(unsigned long start, unsigned long end)
670{ 686{
671 struct tlb_args ta; 687 if (tlb_ops_need_broadcast()) {
672 688 struct tlb_args ta;
673 ta.ta_start = start; 689 ta.ta_start = start;
674 ta.ta_end = end; 690 ta.ta_end = end;
675 691 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
676 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); 692 } else
693 local_flush_tlb_kernel_range(start, end);
677} 694}
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index c90f27250ead..6c0779792546 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -141,6 +141,7 @@ SECTIONS
141 141
142 .data : AT(__data_loc) { 142 .data : AT(__data_loc) {
143 _data = .; /* address in memory */ 143 _data = .; /* address in memory */
144 _sdata = .;
144 145
145 /* 146 /*
146 * first, the init task union, aligned 147 * first, the init task union, aligned
@@ -192,6 +193,7 @@ SECTIONS
192 __bss_start = .; /* BSS */ 193 __bss_start = .; /* BSS */
193 *(.bss) 194 *(.bss)
194 *(COMMON) 195 *(COMMON)
196 __bss_stop = .;
195 _end = .; 197 _end = .;
196 } 198 }
197 /* Stabs debugging sections. */ 199 /* Stabs debugging sections. */
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index bf35cfd89f34..d4cfa2145386 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -47,6 +47,15 @@ config MACH_REALVIEW_PB1176
47 help 47 help
48 Include support for the ARM(R) RealView ARM1176 Platform Baseboard. 48 Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
49 49
50config REALVIEW_PB1176_SECURE_FLASH
51 bool "Allow access to the secure flash memory block"
52 depends on MACH_REALVIEW_PB1176
53 default n
54 help
55 Select this option if Linux will only run in secure mode on the
56 RealView PB1176 platform and access to the secure flash memory
57 block (64MB @ 0x3c000000) is required.
58
50config MACH_REALVIEW_PBA8 59config MACH_REALVIEW_PBA8
51 bool "Support RealView/PB-A8 platform" 60 bool "Support RealView/PB-A8 platform"
52 select CPU_V7 61 select CPU_V7
@@ -57,6 +66,13 @@ config MACH_REALVIEW_PBA8
57 PB-A8 is a platform with an on-board Cortex-A8 and has support for 66 PB-A8 is a platform with an on-board Cortex-A8 and has support for
58 PCI-E and Compact Flash. 67 PCI-E and Compact Flash.
59 68
69config MACH_REALVIEW_PBX
70 bool "Support RealView/PBX platform"
71 select ARM_GIC
72 select HAVE_PATA_PLATFORM
73 help
74 Include support for the ARM(R) RealView PBX platform.
75
60config REALVIEW_HIGH_PHYS_OFFSET 76config REALVIEW_HIGH_PHYS_OFFSET
61 bool "High physical base address for the RealView platform" 77 bool "High physical base address for the RealView platform"
62 depends on !MACH_REALVIEW_PB1176 78 depends on !MACH_REALVIEW_PB1176
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index e13d0947ad0b..e704edb733c0 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
7obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o 7obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
8obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o 8obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
9obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o 9obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o
10obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o
10obj-$(CONFIG_SMP) += platsmp.o headsmp.o 11obj-$(CONFIG_SMP) += platsmp.o headsmp.o
11obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 12obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
12obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 13obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 076acbc50706..9ea9c05093cd 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -48,6 +48,9 @@
48 48
49#include <asm/hardware/gic.h> 49#include <asm/hardware/gic.h>
50 50
51#include <mach/platform.h>
52#include <mach/irqs.h>
53
51#include "core.h" 54#include "core.h"
52#include "clock.h" 55#include "clock.h"
53 56
@@ -578,21 +581,22 @@ void realview_leds_event(led_event_t ledevt)
578{ 581{
579 unsigned long flags; 582 unsigned long flags;
580 u32 val; 583 u32 val;
584 u32 led = 1 << smp_processor_id();
581 585
582 local_irq_save(flags); 586 local_irq_save(flags);
583 val = readl(VA_LEDS_BASE); 587 val = readl(VA_LEDS_BASE);
584 588
585 switch (ledevt) { 589 switch (ledevt) {
586 case led_idle_start: 590 case led_idle_start:
587 val = val & ~REALVIEW_SYS_LED0; 591 val = val & ~led;
588 break; 592 break;
589 593
590 case led_idle_end: 594 case led_idle_end:
591 val = val | REALVIEW_SYS_LED0; 595 val = val | led;
592 break; 596 break;
593 597
594 case led_timer: 598 case led_timer:
595 val = val ^ REALVIEW_SYS_LED1; 599 val = val ^ REALVIEW_SYS_LED7;
596 break; 600 break;
597 601
598 case led_halted: 602 case led_halted:
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
index 268d7701fa9b..794a8d91a6a6 100644
--- a/arch/arm/mach-realview/include/mach/board-eb.h
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -62,111 +62,6 @@
62#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ 62#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
63#endif 63#endif
64 64
65#define IRQ_EB_GIC_START 32
66
67/*
68 * RealView EB interrupt sources
69 */
70#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
71#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
72#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
73#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
74#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
75#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
76#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
77#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
78#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
79 /* 9 reserved */
80#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
81#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
82#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
83#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
84#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
85#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
86#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
87#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
88#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
89#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
90#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
91#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
92#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
93#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
94#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
95#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
96#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
97#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
98#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
99#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
100#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
101#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
102
103/*
104 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
105 */
106#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
107#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
108#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
109#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
110#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
111#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
112#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
113#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
114#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
115#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
116#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
117#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
118#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
119#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
120#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
121#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
122
123#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
124#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
125#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
126#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
127#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
128#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
129#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
130#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
131#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
132#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
133#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
134#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
135
136#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
137#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
138#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
139
140#define IRQ_EB11MP_UART2 -1
141#define IRQ_EB11MP_UART3 -1
142#define IRQ_EB11MP_CLCD -1
143#define IRQ_EB11MP_DMA -1
144#define IRQ_EB11MP_WDOG -1
145#define IRQ_EB11MP_GPIO0 -1
146#define IRQ_EB11MP_GPIO1 -1
147#define IRQ_EB11MP_GPIO2 -1
148#define IRQ_EB11MP_SCI -1
149#define IRQ_EB11MP_SSP -1
150
151#define NR_GIC_EB11MP 2
152
153/*
154 * Only define NR_IRQS if less than NR_IRQS_EB
155 */
156#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
157
158#if defined(CONFIG_MACH_REALVIEW_EB) \
159 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
160#undef NR_IRQS
161#define NR_IRQS NR_IRQS_EB
162#endif
163
164#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \
165 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
166#undef MAX_GIC_NR
167#define MAX_GIC_NR NR_GIC_EB11MP
168#endif
169
170/* 65/*
171 * Core tile identification (REALVIEW_SYS_PROCID) 66 * Core tile identification (REALVIEW_SYS_PROCID)
172 */ 67 */
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 858eea7b1adc..98f8e7eeacc2 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -32,6 +32,8 @@
32#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ 32#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
33#define REALVIEW_PB1176_FLASH_BASE 0x30000000 33#define REALVIEW_PB1176_FLASH_BASE 0x30000000
34#define REALVIEW_PB1176_FLASH_SIZE SZ_64M 34#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
35#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */
36#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M
35 37
36#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */ 38#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
37#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */ 39#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
@@ -71,82 +73,4 @@
71#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ 73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
72#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ 74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
73 75
74/*
75 * Irqs
76 */
77#define IRQ_DC1176_GIC_START 32
78#define IRQ_PB1176_GIC_START 64
79
80/*
81 * ARM1176 DevChip interrupt sources (primary GIC)
82 */
83#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
84#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
85#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
86#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
87#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
88#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
89#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
90#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
91#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
92#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
93#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
94#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
95#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
96#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
97#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
98#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
99
100#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
101#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
102
103/*
104 * RealView PB1176 interrupt sources (secondary GIC)
105 */
106#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */
107#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */
108#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */
109#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */
110#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5)
111#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
112#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */
113#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8)
114#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
115#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
116#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
117
118#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
119
120#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
121
122#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22)
123#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23)
124#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
125#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
126
127#define IRQ_PB1176_GPIO0 -1
128#define IRQ_PB1176_SSP -1
129#define IRQ_PB1176_SCTL -1
130
131#define NR_GIC_PB1176 2
132
133/*
134 * Only define NR_IRQS if less than NR_IRQS_PB1176
135 */
136#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96)
137
138#if defined(CONFIG_MACH_REALVIEW_PB1176)
139
140#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
141#undef NR_IRQS
142#define NR_IRQS NR_IRQS_PB1176
143#endif
144
145#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
146#undef MAX_GIC_NR
147#define MAX_GIC_NR NR_GIC_PB1176
148#endif
149
150#endif /* CONFIG_MACH_REALVIEW_PB1176 */
151
152#endif /* __ASM_ARCH_BOARD_PB1176_H */ 76#endif /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index 53ea0e7a1267..f0d68e0fea01 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -81,105 +81,4 @@
81#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ 81#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
82#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ 82#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
83 83
84/*
85 * Irqs
86 */
87#define IRQ_TC11MP_GIC_START 32
88#define IRQ_PB11MP_GIC_START 64
89
90/*
91 * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
92 */
93#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
94#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
95#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
96#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
97#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
98#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
99#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
100#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
101#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
102#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
103#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
104#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
105#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
106#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
107#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
108#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
109
110#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
111#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
112#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
113#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
114#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
115#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
116#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
117#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
118#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
119#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
120#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
121#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
122
123#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
124#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
125#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
126
127/*
128 * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
129 */
130#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
131#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
132#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
133#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
134#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
135#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
136#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
137 /* 9 reserved */
138#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
139#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
140#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
141#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
142#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
143#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
144#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
145#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
146#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
147#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
148#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
149#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
150#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
151#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
152#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
153#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
154#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
155#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
156#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
157#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
158#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
159#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
160
161#define IRQ_PB11MP_SMC -1
162#define IRQ_PB11MP_SCTL -1
163
164#define NR_GIC_PB11MP 2
165
166/*
167 * Only define NR_IRQS if less than NR_IRQS_PB11MP
168 */
169#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96)
170
171#if defined(CONFIG_MACH_REALVIEW_PB11MP)
172
173#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
174#undef NR_IRQS
175#define NR_IRQS NR_IRQS_PB11MP
176#endif
177
178#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
179#undef MAX_GIC_NR
180#define MAX_GIC_NR NR_GIC_PB11MP
181#endif
182
183#endif /* CONFIG_MACH_REALVIEW_PB11MP */
184
185#endif /* __ASM_ARCH_BOARD_PB11MP_H */ 84#endif /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h
index 307f97b16e5b..4dfc67a4f45f 100644
--- a/arch/arm/mach-realview/include/mach/board-pba8.h
+++ b/arch/arm/mach-realview/include/mach/board-pba8.h
@@ -70,81 +70,4 @@
70#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */ 70#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */
71#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */ 71#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */
72 72
73/*
74 * Irqs
75 */
76#define IRQ_PBA8_GIC_START 32
77
78/* L220
79#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29)
80#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30)
81#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31)
82*/
83
84/*
85 * PB-A8 on-board gic irq sources
86 */
87#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
88#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
89#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
90#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
91#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
92#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
93#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
94#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
95#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
96 /* 9 reserved */
97#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
98#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
99#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
100#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
101#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
102#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
103#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
104#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
105#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
106#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
107#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
108#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
109#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
110#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
111#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
112#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
113#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
114#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
115#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
116#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
117#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
118#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
119
120/* ... */
121#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
122#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
123#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
124#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
125
126#define IRQ_PBA8_SMC -1
127#define IRQ_PBA8_SCTL -1
128
129#define NR_GIC_PBA8 1
130
131/*
132 * Only define NR_IRQS if less than NR_IRQS_PBA8
133 */
134#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64)
135
136#if defined(CONFIG_MACH_REALVIEW_PBA8)
137
138#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8)
139#undef NR_IRQS
140#define NR_IRQS NR_IRQS_PBA8
141#endif
142
143#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8)
144#undef MAX_GIC_NR
145#define MAX_GIC_NR NR_GIC_PBA8
146#endif
147
148#endif /* CONFIG_MACH_REALVIEW_PBA8 */
149
150#endif /* __ASM_ARCH_BOARD_PBA8_H */ 73#endif /* __ASM_ARCH_BOARD_PBA8_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pbx.h b/arch/arm/mach-realview/include/mach/board-pbx.h
new file mode 100644
index 000000000000..848bfff6d8f1
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/board-pbx.h
@@ -0,0 +1,108 @@
1/*
2 * arch/arm/mach-realview/include/mach/board-pbx.h
3 *
4 * Copyright (C) 2009 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_BOARD_PBX_H
21#define __ASM_ARCH_BOARD_PBX_H
22
23#include <mach/platform.h>
24
25/*
26 * Peripheral addresses
27 */
28#define REALVIEW_PBX_UART0_BASE 0x10009000 /* UART 0 */
29#define REALVIEW_PBX_UART1_BASE 0x1000A000 /* UART 1 */
30#define REALVIEW_PBX_UART2_BASE 0x1000B000 /* UART 2 */
31#define REALVIEW_PBX_UART3_BASE 0x1000C000 /* UART 3 */
32#define REALVIEW_PBX_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
33#define REALVIEW_PBX_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
34#define REALVIEW_PBX_WATCHDOG_BASE 0x10010000 /* watchdog interface */
35#define REALVIEW_PBX_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
36#define REALVIEW_PBX_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
37#define REALVIEW_PBX_GPIO0_BASE 0x10013000 /* GPIO port 0 */
38#define REALVIEW_PBX_RTC_BASE 0x10017000 /* Real Time Clock */
39#define REALVIEW_PBX_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
40#define REALVIEW_PBX_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
41#define REALVIEW_PBX_SCTL_BASE 0x1001A000 /* System Controller */
42#define REALVIEW_PBX_CLCD_BASE 0x10020000 /* CLCD */
43#define REALVIEW_PBX_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
44#define REALVIEW_PBX_DMC_BASE 0x100E0000 /* DMC configuration */
45#define REALVIEW_PBX_SMC_BASE 0x100E1000 /* SMC configuration */
46#define REALVIEW_PBX_CAN_BASE 0x100E2000 /* CAN bus */
47#define REALVIEW_PBX_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
48#define REALVIEW_PBX_FLASH0_BASE 0x40000000
49#define REALVIEW_PBX_FLASH0_SIZE SZ_64M
50#define REALVIEW_PBX_FLASH1_BASE 0x44000000
51#define REALVIEW_PBX_FLASH1_SIZE SZ_64M
52#define REALVIEW_PBX_ETH_BASE 0x4E000000 /* Ethernet */
53#define REALVIEW_PBX_USB_BASE 0x4F000000 /* USB */
54#define REALVIEW_PBX_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
55#define REALVIEW_PBX_LT_BASE 0xC0000000 /* Logic Tile expansion */
56#define REALVIEW_PBX_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
57#define REALVIEW_PBX_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
58
59/*
60 * Tile-specific addresses
61 */
62#define REALVIEW_PBX_TILE_SCU_BASE 0x1F000000 /* SCU registers */
63#define REALVIEW_PBX_TILE_GIC_CPU_BASE 0x1F000100 /* Private Generic interrupt controller CPU interface */
64#define REALVIEW_PBX_TILE_TWD_BASE 0x1F000600
65#define REALVIEW_PBX_TILE_TWD_PERCPU_BASE 0x1F000700
66#define REALVIEW_PBX_TILE_TWD_SIZE 0x00000100
67#define REALVIEW_PBX_TILE_GIC_DIST_BASE 0x1F001000 /* Private Generic interrupt controller distributor */
68#define REALVIEW_PBX_TILE_L220_BASE 0x1F002000 /* L220 registers */
69
70#define REALVIEW_PBX_SYS_PLD_CTRL1 0x74
71
72/*
73 * PBX PCI regions
74 */
75#define REALVIEW_PBX_PCI_BASE 0x90040000 /* PCI-X Unit base */
76#define REALVIEW_PBX_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
77#define REALVIEW_PBX_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
78
79#define REALVIEW_PBX_PCI_BASE_SIZE 0x10000 /* 16 Kb */
80#define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */
81#define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */
82
83/*
84 * Core tile identification (REALVIEW_SYS_PROCID)
85 */
86#define REALVIEW_PBX_PROC_MASK 0xFF000000
87#define REALVIEW_PBX_PROC_ARM7TDMI 0x00000000
88#define REALVIEW_PBX_PROC_ARM9 0x02000000
89#define REALVIEW_PBX_PROC_ARM11 0x04000000
90#define REALVIEW_PBX_PROC_ARM11MP 0x06000000
91#define REALVIEW_PBX_PROC_A9MP 0x0C000000
92#define REALVIEW_PBX_PROC_A8 0x0E000000
93
94#define check_pbx_proc(proc_type) \
95 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_PBX_PROC_MASK) \
96 == proc_type)
97
98#ifdef CONFIG_MACH_REALVIEW_PBX
99#define core_tile_pbx11mp() check_pbx_proc(REALVIEW_PBX_PROC_ARM11MP)
100#define core_tile_pbxa9mp() check_pbx_proc(REALVIEW_PBX_PROC_A9MP)
101#define core_tile_pbxa8() check_pbx_proc(REALVIEW_PBX_PROC_A8)
102#else
103#define core_tile_pbx11mp() 0
104#define core_tile_pbxa9mp() 0
105#define core_tile_pbxa8() 0
106#endif
107
108#endif /* __ASM_ARCH_BOARD_PBX_H */
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 92dbcb9e1792..932d8af18062 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -12,7 +12,8 @@
12 12
13#if defined(CONFIG_MACH_REALVIEW_EB) || \ 13#if defined(CONFIG_MACH_REALVIEW_EB) || \
14 defined(CONFIG_MACH_REALVIEW_PB11MP) || \ 14 defined(CONFIG_MACH_REALVIEW_PB11MP) || \
15 defined(CONFIG_MACH_REALVIEW_PBA8) 15 defined(CONFIG_MACH_REALVIEW_PBA8) || \
16 defined(CONFIG_MACH_REALVIEW_PBX)
16#ifndef DEBUG_LL_UART_OFFSET 17#ifndef DEBUG_LL_UART_OFFSET
17#define DEBUG_LL_UART_OFFSET 0x00009000 18#define DEBUG_LL_UART_OFFSET 0x00009000
18#elif DEBUG_LL_UART_OFFSET != 0x00009000 19#elif DEBUG_LL_UART_OFFSET != 0x00009000
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
new file mode 100644
index 000000000000..204d5378f309
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -0,0 +1,129 @@
1/*
2 * arch/arm/mach-realview/include/mach/irqs-eb.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_IRQS_EB_H
22#define __MACH_IRQS_EB_H
23
24#define IRQ_EB_GIC_START 32
25
26/*
27 * RealView EB interrupt sources
28 */
29#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
30#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
31#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
32#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
33#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
34#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
35#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
36#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
37#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
38 /* 9 reserved */
39#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
40#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
41#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
42#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
43#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
44#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
45#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
46#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
47#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
48#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
49#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
50#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
51#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
52#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
53#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
54#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
55#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
56#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
57#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
58#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
59#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
60#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
61
62/*
63 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
64 */
65#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
66#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
67#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
68#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
69#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
70#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
71#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
72#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
73#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
74#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
75#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
76#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
77#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
78#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
79#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
80#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
81
82#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
83#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
84#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
85#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
86#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
87#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
88#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
89#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
90#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
91#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
92#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
93#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
94
95#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
96#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
97#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
98
99#define IRQ_EB11MP_UART2 -1
100#define IRQ_EB11MP_UART3 -1
101#define IRQ_EB11MP_CLCD -1
102#define IRQ_EB11MP_DMA -1
103#define IRQ_EB11MP_WDOG -1
104#define IRQ_EB11MP_GPIO0 -1
105#define IRQ_EB11MP_GPIO1 -1
106#define IRQ_EB11MP_GPIO2 -1
107#define IRQ_EB11MP_SCI -1
108#define IRQ_EB11MP_SSP -1
109
110#define NR_GIC_EB11MP 2
111
112/*
113 * Only define NR_IRQS if less than NR_IRQS_EB
114 */
115#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
116
117#if defined(CONFIG_MACH_REALVIEW_EB) \
118 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
119#undef NR_IRQS
120#define NR_IRQS NR_IRQS_EB
121#endif
122
123#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \
124 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
125#undef MAX_GIC_NR
126#define MAX_GIC_NR NR_GIC_EB11MP
127#endif
128
129#endif /* __MACH_IRQS_EB_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
new file mode 100644
index 000000000000..2410d4f8ddd3
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -0,0 +1,99 @@
1/*
2 * arch/arm/mach-realview/include/mach/irqs-pb1176.h
3 *
4 * Copyright (C) 2008 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_IRQS_PB1176_H
22#define __MACH_IRQS_PB1176_H
23
24#define IRQ_DC1176_GIC_START 32
25#define IRQ_PB1176_GIC_START 64
26
27/*
28 * ARM1176 DevChip interrupt sources (primary GIC)
29 */
30#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
31#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
32#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
33#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
34#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
35#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
36#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
37#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
38#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
39#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
40#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
41#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
42#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
43#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
44#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
45#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
46
47#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
48#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
49
50/*
51 * RealView PB1176 interrupt sources (secondary GIC)
52 */
53#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */
54#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */
55#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */
56#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */
57#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5)
58#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
59#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */
60#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8)
61#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
62#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
63#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
64
65#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
66
67#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
68
69#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22)
70#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23)
71#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
72#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
73
74#define IRQ_PB1176_GPIO0 -1
75#define IRQ_PB1176_SSP -1
76#define IRQ_PB1176_SCTL -1
77
78#define NR_GIC_PB1176 2
79
80/*
81 * Only define NR_IRQS if less than NR_IRQS_PB1176
82 */
83#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96)
84
85#if defined(CONFIG_MACH_REALVIEW_PB1176)
86
87#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
88#undef NR_IRQS
89#define NR_IRQS NR_IRQS_PB1176
90#endif
91
92#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
93#undef MAX_GIC_NR
94#define MAX_GIC_NR NR_GIC_PB1176
95#endif
96
97#endif /* CONFIG_MACH_REALVIEW_PB1176 */
98
99#endif /* __MACH_IRQS_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb11mp.h b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
new file mode 100644
index 000000000000..34e255add21e
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
@@ -0,0 +1,122 @@
1/*
2 * arch/arm/mach-realview/include/mach/irqs-pb11mp.h
3 *
4 * Copyright (C) 2008 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_IRQS_PB11MP_H
22#define __MACH_IRQS_PB11MP_H
23
24#define IRQ_TC11MP_GIC_START 32
25#define IRQ_PB11MP_GIC_START 64
26
27/*
28 * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
29 */
30#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
31#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
32#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
33#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
34#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
35#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
36#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
37#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
38#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
39#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
40#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
41#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
42#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
43#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
44#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
45#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
46
47#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
48#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
49#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
50#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
51#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
52#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
53#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
54#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
55#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
56#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
57#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
58#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
59
60#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
61#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
62#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
63
64/*
65 * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
66 */
67#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
68#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
69#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
70#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
71#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
72#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
73#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
74 /* 9 reserved */
75#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
76#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
77#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
78#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
79#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
80#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
81#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
82#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
83#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
84#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
85#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
86#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
87#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
88#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
89#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
90#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
91#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
92#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
93#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
94#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
95#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
96#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
97
98#define IRQ_PB11MP_SMC -1
99#define IRQ_PB11MP_SCTL -1
100
101#define NR_GIC_PB11MP 2
102
103/*
104 * Only define NR_IRQS if less than NR_IRQS_PB11MP
105 */
106#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96)
107
108#if defined(CONFIG_MACH_REALVIEW_PB11MP)
109
110#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
111#undef NR_IRQS
112#define NR_IRQS NR_IRQS_PB11MP
113#endif
114
115#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
116#undef MAX_GIC_NR
117#define MAX_GIC_NR NR_GIC_PB11MP
118#endif
119
120#endif /* CONFIG_MACH_REALVIEW_PB11MP */
121
122#endif /* __MACH_IRQS_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pba8.h b/arch/arm/mach-realview/include/mach/irqs-pba8.h
new file mode 100644
index 000000000000..86792a9f2ab6
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pba8.h
@@ -0,0 +1,98 @@
1/*
2 * arch/arm/mach-realview/include/mach/irqs-pba8.h
3 *
4 * Copyright (C) 2008 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_IRQS_PBA8_H
22#define __MACH_IRQS_PBA8_H
23
24#define IRQ_PBA8_GIC_START 32
25
26/* L220
27#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29)
28#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30)
29#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31)
30*/
31
32/*
33 * PB-A8 on-board gic irq sources
34 */
35#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
36#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
37#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
38#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
39#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
40#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
41#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
42#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
43#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
44 /* 9 reserved */
45#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
46#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
47#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
48#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
49#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
50#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
51#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
52#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
53#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
54#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
55#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
56#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
57#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
58#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
59#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
60#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
61#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
62#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
63#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
64#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
65#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
66#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
67
68/* ... */
69#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
70#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
71#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
72#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
73
74#define IRQ_PBA8_SMC -1
75#define IRQ_PBA8_SCTL -1
76
77#define NR_GIC_PBA8 1
78
79/*
80 * Only define NR_IRQS if less than NR_IRQS_PBA8
81 */
82#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64)
83
84#if defined(CONFIG_MACH_REALVIEW_PBA8)
85
86#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8)
87#undef NR_IRQS
88#define NR_IRQS NR_IRQS_PBA8
89#endif
90
91#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8)
92#undef MAX_GIC_NR
93#define MAX_GIC_NR NR_GIC_PBA8
94#endif
95
96#endif /* CONFIG_MACH_REALVIEW_PBA8 */
97
98#endif /* __MACH_IRQS_PBA8_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pbx.h b/arch/arm/mach-realview/include/mach/irqs-pbx.h
new file mode 100644
index 000000000000..deaad4302b17
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pbx.h
@@ -0,0 +1,115 @@
1/*
2 * arch/arm/mach-realview/include/mach/irqs-pbx.h
3 *
4 * Copyright (C) 2009 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __MACH_IRQS_PBX_H
21#define __MACH_IRQS_PBX_H
22
23#define IRQ_PBX_GIC_START 32
24
25/* L220
26#define IRQ_PBX_L220_EVENT (IRQ_PBX_GIC_START + 29)
27#define IRQ_PBX_L220_SLAVE (IRQ_PBX_GIC_START + 30)
28#define IRQ_PBX_L220_DECODE (IRQ_PBX_GIC_START + 31)
29*/
30
31/*
32 * PBX on-board gic irq sources
33 */
34#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */
35#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */
36#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */
37#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */
38#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */
39#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */
40#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */
41#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */
42#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */
43 /* 9 reserved */
44#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */
45#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */
46#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */
47#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */
48#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */
49#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */
50#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */
51#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */
52#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */
53#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */
54#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */
55#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */
56#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */
57#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */
58#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */
59#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */
60#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */
61#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */
62#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */
63#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */
64#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */
65#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */
66
67#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */
68#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33)
69#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34)
70#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35)
71#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36)
72#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37)
73#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38)
74#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39)
75
76#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */
77#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */
78#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */
79/* ... */
80#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */
81#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 45)
82#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 46)
83#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 47)
84
85/* ... */
86#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50)
87#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51)
88#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52)
89#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53)
90
91#define IRQ_PBX_SMC -1
92#define IRQ_PBX_SCTL -1
93
94#define NR_GIC_PBX 1
95
96/*
97 * Only define NR_IRQS if less than NR_IRQS_PBX
98 */
99#define NR_IRQS_PBX (IRQ_PBX_GIC_START + 96)
100
101#if defined(CONFIG_MACH_REALVIEW_PBX)
102
103#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX)
104#undef NR_IRQS
105#define NR_IRQS NR_IRQS_PBX
106#endif
107
108#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX)
109#undef MAX_GIC_NR
110#define MAX_GIC_NR NR_GIC_PBX
111#endif
112
113#endif /* CONFIG_MACH_REALVIEW_PBX */
114
115#endif /* __MACH_IRQS_PBX_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h
index fe5cb987aa21..78854f2fa323 100644
--- a/arch/arm/mach-realview/include/mach/irqs.h
+++ b/arch/arm/mach-realview/include/mach/irqs.h
@@ -22,10 +22,11 @@
22#ifndef __ASM_ARCH_IRQS_H 22#ifndef __ASM_ARCH_IRQS_H
23#define __ASM_ARCH_IRQS_H 23#define __ASM_ARCH_IRQS_H
24 24
25#include <mach/board-eb.h> 25#include <mach/irqs-eb.h>
26#include <mach/board-pb11mp.h> 26#include <mach/irqs-pb11mp.h>
27#include <mach/board-pb1176.h> 27#include <mach/irqs-pb1176.h>
28#include <mach/board-pba8.h> 28#include <mach/irqs-pba8.h>
29#include <mach/irqs-pbx.h>
29 30
30#define IRQ_LOCALTIMER 29 31#define IRQ_LOCALTIMER 29
31#define IRQ_LOCALWDOG 30 32#define IRQ_LOCALWDOG 30
diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h
index 415d634d52ab..83050378ffd2 100644
--- a/arch/arm/mach-realview/include/mach/uncompress.h
+++ b/arch/arm/mach-realview/include/mach/uncompress.h
@@ -24,6 +24,7 @@
24#include <mach/board-pb11mp.h> 24#include <mach/board-pb11mp.h>
25#include <mach/board-pb1176.h> 25#include <mach/board-pb1176.h>
26#include <mach/board-pba8.h> 26#include <mach/board-pba8.h>
27#include <mach/board-pbx.h>
27 28
28#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) 29#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
29#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) 30#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
@@ -43,6 +44,8 @@ static inline unsigned long get_uart_base(void)
43 return REALVIEW_PB1176_UART0_BASE; 44 return REALVIEW_PB1176_UART0_BASE;
44 else if (machine_is_realview_pba8()) 45 else if (machine_is_realview_pba8())
45 return REALVIEW_PBA8_UART0_BASE; 46 return REALVIEW_PBA8_UART0_BASE;
47 else if (machine_is_realview_pbx())
48 return REALVIEW_PBX_UART0_BASE;
46 else 49 else
47 return 0; 50 return 0;
48} 51}
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index ca742172ea78..ac0e83f1cc3a 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -23,6 +23,7 @@
23 23
24#include <mach/board-eb.h> 24#include <mach/board-eb.h>
25#include <mach/board-pb11mp.h> 25#include <mach/board-pb11mp.h>
26#include <mach/board-pbx.h>
26#include <asm/smp_scu.h> 27#include <asm/smp_scu.h>
27 28
28#include "core.h" 29#include "core.h"
@@ -41,6 +42,9 @@ static void __iomem *scu_base_addr(void)
41 return __io_address(REALVIEW_EB11MP_SCU_BASE); 42 return __io_address(REALVIEW_EB11MP_SCU_BASE);
42 else if (machine_is_realview_pb11mp()) 43 else if (machine_is_realview_pb11mp())
43 return __io_address(REALVIEW_TC11MP_SCU_BASE); 44 return __io_address(REALVIEW_TC11MP_SCU_BASE);
45 else if (machine_is_realview_pbx() &&
46 (core_tile_pbx11mp() || core_tile_pbxa9mp()))
47 return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
44 else 48 else
45 return (void __iomem *)0; 49 return (void __iomem *)0;
46} 50}
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index a64b84a7a3df..25efe71a67c7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -203,11 +203,23 @@ static struct amba_device *amba_devs[] __initdata = {
203/* 203/*
204 * RealView PB1176 platform devices 204 * RealView PB1176 platform devices
205 */ 205 */
206static struct resource realview_pb1176_flash_resource = { 206static struct resource realview_pb1176_flash_resources[] = {
207 .start = REALVIEW_PB1176_FLASH_BASE, 207 [0] = {
208 .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, 208 .start = REALVIEW_PB1176_FLASH_BASE,
209 .flags = IORESOURCE_MEM, 209 .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = REALVIEW_PB1176_SEC_FLASH_BASE,
214 .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1,
215 .flags = IORESOURCE_MEM,
216 },
210}; 217};
218#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH
219#define PB1176_FLASH_BLOCKS 2
220#else
221#define PB1176_FLASH_BLOCKS 1
222#endif
211 223
212static struct resource realview_pb1176_smsc911x_resources[] = { 224static struct resource realview_pb1176_smsc911x_resources[] = {
213 [0] = { 225 [0] = {
@@ -271,7 +283,8 @@ static void __init realview_pb1176_init(void)
271 l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); 283 l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
272#endif 284#endif
273 285
274 realview_flash_register(&realview_pb1176_flash_resource, 1); 286 realview_flash_register(realview_pb1176_flash_resources,
287 PB1176_FLASH_BLOCKS);
275 realview_eth_register(NULL, realview_pb1176_smsc911x_resources); 288 realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
276 platform_device_register(&realview_i2c_device); 289 platform_device_register(&realview_i2c_device);
277 realview_usb_register(realview_pb1176_isp1761_resources); 290 realview_usb_register(realview_pb1176_isp1761_resources);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
new file mode 100644
index 000000000000..1fe294d0bf9d
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -0,0 +1,335 @@
1/*
2 * arch/arm/mach-realview/realview_pbx.c
3 *
4 * Copyright (C) 2009 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/sysdev.h>
24#include <linux/amba/bus.h>
25#include <linux/io.h>
26
27#include <asm/irq.h>
28#include <asm/leds.h>
29#include <asm/mach-types.h>
30#include <asm/hardware/gic.h>
31#include <asm/hardware/cache-l2x0.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/mmc.h>
36#include <asm/mach/time.h>
37
38#include <mach/hardware.h>
39#include <mach/board-pbx.h>
40#include <mach/irqs.h>
41
42#include "core.h"
43
44static struct map_desc realview_pbx_io_desc[] __initdata = {
45 {
46 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
47 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
48 .length = SZ_4K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
52 .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
57 .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE),
58 .length = SZ_4K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
62 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
63 .length = SZ_4K,
64 .type = MT_DEVICE,
65 }, {
66 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
67 .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE),
68 .length = SZ_4K,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
72 .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 },
76#ifdef CONFIG_PCI
77 {
78 .virtual = PCIX_UNIT_BASE,
79 .pfn = __phys_to_pfn(REALVIEW_PBX_PCI_BASE),
80 .length = REALVIEW_PBX_PCI_BASE_SIZE,
81 .type = MT_DEVICE,
82 },
83#endif
84#ifdef CONFIG_DEBUG_LL
85 {
86 .virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
87 .pfn = __phys_to_pfn(REALVIEW_PBX_UART0_BASE),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 },
91#endif
92};
93
94static struct map_desc realview_local_io_desc[] __initdata = {
95 {
96 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE),
97 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
102 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
107 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE),
108 .length = SZ_8K,
109 .type = MT_DEVICE,
110 }
111};
112
113static void __init realview_pbx_map_io(void)
114{
115 iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc));
116 if (core_tile_pbx11mp() || core_tile_pbxa9mp())
117 iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
118}
119
120/*
121 * RealView PBXCore AMBA devices
122 */
123
124#define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ }
125#define GPIO2_DMA { 0, 0 }
126#define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ }
127#define GPIO3_DMA { 0, 0 }
128#define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ }
129#define AACI_DMA { 0x80, 0x81 }
130#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
131#define MMCI0_DMA { 0x84, 0 }
132#define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ }
133#define KMI0_DMA { 0, 0 }
134#define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ }
135#define KMI1_DMA { 0, 0 }
136#define PBX_SMC_IRQ { NO_IRQ, NO_IRQ }
137#define PBX_SMC_DMA { 0, 0 }
138#define MPMC_IRQ { NO_IRQ, NO_IRQ }
139#define MPMC_DMA { 0, 0 }
140#define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ }
141#define PBX_CLCD_DMA { 0, 0 }
142#define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ }
143#define DMAC_DMA { 0, 0 }
144#define SCTL_IRQ { NO_IRQ, NO_IRQ }
145#define SCTL_DMA { 0, 0 }
146#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ }
147#define PBX_WATCHDOG_DMA { 0, 0 }
148#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ }
149#define PBX_GPIO0_DMA { 0, 0 }
150#define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ }
151#define GPIO1_DMA { 0, 0 }
152#define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ }
153#define PBX_RTC_DMA { 0, 0 }
154#define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ }
155#define SCI_DMA { 7, 6 }
156#define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ }
157#define PBX_UART0_DMA { 15, 14 }
158#define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ }
159#define PBX_UART1_DMA { 13, 12 }
160#define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ }
161#define PBX_UART2_DMA { 11, 10 }
162#define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ }
163#define PBX_UART3_DMA { 0x86, 0x87 }
164#define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ }
165#define PBX_SSP_DMA { 9, 8 }
166
167/* FPGA Primecells */
168AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
169AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
170AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
171AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
172AMBA_DEVICE(uart3, "fpga:09", PBX_UART3, NULL);
173
174/* DevChip Primecells */
175AMBA_DEVICE(smc, "dev:00", PBX_SMC, NULL);
176AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
177AMBA_DEVICE(wdog, "dev:e1", PBX_WATCHDOG, NULL);
178AMBA_DEVICE(gpio0, "dev:e4", PBX_GPIO0, NULL);
179AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
180AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
181AMBA_DEVICE(rtc, "dev:e8", PBX_RTC, NULL);
182AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
183AMBA_DEVICE(uart0, "dev:f1", PBX_UART0, NULL);
184AMBA_DEVICE(uart1, "dev:f2", PBX_UART1, NULL);
185AMBA_DEVICE(uart2, "dev:f3", PBX_UART2, NULL);
186AMBA_DEVICE(ssp0, "dev:f4", PBX_SSP, NULL);
187
188/* Primecells on the NEC ISSP chip */
189AMBA_DEVICE(clcd, "issp:20", PBX_CLCD, &clcd_plat_data);
190AMBA_DEVICE(dmac, "issp:30", DMAC, NULL);
191
192static struct amba_device *amba_devs[] __initdata = {
193 &dmac_device,
194 &uart0_device,
195 &uart1_device,
196 &uart2_device,
197 &uart3_device,
198 &smc_device,
199 &clcd_device,
200 &sctl_device,
201 &wdog_device,
202 &gpio0_device,
203 &gpio1_device,
204 &gpio2_device,
205 &rtc_device,
206 &sci0_device,
207 &ssp0_device,
208 &aaci_device,
209 &mmc0_device,
210 &kmi0_device,
211 &kmi1_device,
212};
213
214/*
215 * RealView PB-X platform devices
216 */
217static struct resource realview_pbx_flash_resources[] = {
218 [0] = {
219 .start = REALVIEW_PBX_FLASH0_BASE,
220 .end = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = REALVIEW_PBX_FLASH1_BASE,
225 .end = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1,
226 .flags = IORESOURCE_MEM,
227 },
228};
229
230static struct resource realview_pbx_smsc911x_resources[] = {
231 [0] = {
232 .start = REALVIEW_PBX_ETH_BASE,
233 .end = REALVIEW_PBX_ETH_BASE + SZ_64K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_PBX_ETH,
238 .end = IRQ_PBX_ETH,
239 .flags = IORESOURCE_IRQ,
240 },
241};
242
243static struct resource realview_pbx_isp1761_resources[] = {
244 [0] = {
245 .start = REALVIEW_PBX_USB_BASE,
246 .end = REALVIEW_PBX_USB_BASE + SZ_128K - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = IRQ_PBX_USB,
251 .end = IRQ_PBX_USB,
252 .flags = IORESOURCE_IRQ,
253 },
254};
255
256static void __init gic_init_irq(void)
257{
258 /* ARM PBX on-board GIC */
259 if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
260 gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
261 gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
262 29);
263 gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
264 } else {
265 gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
266 gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
267 IRQ_PBX_GIC_START);
268 gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
269 }
270}
271
272static void __init realview_pbx_timer_init(void)
273{
274 timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
275 timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20;
276 timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
277 timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
278
279#ifdef CONFIG_LOCAL_TIMERS
280 if (core_tile_pbx11mp() || core_tile_pbxa9mp())
281 twd_base = __io_address(REALVIEW_PBX_TILE_TWD_BASE);
282#endif
283 realview_timer_init(IRQ_PBX_TIMER0_1);
284}
285
286static struct sys_timer realview_pbx_timer = {
287 .init = realview_pbx_timer_init,
288};
289
290static void __init realview_pbx_init(void)
291{
292 int i;
293
294#ifdef CONFIG_CACHE_L2X0
295 if (core_tile_pbxa9mp()) {
296 void __iomem *l2x0_base =
297 __io_address(REALVIEW_PBX_TILE_L220_BASE);
298
299 /* set RAM latencies to 1 cycle for eASIC */
300 writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
301 writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
302
303 /* 16KB way size, 8-way associativity, parity disabled
304 * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
305 l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
306 }
307#endif
308
309 realview_flash_register(realview_pbx_flash_resources,
310 ARRAY_SIZE(realview_pbx_flash_resources));
311 realview_eth_register(NULL, realview_pbx_smsc911x_resources);
312 platform_device_register(&realview_i2c_device);
313 platform_device_register(&realview_cf_device);
314 realview_usb_register(realview_pbx_isp1761_resources);
315
316 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
317 struct amba_device *d = amba_devs[i];
318 amba_device_register(d, &iomem_resource);
319 }
320
321#ifdef CONFIG_LEDS
322 leds_event = realview_leds_event;
323#endif
324}
325
326MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
327 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
328 .phys_io = REALVIEW_PBX_UART0_BASE,
329 .io_pg_offst = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
330 .boot_params = PHYS_OFFSET + 0x00000100,
331 .map_io = realview_pbx_map_io,
332 .init_irq = gic_init_irq,
333 .timer = &realview_pbx_timer,
334 .init_machine = realview_pbx_init,
335MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b9bd481a0ecc..83c025e72ceb 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -391,7 +391,7 @@ config CPU_FEROCEON_OLD_ID
391 391
392# ARMv6 392# ARMv6
393config CPU_V6 393config CPU_V6
394 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 394 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
395 select CPU_32v6 395 select CPU_32v6
396 select CPU_ABRT_EV6 396 select CPU_ABRT_EV6
397 select CPU_PABRT_NOIFAR 397 select CPU_PABRT_NOIFAR
@@ -416,7 +416,7 @@ config CPU_32v6K
416 416
417# ARMv7 417# ARMv7
418config CPU_V7 418config CPU_V7
419 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 419 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
420 select CPU_32v6K 420 select CPU_32v6K
421 select CPU_32v7 421 select CPU_32v7
422 select CPU_ABRT_EV7 422 select CPU_ABRT_EV7
@@ -639,6 +639,20 @@ config CPU_BIG_ENDIAN
639 port must properly enable any big-endian related features 639 port must properly enable any big-endian related features
640 of your chipset/board/processor. 640 of your chipset/board/processor.
641 641
642config CPU_ENDIAN_BE8
643 bool
644 depends on CPU_BIG_ENDIAN
645 default CPU_V6 || CPU_V7
646 help
647 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
648
649config CPU_ENDIAN_BE32
650 bool
651 depends on CPU_BIG_ENDIAN
652 default !CPU_ENDIAN_BE8
653 help
654 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
655
642config CPU_HIGH_VECTOR 656config CPU_HIGH_VECTOR
643 depends on !MMU && CPU_CP15 && !CPU_ARM740T 657 depends on !MMU && CPU_CP15 && !CPU_ARM740T
644 bool "Select the High exception vector" 658 bool "Select the High exception vector"
@@ -744,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
744config CACHE_L2X0 758config CACHE_L2X0
745 bool "Enable the L2x0 outer cache controller" 759 bool "Enable the L2x0 outer cache controller"
746 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 760 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
747 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 761 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
748 default y 762 default y
749 select OUTER_CACHE 763 select OUTER_CACHE
750 help 764 help
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 6f7e70907e44..f332df7f0d37 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -37,6 +37,9 @@ ENTRY(v6_early_abort)
37 movne pc, lr 37 movne pc, lr
38 do_thumb_abort 38 do_thumb_abort
39 ldreq r3, [r2] @ read aborted ARM instruction 39 ldreq r3, [r2] @ read aborted ARM instruction
40#ifdef CONFIG_CPU_ENDIAN_BE8
41 reveq r3, r3
42#endif
40 do_ldrd_abort 43 do_ldrd_abort
41 tst r3, #1 << 20 @ L = 0 -> write 44 tst r3, #1 << 20 @ L = 0 -> write
42 orreq r1, r1, #1 << 11 @ yes. 45 orreq r1, r1, #1 << 11 @ yes.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 087e239704df..524ddae92595 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -170,6 +170,9 @@ __v6_setup:
170#endif /* CONFIG_MMU */ 170#endif /* CONFIG_MMU */
171 adr r5, v6_crval 171 adr r5, v6_crval
172 ldmia r5, {r5, r6} 172 ldmia r5, {r5, r6}
173#ifdef CONFIG_CPU_ENDIAN_BE8
174 orr r6, r6, #1 << 25 @ big-endian page tables
175#endif
173 mrc p15, 0, r0, c1, c0, 0 @ read control register 176 mrc p15, 0, r0, c1, c0, 0 @ read control register
174 bic r0, r0, r5 @ clear bits them 177 bic r0, r0, r5 @ clear bits them
175 orr r0, r0, r6 @ set them 178 orr r0, r0, r6 @ set them
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3397f1e64d76..4f8486475a79 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
19 19
20#include "proc-macros.S" 20#include "proc-macros.S"
21 21
22#define TTB_C (1 << 0)
23#define TTB_S (1 << 1) 22#define TTB_S (1 << 1)
24#define TTB_RGN_NC (0 << 3) 23#define TTB_RGN_NC (0 << 3)
25#define TTB_RGN_OC_WBWA (1 << 3) 24#define TTB_RGN_OC_WBWA (1 << 3)
26#define TTB_RGN_OC_WT (2 << 3) 25#define TTB_RGN_OC_WT (2 << 3)
27#define TTB_RGN_OC_WB (3 << 3) 26#define TTB_RGN_OC_WB (3 << 3)
27#define TTB_NOS (1 << 5)
28#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
28 32
29#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
30#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
31#else 36#else
32#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
33#endif 39#endif
34 40
35ENTRY(cpu_v7_proc_init) 41ENTRY(cpu_v7_proc_init)
@@ -176,8 +182,8 @@ cpu_v7_name:
176 */ 182 */
177__v7_setup: 183__v7_setup:
178#ifdef CONFIG_SMP 184#ifdef CONFIG_SMP
179 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 185 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and
180 orr r0, r0, #(0x1 << 6) 186 orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting
181 mcr p15, 0, r0, c1, c0, 1 187 mcr p15, 0, r0, c1, c0, 1
182#endif 188#endif
183 adr r12, __v7_setup_stack @ the local stack 189 adr r12, __v7_setup_stack @ the local stack
@@ -213,12 +219,43 @@ __v7_setup:
213 mov r10, #0x1f @ domains 0, 1 = manager 219 mov r10, #0x1f @ domains 0, 1 = manager
214 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 220 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
215#endif 221#endif
216 ldr r5, =0xff0aa1a8 222 /*
217 ldr r6, =0x40e040e0 223 * Memory region attributes with SCTLR.TRE=1
224 *
225 * n = TEX[0],C,B
226 * TR = PRRR[2n+1:2n] - memory type
227 * IR = NMRR[2n+1:2n] - inner cacheable property
228 * OR = NMRR[2n+17:2n+16] - outer cacheable property
229 *
230 * n TR IR OR
231 * UNCACHED 000 00
232 * BUFFERABLE 001 10 00 00
233 * WRITETHROUGH 010 10 10 10
234 * WRITEBACK 011 10 11 11
235 * reserved 110
236 * WRITEALLOC 111 10 01 01
237 * DEV_SHARED 100 01
238 * DEV_NONSHARED 100 01
239 * DEV_WC 001 10
240 * DEV_CACHED 011 10
241 *
242 * Other attributes:
243 *
244 * DS0 = PRRR[16] = 0 - device shareable property
245 * DS1 = PRRR[17] = 1 - device shareable property
246 * NS0 = PRRR[18] = 0 - normal shareable property
247 * NS1 = PRRR[19] = 1 - normal shareable property
248 * NOS = PRRR[24+n] = 1 - not outer shareable
249 */
250 ldr r5, =0xff0a81a8 @ PRRR
251 ldr r6, =0x40e040e0 @ NMRR
218 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 252 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
219 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 253 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
220 adr r5, v7_crval 254 adr r5, v7_crval
221 ldmia r5, {r5, r6} 255 ldmia r5, {r5, r6}
256#ifdef CONFIG_CPU_ENDIAN_BE8
257 orr r6, r6, #1 << 25 @ big-endian page tables
258#endif
222 mrc p15, 0, r0, c1, c0, 0 @ read control register 259 mrc p15, 0, r0, c1, c0, 0 @ read control register
223 bic r0, r0, r5 @ clear bits them 260 bic r0, r0, r5 @ clear bits them
224 orr r0, r0, r6 @ set them 261 orr r0, r0, r6 @ set them
@@ -226,14 +263,14 @@ __v7_setup:
226ENDPROC(__v7_setup) 263ENDPROC(__v7_setup)
227 264
228 /* AT 265 /* AT
229 * TFR EV X F I D LR 266 * TFR EV X F I D LR S
230 * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM 267 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
231 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 268 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
232 * 1 0 110 0011 1.00 .111 1101 < we want 269 * 1 0 110 0011 1100 .111 1101 < we want
233 */ 270 */
234 .type v7_crval, #object 271 .type v7_crval, #object
235v7_crval: 272v7_crval:
236 crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c 273 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
237 274
238__v7_setup_stack: 275__v7_setup_stack:
239 .space 4 * 11 @ 11 registers 276 .space 4 * 11 @ 11 registers
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index b637e7380ab7..a26a605b73bd 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -42,9 +42,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
42 mov r1, r1, lsl #PAGE_SHIFT 42 mov r1, r1, lsl #PAGE_SHIFT
43 vma_vm_flags r2, r2 @ get vma->vm_flags 43 vma_vm_flags r2, r2 @ get vma->vm_flags
441: 441:
45 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 45#ifdef CONFIG_SMP
46 tst r2, #VM_EXEC @ Executable area ? 46 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
47 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 47#else
48 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
49#endif
48 add r0, r0, #PAGE_SZ 50 add r0, r0, #PAGE_SZ
49 cmp r0, r1 51 cmp r0, r1
50 blo 1b 52 blo 1b
@@ -69,8 +71,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
69 mov r0, r0, lsl #PAGE_SHIFT 71 mov r0, r0, lsl #PAGE_SHIFT
70 mov r1, r1, lsl #PAGE_SHIFT 72 mov r1, r1, lsl #PAGE_SHIFT
711: 731:
72 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 74#ifdef CONFIG_SMP
73 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 75 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
76#else
77 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
78#endif
74 add r0, r0, #PAGE_SZ 79 add r0, r0, #PAGE_SZ
75 cmp r0, r1 80 cmp r0, r1
76 blo 1b 81 blo 1b
@@ -87,5 +92,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
87ENTRY(v7wbi_tlb_fns) 92ENTRY(v7wbi_tlb_fns)
88 .long v7wbi_flush_user_tlb_range 93 .long v7wbi_flush_user_tlb_range
89 .long v7wbi_flush_kern_tlb_range 94 .long v7wbi_flush_kern_tlb_range
90 .long v6wbi_tlb_flags 95 .long v7wbi_tlb_flags
91 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns 96 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 853d42bb8682..4ce0f9801e2e 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -41,6 +41,7 @@
41#include <asm/irq.h> 41#include <asm/irq.h>
42#include <asm/mach/irq.h> 42#include <asm/mach/irq.h>
43#include <mach/hardware.h> 43#include <mach/hardware.h>
44#include <mach/board-eb.h>
44#include <asm/system.h> 45#include <asm/system.h>
45 46
46#include "op_counter.h" 47#include "op_counter.h"
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 83c4e384b16d..1aeae38725dd 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -100,6 +100,7 @@ ENTRY(vfp_support_entry)
100 beq no_old_VFP_process 100 beq no_old_VFP_process
101 VFPFSTMIA r4, r5 @ save the working registers 101 VFPFSTMIA r4, r5 @ save the working registers
102 VFPFMRX r5, FPSCR @ current status 102 VFPFMRX r5, FPSCR @ current status
103#ifndef CONFIG_CPU_FEROCEON
103 tst r1, #FPEXC_EX @ is there additional state to save? 104 tst r1, #FPEXC_EX @ is there additional state to save?
104 beq 1f 105 beq 1f
105 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) 106 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
@@ -107,6 +108,7 @@ ENTRY(vfp_support_entry)
107 beq 1f 108 beq 1f
108 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 109 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
1091: 1101:
111#endif
110 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 112 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
111 @ and point r4 at the word at the 113 @ and point r4 at the word at the
112 @ start of the register dump 114 @ start of the register dump
@@ -119,6 +121,7 @@ no_old_VFP_process:
119 VFPFLDMIA r10, r5 @ reload the working registers while 121 VFPFLDMIA r10, r5 @ reload the working registers while
120 @ FPEXC is in a safe state 122 @ FPEXC is in a safe state
121 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 123 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
124#ifndef CONFIG_CPU_FEROCEON
122 tst r1, #FPEXC_EX @ is there additional state to restore? 125 tst r1, #FPEXC_EX @ is there additional state to restore?
123 beq 1f 126 beq 1f
124 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) 127 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
@@ -126,6 +129,7 @@ no_old_VFP_process:
126 beq 1f 129 beq 1f
127 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 130 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
1281: 1311:
132#endif
129 VFPFMXR FPSCR, r5 @ restore status 133 VFPFMXR FPSCR, r5 @ restore status
130 134
131check_for_exception: 135check_for_exception:
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 01599c4ef726..2d7423af1197 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
253 } 253 }
254 254
255 if (fpexc & FPEXC_EX) { 255 if (fpexc & FPEXC_EX) {
256#ifndef CONFIG_CPU_FEROCEON
256 /* 257 /*
257 * Asynchronous exception. The instruction is read from FPINST 258 * Asynchronous exception. The instruction is read from FPINST
258 * and the interrupted instruction has to be restarted. 259 * and the interrupted instruction has to be restarted.
259 */ 260 */
260 trigger = fmrx(FPINST); 261 trigger = fmrx(FPINST);
261 regs->ARM_pc -= 4; 262 regs->ARM_pc -= 4;
263#endif
262 } else if (!(fpexc & FPEXC_DEX)) { 264 } else if (!(fpexc & FPEXC_DEX)) {
263 /* 265 /*
264 * Illegal combination of bits. It can be caused by an 266 * Illegal combination of bits. It can be caused by an
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 17:58:09 -0500