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-rw-r--r--arch/mips/Kconfig12
-rw-r--r--arch/mips/bcm47xx/nvram.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c22
-rw-r--r--arch/mips/include/asm/asmmacro.h11
-rw-r--r--arch/mips/include/asm/ftrace.h20
5 files changed, 40 insertions, 27 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 153447452d5e..95fa1f1d5c8b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1776,12 +1776,12 @@ endchoice
1776 1776
1777config FORCE_MAX_ZONEORDER 1777config FORCE_MAX_ZONEORDER
1778 int "Maximum zone order" 1778 int "Maximum zone order"
1779 range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB 1779 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1780 default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB 1780 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1781 range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB 1781 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1782 default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB 1782 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1783 range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB 1783 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1784 default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB 1784 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1785 range 11 64 1785 range 11 64
1786 default "11" 1786 default "11"
1787 help 1787 help
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 6decb27cf48b..2bed73a684ae 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -196,7 +196,7 @@ int bcm47xx_nvram_gpio_pin(const char *name)
196 char nvram_var[10]; 196 char nvram_var[10];
197 char buf[30]; 197 char buf[30];
198 198
199 for (i = 0; i < 16; i++) { 199 for (i = 0; i < 32; i++) {
200 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); 200 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
201 if (err <= 0) 201 if (err <= 0)
202 continue; 202 continue;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 25fbfae06c1f..c2bb4f896ce7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -975,10 +975,6 @@ static int octeon_irq_ciu_xlat(struct irq_domain *d,
975 if (ciu > 1 || bit > 63) 975 if (ciu > 1 || bit > 63)
976 return -EINVAL; 976 return -EINVAL;
977 977
978 /* These are the GPIO lines */
979 if (ciu == 0 && bit >= 16 && bit < 32)
980 return -EINVAL;
981
982 *out_hwirq = (ciu << 6) | bit; 978 *out_hwirq = (ciu << 6) | bit;
983 *out_type = 0; 979 *out_type = 0;
984 980
@@ -1007,6 +1003,10 @@ static int octeon_irq_ciu_map(struct irq_domain *d,
1007 if (!octeon_irq_virq_in_range(virq)) 1003 if (!octeon_irq_virq_in_range(virq))
1008 return -EINVAL; 1004 return -EINVAL;
1009 1005
1006 /* Don't map irq if it is reserved for GPIO. */
1007 if (line == 0 && bit >= 16 && bit <32)
1008 return 0;
1009
1010 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) 1010 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1011 return -EINVAL; 1011 return -EINVAL;
1012 1012
@@ -1525,10 +1525,6 @@ static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1525 ciu = intspec[0]; 1525 ciu = intspec[0];
1526 bit = intspec[1]; 1526 bit = intspec[1];
1527 1527
1528 /* Line 7 are the GPIO lines */
1529 if (ciu > 6 || bit > 63)
1530 return -EINVAL;
1531
1532 *out_hwirq = (ciu << 6) | bit; 1528 *out_hwirq = (ciu << 6) | bit;
1533 *out_type = 0; 1529 *out_type = 0;
1534 1530
@@ -1570,8 +1566,14 @@ static int octeon_irq_ciu2_map(struct irq_domain *d,
1570 if (!octeon_irq_virq_in_range(virq)) 1566 if (!octeon_irq_virq_in_range(virq))
1571 return -EINVAL; 1567 return -EINVAL;
1572 1568
1573 /* Line 7 are the GPIO lines */ 1569 /*
1574 if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0) 1570 * Don't map irq if it is reserved for GPIO.
1571 * (Line 7 are the GPIO lines.)
1572 */
1573 if (line == 7)
1574 return 0;
1575
1576 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1575 return -EINVAL; 1577 return -EINVAL;
1576 1578
1577 if (octeon_irq_ciu2_is_edge(line, bit)) 1579 if (octeon_irq_ciu2_is_edge(line, bit))
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 69a9a22d014a..4225e99bd7bf 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -9,6 +9,7 @@
9#define _ASM_ASMMACRO_H 9#define _ASM_ASMMACRO_H
10 10
11#include <asm/hazards.h> 11#include <asm/hazards.h>
12#include <asm/asm-offsets.h>
12 13
13#ifdef CONFIG_32BIT 14#ifdef CONFIG_32BIT
14#include <asm/asmmacro-32.h> 15#include <asm/asmmacro-32.h>
@@ -54,11 +55,21 @@
54 .endm 55 .endm
55 56
56 .macro local_irq_disable reg=t0 57 .macro local_irq_disable reg=t0
58#ifdef CONFIG_PREEMPT
59 lw \reg, TI_PRE_COUNT($28)
60 addi \reg, \reg, 1
61 sw \reg, TI_PRE_COUNT($28)
62#endif
57 mfc0 \reg, CP0_STATUS 63 mfc0 \reg, CP0_STATUS
58 ori \reg, \reg, 1 64 ori \reg, \reg, 1
59 xori \reg, \reg, 1 65 xori \reg, \reg, 1
60 mtc0 \reg, CP0_STATUS 66 mtc0 \reg, CP0_STATUS
61 irq_disable_hazard 67 irq_disable_hazard
68#ifdef CONFIG_PREEMPT
69 lw \reg, TI_PRE_COUNT($28)
70 addi \reg, \reg, -1
71 sw \reg, TI_PRE_COUNT($28)
72#endif
62 .endm 73 .endm
63#endif /* CONFIG_MIPS_MT_SMTC */ 74#endif /* CONFIG_MIPS_MT_SMTC */
64 75
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index ce35c9af0c28..992aaba603b5 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -22,12 +22,12 @@ extern void _mcount(void);
22#define safe_load(load, src, dst, error) \ 22#define safe_load(load, src, dst, error) \
23do { \ 23do { \
24 asm volatile ( \ 24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\ 25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26 " li %[" STR(error) "], 0\n" \ 26 " li %[tmp_err], 0\n" \
27 "2:\n" \ 27 "2:\n" \
28 \ 28 \
29 ".section .fixup, \"ax\"\n" \ 29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \ 30 "3: li %[tmp_err], 1\n" \
31 " j 2b\n" \ 31 " j 2b\n" \
32 ".previous\n" \ 32 ".previous\n" \
33 \ 33 \
@@ -35,8 +35,8 @@ do { \
35 STR(PTR) "\t1b, 3b\n\t" \ 35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \ 36 ".previous\n" \
37 \ 37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\ 38 : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
39 : [src] "r" (src) \ 39 : [tmp_src] "r" (src) \
40 : "memory" \ 40 : "memory" \
41 ); \ 41 ); \
42} while (0) 42} while (0)
@@ -44,12 +44,12 @@ do { \
44#define safe_store(store, src, dst, error) \ 44#define safe_store(store, src, dst, error) \
45do { \ 45do { \
46 asm volatile ( \ 46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\ 47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48 " li %[" STR(error) "], 0\n" \ 48 " li %[tmp_err], 0\n" \
49 "2:\n" \ 49 "2:\n" \
50 \ 50 \
51 ".section .fixup, \"ax\"\n" \ 51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \ 52 "3: li %[tmp_err], 1\n" \
53 " j 2b\n" \ 53 " j 2b\n" \
54 ".previous\n" \ 54 ".previous\n" \
55 \ 55 \
@@ -57,8 +57,8 @@ do { \
57 STR(PTR) "\t1b, 3b\n\t" \ 57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \ 58 ".previous\n" \
59 \ 59 \
60 : [error] "=r" (error) \ 60 : [tmp_err] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\ 61 : [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
62 : "memory" \ 62 : "memory" \
63 ); \ 63 ); \
64} while (0) 64} while (0)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 09:54:11 -0500