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-rw-r--r--arch/arm/mach-lpc32xx/pm.c146
-rw-r--r--arch/arm/mach-lpc32xx/suspend.S151
2 files changed, 297 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644
index 000000000000..a6e2aed9a49f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
1/*
2 * arch/arm/mach-lpc32xx/pm.c
3 *
4 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * LPC32XX CPU and system power management
15 *
16 * The LCP32XX has three CPU modes for controlling system power: run,
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
19 * mode is not used in normal operation. Halt mode is used when the
20 * system is fully suspended.
21 *
22 * Run mode:
23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25 * the HCLK_PLL rate. Linux runs in this mode.
26 *
27 * Direct-run mode:
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
29 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
30 * source or the frequency of the main oscillator. In this mode, the
31 * HCLK_PLL can be safely enabled, changed, or disabled.
32 *
33 * Halt mode:
34 * SYSCLK is gated off and the CPU and system clocks are halted.
35 * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
36 * key scanner, etc.) still operate if enabled. In this state, an enabled
37 * system event (ie, GPIO state change, RTC match, key press, etc.) will
38 * wake the system up back into direct-run mode.
39 *
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transistion to direct-run mode will stop all DDR accesses (no clocks).
45 * Because of this, the code to switch power modes and the code to enter
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
47 * section of IRAM is used instead for this.
48 *
49 * Suspend is handled with the following logic:
50 * Backup a small area of IRAM used for the suspend code
51 * Copy suspend code to IRAM
52 * Transfer control to code in IRAM
53 * Places DRAMs in self-refresh mode
54 * Enter direct-run mode
55 * Save state of HCLK_PLL PLL
56 * Disable HCLK_PLL PLL
57 * Enter halt mode - CPU and buses will stop
58 * System enters direct-run mode when an enabled event occurs
59 * HCLK PLL state is restored
60 * Run mode is entered
61 * DRAMS are placed back into normal mode
62 * Code execution returns from IRAM
63 * IRAM code are used for suspend is restored
64 * Suspend mode is exited
65 */
66
67#include <linux/suspend.h>
68#include <linux/io.h>
69#include <linux/slab.h>
70
71#include <asm/cacheflush.h>
72
73#include <mach/hardware.h>
74#include <mach/platform.h>
75#include "common.h"
76#include "clock.h"
77
78#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
79
80/*
81 * Both STANDBY and MEM suspend states are handled the same with no
82 * loss of CPU or memory state
83 */
84static int lpc32xx_pm_enter(suspend_state_t state)
85{
86 int (*lpc32xx_suspend_ptr) (void);
87 void *iram_swap_area;
88
89 /* Allocate some space for temporary IRAM storage */
90 iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
91 if (!iram_swap_area) {
92 printk(KERN_ERR
93 "PM Suspend: cannot allocate memory to save portion "
94 "of SRAM\n");
95 return -ENOMEM;
96 }
97
98 /* Backup a small area of IRAM used for the suspend code */
99 memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
100 lpc32xx_sys_suspend_sz);
101
102 /*
103 * Copy code to suspend system into IRAM. The suspend code
104 * needs to run from IRAM as DRAM may no longer be available
105 * when the PLL is stopped.
106 */
107 memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
108 lpc32xx_sys_suspend_sz);
109 flush_icache_range((unsigned long)TEMP_IRAM_AREA,
110 (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
111
112 /* Transfer to suspend code in IRAM */
113 lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
114 flush_cache_all();
115 (void) lpc32xx_suspend_ptr();
116
117 /* Restore original IRAM contents */
118 memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
119 lpc32xx_sys_suspend_sz);
120
121 kfree(iram_swap_area);
122
123 return 0;
124}
125
126static struct platform_suspend_ops lpc32xx_pm_ops = {
127 .valid = suspend_valid_only_mem,
128 .enter = lpc32xx_pm_enter,
129};
130
131#define EMC_DYN_MEM_CTRL_OFS 0x20
132#define EMC_SRMMC (1 << 3)
133#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
134static int __init lpc32xx_pm_init(void)
135{
136 /*
137 * Setup SDRAM self-refresh clock to automatically disable o
138 * start of self-refresh. This only needs to be done once.
139 */
140 __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
141
142 suspend_set_ops(&lpc32xx_pm_ops);
143
144 return 0;
145}
146arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644
index 000000000000..374f9f07fe48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
1/*
2 * arch/arm/mach-lpc32xx/suspend.S
3 *
4 * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <mach/platform.h>
15#include <mach/hardware.h>
16
17/* Using named register defines makes the code easier to follow */
18#define WORK1_REG r0
19#define WORK2_REG r1
20#define SAVED_HCLK_DIV_REG r2
21#define SAVED_HCLK_PLL_REG r3
22#define SAVED_DRAM_CLKCTRL_REG r4
23#define SAVED_PWR_CTRL_REG r5
24#define CLKPWRBASE_REG r6
25#define EMCBASE_REG r7
26
27#define LPC32XX_EMC_STATUS_OFFS 0x04
28#define LPC32XX_EMC_STATUS_BUSY 0x1
29#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
30
31#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
32#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
33#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
34
35#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
36
37 .text
38
39ENTRY(lpc32xx_sys_suspend)
40 @ Save a copy of the used registers in IRAM, r0 is corrupted
41 adr r0, tmp_stack_end
42 stmfd r0!, {r3 - r7, sp, lr}
43
44 @ Load a few common register addresses
45 adr WORK1_REG, reg_bases
46 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
47 ldr EMCBASE_REG, [WORK1_REG, #4]
48
49 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
50 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
51 orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
52
53 @ Wait for SDRAM busy status to go busy and then idle
54 @ This guarantees a small windows where DRAM isn't busy
551:
56 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
57 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
58 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
59 bne 1b @ Branch while idle
602:
61 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
62 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
63 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
64 beq 2b @ Branch until idle
65
66 @ Setup self-refresh with support for manual exit of
67 @ self-refresh mode
68 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
69 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
70 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
71 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
72
73 @ Wait for self-refresh acknowledge, clocks to the DRAM device
74 @ will automatically stop on start of self-refresh
753:
76 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
77 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
78 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
79 bne 3b @ Branch until self-refresh mode starts
80
81 @ Enter direct-run mode from run mode
82 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
83 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
84
85 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
86 @ issues on restart
87 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
88 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
89 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
90 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
91
92 @ Save HCLK PLL state and disable HCLK PLL
93 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
94 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
95 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
96 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
97
98 @ Enter stop mode until an enabled event occurs
99 orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
100 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
101 .rept 9
102 nop
103 .endr
104
105 @ Clear stop status
106 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
107
108 @ Restore original HCLK PLL value and wait for PLL lock
109 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
110 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
1114:
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
113 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
114 bne 4b
115
116 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
117 @ update yet. DRAM is still in self-refresh
118 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
119 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
120
121 @ Restore original DRAM clock mode to restore DRAM clocks
122 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
123 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
124
125 @ Clear self-refresh mode
126 orr WORK1_REG, SAVED_PWR_CTRL_REG,\
127 #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
128 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
129 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
130 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
131
132 @ Wait for EMC to clear self-refresh mode
1335:
134 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
135 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
136 bne 5b @ Branch until self-refresh has exited
137
138 @ restore regs and return
139 adr r0, tmp_stack
140 ldmfd r0!, {r3 - r7, sp, pc}
141
142reg_bases:
143 .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
144 .long IO_ADDRESS(LPC32XX_EMC_BASE)
145
146tmp_stack:
147 .long 0, 0, 0, 0, 0, 0, 0
148tmp_stack_end:
149
150ENTRY(lpc32xx_sys_suspend_sz)
151 .word . - lpc32xx_sys_suspend
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 07:09:58 -0500