228 files changed, 7321 insertions, 16808 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 56a4df952fb0..22e58a99f38b 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK
 
 config VGA_HOSE
         bool
-        depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
+        depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
         default y
         help
           Support VGA on an arbitrary hose; needed for several platforms
diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h
index 1f7fba671ae6..d70408d36677 100644
--- a/arch/alpha/include/asm/rtc.h
+++ b/arch/alpha/include/asm/rtc.h
@@ -1,14 +1,10 @@
 #ifndef _ALPHA_RTC_H
 #define _ALPHA_RTC_H
 
-#if defined(CONFIG_ALPHA_GENERIC)
+#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
+ || defined(CONFIG_ALPHA_GENERIC)
 # define get_rtc_time           alpha_mv.rtc_get_time
 # define set_rtc_time           alpha_mv.rtc_set_time
-#else
-# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
-#  define get_rtc_time          marvel_get_rtc_time
-#  define set_rtc_time          marvel_set_rtc_time
-# endif
 #endif
 
 #include <asm-generic/rtc.h>
diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c
index 5e7c28f92f19..61893d7bdda5 100644
--- a/arch/alpha/kernel/core_tsunami.c
+++ b/arch/alpha/kernel/core_tsunami.c
@@ -11,6 +11,7 @@
 #include <asm/core_tsunami.h>
 #undef __EXTERN_INLINE
 
+#include <linux/module.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/sched.h>
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 14a4b6a7cf59..407accc80877 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -317,7 +317,7 @@ marvel_init_irq(void)
 }
 
 static int 
-marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct pci_controller *hose = dev->sysdata;
         struct io7_port *io7_port = hose->sysdata;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9be624af131f..0a166b52600d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -468,7 +468,9 @@ config ARCH_MXS
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
+        select COMMON_CLK
         select HAVE_CLK_PREPARE
+        select PINCTRL
         help
           Support for Freescale MXS-based family of processors
 
@@ -980,6 +982,7 @@ config PLAT_SPEAR
         select ARM_AMBA
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -1187,6 +1190,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_326103
+        bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+        depends on CPU_V6
+        help
+          Executing a SWP instruction to read-only memory does not set bit 11
+          of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+          treat the access as a read, preventing a COW from occurring and
+          causing the faulting task to livelock.
+
 config ARM_ERRATA_411920
         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
         depends on CPU_V6 || CPU_V6K
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 15ded0deaa79..45bc4bb04e57 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -10,7 +10,7 @@
         intc: interrupt-controller@02080000 {
                 compatible = "qcom,msm-8660-qgic";
                 interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                 reg = < 0x02080000 0x1000 >,
                       < 0x02081000 0x1000 >;
         };
@@ -19,6 +19,6 @@
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x19c40000 0x1000>,
                       <0x19c00000 0x1000>;
-                interrupts = <195>;
+                interrupts = <0 195 0x0>;
         };
 };
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..fc82b1a26458
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,246 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@99000000 {
+                        st,pinmux-mode = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                clcd {
+                                        st,pins = "clcd_pfmode_grp";
+                                        st,function = "clcd";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_4bit_grp";
+                                        st,function = "sdhci";
+                                };
+                                gpio1 {
+                                        st,pins = "gpio1_4_to_7_grp",
+                                                "gpio1_0_to_3_grp";
+                                        st,function = "gpio1";
+                                };
+                        };
+                };
+
+                clcd@60000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@94000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        int-gpio = <&gpio1 0 0>;
+                        power-gpio = <&gpio1 2 1>;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@a9000000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        kbd@a0000000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x60000000 0x60000000 0x50000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@99000000 {
+                        compatible = "st,spear300-pinmux";
+                        reg = <0x99000000 0x1000>;
+                };
+
+                clcd@60000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x60000000 0x1000>;
+                        interrupts = <30>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@94000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x94000000 0x1000        /* FSMC Register */
+                               0x80000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <1>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio1: gpio@a9000000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xa9000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        kbd@a0000000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xa0000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..dc5e2d445a93
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,188 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+        model = "ST SPEAr310 Evaluation Board";
+        compatible = "st,spear310-evb", "st,spear310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b4000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                gpio0 {
+                                        st,pins = "gpio0_pin0_grp",
+                                                "gpio0_pin1_grp",
+                                                "gpio0_pin2_grp",
+                                                "gpio0_pin3_grp",
+                                                "gpio0_pin4_grp",
+                                                "gpio0_pin5_grp";
+                                        st,function = "gpio0";
+                                };
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                emi {
+                                        st,pins = "emi_cs_0_to_5_grp";
+                                        st,function = "emi";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_grp";
+                                        st,function = "fsmc";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                uart3 {
+                                        st,pins = "uart3_grp";
+                                        st,function = "uart3";
+                                };
+                                uart4 {
+                                        st,pins = "uart4_grp";
+                                        st,function = "uart4";
+                                };
+                                uart5 {
+                                        st,pins = "uart5_grp";
+                                        st,function = "uart5";
+                                };
+                        };
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@44000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2080000 {
+                               status = "okay";
+                        };
+
+                        serial@b2100000 {
+                               status = "okay";
+                        };
+
+                        serial@b2180000 {
+                               status = "okay";
+                        };
+
+                        serial@b2200000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b4000000 {
+                        compatible = "st,spear310-pinmux";
+                        reg = <0xb4000000 0x1000>;
+                };
+
+                fsmc: flash@44000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x44000000 0x1000        /* FSMC Register */
+                               0x40000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x10000>;
+                        st,cle-off = <0x20000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        serial@b2000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2080000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2100000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2180000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2180000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2200000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2200000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..6308fa3bec1e
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,198 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b3000000 {
+                        st,pinmux-mode = <3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_cd_51_grp";
+                                        st,function = "sdhci";
+                                };
+                                i2s {
+                                        st,pins = "i2s_grp";
+                                        st,function = "i2s";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                can0 {
+                                        st,pins = "can0_grp";
+                                        st,function = "can0";
+                                };
+                                can1 {
+                                        st,pins = "can1_grp";
+                                        st,function = "can1";
+                                };
+                                mii2 {
+                                        st,pins = "mii2_grp";
+                                        st,function = "mii2";
+                                };
+                                pwm0_1 {
+                                        st,pins = "pwm0_1_pin_14_15_grp";
+                                        st,function = "pwm0_1";
+                                };
+                                pwm2 {
+                                        st,pins = "pwm2_pin_13_grp";
+                                        st,function = "pwm2";
+                                };
+                        };
+                };
+
+                clcd@90000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        power-gpio = <&gpio0 2 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@a3000000 {
+                               status = "okay";
+                        };
+
+                        serial@a4000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x80000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b3000000 {
+                        compatible = "st,spear320-pinmux";
+                        reg = <0xb3000000 0x1000>;
+                };
+
+                clcd@90000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x90000000 0x1000>;
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@4c000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4c000000 0x1000        /* FSMC Register */
+                               0x50000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                spi1: spi@a5000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa5000000 0x1000>;
+                        status = "disabled";
+                };
+
+                spi2: spi@a6000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa6000000 0x1000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        i2c1: i2c@a7000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xa7000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a3000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa3000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a4000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa4000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..91072553963f
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,150 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&vic>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                vic: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <8>;
+                        status = "disabled";
+                };
+
+                gmac: eth@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupts = <23 22>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+
+                spi0: spi@d0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xd0100000 0x1000>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupts = <25>;
+                        status = "disabled";
+                };
+
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio0: gpio@fc980000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xfc980000 0x1000>;
+                                interrupts = <11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0180000 0x1000>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
+
+                        rtc@fc900000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        wdt@fc880000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0xfc880000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+
+                        timer@f0000000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xf0000000 0x400>;
+                                interrupts = <2>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..1119c22c9a82 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,11 +24,44 @@
         };
 
         ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
+
                 gmac: ethernet@e0800000 {
                         phy-mode = "gmii";
                         status = "okay";
                 };
 
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
                 apb {
                         serial@d0000000 {
                                 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..089f0a42c50e 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                         #interrupt-cells = <1>;
                 };
 
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
+
                 gmac: ethernet@e0800000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe0800000 0x8000>;
@@ -169,6 +177,12 @@
                                 interrupts = <28>;
                                 status = "disabled";
                         };
+
+                        timer@f0000000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xf0000000 0x400>;
+                                interrupts = <16>;
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 0b32925f2147..e2fe3195c0d1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
                         mmc@5000 {
                                 compatible = "arm,primecell";
                                 reg = < 0x5000 0x1000>;
-                                interrupts = <22>;
+                                interrupts = <22 34>;
                         };
                         kmi@6000 {
                                 compatible = "arm,pl050", "arm,primecell";
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 166461073b78..7e8175269064 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,7 +41,7 @@
                         mmc@b000 {
                                 compatible = "arm,primecell";
                                 reg = <0xb000 0x1000>;
-                                interrupts = <23>;
+                                interrupts = <23 34>;
                         };
                 };
         };
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 42da9183acc8..082175c54e7c 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_ARCH_S3C24XX=y
+# CONFIG_CPU_S3C2410 is not set
+CONFIG_CPU_S3C2440=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..865980c5f212 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..a2a1265f86b6 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d412a8d..0f04d84582e1 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
 extern void vfp_sync_hwstate(struct thread_info *);
 extern void vfp_flush_hwstate(struct thread_info *);
 
+struct user_vfp;
+struct user_vfp_exc;
+
+extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
+                                           struct user_vfp_exc __user *);
+extern int vfp_restore_user_hwstate(struct user_vfp __user *,
+                                    struct user_vfp_exc __user *);
 #endif
 
 /*
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 60843eb0f61c..73409e6c0251 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -7,6 +7,8 @@
 
         .macro set_tls_v6k, tp, tmp1, tmp2
         mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        mov     \tmp1, #0
+        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         .endm
 
         .macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@
         mov     \tmp2, #0xffff0fff
         tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
         mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        movne   \tmp1, #0
+        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
         .endm
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 71ccdbfed662..8349d4e97e2b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
         }
 
         c = irq_data_get_irq_chip(d);
-        if (c->irq_set_affinity)
-                c->irq_set_affinity(d, affinity, true);
-        else
+        if (!c->irq_set_affinity)
                 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
+        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+                cpumask_copy(d->affinity, affinity);
 
         return ret;
 }
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 7cb532fc8aa4..d68d1b694680 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
 
 static int preserve_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
         const unsigned long magic = VFP_MAGIC;
         const unsigned long size = VFP_STORAGE_SIZE;
         int err = 0;
 
-        vfp_sync_hwstate(thread);
         __put_user_error(magic, &frame->magic, err);
         __put_user_error(size, &frame->size, err);
 
-        /*
-         * Copy the floating point registers. There can be unused
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
-                              sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-        /*
-         * Copy the exception registers.
-         */
-        __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
-        __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
+        if (err)
+                return -EFAULT;
 
-        return err ? -EFAULT : 0;
+        return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 static int restore_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
         unsigned long magic;
         unsigned long size;
-        unsigned long fpexc;
         int err = 0;
 
         __get_user_error(magic, &frame->magic, err);
@@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
         if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
                 return -EINVAL;
 
-        vfp_flush_hwstate(thread);
-
-        /*
-         * Copy the floating point registers. There can be unused
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
-                                sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-        /*
-         * Sanitise and restore the exception registers.
-         */
-        __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
-        /* Ensure the VFP is enabled. */
-        fpexc |= FPEXC_EN;
-        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
-        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-        h->fpexc = fpexc;
-
-        __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
-
-        return err ? -EFAULT : 0;
+        return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index addbbe8028c2..f6a4d32b0421 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu)
         local_fiq_disable();
         local_irq_disable();
 
-#ifdef CONFIG_HOTPLUG_CPU
-        platform_cpu_kill(cpu);
-#endif
-
         while (1)
                 cpu_relax();
 }
@@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu)
         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void smp_kill_cpus(cpumask_t *mask)
+{
+        unsigned int cpu;
+        for_each_cpu(cpu, mask)
+                platform_cpu_kill(cpu);
+}
+#else
+static void smp_kill_cpus(cpumask_t *mask) { }
+#endif
+
 void smp_send_stop(void)
 {
         unsigned long timeout;
+        struct cpumask mask;
 
-        if (num_online_cpus() > 1) {
-                struct cpumask mask;
-                cpumask_copy(&mask, cpu_online_mask);
-                cpumask_clear_cpu(smp_processor_id(), &mask);
-
-                smp_cross_call(&mask, IPI_CPU_STOP);
-        }
+        cpumask_copy(&mask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &mask);
+        smp_cross_call(&mask, IPI_CPU_STOP);
 
         /* Wait up to one second for other CPUs to stop */
         timeout = USEC_PER_SEC;
@@ -595,6 +599,8 @@ void smp_send_stop(void)
 
         if (num_online_cpus() > 1)
                 pr_warning("SMP: failed to stop secondary CPUs\n");
+
+        smp_kill_cpus(&mask);
 }
 
 /*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 5b150afb995b..fef42b21cecb 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
          * The twd clock events must be reprogrammed to account for the new
          * frequency.  The timer is local to a cpu, so cross-call to the
          * changing cpu.
-         *
-         * Only wait for it to finish, if the cpu is active to avoid
-         * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
-         * booting of that cpu.
          */
         if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
                 smp_call_function_single(freqs->cpu, twd_update_frequency,
-                                         NULL, cpu_active(freqs->cpu));
+                        NULL, 1);
 
         return NOTIFY_OK;
 }
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index df54c2a92225..6efd1e5919fd 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_dout_mmc0.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos4_clk_dout_mmc1.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos4_clk_dout_mmc2.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos4_clk_dout_mmc3.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982d0f8e..5cd7a8b8868c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
                 .ctrlbit        = (1 << 20),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 15),
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_dout_mmc0.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos5_clk_dout_mmc1.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos5_clk_dout_mmc2.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos5_clk_dout_mmc3.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8614aab47cc0..5ccd6e80a607 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
         s3c_fimc_setname(2, "exynos4-fimc");
         s3c_fimc_setname(3, "exynos4-fimc");
 
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
+
         /* The I2C bus controllers are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
+
         /* The I2C bus controllers are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
 {
         int irq;
 
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+        of_irq_init(exynos4_dt_irq_match);
+#endif
 
         for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
index b025db4bf602..79035018fb74 100644
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -16,6 +16,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/mmc/dw_mmc.h>
 
 #include <plat/devs.h>
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
 }
 
 static struct resource exynos4_dwmci_resource[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_DWMCI,
-                .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DWMCI,
-                .end    = IRQ_DWMCI,
-                .flags  = IORESOURCE_IRQ,
-        }
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
+        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
 };
 
 static struct dw_mci_board exynos4_dwci_pdata = {
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b4f1f902ce6d..ed90aef404c3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
         .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                 MMC_CAP_ERASE),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 7ebf79c2ab34..cb2b027f09a6 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
         .max_width              = 8,
         .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7561eca131b0..a57a8ecfd93f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -34,6 +34,7 @@ config ARCH_MX53
 config SOC_IMX1
         bool
         select ARCH_MX1
+        select COMMON_CLK
         select CPU_ARM920T
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -42,12 +43,14 @@ config SOC_IMX21
         bool
         select MACH_MX21
         select CPU_ARM926T
+        select COMMON_CLK
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
 
 config SOC_IMX25
         bool
         select ARCH_MX25
+        select COMMON_CLK
         select CPU_ARM926T
         select ARCH_MXC_IOMUX_V3
         select MXC_AVIC
@@ -56,6 +59,7 @@ config SOC_IMX27
         bool
         select MACH_MX27
         select CPU_ARM926T
+        select COMMON_CLK
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
 
@@ -64,12 +68,14 @@ config SOC_IMX31
         select CPU_V6
         select IMX_HAVE_PLATFORM_MXC_RNGA
         select MXC_AVIC
+        select COMMON_CLK
         select SMP_ON_UP if SMP
 
 config SOC_IMX35
         bool
         select CPU_V6
         select ARCH_MXC_IOMUX_V3
+        select COMMON_CLK
         select HAVE_EPIT
         select MXC_AVIC
         select SMP_ON_UP if SMP
@@ -77,6 +83,7 @@ config SOC_IMX35
 config SOC_IMX5
         select CPU_V7
         select MXC_TZIC
+        select COMMON_CLK
         select ARCH_MXC_IOMUX_V3
         select ARCH_HAS_CPUFREQ
         select ARCH_MX5
@@ -836,12 +843,15 @@ config SOC_IMX6Q
         bool "i.MX6 Quad support"
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
+        select COMMON_CLK
         select CPU_V7
         select HAVE_ARM_SCU
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select HAVE_SMP
+        select PINCTRL
+        select PINCTRL_IMX6Q
         select USE_OF
 
         help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ab939c5046c3..629a3394feac 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,15 +1,18 @@
-obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
-obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
+obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
+obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 
-obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+
+obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
+                            clk-pfd.o clk-busy.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -70,7 +73,7 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
 AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
new file mode 100644
index 000000000000..1a7a8dd045a1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include "clk.h"
+
+static int clk_busy_wait(void __iomem *reg, u8 shift)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+        while (readl_relaxed(reg) & (1 << shift))
+                if (time_after(jiffies, timeout))
+                        return -ETIMEDOUT;
+
+        return 0;
+}
+
+struct clk_busy_divider {
+        struct clk_divider div;
+        const struct clk_ops *div_ops;
+        void __iomem *reg;
+        u8 shift;
+};
+
+static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
+{
+        struct clk_divider *div = container_of(hw, struct clk_divider, hw);
+
+        return container_of(div, struct clk_busy_divider, div);
+}
+
+static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
+                                                  unsigned long parent_rate)
+{
+        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+
+        return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
+}
+
+static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long *prate)
+{
+        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+
+        return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
+}
+
+static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+        int ret;
+
+        ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
+        if (!ret)
+                ret = clk_busy_wait(busy->reg, busy->shift);
+
+        return ret;
+}
+
+static struct clk_ops clk_busy_divider_ops = {
+        .recalc_rate = clk_busy_divider_recalc_rate,
+        .round_rate = clk_busy_divider_round_rate,
+        .set_rate = clk_busy_divider_set_rate,
+};
+
+struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
+                                 void __iomem *reg, u8 shift, u8 width,
+                                 void __iomem *busy_reg, u8 busy_shift)
+{
+        struct clk_busy_divider *busy;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        busy = kzalloc(sizeof(*busy), GFP_KERNEL);
+        if (!busy)
+                return ERR_PTR(-ENOMEM);
+
+        busy->reg = busy_reg;
+        busy->shift = busy_shift;
+
+        busy->div.reg = reg;
+        busy->div.shift = shift;
+        busy->div.width = width;
+        busy->div.lock = &imx_ccm_lock;
+        busy->div_ops = &clk_divider_ops;
+
+        init.name = name;
+        init.ops = &clk_busy_divider_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        busy->div.hw.init = &init;
+
+        clk = clk_register(NULL, &busy->div.hw);
+        if (!clk)
+                kfree(busy);
+
+        return clk;
+}
+
+struct clk_busy_mux {
+        struct clk_mux mux;
+        const struct clk_ops *mux_ops;
+        void __iomem *reg;
+        u8 shift;
+};
+
+static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
+{
+        struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
+
+        return container_of(mux, struct clk_busy_mux, mux);
+}
+
+static u8 clk_busy_mux_get_parent(struct clk_hw *hw)
+{
+        struct clk_busy_mux *busy = to_clk_busy_mux(hw);
+
+        return busy->mux_ops->get_parent(&busy->mux.hw);
+}
+
+static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_busy_mux *busy = to_clk_busy_mux(hw);
+        int ret;
+
+        ret = busy->mux_ops->set_parent(&busy->mux.hw, index);
+        if (!ret)
+                ret = clk_busy_wait(busy->reg, busy->shift);
+
+        return ret;
+}
+
+struct clk_ops clk_busy_mux_ops = {
+        .get_parent = clk_busy_mux_get_parent,
+        .set_parent = clk_busy_mux_set_parent,
+};
+
+struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
+                             u8 width, void __iomem *busy_reg, u8 busy_shift,
+                             const char **parent_names, int num_parents)
+{
+        struct clk_busy_mux *busy;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        busy = kzalloc(sizeof(*busy), GFP_KERNEL);
+        if (!busy)
+                return ERR_PTR(-ENOMEM);
+
+        busy->reg = busy_reg;
+        busy->shift = busy_shift;
+
+        busy->mux.reg = reg;
+        busy->mux.shift = shift;
+        busy->mux.width = width;
+        busy->mux.lock = &imx_ccm_lock;
+        busy->mux_ops = &clk_mux_ops;
+
+        init.name = name;
+        init.ops = &clk_busy_mux_ops;
+        init.flags = 0;
+        init.parent_names = parent_names;
+        init.num_parents = num_parents;
+
+        busy->mux.hw.init = &init;
+
+        clk = clk_register(NULL, &busy->mux.hw);
+        if (IS_ERR(clk))
+                kfree(busy);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
new file mode 100644
index 000000000000..3c1b8ff9a0a6
--- /dev/null
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static int clk_gate2_enable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = to_clk_gate(hw);
+        u32 reg;
+        unsigned long flags = 0;
+
+        if (gate->lock)
+                spin_lock_irqsave(gate->lock, flags);
+
+        reg = readl(gate->reg);
+        reg |= 3 << gate->bit_idx;
+        writel(reg, gate->reg);
+
+        if (gate->lock)
+                spin_unlock_irqrestore(gate->lock, flags);
+
+        return 0;
+}
+
+static void clk_gate2_disable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = to_clk_gate(hw);
+        u32 reg;
+        unsigned long flags = 0;
+
+        if (gate->lock)
+                spin_lock_irqsave(gate->lock, flags);
+
+        reg = readl(gate->reg);
+        reg &= ~(3 << gate->bit_idx);
+        writel(reg, gate->reg);
+
+        if (gate->lock)
+                spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_gate2_is_enabled(struct clk_hw *hw)
+{
+        u32 reg;
+        struct clk_gate *gate = to_clk_gate(hw);
+
+        reg = readl(gate->reg);
+
+        if (((reg >> gate->bit_idx) & 3) == 3)
+                return 1;
+
+        return 0;
+}
+
+static struct clk_ops clk_gate2_ops = {
+        .enable = clk_gate2_enable,
+        .disable = clk_gate2_disable,
+        .is_enabled = clk_gate2_is_enabled,
+};
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *reg, u8 bit_idx,
+                u8 clk_gate2_flags, spinlock_t *lock)
+{
+        struct clk_gate *gate;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+        if (!gate)
+                return ERR_PTR(-ENOMEM);
+
+        /* struct clk_gate assignments */
+        gate->reg = reg;
+        gate->bit_idx = bit_idx;
+        gate->flags = clk_gate2_flags;
+        gate->lock = lock;
+
+        init.name = name;
+        init.ops = &clk_gate2_ops;
+        init.flags = flags;
+        init.parent_names = parent_name ? &parent_name : NULL;
+        init.num_parents = parent_name ? 1 : 0;
+
+        gate->hw.init = &init;
+
+        clk = clk_register(dev, &gate->hw);
+        if (IS_ERR(clk))
+                kfree(clk);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
new file mode 100644
index 000000000000..0f0beb580b73
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -0,0 +1,115 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+/* CCM register addresses */
+#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+#define CCM_CSCR        IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
+#define CCM_PCDR        IO_ADDR_CCM(0x20)
+
+/* SCM register addresses */
+#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+#define SCM_GCCR        IO_ADDR_SCM(0xc)
+
+static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
+static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
+                                "fclk", };
+enum imx1_clks {
+        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
+        fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
+        mma_gate, usbd_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx1_clocks_init(unsigned long fref)
+{
+        int i;
+
+        clk[dummy] = imx_clk_fixed("dummy", 0);
+        clk[clk32] = imx_clk_fixed("clk32", fref);
+        clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
+        clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
+        clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+        clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
+                        ARRAY_SIZE(prem_sel_clks));
+        clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+        clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+        clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
+        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
+        clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
+        clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
+        clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
+        clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
+        clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
+        clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
+                        ARRAY_SIZE(clko_sel_clks));
+        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
+        clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
+        clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
+        clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("imx1 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_register_clkdev(clk[dma_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
+        clk_register_clkdev(clk[mma_gate], "mma", NULL);
+        clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
+        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
+        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
+        clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
+        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
+        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
+        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
+        clk_register_clkdev(clk[hclk], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
+        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
+        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
+        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
+        clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
+        clk_register_clkdev(clk[per2], "per", "imx-fb.0");
+        clk_register_clkdev(clk[dummy], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[dummy], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[hclk], "mshc", NULL);
+        clk_register_clkdev(clk[per3], "ssi", NULL);
+        clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
+        clk_register_clkdev(clk[clko], "clko", NULL);
+
+        mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                        MX1_TIM1_INT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
new file mode 100644
index 000000000000..4e4f384ee8dd
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR                IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
+#define CCM_PCDR0               IO_ADDR_CCM(0x18)
+#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0               IO_ADDR_CCM(0x20)
+#define CCM_PCCR1               IO_ADDR_CCM(0x24)
+#define CCM_CCSR                IO_ADDR_CCM(0x28)
+#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
+
+static const char *mpll_sel_clks[] = { "fpm", "ckih", };
+static const char *spll_sel_clks[] = { "fpm", "ckih", };
+
+enum imx21_clks {
+        ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
+        per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
+        uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
+        pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
+        lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
+        per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
+        ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
+        emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
+        gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+        int i;
+
+        clk[ckil] = imx_clk_fixed("ckil", lref);
+        clk[ckih] = imx_clk_fixed("ckih", href);
+        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
+                        ARRAY_SIZE(mpll_sel_clks));
+        clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
+                        ARRAY_SIZE(spll_sel_clks));
+        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+        clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
+        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
+        clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+        clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+        clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
+        clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
+        clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
+        clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
+        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
+        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+        clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
+        clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
+        clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+        clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
+        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
+        clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
+        clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+        clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
+        clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+        clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
+        clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+        clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
+        clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+        clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
+        clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+        clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+        clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
+        clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
+        clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX21 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_register_clkdev(clk[per1], "per1", NULL);
+        clk_register_clkdev(clk[per2], "per2", NULL);
+        clk_register_clkdev(clk[per3], "per3", NULL);
+        clk_register_clkdev(clk[per4], "per4", NULL);
+        clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
+        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
+        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
+        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
+        clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
+        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
+        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
+        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
+        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
+        clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
+        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
+        clk_register_clkdev(clk[per3], "per", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
+        clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
+        clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
+        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
+        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
+        clk_register_clkdev(clk[brom_gate], "brom", NULL);
+        clk_register_clkdev(clk[emma_gate], "emma", NULL);
+        clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
+        clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
+        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
+        clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
+        clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
+        clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
+        clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
+        clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
+
+        mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+                        MX21_INT_GPT1);
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
new file mode 100644
index 000000000000..d9833bb5fd61
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include "clk.h"
+
+#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL       0x00
+#define CCM_UPCTL       0x04
+#define CCM_CCTL        0x08
+#define CCM_CGCR0       0x0C
+#define CCM_CGCR1       0x10
+#define CCM_CGCR2       0x14
+#define CCM_PCDR0       0x18
+#define CCM_PCDR1       0x1C
+#define CCM_PCDR2       0x20
+#define CCM_PCDR3       0x24
+#define CCM_RCSR        0x28
+#define CCM_CRDR        0x2C
+#define CCM_DCVR0       0x30
+#define CCM_DCVR1       0x34
+#define CCM_DCVR2       0x38
+#define CCM_DCVR3       0x3c
+#define CCM_LTR0        0x40
+#define CCM_LTR1        0x44
+#define CCM_LTR2        0x48
+#define CCM_LTR3        0x4c
+#define CCM_MCR         0x64
+
+#define ccm(x)  (CRM_BASE + (x))
+
+static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
+static const char *per_sel_clks[] = { "ahb", "upll", };
+
+enum mx25_clks {
+        dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
+        per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
+        per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
+        per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
+        per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
+        csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
+        lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
+        csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
+        usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
+        cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
+        kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
+        ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
+        uart4_ipg, uart5_ipg, wdt_ipg, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx25_clocks_init(void)
+{
+        int i;
+
+        clk[dummy] = imx_clk_fixed("dummy", 0);
+        clk[osc] = imx_clk_fixed("osc", 24000000);
+        clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
+        clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
+        clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
+        clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+        clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
+        clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
+        clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); 
+        clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+        clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
+        clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
+        clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
+        clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
+        clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
+        clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
+        clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
+        clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
+        clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
+        clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
+        clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
+        clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
+        clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
+        clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
+        clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
+        clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
+        clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
+        clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0),  3);
+        clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0),  4);
+        clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0),  5);
+        clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0),  6);
+        clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0),  7);
+        clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0),  8);
+        clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
+        clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
+        clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
+        clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
+        clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
+        clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
+        clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
+        clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
+        clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
+        clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
+        clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1),  2);
+        clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1),  3);
+        clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1),  4);
+        clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1),  5);
+        clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1),  6);
+        clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1),  7);
+        clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1),  8);
+        clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
+        clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
+        clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
+        clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
+        clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
+        clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
+        clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
+        clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);
+        clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2),  1);
+        clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2),  2);
+        clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2),  6);
+        clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
+        clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
+        clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
+        clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
+        clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
+        clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
+        clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
+        clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
+        clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX25 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        /* i.mx25 has the i.mx21 type uart */
+        clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+        clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
+        /* i.mx25 has the i.mx35 type cspi */
+        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
+        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
+        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
+        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
+        clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
+        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
+        clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
+        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
+        clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
+        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
+        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
+        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
+        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
+        clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
+        clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
+        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
+        clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
+        clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+        clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
+        clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
+        clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
+        clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
+        clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
+        clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
+        clk_register_clkdev(clk[csi_ipg_per], "per", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ipg], "ipg", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ahb], "ahb", "mx2-camera.0");
+        clk_register_clkdev(clk[dummy], "audmux", NULL);
+        clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
+        clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
+        /* i.mx25 has the i.mx35 type sdma */
+        clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
+        clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
+        clk_register_clkdev(clk[iim_ipg], "iim", NULL);
+
+        mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
new file mode 100644
index 000000000000..50a7ebd8d1b2
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -0,0 +1,290 @@
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR                IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
+#define CCM_PCDR0               IO_ADDR_CCM(0x18)
+#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0               IO_ADDR_CCM(0x20)
+#define CCM_PCCR1               IO_ADDR_CCM(0x24)
+#define CCM_CCSR                IO_ADDR_CCM(0x28)
+#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS     (1 << 31)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_VPU            (1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
+static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+static const char *clko_sel_clks[] = {
+        "ckil", "prem", "ckih", "ckih",
+        "ckih", "mpll", "spll", "cpu_div",
+        "ahb", "ipg", "per1_div", "per2_div",
+        "per3_div", "per4_div", "ssi1_div", "ssi2_div",
+        "nfc_div", "mshc_div", "vpu_div", "60m",
+        "32k", "usb_div", "dptc",
+};
+
+static const char *ssi_sel_clks[] = { "spll", "mpll", };
+
+enum mx27_clks {
+        dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
+        per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
+        clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
+        clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
+        sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
+        rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
+        kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
+        gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
+        gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
+        emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
+        cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
+        vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
+        usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
+        vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
+        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
+        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
+        uart2_ipg_gate, uart1_ipg_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+        int i;
+
+        clk[dummy] = imx_clk_fixed("dummy", 0);
+        clk[ckih] = imx_clk_fixed("ckih", fref);
+        clk[ckil] = imx_clk_fixed("ckil", 32768);
+        clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+                clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+        } else {
+                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
+                clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
+        }
+
+        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+        clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+        clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+        clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+        clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+        clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+        clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
+        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+        clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+        clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+        else
+                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
+        clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
+        clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+        clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
+        clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
+        clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+        clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+        clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+        clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+        clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+        clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+        clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+        clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+        clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+        clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+        clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+        clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+        clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+        clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+        clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+        clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
+        clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
+        clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+        clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+        clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+        clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+        clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+        clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+        clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+        clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+        clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+        clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+        clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+        clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+        clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+        clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+        clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+        clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+        clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+        clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+        clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX27 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
+        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
+        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
+        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
+        clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
+        clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
+        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
+        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
+        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
+        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.0");
+        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "mxc-mmc.0");
+        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.1");
+        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.1");
+        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.2");
+        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.2");
+        clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
+        clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
+        clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
+        clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[csi_ahb_gate], NULL, "mx2-camera.0");
+        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
+        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
+        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
+        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
+        clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
+        clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
+        clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
+        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "imx-emma");
+        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "imx-emma");
+        clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
+        clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
+        clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
+        clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
+        clk_register_clkdev(clk[rtc_ipg_gate], "rtc", NULL);
+        clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
+        clk_register_clkdev(clk[cpu_div], "cpu", NULL);
+        clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
+        clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
+
+        mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+                        MX27_INT_GPT1);
+
+        clk_prepare_enable(clk[emi_ahb_gate]);
+
+        return 0;
+}
+
+#ifdef CONFIG_OF
+int __init mx27_clocks_init_dt(void)
+{
+        struct device_node *np;
+        u32 fref = 26000000; /* default */
+
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                        continue;
+
+                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                        break;
+        }
+
+        return mx27_clocks_init(fref);
+}
+#endif
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
new file mode 100644
index 000000000000..a854b9cae5ea
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/mx31.h>
+#include <mach/common.h>
+
+#include "clk.h"
+#include "crmregs-imx3.h"
+
+static const char *mcu_main_sel[] = { "spll", "mpll", };
+static const char *per_sel[] = { "per_div", "ipg", };
+static const char *csi_sel[] = { "upll", "spll", };
+static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
+
+enum mx31_clks {
+        ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
+        per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
+        fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
+        iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
+        uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
+        mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
+        sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
+        uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
+        gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx31_clocks_init(unsigned long fref)
+{
+        void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
+        int i;
+
+        clk[ckih] = imx_clk_fixed("ckih", fref);
+        clk[ckil] = imx_clk_fixed("ckil", 32768);
+        clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
+        clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
+        clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
+        clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
+        clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
+        clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
+        clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
+        clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
+        clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
+        clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
+        clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
+        clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
+        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
+        clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
+        clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
+        clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
+        clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
+        clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
+        clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
+        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
+        clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
+        clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
+        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
+        clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
+        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
+        clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
+        clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
+        clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
+        clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
+        clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
+        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
+        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
+        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
+        clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
+        clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
+        clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
+        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
+        clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
+        clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
+        clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
+        clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
+        clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
+        clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
+        clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
+        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
+        clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
+        clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
+        clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
+        clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
+        clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
+        clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
+        clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
+        clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
+        clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
+        clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
+        clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("imx31 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
+        clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
+        clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
+        clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
+        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
+        clk_register_clkdev(clk[epit1_gate], "epit", NULL);
+        clk_register_clkdev(clk[epit2_gate], "epit", NULL);
+        clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
+        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+        clk_register_clkdev(clk[kpp_gate], "kpp", NULL);
+        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
+        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
+        /* i.mx31 has the i.mx21 type uart */
+        clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
+        clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
+        clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
+        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[firi_gate], "firi", NULL);
+        clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
+        clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
+        clk_register_clkdev(clk[rng_gate], "rng", NULL);
+        clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
+        clk_register_clkdev(clk[iim_gate], "iim", NULL);
+
+        clk_set_parent(clk[csi], clk[upll]);
+        clk_prepare_enable(clk[emi_gate]);
+        clk_prepare_enable(clk[iim_gate]);
+        mx31_revision();
+        clk_disable_unprepare(clk[iim_gate]);
+
+        mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
+                        MX31_INT_GPT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
new file mode 100644
index 000000000000..a9e60bf7dd75
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include "crmregs-imx3.h"
+#include "clk.h"
+
+struct arm_ahb_div {
+        unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+        { .arm = 1, .ahb = 4, .sel = 0},
+        { .arm = 1, .ahb = 3, .sel = 1},
+        { .arm = 2, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 1, .sel = 0},
+        { .arm = 1, .ahb = 5, .sel = 0},
+        { .arm = 1, .ahb = 8, .sel = 0},
+        { .arm = 1, .ahb = 6, .sel = 1},
+        { .arm = 2, .ahb = 4, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static char hsp_div_532[] = { 4, 8, 3, 0 };
+static char hsp_div_400[] = { 3, 6, 3, 0 };
+
+static const char *std_sel[] = {"ppll", "arm"};
+static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
+
+enum mx35_clks {
+        ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
+        arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
+        esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
+        spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
+        ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
+        audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
+        edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
+        esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
+        gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
+        kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
+        rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
+        ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
+        wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
+        clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx35_clocks_init()
+{
+        void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
+        u32 pdr0, consumer_sel, hsp_sel;
+        struct arm_ahb_div *aad;
+        unsigned char *hsp_div;
+        int i;
+
+        pdr0 = __raw_readl(base + MXC_CCM_PDR0);
+        consumer_sel = (pdr0 >> 16) & 0xf;
+        aad = &clk_consumer[consumer_sel];
+        if (!aad->arm) {
+                pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
+                /*
+                 * We are basically stuck. Continue with a default entry and hope we
+                 * get far enough to actually show the above message
+                 */
+                aad = &clk_consumer[0];
+        }
+
+        clk[ckih] = imx_clk_fixed("ckih", 24000000);
+        clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
+        clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
+
+        clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
+
+        if (aad->sel)
+                clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
+        else
+                clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
+
+        if (clk_get_rate(clk[arm]) > 400000000)
+                hsp_div = hsp_div_532;
+        else
+                hsp_div = hsp_div_400;
+
+        hsp_sel = (pdr0 >> 20) & 0x3;
+        if (!hsp_div[hsp_sel]) {
+                pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
+                hsp_sel = 0;
+        }
+
+        clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
+
+        clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
+        clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+
+        clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
+        clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
+        clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
+
+        clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
+
+        clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
+        clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
+        clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
+
+        clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 
+        clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
+
+        clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
+        clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
+        clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
+        clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
+
+        clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
+
+        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
+
+        clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
+        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
+        clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
+        clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0,  6);
+        clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0,  8);
+        clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
+        clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
+        clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
+        clk[edio_gate] = imx_clk_gate2("edio_gate",   "ipg", base + MX35_CCM_CGR0, 16);
+        clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
+        clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
+        clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
+        clk[esai_gate] = imx_clk_gate2("esai_gate",   "ipg", base + MX35_CCM_CGR0, 24);
+        clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
+        clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
+        clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
+
+        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1,  0);
+        clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1,  2);
+        clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1,  4);
+        clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1,  6);
+        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1,  8);
+        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
+        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
+        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
+        clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
+        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
+        clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
+        clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
+        clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
+        clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
+        clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
+        clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
+
+        clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2,  0);
+        clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2,  2);
+        clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2,  4);
+        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2,  6);
+        clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2,  8);
+        clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
+        clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
+        clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
+        clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
+        clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
+        clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
+        clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
+        clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
+        clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
+        clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
+
+        clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3,  0);
+        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
+        clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX35 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+
+        clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
+        clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
+        clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
+        clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
+        clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
+        clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
+        clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
+        clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
+        clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
+        clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
+        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
+        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
+        clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
+        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
+        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
+        clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
+        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
+        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
+        /* i.mx35 has the i.mx27 type fec */
+        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
+        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
+        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
+        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
+        clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
+        clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
+        clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
+        clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+        /* i.mx35 has the i.mx21 type uart */
+        clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
+        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+
+        clk_prepare_enable(clk[spba_gate]);
+        clk_prepare_enable(clk[gpio1_gate]);
+        clk_prepare_enable(clk[gpio2_gate]);
+        clk_prepare_enable(clk[gpio3_gate]);
+        clk_prepare_enable(clk[iim_gate]);
+        clk_prepare_enable(clk[emi_gate]);
+
+        imx_print_silicon_rev("i.MX35", mx35_revision());
+
+#ifdef CONFIG_MXC_USE_EPIT
+        epit_timer_init(&epit1_clk,
+                        MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
+        mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
+                        MX35_INT_GPT);
+#endif
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
new file mode 100644
index 000000000000..b8a382defb23
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include "crm-regs-imx5.h"
+#include "clk.h"
+
+/* Low-power Audio Playback Mode clock */
+static const char *lp_apm_sel[] = { "osc", };
+
+/* This is used multiple times */
+static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
+static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
+static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
+static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
+static const char *per_root_sel[] = { "per_podf", "ipg", };
+static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
+static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
+static const char *emi_slow_sel[] = { "main_bus", "ahb", };
+static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
+static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
+static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
+static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
+static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
+static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
+static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+
+enum imx5_clks {
+        dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
+        uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
+        emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
+        usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
+        tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
+        uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
+        gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
+        gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
+        esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
+        ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
+        ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
+        ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
+        vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
+        uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
+        esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
+        mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
+        ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
+        ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
+        periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
+        tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
+        esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
+        usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
+        pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
+        ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
+        usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
+        clk_max
+};
+
+static struct clk *clk[clk_max];
+
+static void __init mx5_clocks_common_init(unsigned long rate_ckil,
+                unsigned long rate_osc, unsigned long rate_ckih1,
+                unsigned long rate_ckih2)
+{
+        int i;
+
+        clk[dummy] = imx_clk_fixed("dummy", 0);
+        clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
+        clk[osc] = imx_clk_fixed("osc", rate_osc);
+        clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
+        clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
+
+        clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
+                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+        clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
+                                periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
+        clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
+                                main_bus_sel, ARRAY_SIZE(main_bus_sel));
+        clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
+                                per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
+        clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
+        clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
+        clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
+        clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
+                                per_root_sel, ARRAY_SIZE(per_root_sel));
+        clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
+        clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
+        clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
+        clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
+        clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
+        clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
+        clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
+        clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
+        clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
+        clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
+        clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
+        clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
+                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
+        clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
+
+        clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
+                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
+                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
+        clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
+        clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
+        clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
+        clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+        clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
+
+        clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
+                                emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
+        clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
+        clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
+        clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
+                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
+        clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
+        clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
+                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
+        clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
+        clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
+        clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
+        clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
+                                usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
+        clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+        clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
+        clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
+        clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
+        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
+        clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
+        clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
+        clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
+        clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
+        clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
+        clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
+        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
+        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
+        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
+        clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
+        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
+        clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
+        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
+        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
+        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
+        clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
+        clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
+        clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
+        clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
+        clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
+        clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
+        clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
+        clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
+        clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
+        clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
+        clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
+        clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
+        clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
+        clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
+        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
+        clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
+        clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
+        clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
+        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
+        clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
+        clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
+        clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
+        clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
+        clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
+        clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
+        clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+        clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+        clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+        clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
+        clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX5 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+        
+        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
+        clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
+        clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
+        clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
+        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
+        clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
+        clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
+        clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
+        clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
+        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
+        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
+        clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
+        clk_register_clkdev(clk[iim_gate], "iim", NULL);
+        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
+        clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
+        clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+
+        /* Set SDHC parents to be PLL2 */
+        clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
+        clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
+
+        /* move usb phy clk to 24MHz */
+        clk_set_parent(clk[usb_phy_sel], clk[osc]);
+
+        clk_prepare_enable(clk[gpc_dvfs]);
+        clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
+        clk_prepare_enable(clk[aips_tz1]);
+        clk_prepare_enable(clk[aips_tz2]); /* fec */
+        clk_prepare_enable(clk[spba]);
+        clk_prepare_enable(clk[emi_fast_gate]); /* fec */
+        clk_prepare_enable(clk[tmax1]);
+        clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
+        clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
+}
+
+int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+                        unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+        int i;
+
+        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
+        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
+        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
+        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
+        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
+        clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                                mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
+        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
+        clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
+        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
+        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
+        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+        clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
+        clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
+        clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
+        clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
+        clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
+        clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX51 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+        clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
+        clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
+        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
+        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
+        clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+        clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
+        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
+
+        /* set the usboh3 parent to pll2_sw */
+        clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
+
+        /* set SDHC root clock to 166.25MHZ*/
+        clk_set_rate(clk[esdhc_a_podf], 166250000);
+        clk_set_rate(clk[esdhc_b_podf], 166250000);
+
+        /* System timer */
+        mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+                MX51_INT_GPT);
+
+        clk_prepare_enable(clk[iim_gate]);
+        imx_print_silicon_rev("i.MX51", mx51_revision());
+        clk_disable_unprepare(clk[iim_gate]);
+
+        return 0;
+}
+
+int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+                        unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+        int i;
+        unsigned long r;
+
+        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+        clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
+
+        clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
+                                mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
+        clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
+        clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
+        clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
+                                mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
+        clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
+        clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
+        clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
+        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                                mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
+        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                                mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
+        clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                                mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
+        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
+        clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
+        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
+        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
+        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+        clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
+        clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
+        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
+        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX53 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+        clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
+        clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+        clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
+        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
+
+        /* set SDHC root clock to 200MHZ*/
+        clk_set_rate(clk[esdhc_a_podf], 200000000);
+        clk_set_rate(clk[esdhc_b_podf], 200000000);
+
+        /* System timer */
+        mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+                MX53_INT_GPT);
+
+        clk_prepare_enable(clk[iim_gate]);
+        imx_print_silicon_rev("i.MX53", mx53_revision());
+        clk_disable_unprepare(clk[iim_gate]);
+
+        r = clk_round_rate(clk[usboh3_per_gate], 54000000);
+        clk_set_rate(clk[usboh3_per_gate], r);
+
+        return 0;
+}
+
+#ifdef CONFIG_OF
+static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+                                   unsigned long *ckih1, unsigned long *ckih2)
+{
+        struct device_node *np;
+
+        /* retrieve the freqency of fixed clocks from device tree */
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                u32 rate;
+                if (of_property_read_u32(np, "clock-frequency", &rate))
+                        continue;
+
+                if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                        *ckil = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                        *osc = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                        *ckih1 = rate;
+                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+                        *ckih2 = rate;
+        }
+}
+
+int __init mx51_clocks_init_dt(void)
+{
+        unsigned long ckil, osc, ckih1, ckih2;
+
+        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+}
+
+int __init mx53_clocks_init_dt(void)
+{
+        unsigned long ckil, osc, ckih1, ckih2;
+
+        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+}
+#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
new file mode 100644
index 000000000000..f40a35da2e5c
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <mach/common.h>
+#include "clk.h"
+
+#define CCGR0                           0x68
+#define CCGR1                           0x6c
+#define CCGR2                           0x70
+#define CCGR3                           0x74
+#define CCGR4                           0x78
+#define CCGR5                           0x7c
+#define CCGR6                           0x80
+#define CCGR7                           0x84
+
+#define CLPCR                           0x54
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+
+static void __iomem *ccm_base;
+
+void __init imx6q_clock_map_io(void) { }
+
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        u32 val = readl_relaxed(ccm_base + CLPCR);
+
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel_relaxed(val, ccm_base + CLPCR);
+
+        return 0;
+}
+
+static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
+static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
+static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
+static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", };
+static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
+static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
+static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
+static const char *gpu_axi_sels[]       = { "axi", "ahb", };
+static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
+static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
+static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
+static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu2_di0_sels[]      = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu2_di1_sels[]      = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *hsi_tx_sels[]        = { "pll3_120m", "pll2_pfd2_396m", };
+static const char *pcie_axi_sels[]      = { "axi", "ahb", };
+static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
+static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
+static const char *emi_sels[]           = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *vdo_axi_sels[]       = { "axi", "ahb", };
+static const char *vpu_axi_sels[]       = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
+                                    "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
+                                    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
+
+static const char * const clks_init_on[] __initconst = {
+        "mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
+};
+
+enum mx6q_clks {
+        dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+        pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
+        pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
+        periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
+        esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
+        gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
+        ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
+        ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
+        ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
+        usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
+        emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
+        periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
+        asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
+        gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
+        ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
+        ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
+        ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
+        usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
+        emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
+        mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
+        can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
+        esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
+        hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
+        ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
+        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
+        gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
+        ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
+        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
+        pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx6q_clocks_init(void)
+{
+        struct device_node *np;
+        void __iomem *base;
+        struct clk *c;
+        int i, irq;
+
+        clk[dummy] = imx_clk_fixed("dummy", 0);
+
+        /* retrieve the freqency of fixed clocks from device tree */
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                u32 rate;
+                if (of_property_read_u32(np, "clock-frequency", &rate))
+                        continue;
+
+                if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                        clk[ckil] = imx_clk_fixed("ckil", rate);
+                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                        clk[ckih] = imx_clk_fixed("ckih", rate);
+                else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                        clk[osc] = imx_clk_fixed("osc", rate);
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        /*                   type                               name         parent_name  base     gate_mask div_mask */
+        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x2000,   0x7f);
+        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x2000,   0x1);
+        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x2000,   0x3);
+        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x2000,   0x7f);
+        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x2000,   0x7f);
+        clk[pll6_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll6_mlb",     "osc", base + 0xd0, 0x2000,   0x0);
+        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
+        clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
+
+        /*                                name              parent_name        reg       idx */
+        clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+        clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
+        clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
+        clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
+        clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
+        clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
+        clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
+
+        /*                                    name         parent_name     mult div */
+        clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+        clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clk[pll3_80m]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clk[pll3_60m]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+        clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        ccm_base = base;
+
+        /*                                  name                reg       shift width parent_names     num_parents */
+        clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clk[pll1_sw]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
+        clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[spdif_sel]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[gpu2d_axi]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[gpu3d_axi]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[gpu2d_core_sel]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+        clk[gpu3d_core_sel]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
+        clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+        clk[ipu1_sel]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[ipu2_sel]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[ldb_di0_sel]      = imx_clk_mux("ldb_di0_sel",      base + 0x2c, 9,  3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+        clk[ldb_di1_sel]      = imx_clk_mux("ldb_di1_sel",      base + 0x2c, 12, 3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+        clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+        clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+        clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+        clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+        clk[ipu1_di0_sel]     = imx_clk_mux("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels));
+        clk[ipu1_di1_sel]     = imx_clk_mux("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels));
+        clk[ipu2_di0_sel]     = imx_clk_mux("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels));
+        clk[ipu2_di1_sel]     = imx_clk_mux("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels));
+        clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
+        clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
+        clk[ssi1_sel]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clk[ssi2_sel]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clk[ssi3_sel]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clk[usdhc1_sel]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clk[usdhc2_sel]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clk[usdhc3_sel]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clk[usdhc4_sel]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+        clk[emi_sel]          = imx_clk_mux("emi_sel",          base + 0x1c, 27, 2, emi_sels,          ARRAY_SIZE(emi_sels));
+        clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_sels,          ARRAY_SIZE(emi_sels));
+        clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
+        clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
+        clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
+
+        /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
+        clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+        /*                                      name                parent_name          reg       shift width */
+        clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
+        clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
+        clk[ipg_per]          = imx_clk_divider("ipg_per",          "ipg",               base + 0x1c, 0,  6);
+        clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
+        clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
+        clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
+        clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
+        clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
+        clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
+        clk[can_root]         = imx_clk_divider("can_root",         "pll3_usb_otg",      base + 0x20, 2,  6);
+        clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+        clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
+        clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
+        clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
+        clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
+        clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
+        clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_sel",       base + 0x20, 10, 1);
+        clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_sel",       base + 0x20, 11, 1);
+        clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
+        clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
+        clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
+        clk[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
+        clk[hsi_tx_podf]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
+        clk[ssi1_pred]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
+        clk[ssi1_podf]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
+        clk[ssi2_pred]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
+        clk[ssi2_podf]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
+        clk[ssi3_pred]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
+        clk[ssi3_podf]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
+        clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
+        clk[usdhc1_podf]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
+        clk[usdhc2_podf]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
+        clk[usdhc3_podf]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
+        clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
+        clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
+        clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
+        clk[emi_podf]         = imx_clk_divider("emi_podf",         "emi_sel",           base + 0x1c, 20, 3);
+        clk[emi_slow_podf]    = imx_clk_divider("emi_slow_podf",    "emi_slow_sel",      base + 0x1c, 23, 3);
+        clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
+        clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
+
+        /*                                            name                 parent_name    reg        shift width busy: reg, shift */
+        clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
+        clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
+        clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+        clk[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
+        clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
+
+        /*                                name             parent_name          reg         shift */
+        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "ahb",               base + 0x68, 4);
+        clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+        clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
+        clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
+        clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
+        clk[can2_serial]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
+        clk[ecspi1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
+        clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
+        clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
+        clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
+        clk[ecspi5]       = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
+        clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
+        clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
+        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
+        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
+        clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+        clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
+        clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
+        clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+        clk[i2c1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
+        clk[i2c2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
+        clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
+        clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
+        clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+        clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
+        clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
+        clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
+        clk[ipu2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
+        clk[ipu2_di0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
+        clk[ldb_di0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
+        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
+        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+        clk[mlb]          = imx_clk_gate2("mlb",           "pll6_mlb",          base + 0x74, 18);
+        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
+        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
+        clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
+        clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+        clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
+        clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
+        clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
+        clk[pwm4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
+        clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
+        clk[gpmi_bch]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
+        clk[gpmi_io]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
+        clk[gpmi_apb]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
+        clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
+        clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
+        clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+        clk[ssi1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
+        clk[ssi2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
+        clk[ssi3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+        clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
+        clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
+        clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
+        clk[usdhc1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
+        clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
+        clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
+        clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
+        clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
+        clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX6q clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi");
+        clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi");
+        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[twd], NULL, "smp_twd");
+        clk_register_clkdev(clk[usboh3], NULL, "usboh3");
+        clk_register_clkdev(clk[uart_serial], "per", "2020000.uart");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.uart");
+        clk_register_clkdev(clk[uart_serial], "per", "21e8000.uart");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.uart");
+        clk_register_clkdev(clk[uart_serial], "per", "21ec000.uart");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.uart");
+        clk_register_clkdev(clk[uart_serial], "per", "21f0000.uart");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.uart");
+        clk_register_clkdev(clk[uart_serial], "per", "21f4000.uart");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.uart");
+        clk_register_clkdev(clk[enet], NULL, "2188000.enet");
+        clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
+        clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
+        clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
+        clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
+        clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
+        clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
+        clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
+        clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
+        clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
+        clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
+        clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
+        clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
+        clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
+        clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
+        clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
+
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
+                c = clk_get_sys(clks_init_on[i], NULL);
+                if (IS_ERR(c)) {
+                        pr_err("%s: failed to get clk %s", __func__,
+                               clks_init_on[i]);
+                        return PTR_ERR(c);
+                }
+                clk_prepare_enable(c);
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(NULL, base, irq);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
new file mode 100644
index 000000000000..e2ed4160f329
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/**
+ * struct clk_pfd - IMX PFD clock
+ * @clk_hw:     clock source
+ * @reg:        PFD register address
+ * @idx:        the index of PFD encoded in the register
+ *
+ * PFD clock found on i.MX6 series.  Each register for PFD has 4 clk_pfd
+ * data encoded, and member idx is used to specify the one.  And each
+ * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
+ */
+struct clk_pfd {
+        struct clk_hw   hw;
+        void __iomem    *reg;
+        u8              idx;
+};
+
+#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
+
+#define SET     0x4
+#define CLR     0x8
+#define OTG     0xc
+
+static int clk_pfd_enable(struct clk_hw *hw)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+
+        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
+
+        return 0;
+}
+
+static void clk_pfd_disable(struct clk_hw *hw)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+
+        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
+}
+
+static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+        u64 tmp = parent_rate;
+        u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+        tmp *= 18;
+        do_div(tmp, frac);
+
+        return tmp;
+}
+
+static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+        u64 tmp = *prate;
+        u8 frac;
+
+        tmp = tmp * 18 + rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        if (frac < 12)
+                frac = 12;
+        else if (frac > 35)
+                frac = 35;
+        tmp = *prate;
+        tmp *= 18;
+        do_div(tmp, frac);
+
+        return tmp;
+}
+
+static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+        u64 tmp = parent_rate;
+        u8 frac;
+
+        tmp = tmp * 18 + rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        if (frac < 12)
+                frac = 12;
+        else if (frac > 35)
+                frac = 35;
+
+        writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+        writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+        .enable         = clk_pfd_enable,
+        .disable        = clk_pfd_disable,
+        .recalc_rate    = clk_pfd_recalc_rate,
+        .round_rate     = clk_pfd_round_rate,
+        .set_rate       = clk_pfd_set_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+                        void __iomem *reg, u8 idx)
+{
+        struct clk_pfd *pfd;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+        if (!pfd)
+                return ERR_PTR(-ENOMEM);
+
+        pfd->reg = reg;
+        pfd->idx = idx;
+
+        init.name = name;
+        init.ops = &clk_pfd_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        pfd->hw.init = &init;
+
+        clk = clk_register(NULL, &pfd->hw);
+        if (IS_ERR(clk))
+                kfree(pfd);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
new file mode 100644
index 000000000000..2d856f9ccf59
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -0,0 +1,66 @@
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "clk.h"
+
+/**
+ * pll v1
+ *
+ * @clk_hw      clock source
+ * @parent      the parent clock name
+ * @base        base address of pll registers
+ *
+ * PLL clock version 1, found on i.MX1/21/25/27/31/35
+ */
+struct clk_pllv1 {
+        struct clk_hw   hw;
+        void __iomem    *base;
+};
+
+#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
+
+static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_pllv1 *pll = to_clk_pllv1(hw);
+
+        return mxc_decode_pll(readl(pll->base), parent_rate);
+}
+
+struct clk_ops clk_pllv1_ops = {
+        .recalc_rate = clk_pllv1_recalc_rate,
+};
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+                void __iomem *base)
+{
+        struct clk_pllv1 *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll)
+                return ERR_PTR(-ENOMEM);
+
+        pll->base = base;
+
+        init.name = name;
+        init.ops = &clk_pllv1_ops;
+        init.flags = 0;
+        init.parent_names = &parent;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
new file mode 100644
index 000000000000..4685919deb63
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -0,0 +1,249 @@
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <asm/div64.h>
+
+#include "clk.h"
+
+#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                  0x00
+#define MXC_PLL_DP_CONFIG               0x04
+#define MXC_PLL_DP_OP                   0x08
+#define MXC_PLL_DP_MFD                  0x0C
+#define MXC_PLL_DP_MFN                  0x10
+#define MXC_PLL_DP_MFNMINUS             0x14
+#define MXC_PLL_DP_MFNPLUS              0x18
+#define MXC_PLL_DP_HFS_OP               0x1C
+#define MXC_PLL_DP_HFS_MFD              0x20
+#define MXC_PLL_DP_HFS_MFN              0x24
+#define MXC_PLL_DP_MFN_TOGC             0x28
+#define MXC_PLL_DP_DESTAT               0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
+#define MXC_PLL_DP_CTL_ADE              0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
+#define MXC_PLL_DP_CTL_HFSM             0x80
+#define MXC_PLL_DP_CTL_PRE              0x40
+#define MXC_PLL_DP_CTL_UPEN             0x20
+#define MXC_PLL_DP_CTL_RST              0x10
+#define MXC_PLL_DP_CTL_RCP              0x8
+#define MXC_PLL_DP_CTL_PLM              0x4
+#define MXC_PLL_DP_CTL_BRM0             0x2
+#define MXC_PLL_DP_CTL_LRF              0x1
+
+#define MXC_PLL_DP_CONFIG_BIST          0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE        0x4
+#define MXC_PLL_DP_CONFIG_AREN          0x2
+#define MXC_PLL_DP_CONFIG_LDREQ         0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET        4
+#define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET        0
+#define MXC_PLL_DP_OP_PDF_MASK          0xF
+
+#define MXC_PLL_DP_MFD_OFFSET           0
+#define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET           0x0
+#define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
+
+#define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
+
+struct clk_pllv2 {
+        struct clk_hw   hw;
+        void __iomem    *base;
+};
+
+static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+        unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+        void __iomem *pllbase;
+        s64 temp;
+        struct clk_pllv2 *pll = to_clk_pllv2(hw);
+
+        pllbase = pll->base;
+
+        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+        pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+        dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+        if (pll_hfsm == 0) {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+        } else {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+        mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+        /* Sign extend to 32-bits */
+        if (mfn >= 0x04000000) {
+                mfn |= 0xFC000000;
+                mfn_abs = -mfn;
+        }
+
+        ref_clk = 2 * parent_rate;
+        if (dbl != 0)
+                ref_clk *= 2;
+
+        ref_clk /= (pdf + 1);
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd + 1);
+        if (mfn < 0)
+                temp = -temp;
+        temp = (ref_clk * mfi) + temp;
+
+        return temp;
+}
+
+static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pllv2 *pll = to_clk_pllv2(hw);
+        u32 reg;
+        void __iomem *pllbase;
+        long mfi, pdf, mfn, mfd = 999999;
+        s64 temp64;
+        unsigned long quad_parent_rate;
+        unsigned long pll_hfsm, dp_ctl;
+
+        pllbase = pll->base;
+
+        quad_parent_rate = 4 * parent_rate;
+        pdf = mfi = -1;
+        while (++pdf < 16 && mfi < 5)
+                mfi = rate * (pdf+1) / quad_parent_rate;
+        if (mfi > 15)
+                return -EINVAL;
+        pdf--;
+
+        temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
+        do_div(temp64, quad_parent_rate/1000000);
+        mfn = (long)temp64;
+
+        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+        /* use dpdck0_2 */
+        __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+        pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+        if (pll_hfsm == 0) {
+                reg = mfi << 4 | pdf;
+                __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+                __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+                __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+        } else {
+                reg = mfi << 4 | pdf;
+                __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+                __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+                __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+
+        return 0;
+}
+
+static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *prate)
+{
+        return rate;
+}
+
+static int clk_pllv2_prepare(struct clk_hw *hw)
+{
+        struct clk_pllv2 *pll = to_clk_pllv2(hw);
+        u32 reg;
+        void __iomem *pllbase;
+        int i = 0;
+
+        pllbase = pll->base;
+        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
+        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+        /* Wait for lock */
+        do {
+                reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+                if (reg & MXC_PLL_DP_CTL_LRF)
+                        break;
+
+                udelay(1);
+        } while (++i < MAX_DPLL_WAIT_TRIES);
+
+        if (i == MAX_DPLL_WAIT_TRIES) {
+                pr_err("MX5: pll locking failed\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static void clk_pllv2_unprepare(struct clk_hw *hw)
+{
+        struct clk_pllv2 *pll = to_clk_pllv2(hw);
+        u32 reg;
+        void __iomem *pllbase;
+
+        pllbase = pll->base;
+        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+struct clk_ops clk_pllv2_ops = {
+        .prepare = clk_pllv2_prepare,
+        .unprepare = clk_pllv2_unprepare,
+        .recalc_rate = clk_pllv2_recalc_rate,
+        .round_rate = clk_pllv2_round_rate,
+        .set_rate = clk_pllv2_set_rate,
+};
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+                void __iomem *base)
+{
+        struct clk_pllv2 *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll)
+                return ERR_PTR(-ENOMEM);
+
+        pll->base = base;
+
+        init.name = name;
+        init.ops = &clk_pllv2_ops;
+        init.flags = 0;
+        init.parent_names = &parent;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
new file mode 100644
index 000000000000..36aac947bce1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define PLL_NUM_OFFSET          0x10
+#define PLL_DENOM_OFFSET        0x20
+
+#define BM_PLL_POWER            (0x1 << 12)
+#define BM_PLL_ENABLE           (0x1 << 13)
+#define BM_PLL_BYPASS           (0x1 << 16)
+#define BM_PLL_LOCK             (0x1 << 31)
+
+/**
+ * struct clk_pllv3 - IMX PLL clock version 3
+ * @clk_hw:      clock source
+ * @base:        base address of PLL registers
+ * @powerup_set: set POWER bit to power up the PLL
+ * @gate_mask:   mask of gate bits
+ * @div_mask:    mask of divider bits
+ *
+ * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
+ * is actually a multiplier, and always sits at bit 0.
+ */
+struct clk_pllv3 {
+        struct clk_hw   hw;
+        void __iomem    *base;
+        bool            powerup_set;
+        u32             gate_mask;
+        u32             div_mask;
+};
+
+#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
+
+static int clk_pllv3_prepare(struct clk_hw *hw)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
+        u32 val;
+
+        val = readl_relaxed(pll->base);
+        val &= ~BM_PLL_BYPASS;
+        if (pll->powerup_set)
+                val |= BM_PLL_POWER;
+        else
+                val &= ~BM_PLL_POWER;
+        writel_relaxed(val, pll->base);
+
+        /* Wait for PLL to lock */
+        while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
+                if (time_after(jiffies, timeout))
+                        return -ETIMEDOUT;
+
+        return 0;
+}
+
+static void clk_pllv3_unprepare(struct clk_hw *hw)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 val;
+
+        val = readl_relaxed(pll->base);
+        val |= BM_PLL_BYPASS;
+        if (pll->powerup_set)
+                val &= ~BM_PLL_POWER;
+        else
+                val |= BM_PLL_POWER;
+        writel_relaxed(val, pll->base);
+}
+
+static int clk_pllv3_enable(struct clk_hw *hw)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 val;
+
+        val = readl_relaxed(pll->base);
+        val |= pll->gate_mask;
+        writel_relaxed(val, pll->base);
+
+        return 0;
+}
+
+static void clk_pllv3_disable(struct clk_hw *hw)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 val;
+
+        val = readl_relaxed(pll->base);
+        val &= ~pll->gate_mask;
+        writel_relaxed(val, pll->base);
+}
+
+static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 div = readl_relaxed(pll->base)  & pll->div_mask;
+
+        return (div == 1) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+
+        return (rate >= parent_rate * 22) ? parent_rate * 22 :
+                                            parent_rate * 20;
+}
+
+static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 val, div;
+
+        if (rate == parent_rate * 22)
+                div = 1;
+        else if (rate == parent_rate * 20)
+                div = 0;
+        else
+                return -EINVAL;
+
+        val = readl_relaxed(pll->base);
+        val &= ~pll->div_mask;
+        val |= div;
+        writel_relaxed(val, pll->base);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pllv3_ops = {
+        .prepare        = clk_pllv3_prepare,
+        .unprepare      = clk_pllv3_unprepare,
+        .enable         = clk_pllv3_enable,
+        .disable        = clk_pllv3_disable,
+        .recalc_rate    = clk_pllv3_recalc_rate,
+        .round_rate     = clk_pllv3_round_rate,
+        .set_rate       = clk_pllv3_set_rate,
+};
+
+static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
+                                               unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+        return parent_rate * div / 2;
+}
+
+static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
+                                     unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        unsigned long min_rate = parent_rate * 54 / 2;
+        unsigned long max_rate = parent_rate * 108 / 2;
+        u32 div;
+
+        if (rate > max_rate)
+                rate = max_rate;
+        else if (rate < min_rate)
+                rate = min_rate;
+        div = rate * 2 / parent_rate;
+
+        return parent_rate * div / 2;
+}
+
+static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        unsigned long min_rate = parent_rate * 54 / 2;
+        unsigned long max_rate = parent_rate * 108 / 2;
+        u32 val, div;
+
+        if (rate < min_rate || rate > max_rate)
+                return -EINVAL;
+
+        div = rate * 2 / parent_rate;
+        val = readl_relaxed(pll->base);
+        val &= ~pll->div_mask;
+        val |= div;
+        writel_relaxed(val, pll->base);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_ops = {
+        .prepare        = clk_pllv3_prepare,
+        .unprepare      = clk_pllv3_unprepare,
+        .enable         = clk_pllv3_enable,
+        .disable        = clk_pllv3_disable,
+        .recalc_rate    = clk_pllv3_sys_recalc_rate,
+        .round_rate     = clk_pllv3_sys_round_rate,
+        .set_rate       = clk_pllv3_sys_set_rate,
+};
+
+static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
+                                              unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
+        u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
+        u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
+static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        unsigned long min_rate = parent_rate * 27;
+        unsigned long max_rate = parent_rate * 54;
+        u32 div;
+        u32 mfn, mfd = 1000000;
+        s64 temp64;
+
+        if (rate > max_rate)
+                rate = max_rate;
+        else if (rate < min_rate)
+                rate = min_rate;
+
+        div = rate / parent_rate;
+        temp64 = (u64) (rate - div * parent_rate);
+        temp64 *= mfd;
+        do_div(temp64, parent_rate);
+        mfn = temp64;
+
+        return parent_rate * div + parent_rate / mfd * mfn;
+}
+
+static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        unsigned long min_rate = parent_rate * 27;
+        unsigned long max_rate = parent_rate * 54;
+        u32 val, div;
+        u32 mfn, mfd = 1000000;
+        s64 temp64;
+
+        if (rate < min_rate || rate > max_rate)
+                return -EINVAL;
+
+        div = rate / parent_rate;
+        temp64 = (u64) (rate - div * parent_rate);
+        temp64 *= mfd;
+        do_div(temp64, parent_rate);
+        mfn = temp64;
+
+        val = readl_relaxed(pll->base);
+        val &= ~pll->div_mask;
+        val |= div;
+        writel_relaxed(val, pll->base);
+        writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
+        writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+        .prepare        = clk_pllv3_prepare,
+        .unprepare      = clk_pllv3_unprepare,
+        .enable         = clk_pllv3_enable,
+        .disable        = clk_pllv3_disable,
+        .recalc_rate    = clk_pllv3_av_recalc_rate,
+        .round_rate     = clk_pllv3_av_round_rate,
+        .set_rate       = clk_pllv3_av_set_rate,
+};
+
+static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
+                                                unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+        switch (div) {
+        case 0:
+                return 25000000;
+        case 1:
+                return 50000000;
+        case 2:
+                return 100000000;
+        case 3:
+                return 125000000;
+        }
+
+        return 0;
+}
+
+static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
+                                      unsigned long *prate)
+{
+        if (rate >= 125000000)
+                rate = 125000000;
+        else if (rate >= 100000000)
+                rate = 100000000;
+        else if (rate >= 50000000)
+                rate = 50000000;
+        else
+                rate = 25000000;
+        return rate;
+}
+
+static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        u32 val, div;
+
+        switch (rate) {
+        case 25000000:
+                div = 0;
+                break;
+        case 50000000:
+                div = 1;
+                break;
+        case 100000000:
+                div = 2;
+                break;
+        case 125000000:
+                div = 3;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        val = readl_relaxed(pll->base);
+        val &= ~pll->div_mask;
+        val |= div;
+        writel_relaxed(val, pll->base);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pllv3_enet_ops = {
+        .prepare        = clk_pllv3_prepare,
+        .unprepare      = clk_pllv3_unprepare,
+        .enable         = clk_pllv3_enable,
+        .disable        = clk_pllv3_disable,
+        .recalc_rate    = clk_pllv3_enet_recalc_rate,
+        .round_rate     = clk_pllv3_enet_round_rate,
+        .set_rate       = clk_pllv3_enet_set_rate,
+};
+
+static const struct clk_ops clk_pllv3_mlb_ops = {
+        .prepare        = clk_pllv3_prepare,
+        .unprepare      = clk_pllv3_unprepare,
+        .enable         = clk_pllv3_enable,
+        .disable        = clk_pllv3_disable,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+                          const char *parent_name, void __iomem *base,
+                          u32 gate_mask, u32 div_mask)
+{
+        struct clk_pllv3 *pll;
+        const struct clk_ops *ops;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll)
+                return ERR_PTR(-ENOMEM);
+
+        switch (type) {
+        case IMX_PLLV3_SYS:
+                ops = &clk_pllv3_sys_ops;
+                break;
+        case IMX_PLLV3_USB:
+                ops = &clk_pllv3_ops;
+                pll->powerup_set = true;
+                break;
+        case IMX_PLLV3_AV:
+                ops = &clk_pllv3_av_ops;
+                break;
+        case IMX_PLLV3_ENET:
+                ops = &clk_pllv3_enet_ops;
+                break;
+        case IMX_PLLV3_MLB:
+                ops = &clk_pllv3_mlb_ops;
+                break;
+        default:
+                ops = &clk_pllv3_ops;
+        }
+        pll->base = base;
+        pll->gate_mask = gate_mask;
+        pll->div_mask = div_mask;
+
+        init.name = name;
+        init.ops = ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
new file mode 100644
index 000000000000..1bf64fe2523c
--- /dev/null
+++ b/arch/arm/mach-imx/clk.h
@@ -0,0 +1,83 @@
+#ifndef __MACH_IMX_CLK_H
+#define __MACH_IMX_CLK_H
+
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <mach/clock.h>
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+                void __iomem *base);
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+                void __iomem *base);
+
+enum imx_pllv3_type {
+        IMX_PLLV3_GENERIC,
+        IMX_PLLV3_SYS,
+        IMX_PLLV3_USB,
+        IMX_PLLV3_AV,
+        IMX_PLLV3_ENET,
+        IMX_PLLV3_MLB,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+                const char *parent_name, void __iomem *base, u32 gate_mask,
+                u32 div_mask);
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *reg, u8 bit_idx,
+                u8 clk_gate_flags, spinlock_t *lock);
+
+static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+                void __iomem *reg, u8 shift)
+{
+        return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                        shift, 0, &imx_ccm_lock);
+}
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+                void __iomem *reg, u8 idx);
+
+struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
+                                 void __iomem *reg, u8 shift, u8 width,
+                                 void __iomem *busy_reg, u8 busy_shift);
+
+struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
+                             u8 width, void __iomem *busy_reg, u8 busy_shift,
+                             const char **parent_names, int num_parents);
+
+static inline struct clk *imx_clk_fixed(const char *name, int rate)
+{
+        return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+                void __iomem *reg, u8 shift, u8 width)
+{
+        return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+                        reg, shift, width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+                void __iomem *reg, u8 shift)
+{
+        return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                        shift, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+                u8 shift, u8 width, const char **parents, int num_parents)
+{
+        return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+                        width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+                const char *parent, unsigned int mult, unsigned int div)
+{
+        return clk_register_fixed_factor(NULL, name, parent,
+                        CLK_SET_RATE_PARENT, mult, div);
+}
+
+#endif
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
deleted file mode 100644
index 4aabeb241563..000000000000
--- a/arch/arm/mach-imx/clock-imx1.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/math64.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-/* CCM register addresses */
-#define CCM_CSCR        IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
-#define CCM_PCDR        IO_ADDR_CCM(0x20)
-
-#define CCM_CSCR_CLKO_OFFSET    29
-#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
-#define CCM_CSCR_USB_OFFSET     26
-#define CCM_CSCR_USB_MASK       (0x7 << 26)
-#define CCM_CSCR_OSC_EN_SHIFT   17
-#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET    10
-#define CCM_CSCR_BCLK_MASK      (0xf << 10)
-#define CCM_CSCR_PRESC          (1 << 15)
-
-#define CCM_PCDR_PCLK3_OFFSET   16
-#define CCM_PCDR_PCLK3_MASK     (0x7f << 16)
-#define CCM_PCDR_PCLK2_OFFSET   4
-#define CCM_PCDR_PCLK2_MASK     (0xf << 4)
-#define CCM_PCDR_PCLK1_OFFSET   0
-#define CCM_PCDR_PCLK1_MASK     0xf
-
-#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-/* SCM register addresses */
-#define SCM_GCCR        IO_ADDR_SCM(0xc)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
-
-static int _clk_enable(struct clk *clk)
-{
-        unsigned int reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 1 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-        unsigned int reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
-                               struct clk *parent)
-{
-        int i;
-
-        for (i = 0; i < size; i++)
-                if (parent == clk_arr[i])
-                        return i;
-
-        return -EINVAL;
-}
-
-static unsigned long
-_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
-{
-        int div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-
-        if (div > limit)
-                div = limit;
-
-        return parent_rate / div;
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long clk16m_get_rate(struct clk *clk)
-{
-        return 16000000;
-}
-
-static struct clk clk16m = {
-        .get_rate = clk16m_get_rate,
-        .enable = _clk_enable,
-        .enable_reg = CCM_CSCR,
-        .enable_shift = CCM_CSCR_OSC_EN_SHIFT,
-        .disable = _clk_disable,
-};
-
-/* in Hz */
-static unsigned long clk32_rate;
-
-static unsigned long clk32_get_rate(struct clk *clk)
-{
-        return clk32_rate;
-}
-
-static struct clk clk32 = {
-        .get_rate = clk32_get_rate,
-};
-
-static unsigned long clk32_premult_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) * 512;
-}
-
-static struct clk clk32_premult = {
-        .parent = &clk32,
-        .get_rate = clk32_premult_get_rate,
-};
-
-static const struct clk *prem_clk_clocks[] = {
-        &clk32_premult,
-        &clk16m,
-};
-
-static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int i;
-        unsigned int reg = __raw_readl(CCM_CSCR);
-
-        i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
-                                parent);
-
-        switch (i) {
-        case 0:
-                reg &= ~CCM_CSCR_SYSTEM_SEL;
-                break;
-        case 1:
-                reg |= CCM_CSCR_SYSTEM_SEL;
-                break;
-        default:
-                return i;
-        }
-
-        __raw_writel(reg, CCM_CSCR);
-
-        return 0;
-}
-
-static struct clk prem_clk = {
-        .set_parent = prem_clk_set_parent,
-};
-
-static unsigned long system_clk_get_rate(struct clk *clk)
-{
-        return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
-                              clk_get_rate(clk->parent));
-}
-
-static struct clk system_clk = {
-        .parent = &prem_clk,
-        .get_rate = system_clk_get_rate,
-};
-
-static unsigned long mcu_clk_get_rate(struct clk *clk)
-{
-        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
-                              clk_get_rate(clk->parent));
-}
-
-static struct clk mcu_clk = {
-        .parent = &clk32_premult,
-        .get_rate = mcu_clk_get_rate,
-};
-
-static unsigned long fclk_get_rate(struct clk *clk)
-{
-        unsigned long fclk = clk_get_rate(clk->parent);
-
-        if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
-                fclk /= 2;
-
-        return fclk;
-}
-
-static struct clk fclk = {
-        .parent = &mcu_clk,
-        .get_rate = fclk_get_rate,
-};
-
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-static unsigned long hclk_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-                        CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
-}
-
-static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int hclk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        unsigned int reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg &= ~CCM_CSCR_BCLK_MASK;
-        reg |= div << CCM_CSCR_BCLK_OFFSET;
-        __raw_writel(reg, CCM_CSCR);
-
-        return 0;
-}
-
-static struct clk hclk = {
-        .parent = &system_clk,
-        .get_rate = hclk_get_rate,
-        .round_rate = hclk_round_rate,
-        .set_rate = hclk_set_rate,
-};
-
-static unsigned long clk48m_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-                        CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
-}
-
-static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_simple_round_rate(clk, rate, 8);
-}
-
-static int clk48m_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        unsigned int reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg &= ~CCM_CSCR_USB_MASK;
-        reg |= div << CCM_CSCR_USB_OFFSET;
-        __raw_writel(reg, CCM_CSCR);
-
-        return 0;
-}
-
-static struct clk clk48m = {
-        .parent = &system_clk,
-        .get_rate = clk48m_get_rate,
-        .round_rate = clk48m_round_rate,
-        .set_rate = clk48m_set_rate,
-};
-
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-static unsigned long perclk1_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                        CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
-}
-
-static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk1_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        unsigned int reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_PCDR);
-        reg &= ~CCM_PCDR_PCLK1_MASK;
-        reg |= div << CCM_PCDR_PCLK1_OFFSET;
-        __raw_writel(reg, CCM_PCDR);
-
-        return 0;
-}
-
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-static unsigned long perclk2_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                        CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
-}
-
-static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk2_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        unsigned int reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_PCDR);
-        reg &= ~CCM_PCDR_PCLK2_MASK;
-        reg |= div << CCM_PCDR_PCLK2_OFFSET;
-        __raw_writel(reg, CCM_PCDR);
-
-        return 0;
-}
-
-/*
- *  get peripheral clock 3 ( SSI )
- */
-static unsigned long perclk3_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                        CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
-}
-
-static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_simple_round_rate(clk, rate, 128);
-}
-
-static int perclk3_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        unsigned int reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 128 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_PCDR);
-        reg &= ~CCM_PCDR_PCLK3_MASK;
-        reg |= div << CCM_PCDR_PCLK3_OFFSET;
-        __raw_writel(reg, CCM_PCDR);
-
-        return 0;
-}
-
-static struct clk perclk[] = {
-        {
-                .id = 0,
-                .parent = &system_clk,
-                .get_rate = perclk1_get_rate,
-                .round_rate = perclk1_round_rate,
-                .set_rate = perclk1_set_rate,
-        }, {
-                .id = 1,
-                .parent = &system_clk,
-                .get_rate = perclk2_get_rate,
-                .round_rate = perclk2_round_rate,
-                .set_rate = perclk2_set_rate,
-        }, {
-                .id = 2,
-                .parent = &system_clk,
-                .get_rate = perclk3_get_rate,
-                .round_rate = perclk3_round_rate,
-                .set_rate = perclk3_set_rate,
-        }
-};
-
-static const struct clk *clko_clocks[] = {
-        &perclk[0],
-        &hclk,
-        &clk48m,
-        &clk16m,
-        &prem_clk,
-        &fclk,
-};
-
-static int clko_set_parent(struct clk *clk, struct clk *parent)
-{
-        int i;
-        unsigned int reg;
-
-        i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
-        if (i < 0)
-                return i;
-
-        reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
-        reg |= i << CCM_CSCR_CLKO_OFFSET;
-        __raw_writel(reg, CCM_CSCR);
-
-        if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
-                clk->set_rate = _clk_parent_set_rate;
-                clk->round_rate = _clk_parent_round_rate;
-        } else {
-                clk->set_rate = NULL;
-                clk->round_rate = NULL;
-        }
-
-        return 0;
-}
-
-static struct clk clko_clk = {
-        .set_parent = clko_set_parent,
-};
-
-static struct clk dma_clk = {
-        .parent = &hclk,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-        .enable = _clk_enable,
-        .enable_reg = SCM_GCCR,
-        .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk csi_clk = {
-        .parent = &hclk,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-        .enable = _clk_enable,
-        .enable_reg = SCM_GCCR,
-        .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk mma_clk = {
-        .parent = &hclk,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-        .enable = _clk_enable,
-        .enable_reg = SCM_GCCR,
-        .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk usbd_clk = {
-        .parent = &clk48m,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-        .enable = _clk_enable,
-        .enable_reg = SCM_GCCR,
-        .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk gpt_clk = {
-        .parent = &perclk[0],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk uart_clk = {
-        .parent = &perclk[0],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk i2c_clk = {
-        .parent = &hclk,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk spi_clk = {
-        .parent = &perclk[1],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk sdhc_clk = {
-        .parent = &perclk[1],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk lcdc_clk = {
-        .parent = &perclk[1],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk mshc_clk = {
-        .parent = &hclk,
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk ssi_clk = {
-        .parent = &perclk[2],
-        .round_rate = _clk_parent_round_rate,
-        .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk rtc_clk = {
-        .parent = &clk32,
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-static struct clk_lookup lookups[] __initdata = {
-        _REGISTER_CLOCK(NULL, "dma", dma_clk)
-        _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
-        _REGISTER_CLOCK(NULL, "mma", mma_clk)
-        _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
-        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-        _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk)
-        _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk)
-        _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
-        _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
-        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
-        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
-        _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
-};
-
-int __init mx1_clocks_init(unsigned long fref)
-{
-        unsigned int reg;
-
-        /* disable clocks we are able to */
-        __raw_writel(0, SCM_GCCR);
-
-        clk32_rate = fref;
-        reg = __raw_readl(CCM_CSCR);
-
-        /* detect clock reference for system PLL */
-        if (reg & CCM_CSCR_SYSTEM_SEL) {
-                prem_clk.parent = &clk16m;
-        } else {
-                /* ensure that oscillator is disabled */
-                reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
-                __raw_writel(reg, CCM_CSCR);
-                prem_clk.parent = &clk32_premult;
-        }
-
-        /* detect reference for CLKO */
-        reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
-        clko_clk.parent = (struct clk *)clko_clocks[reg];
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        clk_enable(&hclk);
-        clk_enable(&fclk);
-
-        mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
-                        MX1_TIM1_INT);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
deleted file mode 100644
index ee15d8c9db08..000000000000
--- a/arch/arm/mach-imx/clock-imx21.c
+++ /dev/null
@@ -1,1239 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/div64.h>
-
-#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_PRESC_OFFSET   29
-#define CCM_CSCR_PRESC_MASK     (0x7 << CCM_CSCR_PRESC_OFFSET)
-
-#define CCM_CSCR_USB_OFFSET     26
-#define CCM_CSCR_USB_MASK       (0x7 << CCM_CSCR_USB_OFFSET)
-#define CCM_CSCR_SD_OFFSET      24
-#define CCM_CSCR_SD_MASK        (0x3 << CCM_CSCR_SD_OFFSET)
-#define CCM_CSCR_SPLLRES        (1 << 22)
-#define CCM_CSCR_MPLLRES        (1 << 21)
-#define CCM_CSCR_SSI2_OFFSET    20
-#define CCM_CSCR_SSI2           (1 << CCM_CSCR_SSI2_OFFSET)
-#define CCM_CSCR_SSI1_OFFSET    19
-#define CCM_CSCR_SSI1           (1 << CCM_CSCR_SSI1_OFFSET)
-#define CCM_CSCR_FIR_OFFSET     18
-#define CCM_CSCR_FIR            (1 << CCM_CSCR_FIR_OFFSET)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET    10
-#define CCM_CSCR_BCLK_MASK      (0xf << CCM_CSCR_BCLK_OFFSET)
-#define CCM_CSCR_IPDIV_OFFSET   9
-#define CCM_CSCR_IPDIV          (1 << CCM_CSCR_IPDIV_OFFSET)
-
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           1
-
-#define CCM_MPCTL0_CPLM         (1 << 31)
-#define CCM_MPCTL0_PD_OFFSET    26
-#define CCM_MPCTL0_PD_MASK      (0xf << 26)
-#define CCM_MPCTL0_MFD_OFFSET   16
-#define CCM_MPCTL0_MFD_MASK     (0x3ff << 16)
-#define CCM_MPCTL0_MFI_OFFSET   10
-#define CCM_MPCTL0_MFI_MASK     (0xf << 10)
-#define CCM_MPCTL0_MFN_OFFSET   0
-#define CCM_MPCTL0_MFN_MASK     0x3ff
-
-#define CCM_MPCTL1_LF           (1 << 15)
-#define CCM_MPCTL1_BRMO         (1 << 6)
-
-#define CCM_SPCTL0_CPLM         (1 << 31)
-#define CCM_SPCTL0_PD_OFFSET    26
-#define CCM_SPCTL0_PD_MASK      (0xf << 26)
-#define CCM_SPCTL0_MFD_OFFSET   16
-#define CCM_SPCTL0_MFD_MASK     (0x3ff << 16)
-#define CCM_SPCTL0_MFI_OFFSET   10
-#define CCM_SPCTL0_MFI_MASK     (0xf << 10)
-#define CCM_SPCTL0_MFN_OFFSET   0
-#define CCM_SPCTL0_MFN_MASK     0x3ff
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
-
-#define CCM_OSC26MCTL_PEAK_OFFSET       16
-#define CCM_OSC26MCTL_PEAK_MASK         (0x3 << 16)
-#define CCM_OSC26MCTL_AGC_OFFSET        8
-#define CCM_OSC26MCTL_AGC_MASK          (0x3f << 8)
-#define CCM_OSC26MCTL_ANATEST_OFFSET    0
-#define CCM_OSC26MCTL_ANATEST_MASK      0x3f
-
-#define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
-#define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
-#define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
-#define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
-#define CCM_PCDR0_NFCDIV_OFFSET         12
-#define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
-#define CCM_PCDR0_48MDIV_OFFSET         5
-#define CCM_PCDR0_48MDIV_MASK           (0x7 << CCM_PCDR0_48MDIV_OFFSET)
-#define CCM_PCDR0_FIRIDIV_OFFSET        0
-#define CCM_PCDR0_FIRIDIV_MASK          0x1f
-#define CCM_PCDR1_PERDIV4_OFFSET        24
-#define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
-#define CCM_PCDR1_PERDIV3_OFFSET        16
-#define CCM_PCDR1_PERDIV3_MASK          (0x3f << 16)
-#define CCM_PCDR1_PERDIV2_OFFSET        8
-#define CCM_PCDR1_PERDIV2_MASK          (0x3f << 8)
-#define CCM_PCDR1_PERDIV1_OFFSET        0
-#define CCM_PCDR1_PERDIV1_MASK          0x3f
-
-#define CCM_PCCR_HCLK_CSI_OFFSET        31
-#define CCM_PCCR_HCLK_CSI_REG           CCM_PCCR0
-#define CCM_PCCR_HCLK_DMA_OFFSET        30
-#define CCM_PCCR_HCLK_DMA_REG           CCM_PCCR0
-#define CCM_PCCR_HCLK_BROM_OFFSET       28
-#define CCM_PCCR_HCLK_BROM_REG          CCM_PCCR0
-#define CCM_PCCR_HCLK_EMMA_OFFSET       27
-#define CCM_PCCR_HCLK_EMMA_REG          CCM_PCCR0
-#define CCM_PCCR_HCLK_LCDC_OFFSET       26
-#define CCM_PCCR_HCLK_LCDC_REG          CCM_PCCR0
-#define CCM_PCCR_HCLK_SLCDC_OFFSET      25
-#define CCM_PCCR_HCLK_SLCDC_REG         CCM_PCCR0
-#define CCM_PCCR_HCLK_USBOTG_OFFSET     24
-#define CCM_PCCR_HCLK_USBOTG_REG        CCM_PCCR0
-#define CCM_PCCR_HCLK_BMI_OFFSET        23
-#define CCM_PCCR_BMI_MASK               (1 << CCM_PCCR_BMI_MASK)
-#define CCM_PCCR_HCLK_BMI_REG           CCM_PCCR0
-#define CCM_PCCR_PERCLK4_OFFSET         22
-#define CCM_PCCR_PERCLK4_REG            CCM_PCCR0
-#define CCM_PCCR_SLCDC_OFFSET           21
-#define CCM_PCCR_SLCDC_REG              CCM_PCCR0
-#define CCM_PCCR_FIRI_BAUD_OFFSET       20
-#define CCM_PCCR_FIRI_BAUD_MASK         (1 << CCM_PCCR_FIRI_BAUD_MASK)
-#define CCM_PCCR_FIRI_BAUD_REG          CCM_PCCR0
-#define CCM_PCCR_NFC_OFFSET             19
-#define CCM_PCCR_NFC_REG                CCM_PCCR0
-#define CCM_PCCR_LCDC_OFFSET            18
-#define CCM_PCCR_LCDC_REG               CCM_PCCR0
-#define CCM_PCCR_SSI1_BAUD_OFFSET       17
-#define CCM_PCCR_SSI1_BAUD_REG          CCM_PCCR0
-#define CCM_PCCR_SSI2_BAUD_OFFSET       16
-#define CCM_PCCR_SSI2_BAUD_REG          CCM_PCCR0
-#define CCM_PCCR_EMMA_OFFSET            15
-#define CCM_PCCR_EMMA_REG               CCM_PCCR0
-#define CCM_PCCR_USBOTG_OFFSET          14
-#define CCM_PCCR_USBOTG_REG             CCM_PCCR0
-#define CCM_PCCR_DMA_OFFSET             13
-#define CCM_PCCR_DMA_REG                CCM_PCCR0
-#define CCM_PCCR_I2C1_OFFSET            12
-#define CCM_PCCR_I2C1_REG               CCM_PCCR0
-#define CCM_PCCR_GPIO_OFFSET            11
-#define CCM_PCCR_GPIO_REG               CCM_PCCR0
-#define CCM_PCCR_SDHC2_OFFSET           10
-#define CCM_PCCR_SDHC2_REG              CCM_PCCR0
-#define CCM_PCCR_SDHC1_OFFSET           9
-#define CCM_PCCR_SDHC1_REG              CCM_PCCR0
-#define CCM_PCCR_FIRI_OFFSET            8
-#define CCM_PCCR_FIRI_MASK              (1 << CCM_PCCR_BAUD_MASK)
-#define CCM_PCCR_FIRI_REG               CCM_PCCR0
-#define CCM_PCCR_SSI2_IPG_OFFSET        7
-#define CCM_PCCR_SSI2_REG               CCM_PCCR0
-#define CCM_PCCR_SSI1_IPG_OFFSET        6
-#define CCM_PCCR_SSI1_REG               CCM_PCCR0
-#define CCM_PCCR_CSPI2_OFFSET           5
-#define CCM_PCCR_CSPI2_REG              CCM_PCCR0
-#define CCM_PCCR_CSPI1_OFFSET           4
-#define CCM_PCCR_CSPI1_REG              CCM_PCCR0
-#define CCM_PCCR_UART4_OFFSET           3
-#define CCM_PCCR_UART4_REG              CCM_PCCR0
-#define CCM_PCCR_UART3_OFFSET           2
-#define CCM_PCCR_UART3_REG              CCM_PCCR0
-#define CCM_PCCR_UART2_OFFSET           1
-#define CCM_PCCR_UART2_REG              CCM_PCCR0
-#define CCM_PCCR_UART1_OFFSET           0
-#define CCM_PCCR_UART1_REG              CCM_PCCR0
-
-#define CCM_PCCR_OWIRE_OFFSET           31
-#define CCM_PCCR_OWIRE_REG              CCM_PCCR1
-#define CCM_PCCR_KPP_OFFSET             30
-#define CCM_PCCR_KPP_REG                CCM_PCCR1
-#define CCM_PCCR_RTC_OFFSET             29
-#define CCM_PCCR_RTC_REG                CCM_PCCR1
-#define CCM_PCCR_PWM_OFFSET             28
-#define CCM_PCCR_PWM_REG                CCM_PCCR1
-#define CCM_PCCR_GPT3_OFFSET            27
-#define CCM_PCCR_GPT3_REG               CCM_PCCR1
-#define CCM_PCCR_GPT2_OFFSET            26
-#define CCM_PCCR_GPT2_REG               CCM_PCCR1
-#define CCM_PCCR_GPT1_OFFSET            25
-#define CCM_PCCR_GPT1_REG               CCM_PCCR1
-#define CCM_PCCR_WDT_OFFSET             24
-#define CCM_PCCR_WDT_REG                CCM_PCCR1
-#define CCM_PCCR_CSPI3_OFFSET           23
-#define CCM_PCCR_CSPI3_REG              CCM_PCCR1
-
-#define CCM_PCCR_CSPI1_MASK             (1 << CCM_PCCR_CSPI1_OFFSET)
-#define CCM_PCCR_CSPI2_MASK             (1 << CCM_PCCR_CSPI2_OFFSET)
-#define CCM_PCCR_CSPI3_MASK             (1 << CCM_PCCR_CSPI3_OFFSET)
-#define CCM_PCCR_DMA_MASK               (1 << CCM_PCCR_DMA_OFFSET)
-#define CCM_PCCR_EMMA_MASK              (1 << CCM_PCCR_EMMA_OFFSET)
-#define CCM_PCCR_GPIO_MASK              (1 << CCM_PCCR_GPIO_OFFSET)
-#define CCM_PCCR_GPT1_MASK              (1 << CCM_PCCR_GPT1_OFFSET)
-#define CCM_PCCR_GPT2_MASK              (1 << CCM_PCCR_GPT2_OFFSET)
-#define CCM_PCCR_GPT3_MASK              (1 << CCM_PCCR_GPT3_OFFSET)
-#define CCM_PCCR_HCLK_BROM_MASK         (1 << CCM_PCCR_HCLK_BROM_OFFSET)
-#define CCM_PCCR_HCLK_CSI_MASK          (1 << CCM_PCCR_HCLK_CSI_OFFSET)
-#define CCM_PCCR_HCLK_DMA_MASK          (1 << CCM_PCCR_HCLK_DMA_OFFSET)
-#define CCM_PCCR_HCLK_EMMA_MASK         (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
-#define CCM_PCCR_HCLK_LCDC_MASK         (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
-#define CCM_PCCR_HCLK_SLCDC_MASK        (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
-#define CCM_PCCR_HCLK_USBOTG_MASK       (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
-#define CCM_PCCR_I2C1_MASK              (1 << CCM_PCCR_I2C1_OFFSET)
-#define CCM_PCCR_KPP_MASK               (1 << CCM_PCCR_KPP_OFFSET)
-#define CCM_PCCR_LCDC_MASK              (1 << CCM_PCCR_LCDC_OFFSET)
-#define CCM_PCCR_NFC_MASK               (1 << CCM_PCCR_NFC_OFFSET)
-#define CCM_PCCR_OWIRE_MASK             (1 << CCM_PCCR_OWIRE_OFFSET)
-#define CCM_PCCR_PERCLK4_MASK           (1 << CCM_PCCR_PERCLK4_OFFSET)
-#define CCM_PCCR_PWM_MASK               (1 << CCM_PCCR_PWM_OFFSET)
-#define CCM_PCCR_RTC_MASK               (1 << CCM_PCCR_RTC_OFFSET)
-#define CCM_PCCR_SDHC1_MASK             (1 << CCM_PCCR_SDHC1_OFFSET)
-#define CCM_PCCR_SDHC2_MASK             (1 << CCM_PCCR_SDHC2_OFFSET)
-#define CCM_PCCR_SLCDC_MASK             (1 << CCM_PCCR_SLCDC_OFFSET)
-#define CCM_PCCR_SSI1_BAUD_MASK         (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
-#define CCM_PCCR_SSI1_IPG_MASK          (1 << CCM_PCCR_SSI1_IPG_OFFSET)
-#define CCM_PCCR_SSI2_BAUD_MASK         (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
-#define CCM_PCCR_SSI2_IPG_MASK          (1 << CCM_PCCR_SSI2_IPG_OFFSET)
-#define CCM_PCCR_UART1_MASK             (1 << CCM_PCCR_UART1_OFFSET)
-#define CCM_PCCR_UART2_MASK             (1 << CCM_PCCR_UART2_OFFSET)
-#define CCM_PCCR_UART3_MASK             (1 << CCM_PCCR_UART3_OFFSET)
-#define CCM_PCCR_UART4_MASK             (1 << CCM_PCCR_UART4_OFFSET)
-#define CCM_PCCR_USBOTG_MASK            (1 << CCM_PCCR_USBOTG_OFFSET)
-#define CCM_PCCR_WDT_MASK               (1 << CCM_PCCR_WDT_OFFSET)
-
-#define CCM_CCSR_32KSR          (1 << 15)
-
-#define CCM_CCSR_CLKMODE1       (1 << 9)
-#define CCM_CCSR_CLKMODE0       (1 << 8)
-
-#define CCM_CCSR_CLKOSEL_OFFSET 0
-#define CCM_CCSR_CLKOSEL_MASK   0x1f
-
-#define SYS_FMCR                0x14    /* Functional Muxing Control Reg */
-#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
-
-static int _clk_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 1 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-        return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long _clk_generic_round_rate(struct clk *clk,
-                        unsigned long rate,
-                        u32 max_divisor)
-{
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-
-        if (div > max_divisor)
-                div = max_divisor;
-
-        return parent_rate / div;
-}
-
-static int _clk_spll_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg |= CCM_CSCR_SPEN;
-        __raw_writel(reg, CCM_CSCR);
-
-        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
-                ;
-        return 0;
-}
-
-static void _clk_spll_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg &= ~CCM_CSCR_SPEN;
-        __raw_writel(reg, CCM_CSCR);
-}
-
-
-#define CSCR() (__raw_readl(CCM_CSCR))
-#define PCDR0() (__raw_readl(CCM_PCDR0))
-#define PCDR1() (__raw_readl(CCM_PCDR1))
-
-static unsigned long _clk_perclkx_round_rate(struct clk *clk,
-                                             unsigned long rate)
-{
-        return _clk_generic_round_rate(clk, rate, 64);
-}
-
-static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->id < 0 || clk->id > 3)
-                return -EINVAL;
-
-        div = parent_rate / rate;
-        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-        div--;
-
-        reg =
-            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
-                                       (clk->id << 3));
-        reg |= div << (clk->id << 3);
-        __raw_writel(reg, CCM_PCDR1);
-
-        return 0;
-}
-
-static unsigned long _clk_usb_recalc(struct clk *clk)
-{
-        unsigned long usb_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
-
-        return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long _clk_usb_round_rate(struct clk *clk,
-                                             unsigned long rate)
-{
-        return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-        div--;
-
-        reg = CSCR() & ~CCM_CSCR_USB_MASK;
-        reg |= div << CCM_CSCR_USB_OFFSET;
-        __raw_writel(reg, CCM_CSCR);
-
-        return 0;
-}
-
-static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
-{
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
-
-        return 2UL * parent_rate / pdf;
-}
-
-static unsigned long _clk_ssi1_recalc(struct clk *clk)
-{
-        return _clk_ssix_recalc(clk,
-                (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
-                >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_ssi2_recalc(struct clk *clk)
-{
-        return _clk_ssix_recalc(clk,
-                (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
-                CCM_PCDR0_SSI2BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_nfc_recalc(struct clk *clk)
-{
-        unsigned long nfc_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
-                >> CCM_PCDR0_NFCDIV_OFFSET;
-
-        return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long external_high_reference; /* in Hz */
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-        return external_high_reference;
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz.
- */
-static struct clk ckih_clk = {
-        .get_rate = get_high_reference_clock_rate,
-};
-
-static unsigned long external_low_reference; /* in Hz */
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-        return external_low_reference;
-}
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
-        .get_rate = get_low_reference_clock_rate,
-};
-
-
-static unsigned long _clk_fpm_recalc(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) * 512;
-}
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
-        .parent = &ckil_clk,
-        .get_rate = _clk_fpm_recalc,
-};
-
-static unsigned long get_mpll_clk(struct clk *clk)
-{
-        uint32_t reg;
-        unsigned long ref_clk;
-        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-        unsigned long long temp;
-
-        ref_clk = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(CCM_MPCTL0);
-        pdf = (reg & CCM_MPCTL0_PD_MASK)  >> CCM_MPCTL0_PD_OFFSET;
-        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
-        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
-        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
-
-        mfi = (mfi <= 5) ? 5 : mfi;
-        temp = 2LL * ref_clk * mfn;
-        do_div(temp, mfd + 1);
-        temp = 2LL * ref_clk * mfi + temp;
-        do_div(temp, pdf + 1);
-
-        return (unsigned long)temp;
-}
-
-static struct clk mpll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = get_mpll_clk,
-};
-
-static unsigned long _clk_fclk_get_rate(struct clk *clk)
-{
-        unsigned long parent_rate;
-        u32 div;
-
-        div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
-        parent_rate = clk_get_rate(clk->parent);
-
-        return parent_rate / (div+1);
-}
-
-static struct clk fclk_clk = {
-        .parent = &mpll_clk,
-        .get_rate = _clk_fclk_get_rate
-};
-
-static unsigned long get_spll_clk(struct clk *clk)
-{
-        uint32_t reg;
-        unsigned long ref_clk;
-        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-        unsigned long long temp;
-
-        ref_clk = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(CCM_SPCTL0);
-        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
-        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
-        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
-        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
-
-        mfi = (mfi <= 5) ? 5 : mfi;
-        temp = 2LL * ref_clk * mfn;
-        do_div(temp, mfd + 1);
-        temp = 2LL * ref_clk * mfi + temp;
-        do_div(temp, pdf + 1);
-
-        return (unsigned long)temp;
-}
-
-static struct clk spll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = get_spll_clk,
-        .enable = _clk_spll_enable,
-        .disable = _clk_spll_disable,
-};
-
-static unsigned long get_hclk_clk(struct clk *clk)
-{
-        unsigned long rate;
-        unsigned long bclk_pdf;
-
-        bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
-                >> CCM_CSCR_BCLK_OFFSET;
-
-        rate = clk_get_rate(clk->parent);
-        return rate / (bclk_pdf + 1);
-}
-
-static struct clk hclk_clk = {
-        .parent = &fclk_clk,
-        .get_rate = get_hclk_clk,
-};
-
-static unsigned long get_ipg_clk(struct clk *clk)
-{
-        unsigned long rate;
-        unsigned long ipg_pdf;
-
-        ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
-
-        rate = clk_get_rate(clk->parent);
-        return rate / (ipg_pdf + 1);
-}
-
-static struct clk ipg_clk = {
-        .parent = &hclk_clk,
-        .get_rate = get_ipg_clk,
-};
-
-static unsigned long _clk_perclkx_recalc(struct clk *clk)
-{
-        unsigned long perclk_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->id < 0 || clk->id > 3)
-                return 0;
-
-        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
-
-        return parent_rate / (perclk_pdf + 1);
-}
-
-static struct clk per_clk[] = {
-        {
-                .id = 0,
-                .parent = &mpll_clk,
-                .get_rate = _clk_perclkx_recalc,
-        }, {
-                .id = 1,
-                .parent = &mpll_clk,
-                .get_rate = _clk_perclkx_recalc,
-        }, {
-                .id = 2,
-                .parent = &mpll_clk,
-                .round_rate = _clk_perclkx_round_rate,
-                .set_rate = _clk_perclkx_set_rate,
-                .get_rate = _clk_perclkx_recalc,
-                /* Enable/Disable done via lcd_clkc[1] */
-        }, {
-                .id = 3,
-                .parent = &mpll_clk,
-                .round_rate = _clk_perclkx_round_rate,
-                .set_rate = _clk_perclkx_set_rate,
-                .get_rate = _clk_perclkx_recalc,
-                /* Enable/Disable done via csi_clk[1] */
-        },
-};
-
-static struct clk uart_ipg_clk[];
-
-static struct clk uart_clk[] = {
-        {
-                .id = 0,
-                .parent = &per_clk[0],
-                .secondary = &uart_ipg_clk[0],
-        }, {
-                .id = 1,
-                .parent = &per_clk[0],
-                .secondary = &uart_ipg_clk[1],
-        }, {
-                .id = 2,
-                .parent = &per_clk[0],
-                .secondary = &uart_ipg_clk[2],
-        }, {
-                .id = 3,
-                .parent = &per_clk[0],
-                .secondary = &uart_ipg_clk[3],
-        },
-};
-
-static struct clk uart_ipg_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_UART1_REG,
-                .enable_shift = CCM_PCCR_UART1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_UART2_REG,
-                .enable_shift = CCM_PCCR_UART2_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_UART3_REG,
-                .enable_shift = CCM_PCCR_UART3_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 3,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_UART4_REG,
-                .enable_shift = CCM_PCCR_UART4_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt_ipg_clk[];
-
-static struct clk gpt_clk[] = {
-        {
-                .id = 0,
-                .parent = &per_clk[0],
-                .secondary = &gpt_ipg_clk[0],
-        }, {
-                .id = 1,
-                .parent = &per_clk[0],
-                .secondary = &gpt_ipg_clk[1],
-        }, {
-                .id = 2,
-                .parent = &per_clk[0],
-                .secondary = &gpt_ipg_clk[2],
-        },
-};
-
-static struct clk gpt_ipg_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_GPT1_REG,
-                .enable_shift = CCM_PCCR_GPT1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_GPT2_REG,
-                .enable_shift = CCM_PCCR_GPT2_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_GPT3_REG,
-                .enable_shift = CCM_PCCR_GPT3_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk pwm_clk[] = {
-        {
-                .parent = &per_clk[0],
-                .secondary = &pwm_clk[1],
-        }, {
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_PWM_REG,
-                .enable_shift = CCM_PCCR_PWM_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk sdhc_ipg_clk[];
-
-static struct clk sdhc_clk[] = {
-        {
-                .id = 0,
-                .parent = &per_clk[1],
-                .secondary = &sdhc_ipg_clk[0],
-        }, {
-                .id = 1,
-                .parent = &per_clk[1],
-                .secondary = &sdhc_ipg_clk[1],
-        },
-};
-
-static struct clk sdhc_ipg_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SDHC1_REG,
-                .enable_shift = CCM_PCCR_SDHC1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SDHC2_REG,
-                .enable_shift = CCM_PCCR_SDHC2_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk cspi_ipg_clk[];
-
-static struct clk cspi_clk[] = {
-        {
-                .id = 0,
-                .parent = &per_clk[1],
-                .secondary = &cspi_ipg_clk[0],
-        }, {
-                .id = 1,
-                .parent = &per_clk[1],
-                .secondary = &cspi_ipg_clk[1],
-        }, {
-                .id = 2,
-                .parent = &per_clk[1],
-                .secondary = &cspi_ipg_clk[2],
-        },
-};
-
-static struct clk cspi_ipg_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_CSPI1_REG,
-                .enable_shift = CCM_PCCR_CSPI1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_CSPI2_REG,
-                .enable_shift = CCM_PCCR_CSPI2_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 3,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_CSPI3_REG,
-                .enable_shift = CCM_PCCR_CSPI3_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk lcdc_clk[] = {
-        {
-                .parent = &per_clk[2],
-                .secondary = &lcdc_clk[1],
-                .round_rate = _clk_parent_round_rate,
-                .set_rate = _clk_parent_set_rate,
-        }, {
-                .parent = &ipg_clk,
-                .secondary = &lcdc_clk[2],
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_LCDC_REG,
-                .enable_shift = CCM_PCCR_LCDC_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
-                .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk csi_clk[] = {
-        {
-                .parent = &per_clk[3],
-                .secondary = &csi_clk[1],
-                .round_rate = _clk_parent_round_rate,
-                .set_rate = _clk_parent_set_rate,
-        }, {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_CSI_REG,
-                .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk usb_clk[] = {
-        {
-                .parent = &spll_clk,
-                .secondary = &usb_clk[1],
-                .get_rate = _clk_usb_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_USBOTG_REG,
-                .enable_shift = CCM_PCCR_USBOTG_OFFSET,
-                .disable = _clk_disable,
-                .round_rate = _clk_usb_round_rate,
-                .set_rate = _clk_usb_set_rate,
-        }, {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
-                .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
-                .disable = _clk_disable,
-        }
-};
-
-static struct clk ssi_ipg_clk[];
-
-static struct clk ssi_clk[] = {
-        {
-                .id = 0,
-                .parent = &mpll_clk,
-                .secondary = &ssi_ipg_clk[0],
-                .get_rate = _clk_ssi1_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
-                .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &mpll_clk,
-                .secondary = &ssi_ipg_clk[1],
-                .get_rate = _clk_ssi2_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
-                .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk ssi_ipg_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SSI1_REG,
-                .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SSI2_REG,
-                .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-
-static struct clk nfc_clk = {
-        .parent = &fclk_clk,
-        .get_rate = _clk_nfc_recalc,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_NFC_REG,
-        .enable_shift = CCM_PCCR_NFC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk dma_clk[] = {
-        {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_DMA_REG,
-                .enable_shift = CCM_PCCR_DMA_OFFSET,
-                .disable = _clk_disable,
-                .secondary = &dma_clk[1],
-        },  {
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_DMA_REG,
-                .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk brom_clk = {
-        .parent = &hclk_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_HCLK_BROM_REG,
-        .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk emma_clk[] = {
-        {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_EMMA_REG,
-                .enable_shift = CCM_PCCR_EMMA_OFFSET,
-                .disable = _clk_disable,
-                .secondary = &emma_clk[1],
-        }, {
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
-                .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
-                .disable = _clk_disable,
-        }
-};
-
-static struct clk slcdc_clk[] = {
-        {
-                .parent = &hclk_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_SLCDC_REG,
-                .enable_shift = CCM_PCCR_SLCDC_OFFSET,
-                .disable = _clk_disable,
-                .secondary = &slcdc_clk[1],
-        }, {
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
-                .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
-                .disable = _clk_disable,
-        }
-};
-
-static struct clk wdog_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_WDT_REG,
-        .enable_shift = CCM_PCCR_WDT_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk gpio_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_GPIO_REG,
-        .enable_shift = CCM_PCCR_GPIO_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk i2c_clk = {
-        .id = 0,
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_I2C1_REG,
-        .enable_shift = CCM_PCCR_I2C1_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk kpp_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_KPP_REG,
-        .enable_shift = CCM_PCCR_KPP_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk owire_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_OWIRE_REG,
-        .enable_shift = CCM_PCCR_OWIRE_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk rtc_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR_RTC_REG,
-        .enable_shift = CCM_PCCR_RTC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
-{
-        return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-        div--;
-
-        reg = __raw_readl(CCM_PCDR0);
-
-        if (clk->parent == &usb_clk[0]) {
-                reg &= ~CCM_PCDR0_48MDIV_MASK;
-                reg |= div << CCM_PCDR0_48MDIV_OFFSET;
-        }
-        __raw_writel(reg, CCM_PCDR0);
-
-        return 0;
-}
-
-static unsigned long _clk_clko_recalc(struct clk *clk)
-{
-        u32 div = 0;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->parent == &usb_clk[0]) /* 48M */
-                div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
-                         >> CCM_PCDR0_48MDIV_OFFSET;
-        div++;
-
-        return parent_rate / div;
-}
-
-static struct clk clko_clk;
-
-static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
-
-        if (parent == &ckil_clk)
-                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &fpm_clk)
-                reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ckih_clk)
-                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == mpll_clk.parent)
-                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == spll_clk.parent)
-                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &mpll_clk)
-                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &spll_clk)
-                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &fclk_clk)
-                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &hclk_clk)
-                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ipg_clk)
-                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[0])
-                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[1])
-                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[2])
-                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[3])
-                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ssi_clk[0])
-                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ssi_clk[1])
-                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &nfc_clk)
-                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &usb_clk[0])
-                reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &clko_clk)
-                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
-        else
-                return -EINVAL;
-
-        __raw_writel(reg, CCM_CCSR);
-
-        return 0;
-}
-
-static struct clk clko_clk = {
-        .get_rate = _clk_clko_recalc,
-        .set_rate = _clk_clko_set_rate,
-        .round_rate = _clk_clko_round_rate,
-        .set_parent = _clk_clko_set_parent,
-};
-
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-static struct clk_lookup lookups[] = {
-/* It's unlikely that any driver wants one of them directly:
-        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
-        _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
-        _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
-        _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
-        _REGISTER_CLOCK(NULL, "spll", spll_clk)
-        _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
-        _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
-        _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
-*/
-        _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
-        _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
-        _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
-        _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
-        _REGISTER_CLOCK(NULL, "clko", clko_clk)
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart_clk[0])
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart_clk[1])
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart_clk[2])
-        _REGISTER_CLOCK("imx21-uart.3", NULL, uart_clk[3])
-        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
-        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
-        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
-        _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
-        _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
-        _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
-        _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
-        _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
-        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
-        _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
-        _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
-        _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
-        _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
-        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
-        _REGISTER_CLOCK(NULL, "brom", brom_clk)
-        _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
-        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
-        _REGISTER_CLOCK(NULL, "owire", owire_clk)
-        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-};
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx21_clocks_init(unsigned long lref, unsigned long href)
-{
-        u32 cscr;
-
-        external_low_reference = lref;
-        external_high_reference = href;
-
-        /* detect clock reference for both system PLL */
-        cscr = CSCR();
-        if (cscr & CCM_CSCR_MCU)
-                mpll_clk.parent = &ckih_clk;
-        else
-                mpll_clk.parent = &fpm_clk;
-
-        if (cscr & CCM_CSCR_SP)
-                spll_clk.parent = &ckih_clk;
-        else
-                spll_clk.parent = &fpm_clk;
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        /* Turn off all clock gates */
-        __raw_writel(0, CCM_PCCR0);
-        __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
-
-        /* This turns of the serial PLL as well */
-        spll_clk.disable(&spll_clk);
-
-        /* This will propagate to all children and init all the clock rates. */
-        clk_enable(&per_clk[0]);
-        clk_enable(&gpio_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-        clk_enable(&uart_clk[0]);
-#endif
-
-        mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
-                        MX21_INT_GPT1);
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
deleted file mode 100644
index b0fec74c8c91..000000000000
--- a/arch/arm/mach-imx/clock-imx25.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/mx25.h>
-
-#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
-
-#define CCM_MPCTL       0x00
-#define CCM_UPCTL       0x04
-#define CCM_CCTL        0x08
-#define CCM_CGCR0       0x0C
-#define CCM_CGCR1       0x10
-#define CCM_CGCR2       0x14
-#define CCM_PCDR0       0x18
-#define CCM_PCDR1       0x1C
-#define CCM_PCDR2       0x20
-#define CCM_PCDR3       0x24
-#define CCM_RCSR        0x28
-#define CCM_CRDR        0x2C
-#define CCM_DCVR0       0x30
-#define CCM_DCVR1       0x34
-#define CCM_DCVR2       0x38
-#define CCM_DCVR3       0x3c
-#define CCM_LTR0        0x40
-#define CCM_LTR1        0x44
-#define CCM_LTR2        0x48
-#define CCM_LTR3        0x4c
-
-static unsigned long get_rate_mpll(void)
-{
-        ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
-
-        return mxc_decode_pll(mpctl, 24000000);
-}
-
-static unsigned long get_rate_upll(void)
-{
-        ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
-
-        return mxc_decode_pll(mpctl, 24000000);
-}
-
-unsigned long get_rate_arm(struct clk *clk)
-{
-        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-        unsigned long rate = get_rate_mpll();
-
-        if (cctl & (1 << 14))
-                rate = (rate * 3) >> 2;
-
-        return rate / ((cctl >> 30) + 1);
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-
-        return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-        return get_rate_ahb(NULL) >> 1;
-}
-
-static unsigned long get_rate_per(int per)
-{
-        unsigned long ofs = (per & 0x3) * 8;
-        unsigned long reg = per & ~0x3;
-        unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
-        unsigned long fref;
-
-        if (readl(CRM_BASE + 0x64) & (1 << per))
-                fref = get_rate_upll();
-        else
-                fref = get_rate_ahb(NULL);
-
-        return fref / (val + 1);
-}
-
-static unsigned long get_rate_uart(struct clk *clk)
-{
-        return get_rate_per(15);
-}
-
-static unsigned long get_rate_ssi2(struct clk *clk)
-{
-        return get_rate_per(14);
-}
-
-static unsigned long get_rate_ssi1(struct clk *clk)
-{
-        return get_rate_per(13);
-}
-
-static unsigned long get_rate_i2c(struct clk *clk)
-{
-        return get_rate_per(6);
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-        return get_rate_per(8);
-}
-
-static unsigned long get_rate_gpt(struct clk *clk)
-{
-        return get_rate_per(5);
-}
-
-static unsigned long get_rate_lcdc(struct clk *clk)
-{
-        return get_rate_per(7);
-}
-
-static unsigned long get_rate_esdhc1(struct clk *clk)
-{
-        return get_rate_per(3);
-}
-
-static unsigned long get_rate_esdhc2(struct clk *clk)
-{
-        return get_rate_per(4);
-}
-
-static unsigned long get_rate_csi(struct clk *clk)
-{
-        return get_rate_per(0);
-}
-
-static unsigned long get_rate_otg(struct clk *clk)
-{
-        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-        unsigned long rate = get_rate_upll();
-
-        return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
-}
-
-static int clk_cgcr_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 1 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void clk_cgcr_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, s)        \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = CRM_BASE + er,        \
-                .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .set_rate       = sr,                   \
-                .enable         = clk_cgcr_enable,      \
-                .disable        = clk_cgcr_disable,     \
-                .secondary      = s,                    \
-        }
-
-/*
- * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
- * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
- * taken from the Freescale released BSP.
- *
- * bit  reg     offset  clock
- *
- * 0    CGCR1   0       AUDMUX
- * 12   CGCR1   12      ESAI
- * 16   CGCR1   16      GPIO1
- * 17   CGCR1   17      GPIO2
- * 18   CGCR1   18      GPIO3
- * 23   CGCR1   23      I2C1
- * 24   CGCR1   24      I2C2
- * 25   CGCR1   25      I2C3
- * 27   CGCR1   27      IOMUXC
- * 28   CGCR1   28      KPP
- * 30   CGCR1   30      OWIRE
- * 36   CGCR2   4       RTIC
- * 51   CGCR2   19      WDOG
- */
-
-DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
-DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
-DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,  NULL, NULL);
-DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,  NULL,
-                &esdhc1_ahb_clk);
-DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
-DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
-                &esdhc2_ahb_clk);
-DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,       NULL, NULL);
-DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
-DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
-DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
-DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
-DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
-DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
-DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
-DEFINE_CLOCK(fec_clk,    0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
-DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(lcdc_clk,   0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
-DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
-DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
-DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
-DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
-DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
-                &esdhc1_per_clk);
-DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
-                &esdhc2_per_clk);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
-DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
-DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(can2_clk,   1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(iim_clk,    0, CCM_CGCR1, 26, NULL, NULL, NULL);
-
-#define _REGISTER_CLOCK(d, n, c)        \
-        {                               \
-                .dev_id = d,            \
-                .con_id = n,            \
-                .clk = &c,              \
-        },
-
-static struct clk_lookup lookups[] = {
-        /* i.mx25 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
-        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        /* i.mx25 has the i.mx35 type cspi */
-        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
-        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
-        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
-        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
-        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
-        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
-        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
-        _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
-        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
-        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
-        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
-        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
-        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-        /* i.mx25 has the i.mx35 type sdma */
-        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-        _REGISTER_CLOCK(NULL, "iim", iim_clk)
-};
-
-int __init mx25_clocks_init(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        /* Turn off all clocks except the ones we need to survive, namely:
-         * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
-         * SCC
-         */
-        __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
-        __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
-        __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-        clk_enable(&uart1_clk);
-#endif
-
-        /* Clock source for lcdc and csi is upll */
-        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
-                        CRM_BASE + 0x64);
-
-        /* Clock source for gpt is ahb_div */
-        __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
-
-        clk_enable(&iim_clk);
-        imx_print_silicon_rev("i.MX25", mx25_revision());
-        clk_disable(&iim_clk);
-
-        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
deleted file mode 100644
index 98e04f5a87dd..000000000000
--- a/arch/arm/mach-imx/clock-imx27.c
+++ /dev/null
@@ -1,785 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS     (1 << 31)
-#define CCM_CSCR_SSI2           (1 << 23)
-#define CCM_CSCR_SSI1           (1 << 22)
-#define CCM_CSCR_VPU            (1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
-
-static struct clk mpll_main1_clk, mpll_main2_clk;
-
-static int clk_pccr_enable(struct clk *clk)
-{
-        unsigned long reg;
-
-        if (!clk->enable_reg)
-                return 0;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 1 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void clk_pccr_disable(struct clk *clk)
-{
-        unsigned long reg;
-
-        if (!clk->enable_reg)
-                return;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static int clk_spll_enable(struct clk *clk)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg |= CCM_CSCR_SPEN;
-        __raw_writel(reg, CCM_CSCR);
-
-        while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
-
-        return 0;
-}
-
-static void clk_spll_disable(struct clk *clk)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_CSCR);
-        reg &= ~CCM_CSCR_SPEN;
-        __raw_writel(reg, CCM_CSCR);
-}
-
-static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
-{
-        int cscr = __raw_readl(CCM_CSCR);
-
-        if (clk->parent == parent)
-                return 0;
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                if (parent == &mpll_main1_clk) {
-                        cscr |= CCM_CSCR_ARM_SRC;
-                } else {
-                        if (parent == &mpll_main2_clk)
-                                cscr &= ~CCM_CSCR_ARM_SRC;
-                        else
-                                return -EINVAL;
-                }
-                __raw_writel(cscr, CCM_CSCR);
-                clk->parent = parent;
-                return 0;
-        }
-        return -ENODEV;
-}
-
-static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
-{
-        int div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-
-        if (div > 4)
-                div = 4;
-
-        return parent_rate / div;
-}
-
-static int set_rate_cpu(struct clk *clk, unsigned long rate)
-{
-        unsigned int div;
-        uint32_t reg;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 4 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        div--;
-
-        reg = __raw_readl(CCM_CSCR);
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                reg &= ~(3 << 12);
-                reg |= div << 12;
-                reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
-                __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
-        } else {
-                printk(KERN_ERR "Can't set CPU frequency!\n");
-        }
-
-        return 0;
-}
-
-static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
-{
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-
-        if (div > 64)
-                div = 64;
-
-        return parent_rate / div;
-}
-
-static int set_rate_per(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->id < 0 || clk->id > 3)
-                return -EINVAL;
-
-        div = parent_rate / rate;
-        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-        div--;
-
-        reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
-        reg |= div << (clk->id << 3);
-        __raw_writel(reg, CCM_PCDR1);
-
-        return 0;
-}
-
-static unsigned long get_rate_usb(struct clk *clk)
-{
-        unsigned long usb_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
-
-        return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
-{
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                pdf += 4;  /* MX27 TO2+ */
-        else
-                pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
-
-        return 2UL * parent_rate / pdf;
-}
-
-static unsigned long get_rate_ssi1(struct clk *clk)
-{
-        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
-}
-
-static unsigned long get_rate_ssi2(struct clk *clk)
-{
-        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-        unsigned long nfc_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
-        else
-                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
-
-        return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long get_rate_vpu(struct clk *clk)
-{
-        unsigned long vpu_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
-                vpu_pdf += 4;
-        } else {
-                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
-                vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
-        }
-
-        return 2UL * parent_rate / vpu_pdf;
-}
-
-static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->round_rate(clk->parent, rate);
-}
-
-static unsigned long get_rate_parent(struct clk *clk)
-{
-        return clk_get_rate(clk->parent);
-}
-
-static int set_rate_parent(struct clk *clk, unsigned long rate)
-{
-        return clk->parent->set_rate(clk->parent, rate);
-}
-
-/* in Hz */
-static unsigned long external_high_reference = 26000000;
-
-static unsigned long get_rate_high_reference(struct clk *clk)
-{
-        return external_high_reference;
-}
-
-/* in Hz */
-static unsigned long external_low_reference = 32768;
-
-static unsigned long get_rate_low_reference(struct clk *clk)
-{
-        return external_low_reference;
-}
-
-static unsigned long get_rate_fpm(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) * 1024;
-}
-
-static unsigned long get_rate_mpll(struct clk *clk)
-{
-        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
-                        clk_get_rate(clk->parent));
-}
-
-static unsigned long get_rate_mpll_main(struct clk *clk)
-{
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        /* i.MX27 TO2:
-         * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
-         * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
-         */
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
-                return 2UL * parent_rate / 3UL;
-
-        return parent_rate;
-}
-
-static unsigned long get_rate_spll(struct clk *clk)
-{
-        uint32_t reg;
-        unsigned long rate;
-
-        rate = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(CCM_SPCTL0);
-
-        /* On TO2 we have to write the value back. Otherwise we
-         * read 0 from this register the next time.
-         */
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                __raw_writel(reg, CCM_SPCTL0);
-
-        return mxc_decode_pll(reg, rate);
-}
-
-static unsigned long get_rate_cpu(struct clk *clk)
-{
-        u32 div;
-        unsigned long rate;
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
-        else
-                div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
-
-        rate = clk_get_rate(clk->parent);
-        return rate / (div + 1);
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-        unsigned long rate, bclk_pdf;
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
-        else
-                bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
-
-        rate = clk_get_rate(clk->parent);
-        return rate / (bclk_pdf + 1);
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-        unsigned long rate, ipg_pdf;
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                return clk_get_rate(clk->parent);
-        else
-                ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
-
-        rate = clk_get_rate(clk->parent);
-        return rate / (ipg_pdf + 1);
-}
-
-static unsigned long get_rate_per(struct clk *clk)
-{
-        unsigned long perclk_pdf, parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->id < 0 || clk->id > 3)
-                return 0;
-
-        perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
-
-        return parent_rate / (perclk_pdf + 1);
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz. Could be changed at runtime
- * with a call to change_external_high_reference()
- */
-static struct clk ckih_clk = {
-        .get_rate       = get_rate_high_reference,
-};
-
-static struct clk mpll_clk = {
-        .parent         = &ckih_clk,
-        .get_rate       = get_rate_mpll,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
- * It provides the clock source whose rate is same as MPLL
- */
-static struct clk mpll_main1_clk = {
-        .id             = 0,
-        .parent         = &mpll_clk,
-        .get_rate       = get_rate_mpll_main,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
- * It provides the clock source whose rate is same MPLL * 2 / 3
- */
-static struct clk mpll_main2_clk = {
-        .id             = 1,
-        .parent         = &mpll_clk,
-        .get_rate       = get_rate_mpll_main,
-};
-
-static struct clk ahb_clk = {
-        .parent         = &mpll_main2_clk,
-        .get_rate       = get_rate_ahb,
-};
-
-static struct clk ipg_clk = {
-        .parent         = &ahb_clk,
-        .get_rate       = get_rate_ipg,
-};
-
-static struct clk cpu_clk = {
-        .parent = &mpll_main2_clk,
-        .set_parent = clk_cpu_set_parent,
-        .round_rate = round_rate_cpu,
-        .get_rate = get_rate_cpu,
-        .set_rate = set_rate_cpu,
-};
-
-static struct clk spll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = get_rate_spll,
-        .enable = clk_spll_enable,
-        .disable = clk_spll_disable,
-};
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
-        .get_rate = get_rate_low_reference,
-};
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
-        .parent = &ckil_clk,
-        .get_rate = get_rate_fpm,
-};
-
-#define PCCR0 CCM_PCCR0
-#define PCCR1 CCM_PCCR1
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .enable         = clk_pccr_enable,      \
-                .disable        = clk_pccr_disable,     \
-                .secondary      = s,                    \
-                .parent         = p,                    \
-        }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
-        static struct clk name = {                              \
-                .id             = i,                            \
-                .enable_reg     = er,                           \
-                .enable_shift   = es,                           \
-                .get_rate       = get_rate_##getsetround,       \
-                .set_rate       = set_rate_##getsetround,       \
-                .round_rate     = round_rate_##getsetround,     \
-                .enable         = clk_pccr_enable,              \
-                .disable        = clk_pccr_disable,             \
-                .secondary      = s,                            \
-                .parent         = p,                            \
-        }
-
-/* Forward declaration to keep the following list in order */
-static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
-                  dma_clk1, lcdc_clk2, vpu_clk1;
-
-/* All clocks we can gate through PCCRx in the order of PCCRx bits */
-DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
-DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
-DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
-DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
-DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
-DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
-DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
-DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
-
-DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
-DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
-DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
-DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(pata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
-DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
-
-/* Clocks we cannot directly gate, but drivers need their rates */
-DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
-DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
-DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
-DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
-DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
-DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
-DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
-DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
-DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
-DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
-DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
-DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
-DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
-DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
-DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
-DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
-DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
-DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-
-static struct clk_lookup lookups[] = {
-        /* i.mx27 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-        _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
-        _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
-        _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
-        _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
-        _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
-        _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
-        _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
-        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
-        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-        _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
-        _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
-        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
-        _REGISTER_CLOCK(NULL, "dma", dma_clk)
-        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-        _REGISTER_CLOCK(NULL, "brom", brom_clk)
-        _REGISTER_CLOCK(NULL, "emma", emma_clk)
-        _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
-        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
-        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
-        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-        _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-        _REGISTER_CLOCK(NULL, "iim", iim_clk)
-        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
-        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-        _REGISTER_CLOCK(NULL, "scc", scc_clk)
-};
-
-/* Adjust the clock path for TO2 and later */
-static void __init to2_adjust_clocks(void)
-{
-        unsigned long cscr = __raw_readl(CCM_CSCR);
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                if (cscr & CCM_CSCR_ARM_SRC)
-                        cpu_clk.parent = &mpll_main1_clk;
-
-                if (!(cscr & CCM_CSCR_SSI2))
-                        ssi1_clk.parent = &spll_clk;
-
-                if (!(cscr & CCM_CSCR_SSI1))
-                        ssi1_clk.parent = &spll_clk;
-
-                if (!(cscr & CCM_CSCR_VPU))
-                        vpu_clk.parent = &spll_clk;
-        } else {
-                cpu_clk.parent = &mpll_clk;
-                cpu_clk.set_parent = NULL;
-                cpu_clk.round_rate = NULL;
-                cpu_clk.set_rate = NULL;
-                ahb_clk.parent = &mpll_clk;
-
-                per1_clk.parent = &mpll_clk;
-                per2_clk.parent = &mpll_clk;
-                per3_clk.parent = &mpll_clk;
-                per4_clk.parent = &mpll_clk;
-
-                ssi1_clk.parent = &mpll_clk;
-                ssi2_clk.parent = &mpll_clk;
-
-                vpu_clk.parent = &mpll_clk;
-        }
-}
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx27_clocks_init(unsigned long fref)
-{
-        u32 cscr = __raw_readl(CCM_CSCR);
-
-        external_high_reference = fref;
-
-        /* detect clock reference for both system PLLs */
-        if (cscr & CCM_CSCR_MCU)
-                mpll_clk.parent = &ckih_clk;
-        else
-                mpll_clk.parent = &fpm_clk;
-
-        if (cscr & CCM_CSCR_SP)
-                spll_clk.parent = &ckih_clk;
-        else
-                spll_clk.parent = &fpm_clk;
-
-        to2_adjust_clocks();
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        /* Turn off all clocks we do not need */
-        __raw_writel(0, CCM_PCCR0);
-        __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
-
-        spll_clk.disable(&spll_clk);
-
-        /* enable basic clocks */
-        clk_enable(&per1_clk);
-        clk_enable(&gpio_clk);
-        clk_enable(&emi_clk);
-        clk_enable(&iim_clk);
-        imx_print_silicon_rev("i.MX27", mx27_revision());
-        clk_disable(&iim_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-        clk_enable(&uart1_clk);
-#endif
-
-        mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
-                        MX27_INT_GPT1);
-
-        return 0;
-}
-
-#ifdef CONFIG_OF
-int __init mx27_clocks_init_dt(void)
-{
-        struct device_node *np;
-        u32 fref = 26000000; /* default */
-
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
-                        continue;
-
-                if (!of_property_read_u32(np, "clock-frequency", &fref))
-                        break;
-        }
-
-        return mx27_clocks_init(fref);
-}
-#endif
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
deleted file mode 100644
index 3a943cd4159f..000000000000
--- a/arch/arm/mach-imx/clock-imx31.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/mx31.h>
-#include <mach/common.h>
-
-#include "crmregs-imx3.h"
-
-#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
-
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
-{
-        u32 min_pre, temp_pre, old_err, err;
-
-        if (div >= 512) {
-                *pre = 8;
-                *post = 64;
-        } else if (div >= 64) {
-                min_pre = (div - 1) / 64 + 1;
-                old_err = 8;
-                for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
-                        err = div % temp_pre;
-                        if (err == 0) {
-                                *pre = temp_pre;
-                                break;
-                        }
-                        err = temp_pre - err;
-                        if (err < old_err) {
-                                old_err = err;
-                                *pre = temp_pre;
-                        }
-                }
-                *post = (div + *pre - 1) / *pre;
-        } else if (div <= 8) {
-                *pre = div;
-                *post = 1;
-        } else {
-                *pre = 1;
-                *post = div;
-        }
-}
-
-static struct clk mcu_pll_clk;
-static struct clk serial_pll_clk;
-static struct clk ipg_clk;
-static struct clk ckih_clk;
-
-static int cgr_enable(struct clk *clk)
-{
-        u32 reg;
-
-        if (!clk->enable_reg)
-                return 0;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 3 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void cgr_disable(struct clk *clk)
-{
-        u32 reg;
-
-        if (!clk->enable_reg)
-                return;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(3 << clk->enable_shift);
-
-        /* special case for EMI clock */
-        if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
-                reg |= (1 << clk->enable_shift);
-
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long pll_ref_get_rate(void)
-{
-        unsigned long ccmr;
-        unsigned int prcs;
-
-        ccmr = __raw_readl(MXC_CCM_CCMR);
-        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
-        if (prcs == 0x1)
-                return CKIL_CLK_FREQ * 1024;
-        else
-                return clk_get_rate(&ckih_clk);
-}
-
-static unsigned long usb_pll_get_rate(struct clk *clk)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(MXC_CCM_UPCTL);
-
-        return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long serial_pll_get_rate(struct clk *clk)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(MXC_CCM_SRPCTL);
-
-        return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long mcu_pll_get_rate(struct clk *clk)
-{
-        unsigned long reg, ccmr;
-
-        ccmr = __raw_readl(MXC_CCM_CCMR);
-
-        if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
-                return clk_get_rate(&ckih_clk);
-
-        reg = __raw_readl(MXC_CCM_MPCTL);
-
-        return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static int usb_pll_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CCMR);
-        reg |= MXC_CCM_CCMR_UPE;
-        __raw_writel(reg, MXC_CCM_CCMR);
-
-        /* No lock bit on MX31, so using max time from spec */
-        udelay(80);
-
-        return 0;
-}
-
-static void usb_pll_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CCMR);
-        reg &= ~MXC_CCM_CCMR_UPE;
-        __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-static int serial_pll_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CCMR);
-        reg |= MXC_CCM_CCMR_SPE;
-        __raw_writel(reg, MXC_CCM_CCMR);
-
-        /* No lock bit on MX31, so using max time from spec */
-        udelay(80);
-
-        return 0;
-}
-
-static void serial_pll_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CCMR);
-        reg &= ~MXC_CCM_CCMR_SPE;
-        __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
-#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
-#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
-
-static unsigned long mcu_main_get_rate(struct clk *clk)
-{
-        u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
-
-        if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
-                return clk_get_rate(&serial_pll_clk);
-        else
-                return clk_get_rate(&mcu_pll_clk);
-}
-
-static unsigned long ahb_get_rate(struct clk *clk)
-{
-        unsigned long max_pdf;
-
-        max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
-                       MXC_CCM_PDR0_MAX_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (max_pdf + 1);
-}
-
-static unsigned long ipg_get_rate(struct clk *clk)
-{
-        unsigned long ipg_pdf;
-
-        ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
-                       MXC_CCM_PDR0_IPG_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (ipg_pdf + 1);
-}
-
-static unsigned long nfc_get_rate(struct clk *clk)
-{
-        unsigned long nfc_pdf;
-
-        nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
-                       MXC_CCM_PDR0_NFC_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (nfc_pdf + 1);
-}
-
-static unsigned long hsp_get_rate(struct clk *clk)
-{
-        unsigned long hsp_pdf;
-
-        hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
-                       MXC_CCM_PDR0_HSP_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (hsp_pdf + 1);
-}
-
-static unsigned long usb_get_rate(struct clk *clk)
-{
-        unsigned long usb_pdf, usb_prepdf;
-
-        usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
-                       MXC_CCM_PDR1_USB_PODF_OFFSET);
-        usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
-                          MXC_CCM_PDR1_USB_PRDF_OFFSET);
-        return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
-}
-
-static unsigned long csi_get_rate(struct clk *clk)
-{
-        u32 reg, pre, post;
-
-        reg = __raw_readl(MXC_CCM_PDR0);
-        pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
-            MXC_CCM_PDR0_CSI_PRDF_OFFSET;
-        pre++;
-        post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
-            MXC_CCM_PDR0_CSI_PODF_OFFSET;
-        post++;
-        return clk_get_rate(clk->parent) / (pre * post);
-}
-
-static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
-{
-        u32 pre, post, parent = clk_get_rate(clk->parent);
-        u32 div = parent / rate;
-
-        if (parent % rate)
-                div++;
-
-        __calc_pre_post_dividers(div, &pre, &post);
-
-        return parent / (pre * post);
-}
-
-static int csi_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
-        div = parent / rate;
-
-        if ((parent / div) != rate)
-                return -EINVAL;
-
-        __calc_pre_post_dividers(div, &pre, &post);
-
-        /* Set CSI clock divider */
-        reg = __raw_readl(MXC_CCM_PDR0) &
-            ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
-        reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
-        reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
-        __raw_writel(reg, MXC_CCM_PDR0);
-
-        return 0;
-}
-
-static unsigned long ssi1_get_rate(struct clk *clk)
-{
-        unsigned long ssi1_pdf, ssi1_prepdf;
-
-        ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
-                        MXC_CCM_PDR1_SSI1_PODF_OFFSET);
-        ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
-                           MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
-}
-
-static unsigned long ssi2_get_rate(struct clk *clk)
-{
-        unsigned long ssi2_pdf, ssi2_prepdf;
-
-        ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
-                        MXC_CCM_PDR1_SSI2_PODF_OFFSET);
-        ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
-                           MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
-}
-
-static unsigned long firi_get_rate(struct clk *clk)
-{
-        unsigned long firi_pdf, firi_prepdf;
-
-        firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
-                        MXC_CCM_PDR1_FIRI_PODF_OFFSET);
-        firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
-                           MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
-}
-
-static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
-{
-        u32 pre, post;
-        u32 parent = clk_get_rate(clk->parent);
-        u32 div = parent / rate;
-
-        if (parent % rate)
-                div++;
-
-        __calc_pre_post_dividers(div, &pre, &post);
-
-        return parent / (pre * post);
-
-}
-
-static int firi_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
-        div = parent / rate;
-
-        if ((parent / div) != rate)
-                return -EINVAL;
-
-        __calc_pre_post_dividers(div, &pre, &post);
-
-        /* Set FIRI clock divider */
-        reg = __raw_readl(MXC_CCM_PDR1) &
-            ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
-        reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
-        reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
-        __raw_writel(reg, MXC_CCM_PDR1);
-
-        return 0;
-}
-
-static unsigned long mbx_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 2;
-}
-
-static unsigned long mstick1_get_rate(struct clk *clk)
-{
-        unsigned long msti_pdf;
-
-        msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
-                        MXC_CCM_PDR2_MST1_PDF_OFFSET);
-        return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long mstick2_get_rate(struct clk *clk)
-{
-        unsigned long msti_pdf;
-
-        msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
-                        MXC_CCM_PDR2_MST2_PDF_OFFSET);
-        return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long ckih_rate;
-
-static unsigned long clk_ckih_get_rate(struct clk *clk)
-{
-        return ckih_rate;
-}
-
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
-        return CKIL_CLK_FREQ;
-}
-
-static struct clk ckih_clk = {
-        .get_rate = clk_ckih_get_rate,
-};
-
-static struct clk mcu_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = mcu_pll_get_rate,
-};
-
-static struct clk mcu_main_clk = {
-        .parent = &mcu_pll_clk,
-        .get_rate = mcu_main_get_rate,
-};
-
-static struct clk serial_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = serial_pll_get_rate,
-        .enable = serial_pll_enable,
-        .disable = serial_pll_disable,
-};
-
-static struct clk usb_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = usb_pll_get_rate,
-        .enable = usb_pll_enable,
-        .disable = usb_pll_disable,
-};
-
-static struct clk ahb_clk = {
-        .parent = &mcu_main_clk,
-        .get_rate = ahb_get_rate,
-};
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .enable         = cgr_enable,           \
-                .disable        = cgr_disable,          \
-                .secondary      = s,                    \
-                .parent         = p,                    \
-        }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
-        static struct clk name = {                              \
-                .id             = i,                            \
-                .enable_reg     = er,                           \
-                .enable_shift   = es,                           \
-                .get_rate       = getsetround##_get_rate,       \
-                .set_rate       = getsetround##_set_rate,       \
-                .round_rate     = getsetround##_round_rate,     \
-                .enable         = cgr_enable,                   \
-                .disable        = cgr_disable,                  \
-                .secondary      = s,                            \
-                .parent         = p,                            \
-        }
-
-DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
-
-DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
-DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
-DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
-DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
-
-DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-
-static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
-        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
-        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
-        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
-        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
-        _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
-        /* i.mx31 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
-        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
-        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
-        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        _REGISTER_CLOCK(NULL, "firi", firi_clk)
-        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-        _REGISTER_CLOCK(NULL, "rng", rng_clk)
-        _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
-        _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
-        _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
-        _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
-        _REGISTER_CLOCK(NULL, "scc", scc_clk)
-        _REGISTER_CLOCK(NULL, "iim", iim_clk)
-        _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
-        _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
-};
-
-int __init mx31_clocks_init(unsigned long fref)
-{
-        u32 reg;
-
-        ckih_rate = fref;
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        /* change the csi_clk parent if necessary */
-        reg = __raw_readl(MXC_CCM_CCMR);
-        if (!(reg & MXC_CCM_CCMR_CSCS))
-                if (clk_set_parent(&csi_clk, &usb_pll_clk))
-                        pr_err("%s: error changing csi_clk parent\n", __func__);
-
-
-        /* Turn off all possible clocks */
-        __raw_writel((3 << 4), MXC_CCM_CGR0);
-        __raw_writel(0, MXC_CCM_CGR1);
-        __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
-                     1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
-                                           MX32, but still required to be set */
-                     MXC_CCM_CGR2);
-
-        /*
-         * Before turning off usb_pll make sure ipg_per_clk is generated
-         * by ipg_clk and not usb_pll.
-         */
-        __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
-
-        usb_pll_disable(&usb_pll_clk);
-
-        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
-
-        clk_enable(&gpt_clk);
-        clk_enable(&emi_clk);
-        clk_enable(&iim_clk);
-        mx31_revision();
-        clk_disable(&iim_clk);
-
-        clk_enable(&serial_pll_clk);
-
-        if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
-                reg = __raw_readl(MXC_CCM_PMCR1);
-                /* No PLL restart on DVFS switch; enable auto EMI handshake */
-                reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
-                __raw_writel(reg, MXC_CCM_PMCR1);
-        }
-
-        mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
-                        MX31_INT_GPT);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
deleted file mode 100644
index e56c1a83eee3..000000000000
--- a/arch/arm/mach-imx/clock-imx35.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#include "crmregs-imx3.h"
-
-#ifdef HAVE_SET_RATE_SUPPORT
-static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
-{
-        u32 min_pre, temp_pre, old_err, err;
-
-        min_pre = (div - 1) / maxpost + 1;
-        old_err = 8;
-
-        for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
-                if (div > (temp_pre * maxpost))
-                        break;
-
-                if (div < (temp_pre * temp_pre))
-                        continue;
-
-                err = div % temp_pre;
-
-                if (err == 0) {
-                        *pre = temp_pre;
-                        break;
-                }
-
-                err = temp_pre - err;
-
-                if (err < old_err) {
-                        old_err = err;
-                        *pre = temp_pre;
-                }
-        }
-
-        *post = (div + *pre - 1) / *pre;
-}
-
-/* get the best values for a 3-bit divider combined with a 6-bit divider */
-static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
-{
-        if (div >= 512) {
-                *pre = 8;
-                *post = 64;
-        } else if (div >= 64) {
-                calc_dividers(div, pre, post, 64);
-        } else if (div <= 8) {
-                *pre = div;
-                *post = 1;
-        } else {
-                *pre = 1;
-                *post = div;
-        }
-}
-
-/* get the best values for two cascaded 3-bit dividers */
-static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
-{
-        if (div >= 64) {
-                *pre = *post = 8;
-        } else if (div > 8) {
-                calc_dividers(div, pre, post, 8);
-        } else {
-                *pre = 1;
-                *post = div;
-        }
-}
-#endif
-
-static unsigned long get_rate_mpll(void)
-{
-        ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
-
-        return mxc_decode_pll(mpctl, 24000000);
-}
-
-static unsigned long get_rate_ppll(void)
-{
-        ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
-
-        return mxc_decode_pll(ppctl, 24000000);
-}
-
-struct arm_ahb_div {
-        unsigned char arm, ahb, sel;
-};
-
-static struct arm_ahb_div clk_consumer[] = {
-        { .arm = 1, .ahb = 4, .sel = 0},
-        { .arm = 1, .ahb = 3, .sel = 1},
-        { .arm = 2, .ahb = 2, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 4, .ahb = 1, .sel = 0},
-        { .arm = 1, .ahb = 5, .sel = 0},
-        { .arm = 1, .ahb = 8, .sel = 0},
-        { .arm = 1, .ahb = 6, .sel = 1},
-        { .arm = 2, .ahb = 4, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 4, .ahb = 2, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-};
-
-static unsigned long get_rate_arm(void)
-{
-        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-        struct arm_ahb_div *aad;
-        unsigned long fref = get_rate_mpll();
-
-        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-        if (aad->sel)
-                fref = fref * 3 / 4;
-
-        return fref / aad->arm;
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-        struct arm_ahb_div *aad;
-        unsigned long fref = get_rate_arm();
-
-        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-
-        return fref / aad->ahb;
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-        return get_rate_ahb(NULL) >> 1;
-}
-
-static unsigned long get_rate_uart(struct clk *clk)
-{
-        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
-        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-        unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
-
-        if (pdr3 & (1 << 14))
-                return get_rate_arm() / div;
-        else
-                return get_rate_ppll() / div;
-}
-
-static unsigned long get_rate_sdhc(struct clk *clk)
-{
-        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
-        unsigned long div, rate;
-
-        if (pdr3 & (1 << 6))
-                rate = get_rate_arm();
-        else
-                rate = get_rate_ppll();
-
-        switch (clk->id) {
-        default:
-        case 0:
-                div = pdr3 & 0x3f;
-                break;
-        case 1:
-                div = (pdr3 >> 8) & 0x3f;
-                break;
-        case 2:
-                div = (pdr3 >> 16) & 0x3f;
-                break;
-        }
-
-        return rate / (div + 1);
-}
-
-static unsigned long get_rate_mshc(struct clk *clk)
-{
-        unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
-        unsigned long div1, div2, rate;
-
-        if (pdr1 & (1 << 7))
-                rate = get_rate_arm();
-        else
-                rate = get_rate_ppll();
-
-        div1 = (pdr1 >> 29) & 0x7;
-        div2 = (pdr1 >> 22) & 0x3f;
-
-        return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_ssi(struct clk *clk)
-{
-        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
-        unsigned long div1, div2, rate;
-
-        if (pdr2 & (1 << 6))
-                rate = get_rate_arm();
-        else
-                rate = get_rate_ppll();
-
-        switch (clk->id) {
-        default:
-        case 0:
-                div1 = pdr2 & 0x3f;
-                div2 = (pdr2 >> 24) & 0x7;
-                break;
-        case 1:
-                div1 = (pdr2 >> 8) & 0x3f;
-                div2 = (pdr2 >> 27) & 0x7;
-                break;
-        }
-
-        return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_csi(struct clk *clk)
-{
-        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
-        unsigned long rate;
-
-        if (pdr2 & (1 << 7))
-                rate = get_rate_arm();
-        else
-                rate = get_rate_ppll();
-
-        return rate / (((pdr2 >> 16) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_otg(struct clk *clk)
-{
-        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-        unsigned long rate;
-
-        if (pdr4 & (1 << 9))
-                rate = get_rate_arm();
-        else
-                rate = get_rate_ppll();
-
-        return rate / (((pdr4 >> 22) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_ipg_per(struct clk *clk)
-{
-        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-        unsigned long div;
-
-        if (pdr0 & (1 << 26)) {
-                div = (pdr4 >> 16) & 0x3f;
-                return get_rate_arm() / (div + 1);
-        } else {
-                div = (pdr0 >> 12) & 0x7;
-                return get_rate_ahb(NULL) / (div + 1);
-        }
-}
-
-static unsigned long get_rate_hsp(struct clk *clk)
-{
-        unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
-        unsigned long fref = get_rate_mpll();
-
-        if (fref > 400 * 1000 * 1000) {
-                switch (hsp_podf) {
-                case 0:
-                        return fref >> 2;
-                case 1:
-                        return fref >> 3;
-                case 2:
-                        return fref / 3;
-                }
-        } else {
-                switch (hsp_podf) {
-                case 0:
-                case 2:
-                        return fref / 3;
-                case 1:
-                        return fref / 6;
-                }
-        }
-
-        return 0;
-}
-
-static int clk_cgr_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 3 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void clk_cgr_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(3 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .set_rate       = sr,                   \
-                .enable         = clk_cgr_enable,       \
-                .disable        = clk_cgr_disable,      \
-        }
-
-DEFINE_CLOCK(asrc_clk,   0, MX35_CCM_CGR0,  0, NULL, NULL);
-DEFINE_CLOCK(pata_clk,    0, MX35_CCM_CGR0,  2, get_rate_ipg, NULL);
-/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0,  4, NULL, NULL); */
-DEFINE_CLOCK(can1_clk,   0, MX35_CCM_CGR0,  6, get_rate_ipg, NULL);
-DEFINE_CLOCK(can2_clk,   1, MX35_CCM_CGR0,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi2_clk,  1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
-DEFINE_CLOCK(ect_clk,    0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
-DEFINE_CLOCK(edio_clk,   0, MX35_CCM_CGR0, 16, NULL, NULL);
-DEFINE_CLOCK(emi_clk,    0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit2_clk,  1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
-DEFINE_CLOCK(esai_clk,   0, MX35_CCM_CGR0, 24, NULL, NULL);
-DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
-
-DEFINE_CLOCK(fec_clk,    0, MX35_CCM_CGR1,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(gpio1_clk,  0, MX35_CCM_CGR1,  2, NULL, NULL);
-DEFINE_CLOCK(gpio2_clk,  1, MX35_CCM_CGR1,  4, NULL, NULL);
-DEFINE_CLOCK(gpio3_clk,  2, MX35_CCM_CGR1,  6, NULL, NULL);
-DEFINE_CLOCK(gpt_clk,    0, MX35_CCM_CGR1,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(i2c1_clk,   0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c2_clk,   1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c3_clk,   2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
-DEFINE_CLOCK(kpp_clk,    0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(mlb_clk,    0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
-DEFINE_CLOCK(mshc_clk,   0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
-DEFINE_CLOCK(owire_clk,  0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(pwm_clk,    0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(rngc_clk,   0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
-
-DEFINE_CLOCK(rtc_clk,    0, MX35_CCM_CGR2,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(rtic_clk,   0, MX35_CCM_CGR2,  2, get_rate_ahb, NULL);
-DEFINE_CLOCK(scc_clk,    0, MX35_CCM_CGR2,  4, get_rate_ipg, NULL);
-DEFINE_CLOCK(sdma_clk,   0, MX35_CCM_CGR2,  6, NULL, NULL);
-DEFINE_CLOCK(spba_clk,   0, MX35_CCM_CGR2,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(spdif_clk,  0, MX35_CCM_CGR2, 10, NULL, NULL);
-DEFINE_CLOCK(ssi1_clk,   0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
-DEFINE_CLOCK(ssi2_clk,   1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
-DEFINE_CLOCK(uart1_clk,  0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
-DEFINE_CLOCK(uart2_clk,  1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
-DEFINE_CLOCK(uart3_clk,  2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
-DEFINE_CLOCK(wdog_clk,   0, MX35_CCM_CGR2, 24, NULL, NULL);
-DEFINE_CLOCK(max_clk,    0, MX35_CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
-
-DEFINE_CLOCK(csi_clk,    0, MX35_CCM_CGR3,  0, get_rate_csi, NULL);
-DEFINE_CLOCK(iim_clk,    0, MX35_CCM_CGR3,  2, NULL, NULL);
-DEFINE_CLOCK(gpu2d_clk,  0, MX35_CCM_CGR3,  4, NULL, NULL);
-
-DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
-
-static int clk_dummy_enable(struct clk *clk)
-{
-        return 0;
-}
-
-static void clk_dummy_disable(struct clk *clk)
-{
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-        unsigned long div1;
-
-        div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
-
-        return get_rate_ahb(NULL) / div1;
-}
-
-/* NAND Controller: It seems it can't be disabled */
-static struct clk nfc_clk = {
-        .id             = 0,
-        .enable_reg     = 0,
-        .enable_shift   = 0,
-        .get_rate       = get_rate_nfc,
-        .set_rate       = NULL, /* set_rate_nfc, */
-        .enable         = clk_dummy_enable,
-        .disable        = clk_dummy_disable
-};
-
-#define _REGISTER_CLOCK(d, n, c)        \
-        {                               \
-                .dev_id = d,            \
-                .con_id = n,            \
-                .clk = &c,              \
-        },
-
-static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
-        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
-        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK(NULL, "ect", ect_clk)
-        _REGISTER_CLOCK(NULL, "edio", edio_clk)
-        _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
-        _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
-        _REGISTER_CLOCK(NULL, "esai", esai_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk)
-        /* i.mx35 has the i.mx27 type fec */
-        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
-        _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
-        _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
-        _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
-        _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
-        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
-        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
-        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-        _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
-        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-        _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
-        _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
-        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-        _REGISTER_CLOCK(NULL, "scc", scc_clk)
-        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-        _REGISTER_CLOCK(NULL, "spba", spba_clk)
-        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        /* i.mx35 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-        _REGISTER_CLOCK(NULL, "max", max_clk)
-        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
-        _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
-        _REGISTER_CLOCK(NULL, "iim", iim_clk)
-        _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
-        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-};
-
-int __init mx35_clocks_init()
-{
-        unsigned int cgr2 = 3 << 26;
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-        cgr2 |= 3 << 16;
-#endif
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        /* Turn off all clocks except the ones we need to survive, namely:
-         * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
-         */
-        __raw_writel((3 << 18), MX35_CCM_CGR0);
-        __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
-                        MX35_CCM_CGR1);
-        __raw_writel(cgr2, MX35_CCM_CGR2);
-        __raw_writel(0, MX35_CCM_CGR3);
-
-        clk_enable(&iim_clk);
-        imx_print_silicon_rev("i.MX35", mx35_revision());
-        clk_disable(&iim_clk);
-
-        /*
-         * Check if we came up in internal boot mode. If yes, we need some
-         * extra clocks turned on, otherwise the MX35 boot ROM code will
-         * hang after a watchdog reset.
-         */
-        if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
-                /* Additionally turn on UART1, SCC, and IIM clocks */
-                clk_enable(&iim_clk);
-                clk_enable(&uart1_clk);
-                clk_enable(&scc_clk);
-        }
-
-#ifdef CONFIG_MXC_USE_EPIT
-        epit_timer_init(&epit1_clk,
-                        MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
-#else
-        mxc_timer_init(&gpt_clk,
-                        MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
-#endif
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
deleted file mode 100644
index 111c328f5420..000000000000
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ /dev/null
@@ -1,2111 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/div64.h>
-#include <asm/mach/map.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-#define PLL_BASE                IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
-#define PLL1_SYS                (PLL_BASE + 0x000)
-#define PLL2_BUS                (PLL_BASE + 0x030)
-#define PLL3_USB_OTG            (PLL_BASE + 0x010)
-#define PLL4_AUDIO              (PLL_BASE + 0x070)
-#define PLL5_VIDEO              (PLL_BASE + 0x0a0)
-#define PLL6_MLB                (PLL_BASE + 0x0d0)
-#define PLL7_USB_HOST           (PLL_BASE + 0x020)
-#define PLL8_ENET               (PLL_BASE + 0x0e0)
-#define PFD_480                 (PLL_BASE + 0x0f0)
-#define PFD_528                 (PLL_BASE + 0x100)
-#define PLL_NUM_OFFSET          0x010
-#define PLL_DENOM_OFFSET        0x020
-
-#define PFD0                    7
-#define PFD1                    15
-#define PFD2                    23
-#define PFD3                    31
-#define PFD_FRAC_MASK           0x3f
-
-#define BM_PLL_BYPASS                   (0x1 << 16)
-#define BM_PLL_ENABLE                   (0x1 << 13)
-#define BM_PLL_POWER_DOWN               (0x1 << 12)
-#define BM_PLL_LOCK                     (0x1 << 31)
-#define BP_PLL_SYS_DIV_SELECT           0
-#define BM_PLL_SYS_DIV_SELECT           (0x7f << 0)
-#define BP_PLL_BUS_DIV_SELECT           0
-#define BM_PLL_BUS_DIV_SELECT           (0x1 << 0)
-#define BP_PLL_USB_DIV_SELECT           0
-#define BM_PLL_USB_DIV_SELECT           (0x3 << 0)
-#define BP_PLL_AV_DIV_SELECT            0
-#define BM_PLL_AV_DIV_SELECT            (0x7f << 0)
-#define BP_PLL_ENET_DIV_SELECT          0
-#define BM_PLL_ENET_DIV_SELECT          (0x3 << 0)
-#define BM_PLL_ENET_EN_PCIE             (0x1 << 19)
-#define BM_PLL_ENET_EN_SATA             (0x1 << 20)
-
-#define CCM_BASE        IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
-#define CCR             (CCM_BASE + 0x00)
-#define CCDR            (CCM_BASE + 0x04)
-#define CSR             (CCM_BASE + 0x08)
-#define CCSR            (CCM_BASE + 0x0c)
-#define CACRR           (CCM_BASE + 0x10)
-#define CBCDR           (CCM_BASE + 0x14)
-#define CBCMR           (CCM_BASE + 0x18)
-#define CSCMR1          (CCM_BASE + 0x1c)
-#define CSCMR2          (CCM_BASE + 0x20)
-#define CSCDR1          (CCM_BASE + 0x24)
-#define CS1CDR          (CCM_BASE + 0x28)
-#define CS2CDR          (CCM_BASE + 0x2c)
-#define CDCDR           (CCM_BASE + 0x30)
-#define CHSCCDR         (CCM_BASE + 0x34)
-#define CSCDR2          (CCM_BASE + 0x38)
-#define CSCDR3          (CCM_BASE + 0x3c)
-#define CSCDR4          (CCM_BASE + 0x40)
-#define CWDR            (CCM_BASE + 0x44)
-#define CDHIPR          (CCM_BASE + 0x48)
-#define CDCR            (CCM_BASE + 0x4c)
-#define CTOR            (CCM_BASE + 0x50)
-#define CLPCR           (CCM_BASE + 0x54)
-#define CISR            (CCM_BASE + 0x58)
-#define CIMR            (CCM_BASE + 0x5c)
-#define CCOSR           (CCM_BASE + 0x60)
-#define CGPR            (CCM_BASE + 0x64)
-#define CCGR0           (CCM_BASE + 0x68)
-#define CCGR1           (CCM_BASE + 0x6c)
-#define CCGR2           (CCM_BASE + 0x70)
-#define CCGR3           (CCM_BASE + 0x74)
-#define CCGR4           (CCM_BASE + 0x78)
-#define CCGR5           (CCM_BASE + 0x7c)
-#define CCGR6           (CCM_BASE + 0x80)
-#define CCGR7           (CCM_BASE + 0x84)
-#define CMEOR           (CCM_BASE + 0x88)
-
-#define CG0             0
-#define CG1             2
-#define CG2             4
-#define CG3             6
-#define CG4             8
-#define CG5             10
-#define CG6             12
-#define CG7             14
-#define CG8             16
-#define CG9             18
-#define CG10            20
-#define CG11            22
-#define CG12            24
-#define CG13            26
-#define CG14            28
-#define CG15            30
-
-#define BM_CCSR_PLL1_SW_SEL             (0x1 << 2)
-#define BM_CCSR_STEP_SEL                (0x1 << 8)
-
-#define BP_CACRR_ARM_PODF               0
-#define BM_CACRR_ARM_PODF               (0x7 << 0)
-
-#define BP_CBCDR_PERIPH2_CLK2_PODF      0
-#define BM_CBCDR_PERIPH2_CLK2_PODF      (0x7 << 0)
-#define BP_CBCDR_MMDC_CH1_AXI_PODF      3
-#define BM_CBCDR_MMDC_CH1_AXI_PODF      (0x7 << 3)
-#define BP_CBCDR_AXI_SEL                6
-#define BM_CBCDR_AXI_SEL                (0x3 << 6)
-#define BP_CBCDR_IPG_PODF               8
-#define BM_CBCDR_IPG_PODF               (0x3 << 8)
-#define BP_CBCDR_AHB_PODF               10
-#define BM_CBCDR_AHB_PODF               (0x7 << 10)
-#define BP_CBCDR_AXI_PODF               16
-#define BM_CBCDR_AXI_PODF               (0x7 << 16)
-#define BP_CBCDR_MMDC_CH0_AXI_PODF      19
-#define BM_CBCDR_MMDC_CH0_AXI_PODF      (0x7 << 19)
-#define BP_CBCDR_PERIPH_CLK_SEL         25
-#define BM_CBCDR_PERIPH_CLK_SEL         (0x1 << 25)
-#define BP_CBCDR_PERIPH2_CLK_SEL        26
-#define BM_CBCDR_PERIPH2_CLK_SEL        (0x1 << 26)
-#define BP_CBCDR_PERIPH_CLK2_PODF       27
-#define BM_CBCDR_PERIPH_CLK2_PODF       (0x7 << 27)
-
-#define BP_CBCMR_GPU2D_AXI_SEL          0
-#define BM_CBCMR_GPU2D_AXI_SEL          (0x1 << 0)
-#define BP_CBCMR_GPU3D_AXI_SEL          1
-#define BM_CBCMR_GPU3D_AXI_SEL          (0x1 << 1)
-#define BP_CBCMR_GPU3D_CORE_SEL         4
-#define BM_CBCMR_GPU3D_CORE_SEL         (0x3 << 4)
-#define BP_CBCMR_GPU3D_SHADER_SEL       8
-#define BM_CBCMR_GPU3D_SHADER_SEL       (0x3 << 8)
-#define BP_CBCMR_PCIE_AXI_SEL           10
-#define BM_CBCMR_PCIE_AXI_SEL           (0x1 << 10)
-#define BP_CBCMR_VDO_AXI_SEL            11
-#define BM_CBCMR_VDO_AXI_SEL            (0x1 << 11)
-#define BP_CBCMR_PERIPH_CLK2_SEL        12
-#define BM_CBCMR_PERIPH_CLK2_SEL        (0x3 << 12)
-#define BP_CBCMR_VPU_AXI_SEL            14
-#define BM_CBCMR_VPU_AXI_SEL            (0x3 << 14)
-#define BP_CBCMR_GPU2D_CORE_SEL         16
-#define BM_CBCMR_GPU2D_CORE_SEL         (0x3 << 16)
-#define BP_CBCMR_PRE_PERIPH_CLK_SEL     18
-#define BM_CBCMR_PRE_PERIPH_CLK_SEL     (0x3 << 18)
-#define BP_CBCMR_PERIPH2_CLK2_SEL       20
-#define BM_CBCMR_PERIPH2_CLK2_SEL       (0x1 << 20)
-#define BP_CBCMR_PRE_PERIPH2_CLK_SEL    21
-#define BM_CBCMR_PRE_PERIPH2_CLK_SEL    (0x3 << 21)
-#define BP_CBCMR_GPU2D_CORE_PODF        23
-#define BM_CBCMR_GPU2D_CORE_PODF        (0x7 << 23)
-#define BP_CBCMR_GPU3D_CORE_PODF        26
-#define BM_CBCMR_GPU3D_CORE_PODF        (0x7 << 26)
-#define BP_CBCMR_GPU3D_SHADER_PODF      29
-#define BM_CBCMR_GPU3D_SHADER_PODF      (0x7 << 29)
-
-#define BP_CSCMR1_PERCLK_PODF           0
-#define BM_CSCMR1_PERCLK_PODF           (0x3f << 0)
-#define BP_CSCMR1_SSI1_SEL              10
-#define BM_CSCMR1_SSI1_SEL              (0x3 << 10)
-#define BP_CSCMR1_SSI2_SEL              12
-#define BM_CSCMR1_SSI2_SEL              (0x3 << 12)
-#define BP_CSCMR1_SSI3_SEL              14
-#define BM_CSCMR1_SSI3_SEL              (0x3 << 14)
-#define BP_CSCMR1_USDHC1_SEL            16
-#define BM_CSCMR1_USDHC1_SEL            (0x1 << 16)
-#define BP_CSCMR1_USDHC2_SEL            17
-#define BM_CSCMR1_USDHC2_SEL            (0x1 << 17)
-#define BP_CSCMR1_USDHC3_SEL            18
-#define BM_CSCMR1_USDHC3_SEL            (0x1 << 18)
-#define BP_CSCMR1_USDHC4_SEL            19
-#define BM_CSCMR1_USDHC4_SEL            (0x1 << 19)
-#define BP_CSCMR1_EMI_PODF              20
-#define BM_CSCMR1_EMI_PODF              (0x7 << 20)
-#define BP_CSCMR1_EMI_SLOW_PODF         23
-#define BM_CSCMR1_EMI_SLOW_PODF         (0x7 << 23)
-#define BP_CSCMR1_EMI_SEL               27
-#define BM_CSCMR1_EMI_SEL               (0x3 << 27)
-#define BP_CSCMR1_EMI_SLOW_SEL          29
-#define BM_CSCMR1_EMI_SLOW_SEL          (0x3 << 29)
-
-#define BP_CSCMR2_CAN_PODF              2
-#define BM_CSCMR2_CAN_PODF              (0x3f << 2)
-#define BM_CSCMR2_LDB_DI0_IPU_DIV       (0x1 << 10)
-#define BM_CSCMR2_LDB_DI1_IPU_DIV       (0x1 << 11)
-#define BP_CSCMR2_ESAI_SEL              19
-#define BM_CSCMR2_ESAI_SEL              (0x3 << 19)
-
-#define BP_CSCDR1_UART_PODF             0
-#define BM_CSCDR1_UART_PODF             (0x3f << 0)
-#define BP_CSCDR1_USDHC1_PODF           11
-#define BM_CSCDR1_USDHC1_PODF           (0x7 << 11)
-#define BP_CSCDR1_USDHC2_PODF           16
-#define BM_CSCDR1_USDHC2_PODF           (0x7 << 16)
-#define BP_CSCDR1_USDHC3_PODF           19
-#define BM_CSCDR1_USDHC3_PODF           (0x7 << 19)
-#define BP_CSCDR1_USDHC4_PODF           22
-#define BM_CSCDR1_USDHC4_PODF           (0x7 << 22)
-#define BP_CSCDR1_VPU_AXI_PODF          25
-#define BM_CSCDR1_VPU_AXI_PODF          (0x7 << 25)
-
-#define BP_CS1CDR_SSI1_PODF             0
-#define BM_CS1CDR_SSI1_PODF             (0x3f << 0)
-#define BP_CS1CDR_SSI1_PRED             6
-#define BM_CS1CDR_SSI1_PRED             (0x7 << 6)
-#define BP_CS1CDR_ESAI_PRED             9
-#define BM_CS1CDR_ESAI_PRED             (0x7 << 9)
-#define BP_CS1CDR_SSI3_PODF             16
-#define BM_CS1CDR_SSI3_PODF             (0x3f << 16)
-#define BP_CS1CDR_SSI3_PRED             22
-#define BM_CS1CDR_SSI3_PRED             (0x7 << 22)
-#define BP_CS1CDR_ESAI_PODF             25
-#define BM_CS1CDR_ESAI_PODF             (0x7 << 25)
-
-#define BP_CS2CDR_SSI2_PODF             0
-#define BM_CS2CDR_SSI2_PODF             (0x3f << 0)
-#define BP_CS2CDR_SSI2_PRED             6
-#define BM_CS2CDR_SSI2_PRED             (0x7 << 6)
-#define BP_CS2CDR_LDB_DI0_SEL           9
-#define BM_CS2CDR_LDB_DI0_SEL           (0x7 << 9)
-#define BP_CS2CDR_LDB_DI1_SEL           12
-#define BM_CS2CDR_LDB_DI1_SEL           (0x7 << 12)
-#define BP_CS2CDR_ENFC_SEL              16
-#define BM_CS2CDR_ENFC_SEL              (0x3 << 16)
-#define BP_CS2CDR_ENFC_PRED             18
-#define BM_CS2CDR_ENFC_PRED             (0x7 << 18)
-#define BP_CS2CDR_ENFC_PODF             21
-#define BM_CS2CDR_ENFC_PODF             (0x3f << 21)
-
-#define BP_CDCDR_ASRC_SERIAL_SEL        7
-#define BM_CDCDR_ASRC_SERIAL_SEL        (0x3 << 7)
-#define BP_CDCDR_ASRC_SERIAL_PODF       9
-#define BM_CDCDR_ASRC_SERIAL_PODF       (0x7 << 9)
-#define BP_CDCDR_ASRC_SERIAL_PRED       12
-#define BM_CDCDR_ASRC_SERIAL_PRED       (0x7 << 12)
-#define BP_CDCDR_SPDIF_SEL              20
-#define BM_CDCDR_SPDIF_SEL              (0x3 << 20)
-#define BP_CDCDR_SPDIF_PODF             22
-#define BM_CDCDR_SPDIF_PODF             (0x7 << 22)
-#define BP_CDCDR_SPDIF_PRED             25
-#define BM_CDCDR_SPDIF_PRED             (0x7 << 25)
-#define BP_CDCDR_HSI_TX_PODF            29
-#define BM_CDCDR_HSI_TX_PODF            (0x7 << 29)
-#define BP_CDCDR_HSI_TX_SEL             28
-#define BM_CDCDR_HSI_TX_SEL             (0x1 << 28)
-
-#define BP_CHSCCDR_IPU1_DI0_SEL         0
-#define BM_CHSCCDR_IPU1_DI0_SEL         (0x7 << 0)
-#define BP_CHSCCDR_IPU1_DI0_PRE_PODF    3
-#define BM_CHSCCDR_IPU1_DI0_PRE_PODF    (0x7 << 3)
-#define BP_CHSCCDR_IPU1_DI0_PRE_SEL     6
-#define BM_CHSCCDR_IPU1_DI0_PRE_SEL     (0x7 << 6)
-#define BP_CHSCCDR_IPU1_DI1_SEL         9
-#define BM_CHSCCDR_IPU1_DI1_SEL         (0x7 << 9)
-#define BP_CHSCCDR_IPU1_DI1_PRE_PODF    12
-#define BM_CHSCCDR_IPU1_DI1_PRE_PODF    (0x7 << 12)
-#define BP_CHSCCDR_IPU1_DI1_PRE_SEL     15
-#define BM_CHSCCDR_IPU1_DI1_PRE_SEL     (0x7 << 15)
-
-#define BP_CSCDR2_IPU2_DI0_SEL          0
-#define BM_CSCDR2_IPU2_DI0_SEL          (0x7)
-#define BP_CSCDR2_IPU2_DI0_PRE_PODF     3
-#define BM_CSCDR2_IPU2_DI0_PRE_PODF     (0x7 << 3)
-#define BP_CSCDR2_IPU2_DI0_PRE_SEL      6
-#define BM_CSCDR2_IPU2_DI0_PRE_SEL      (0x7 << 6)
-#define BP_CSCDR2_IPU2_DI1_SEL          9
-#define BM_CSCDR2_IPU2_DI1_SEL          (0x7 << 9)
-#define BP_CSCDR2_IPU2_DI1_PRE_PODF     12
-#define BM_CSCDR2_IPU2_DI1_PRE_PODF     (0x7 << 12)
-#define BP_CSCDR2_IPU2_DI1_PRE_SEL      15
-#define BM_CSCDR2_IPU2_DI1_PRE_SEL      (0x7 << 15)
-#define BP_CSCDR2_ECSPI_CLK_PODF        19
-#define BM_CSCDR2_ECSPI_CLK_PODF        (0x3f << 19)
-
-#define BP_CSCDR3_IPU1_HSP_SEL          9
-#define BM_CSCDR3_IPU1_HSP_SEL          (0x3 << 9)
-#define BP_CSCDR3_IPU1_HSP_PODF         11
-#define BM_CSCDR3_IPU1_HSP_PODF         (0x7 << 11)
-#define BP_CSCDR3_IPU2_HSP_SEL          14
-#define BM_CSCDR3_IPU2_HSP_SEL          (0x3 << 14)
-#define BP_CSCDR3_IPU2_HSP_PODF         16
-#define BM_CSCDR3_IPU2_HSP_PODF         (0x7 << 16)
-
-#define BM_CDHIPR_AXI_PODF_BUSY         (0x1 << 0)
-#define BM_CDHIPR_AHB_PODF_BUSY         (0x1 << 1)
-#define BM_CDHIPR_MMDC_CH1_PODF_BUSY    (0x1 << 2)
-#define BM_CDHIPR_PERIPH2_SEL_BUSY      (0x1 << 3)
-#define BM_CDHIPR_MMDC_CH0_PODF_BUSY    (0x1 << 4)
-#define BM_CDHIPR_PERIPH_SEL_BUSY       (0x1 << 5)
-#define BM_CDHIPR_ARM_PODF_BUSY         (0x1 << 16)
-
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-
-#define BP_CCOSR_CKO1_EN                7
-#define BP_CCOSR_CKO1_PODF              4
-#define BM_CCOSR_CKO1_PODF              (0x7 << 4)
-#define BP_CCOSR_CKO1_SEL               0
-#define BM_CCOSR_CKO1_SEL               (0xf << 0)
-
-#define FREQ_480M       480000000
-#define FREQ_528M       528000000
-#define FREQ_594M       594000000
-#define FREQ_650M       650000000
-#define FREQ_1300M      1300000000
-
-static struct clk pll1_sys;
-static struct clk pll2_bus;
-static struct clk pll3_usb_otg;
-static struct clk pll4_audio;
-static struct clk pll5_video;
-static struct clk pll6_mlb;
-static struct clk pll7_usb_host;
-static struct clk pll8_enet;
-static struct clk apbh_dma_clk;
-static struct clk arm_clk;
-static struct clk ipg_clk;
-static struct clk ahb_clk;
-static struct clk axi_clk;
-static struct clk mmdc_ch0_axi_clk;
-static struct clk mmdc_ch1_axi_clk;
-static struct clk periph_clk;
-static struct clk periph_pre_clk;
-static struct clk periph_clk2_clk;
-static struct clk periph2_clk;
-static struct clk periph2_pre_clk;
-static struct clk periph2_clk2_clk;
-static struct clk gpu2d_core_clk;
-static struct clk gpu3d_core_clk;
-static struct clk gpu3d_shader_clk;
-static struct clk ipg_perclk;
-static struct clk emi_clk;
-static struct clk emi_slow_clk;
-static struct clk can1_clk;
-static struct clk uart_clk;
-static struct clk usdhc1_clk;
-static struct clk usdhc2_clk;
-static struct clk usdhc3_clk;
-static struct clk usdhc4_clk;
-static struct clk vpu_clk;
-static struct clk hsi_tx_clk;
-static struct clk ipu1_di0_pre_clk;
-static struct clk ipu1_di1_pre_clk;
-static struct clk ipu2_di0_pre_clk;
-static struct clk ipu2_di1_pre_clk;
-static struct clk ipu1_clk;
-static struct clk ipu2_clk;
-static struct clk ssi1_clk;
-static struct clk ssi3_clk;
-static struct clk esai_clk;
-static struct clk ssi2_clk;
-static struct clk spdif_clk;
-static struct clk asrc_serial_clk;
-static struct clk gpu2d_axi_clk;
-static struct clk gpu3d_axi_clk;
-static struct clk pcie_clk;
-static struct clk vdo_axi_clk;
-static struct clk ldb_di0_clk;
-static struct clk ldb_di1_clk;
-static struct clk ipu1_di0_clk;
-static struct clk ipu1_di1_clk;
-static struct clk ipu2_di0_clk;
-static struct clk ipu2_di1_clk;
-static struct clk enfc_clk;
-static struct clk cko1_clk;
-static struct clk dummy_clk = {};
-
-static unsigned long external_high_reference;
-static unsigned long external_low_reference;
-static unsigned long oscillator_reference;
-
-static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
-{
-        return oscillator_reference;
-}
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-        return external_high_reference;
-}
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-        return external_low_reference;
-}
-
-static struct clk ckil_clk = {
-        .get_rate = get_low_reference_clock_rate,
-};
-
-static struct clk ckih_clk = {
-        .get_rate = get_high_reference_clock_rate,
-};
-
-static struct clk osc_clk = {
-        .get_rate = get_oscillator_reference_clock_rate,
-};
-
-static inline void __iomem *pll_get_reg_addr(struct clk *pll)
-{
-        if (pll == &pll1_sys)
-                return PLL1_SYS;
-        else if (pll == &pll2_bus)
-                return PLL2_BUS;
-        else if (pll == &pll3_usb_otg)
-                return PLL3_USB_OTG;
-        else if (pll == &pll4_audio)
-                return PLL4_AUDIO;
-        else if (pll == &pll5_video)
-                return PLL5_VIDEO;
-        else if (pll == &pll6_mlb)
-                return PLL6_MLB;
-        else if (pll == &pll7_usb_host)
-                return PLL7_USB_HOST;
-        else if (pll == &pll8_enet)
-                return PLL8_ENET;
-        else
-                BUG();
-
-        return NULL;
-}
-
-static int pll_enable(struct clk *clk)
-{
-        int timeout = 0x100000;
-        void __iomem *reg;
-        u32 val;
-
-        reg = pll_get_reg_addr(clk);
-        val = readl_relaxed(reg);
-        val &= ~BM_PLL_BYPASS;
-        val &= ~BM_PLL_POWER_DOWN;
-        /* 480MHz PLLs have the opposite definition for power bit */
-        if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
-                val |= BM_PLL_POWER_DOWN;
-        writel_relaxed(val, reg);
-
-        /* Wait for PLL to lock */
-        while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                return -EBUSY;
-
-        /* Enable the PLL output now */
-        val = readl_relaxed(reg);
-        val |= BM_PLL_ENABLE;
-        writel_relaxed(val, reg);
-
-        return 0;
-}
-
-static void pll_disable(struct clk *clk)
-{
-        void __iomem *reg;
-        u32 val;
-
-        reg = pll_get_reg_addr(clk);
-        val = readl_relaxed(reg);
-        val &= ~BM_PLL_ENABLE;
-        val |= BM_PLL_BYPASS;
-        val |= BM_PLL_POWER_DOWN;
-        if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
-                val &= ~BM_PLL_POWER_DOWN;
-        writel_relaxed(val, reg);
-}
-
-static unsigned long pll1_sys_get_rate(struct clk *clk)
-{
-        u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
-                  BP_PLL_SYS_DIV_SELECT;
-
-        return clk_get_rate(clk->parent) * div / 2;
-}
-
-static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 val, div;
-
-        if (rate < FREQ_650M || rate > FREQ_1300M)
-                return -EINVAL;
-
-        div = rate * 2 / clk_get_rate(clk->parent);
-        val = readl_relaxed(PLL1_SYS);
-        val &= ~BM_PLL_SYS_DIV_SELECT;
-        val |= div << BP_PLL_SYS_DIV_SELECT;
-        writel_relaxed(val, PLL1_SYS);
-
-        return 0;
-}
-
-static unsigned long pll8_enet_get_rate(struct clk *clk)
-{
-        u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
-                  BP_PLL_ENET_DIV_SELECT;
-
-        switch (div) {
-        case 0:
-                return 25000000;
-        case 1:
-                return 50000000;
-        case 2:
-                return 100000000;
-        case 3:
-                return 125000000;
-        }
-
-        return 0;
-}
-
-static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 val, div;
-
-        switch (rate) {
-        case 25000000:
-                div = 0;
-                break;
-        case 50000000:
-                div = 1;
-                break;
-        case 100000000:
-                div = 2;
-                break;
-        case 125000000:
-                div = 3;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        val = readl_relaxed(PLL8_ENET);
-        val &= ~BM_PLL_ENET_DIV_SELECT;
-        val |= div << BP_PLL_ENET_DIV_SELECT;
-        writel_relaxed(val, PLL8_ENET);
-
-        return 0;
-}
-
-static unsigned long pll_av_get_rate(struct clk *clk)
-{
-        void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
-        u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
-        u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
-                  BP_PLL_AV_DIV_SELECT;
-
-        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
-}
-
-static int pll_av_set_rate(struct clk *clk, unsigned long rate)
-{
-        void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
-        unsigned int parent_rate = clk_get_rate(clk->parent);
-        u32 val, div;
-        u32 mfn, mfd = 1000000;
-        s64 temp64;
-
-        if (rate < FREQ_650M || rate > FREQ_1300M)
-                return -EINVAL;
-
-        div = rate / parent_rate;
-        temp64 = (u64) (rate - div * parent_rate);
-        temp64 *= mfd;
-        do_div(temp64, parent_rate);
-        mfn = temp64;
-
-        val = readl_relaxed(reg);
-        val &= ~BM_PLL_AV_DIV_SELECT;
-        val |= div << BP_PLL_AV_DIV_SELECT;
-        writel_relaxed(val, reg);
-        writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
-        writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);
-
-        return 0;
-}
-
-static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
-{
-        void __iomem *reg;
-
-        if (clk == &pll2_bus) {
-                reg = PLL2_BUS;
-                *bp = BP_PLL_BUS_DIV_SELECT;
-                *bm = BM_PLL_BUS_DIV_SELECT;
-        } else if (clk == &pll3_usb_otg) {
-                reg = PLL3_USB_OTG;
-                *bp = BP_PLL_USB_DIV_SELECT;
-                *bm = BM_PLL_USB_DIV_SELECT;
-        } else if (clk == &pll7_usb_host) {
-                reg = PLL7_USB_HOST;
-                *bp = BP_PLL_USB_DIV_SELECT;
-                *bm = BM_PLL_USB_DIV_SELECT;
-        } else {
-                BUG();
-        }
-
-        return reg;
-}
-
-static unsigned long pll_get_rate(struct clk *clk)
-{
-        void __iomem *reg;
-        u32 div, bp, bm;
-
-        reg = pll_get_div_reg_bit(clk, &bp, &bm);
-        div = (readl_relaxed(reg) & bm) >> bp;
-
-        return (div == 1) ? clk_get_rate(clk->parent) * 22 :
-                            clk_get_rate(clk->parent) * 20;
-}
-
-static int pll_set_rate(struct clk *clk, unsigned long rate)
-{
-        void __iomem *reg;
-        u32 val, div, bp, bm;
-
-        if (rate == FREQ_528M)
-                div = 1;
-        else if (rate == FREQ_480M)
-                div = 0;
-        else
-                return -EINVAL;
-
-        reg = pll_get_div_reg_bit(clk, &bp, &bm);
-        val = readl_relaxed(reg);
-        val &= ~bm;
-        val |= div << bp;
-        writel_relaxed(val, reg);
-
-        return 0;
-}
-
-#define pll2_bus_get_rate       pll_get_rate
-#define pll2_bus_set_rate       pll_set_rate
-#define pll3_usb_otg_get_rate   pll_get_rate
-#define pll3_usb_otg_set_rate   pll_set_rate
-#define pll7_usb_host_get_rate  pll_get_rate
-#define pll7_usb_host_set_rate  pll_set_rate
-#define pll4_audio_get_rate     pll_av_get_rate
-#define pll4_audio_set_rate     pll_av_set_rate
-#define pll5_video_get_rate     pll_av_get_rate
-#define pll5_video_set_rate     pll_av_set_rate
-#define pll6_mlb_get_rate       NULL
-#define pll6_mlb_set_rate       NULL
-
-#define DEF_PLL(name)                                   \
-        static struct clk name = {                      \
-                .enable         = pll_enable,           \
-                .disable        = pll_disable,          \
-                .get_rate       = name##_get_rate,      \
-                .set_rate       = name##_set_rate,      \
-                .parent         = &osc_clk,             \
-        }
-
-DEF_PLL(pll1_sys);
-DEF_PLL(pll2_bus);
-DEF_PLL(pll3_usb_otg);
-DEF_PLL(pll4_audio);
-DEF_PLL(pll5_video);
-DEF_PLL(pll6_mlb);
-DEF_PLL(pll7_usb_host);
-DEF_PLL(pll8_enet);
-
-static unsigned long pfd_get_rate(struct clk *clk)
-{
-        u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
-        u32 frac, bp_frac;
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.enable(&apbh_dma_clk);
-
-        bp_frac = clk->enable_shift - 7;
-        frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
-        do_div(tmp, frac);
-
-        return tmp;
-}
-
-static int pfd_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 val, frac, bp_frac;
-        u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.enable(&apbh_dma_clk);
-
-        /*
-         * Round up the divider so that we don't set a rate
-         * higher than what is requested
-         */
-        tmp += rate / 2;
-        do_div(tmp, rate);
-        frac = tmp;
-        frac = (frac < 12) ? 12 : frac;
-        frac = (frac > 35) ? 35 : frac;
-
-        /*
-         * The frac field always starts from 7 bits lower
-         * position of enable bit
-         */
-        bp_frac = clk->enable_shift - 7;
-        val = readl_relaxed(clk->enable_reg);
-        val &= ~(PFD_FRAC_MASK << bp_frac);
-        val |= frac << bp_frac;
-        writel_relaxed(val, clk->enable_reg);
-
-        tmp = (u64) clk_get_rate(clk->parent) * 18;
-        do_div(tmp, frac);
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.disable(&apbh_dma_clk);
-
-        return 0;
-}
-
-static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
-{
-        u32 frac;
-        u64 tmp;
-
-        tmp = (u64) clk_get_rate(clk->parent) * 18;
-        tmp += rate / 2;
-        do_div(tmp, rate);
-        frac = tmp;
-        frac = (frac < 12) ? 12 : frac;
-        frac = (frac > 35) ? 35 : frac;
-        tmp = (u64) clk_get_rate(clk->parent) * 18;
-        do_div(tmp, frac);
-
-        return tmp;
-}
-
-static int pfd_enable(struct clk *clk)
-{
-        u32 val;
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.enable(&apbh_dma_clk);
-
-        val = readl_relaxed(clk->enable_reg);
-        val &= ~(1 << clk->enable_shift);
-        writel_relaxed(val, clk->enable_reg);
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.disable(&apbh_dma_clk);
-
-        return 0;
-}
-
-static void pfd_disable(struct clk *clk)
-{
-        u32 val;
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.enable(&apbh_dma_clk);
-
-        val = readl_relaxed(clk->enable_reg);
-        val |= 1 << clk->enable_shift;
-        writel_relaxed(val, clk->enable_reg);
-
-        if (apbh_dma_clk.usecount == 0)
-                apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
-#define DEF_PFD(name, er, es, p)                        \
-        static struct clk name = {                      \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .enable         = pfd_enable,           \
-                .disable        = pfd_disable,          \
-                .get_rate       = pfd_get_rate,         \
-                .set_rate       = pfd_set_rate,         \
-                .round_rate     = pfd_round_rate,       \
-                .parent         = p,                    \
-        }
-
-DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
-DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
-DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
-DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
-
-static unsigned long twd_clk_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk twd_clk = {
-        .parent = &arm_clk,
-        .get_rate = twd_clk_get_rate,
-};
-
-static unsigned long pll2_200m_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk pll2_200m = {
-        .parent = &pll2_pfd_400m,
-        .get_rate = pll2_200m_get_rate,
-};
-
-static unsigned long pll3_120m_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 4;
-}
-
-static struct clk pll3_120m = {
-        .parent = &pll3_usb_otg,
-        .get_rate = pll3_120m_get_rate,
-};
-
-static unsigned long pll3_80m_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 6;
-}
-
-static struct clk pll3_80m = {
-        .parent = &pll3_usb_otg,
-        .get_rate = pll3_80m_get_rate,
-};
-
-static unsigned long pll3_60m_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 8;
-}
-
-static struct clk pll3_60m = {
-        .parent = &pll3_usb_otg,
-        .get_rate = pll3_60m_get_rate,
-};
-
-static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 val = readl_relaxed(CCSR);
-
-        if (parent == &pll1_sys) {
-                val &= ~BM_CCSR_PLL1_SW_SEL;
-                val &= ~BM_CCSR_STEP_SEL;
-        } else if (parent == &osc_clk) {
-                val |= BM_CCSR_PLL1_SW_SEL;
-                val &= ~BM_CCSR_STEP_SEL;
-        } else if (parent == &pll2_pfd_400m) {
-                val |= BM_CCSR_PLL1_SW_SEL;
-                val |= BM_CCSR_STEP_SEL;
-        } else {
-                return -EINVAL;
-        }
-
-        writel_relaxed(val, CCSR);
-
-        return 0;
-}
-
-static struct clk pll1_sw_clk = {
-        .parent = &pll1_sys,
-        .set_parent = pll1_sw_clk_set_parent,
-};
-
-static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
-{
-        u32 min_pred, temp_pred, old_err, err;
-
-        if (div >= 512) {
-                *pred = 8;
-                *podf = 64;
-        } else if (div >= 8) {
-                min_pred = (div - 1) / 64 + 1;
-                old_err = 8;
-                for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
-                        err = div % temp_pred;
-                        if (err == 0) {
-                                *pred = temp_pred;
-                                break;
-                        }
-                        err = temp_pred - err;
-                        if (err < old_err) {
-                                old_err = err;
-                                *pred = temp_pred;
-                        }
-                }
-                *podf = (div + *pred - 1) / *pred;
-        } else if (div < 8) {
-                *pred = div;
-                *podf = 1;
-        }
-}
-
-static int _clk_enable(struct clk *clk)
-{
-        u32 reg;
-        reg = readl_relaxed(clk->enable_reg);
-        reg |= 0x3 << clk->enable_shift;
-        writel_relaxed(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-        u32 reg;
-        reg = readl_relaxed(clk->enable_reg);
-        reg &= ~(0x3 << clk->enable_shift);
-        writel_relaxed(reg, clk->enable_reg);
-}
-
-static int _clk_enable_1b(struct clk *clk)
-{
-        u32 reg;
-        reg = readl_relaxed(clk->enable_reg);
-        reg |= 0x1 << clk->enable_shift;
-        writel_relaxed(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void _clk_disable_1b(struct clk *clk)
-{
-        u32 reg;
-        reg = readl_relaxed(clk->enable_reg);
-        reg &= ~(0x1 << clk->enable_shift);
-        writel_relaxed(reg, clk->enable_reg);
-}
-
-struct divider {
-        struct clk *clk;
-        void __iomem *reg;
-        u32 bp_pred;
-        u32 bm_pred;
-        u32 bp_podf;
-        u32 bm_podf;
-};
-
-#define DEF_CLK_DIV1(d, c, r, b)                                \
-        static struct divider d = {                             \
-                .clk = c,                                       \
-                .reg = r,                                       \
-                .bp_podf = BP_##r##_##b##_PODF,                 \
-                .bm_podf = BM_##r##_##b##_PODF,                 \
-        }
-
-DEF_CLK_DIV1(arm_div,           &arm_clk,               CACRR,  ARM);
-DEF_CLK_DIV1(ipg_div,           &ipg_clk,               CBCDR,  IPG);
-DEF_CLK_DIV1(ahb_div,           &ahb_clk,               CBCDR,  AHB);
-DEF_CLK_DIV1(axi_div,           &axi_clk,               CBCDR,  AXI);
-DEF_CLK_DIV1(mmdc_ch0_axi_div,  &mmdc_ch0_axi_clk,      CBCDR,  MMDC_CH0_AXI);
-DEF_CLK_DIV1(mmdc_ch1_axi_div,  &mmdc_ch1_axi_clk,      CBCDR,  MMDC_CH1_AXI);
-DEF_CLK_DIV1(periph_clk2_div,   &periph_clk2_clk,       CBCDR,  PERIPH_CLK2);
-DEF_CLK_DIV1(periph2_clk2_div,  &periph2_clk2_clk,      CBCDR,  PERIPH2_CLK2);
-DEF_CLK_DIV1(gpu2d_core_div,    &gpu2d_core_clk,        CBCMR,  GPU2D_CORE);
-DEF_CLK_DIV1(gpu3d_core_div,    &gpu3d_core_clk,        CBCMR,  GPU3D_CORE);
-DEF_CLK_DIV1(gpu3d_shader_div,  &gpu3d_shader_clk,      CBCMR,  GPU3D_SHADER);
-DEF_CLK_DIV1(ipg_perclk_div,    &ipg_perclk,            CSCMR1, PERCLK);
-DEF_CLK_DIV1(emi_div,           &emi_clk,               CSCMR1, EMI);
-DEF_CLK_DIV1(emi_slow_div,      &emi_slow_clk,          CSCMR1, EMI_SLOW);
-DEF_CLK_DIV1(can_div,           &can1_clk,              CSCMR2, CAN);
-DEF_CLK_DIV1(uart_div,          &uart_clk,              CSCDR1, UART);
-DEF_CLK_DIV1(usdhc1_div,        &usdhc1_clk,            CSCDR1, USDHC1);
-DEF_CLK_DIV1(usdhc2_div,        &usdhc2_clk,            CSCDR1, USDHC2);
-DEF_CLK_DIV1(usdhc3_div,        &usdhc3_clk,            CSCDR1, USDHC3);
-DEF_CLK_DIV1(usdhc4_div,        &usdhc4_clk,            CSCDR1, USDHC4);
-DEF_CLK_DIV1(vpu_div,           &vpu_clk,               CSCDR1, VPU_AXI);
-DEF_CLK_DIV1(hsi_tx_div,        &hsi_tx_clk,            CDCDR,  HSI_TX);
-DEF_CLK_DIV1(ipu1_di0_pre_div,  &ipu1_di0_pre_clk,      CHSCCDR, IPU1_DI0_PRE);
-DEF_CLK_DIV1(ipu1_di1_pre_div,  &ipu1_di1_pre_clk,      CHSCCDR, IPU1_DI1_PRE);
-DEF_CLK_DIV1(ipu2_di0_pre_div,  &ipu2_di0_pre_clk,      CSCDR2, IPU2_DI0_PRE);
-DEF_CLK_DIV1(ipu2_di1_pre_div,  &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
-DEF_CLK_DIV1(ipu1_div,          &ipu1_clk,              CSCDR3, IPU1_HSP);
-DEF_CLK_DIV1(ipu2_div,          &ipu2_clk,              CSCDR3, IPU2_HSP);
-DEF_CLK_DIV1(cko1_div,          &cko1_clk,              CCOSR, CKO1);
-
-#define DEF_CLK_DIV2(d, c, r, b)                                \
-        static struct divider d = {                             \
-                .clk = c,                                       \
-                .reg = r,                                       \
-                .bp_pred = BP_##r##_##b##_PRED,                 \
-                .bm_pred = BM_##r##_##b##_PRED,                 \
-                .bp_podf = BP_##r##_##b##_PODF,                 \
-                .bm_podf = BM_##r##_##b##_PODF,                 \
-        }
-
-DEF_CLK_DIV2(ssi1_div,          &ssi1_clk,              CS1CDR, SSI1);
-DEF_CLK_DIV2(ssi3_div,          &ssi3_clk,              CS1CDR, SSI3);
-DEF_CLK_DIV2(esai_div,          &esai_clk,              CS1CDR, ESAI);
-DEF_CLK_DIV2(ssi2_div,          &ssi2_clk,              CS2CDR, SSI2);
-DEF_CLK_DIV2(enfc_div,          &enfc_clk,              CS2CDR, ENFC);
-DEF_CLK_DIV2(spdif_div,         &spdif_clk,             CDCDR,  SPDIF);
-DEF_CLK_DIV2(asrc_serial_div,   &asrc_serial_clk,       CDCDR,  ASRC_SERIAL);
-
-static struct divider *dividers[] = {
-        &arm_div,
-        &ipg_div,
-        &ahb_div,
-        &axi_div,
-        &mmdc_ch0_axi_div,
-        &mmdc_ch1_axi_div,
-        &periph_clk2_div,
-        &periph2_clk2_div,
-        &gpu2d_core_div,
-        &gpu3d_core_div,
-        &gpu3d_shader_div,
-        &ipg_perclk_div,
-        &emi_div,
-        &emi_slow_div,
-        &can_div,
-        &uart_div,
-        &usdhc1_div,
-        &usdhc2_div,
-        &usdhc3_div,
-        &usdhc4_div,
-        &vpu_div,
-        &hsi_tx_div,
-        &ipu1_di0_pre_div,
-        &ipu1_di1_pre_div,
-        &ipu2_di0_pre_div,
-        &ipu2_di1_pre_div,
-        &ipu1_div,
-        &ipu2_div,
-        &ssi1_div,
-        &ssi3_div,
-        &esai_div,
-        &ssi2_div,
-        &enfc_div,
-        &spdif_div,
-        &asrc_serial_div,
-        &cko1_div,
-};
-
-static unsigned long ldb_di_clk_get_rate(struct clk *clk)
-{
-        u32 val = readl_relaxed(CSCMR2);
-
-        val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
-                                       BM_CSCMR2_LDB_DI1_IPU_DIV;
-        if (val)
-                return clk_get_rate(clk->parent) / 7;
-        else
-                return clk_get_rate(clk->parent) * 2 / 7;
-}
-
-static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        u32 val = readl_relaxed(CSCMR2);
-
-        if (rate * 7 <= parent_rate + parent_rate / 20)
-                val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
-        else
-                val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;
-
-        writel_relaxed(val, CSCMR2);
-
-        return 0;
-}
-
-static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-
-        if (rate * 7 <= parent_rate + parent_rate / 20)
-                return parent_rate / 7;
-        else
-                return 2 * parent_rate / 7;
-}
-
-static unsigned long _clk_get_rate(struct clk *clk)
-{
-        struct divider *d;
-        u32 val, pred, podf;
-        int i, num;
-
-        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-                return ldb_di_clk_get_rate(clk);
-
-        num = ARRAY_SIZE(dividers);
-        for (i = 0; i < num; i++)
-                if (dividers[i]->clk == clk) {
-                        d = dividers[i];
-                        break;
-                }
-        if (i == num)
-                return clk_get_rate(clk->parent);
-
-        val = readl_relaxed(d->reg);
-        pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
-        podf = ((val & d->bm_podf) >> d->bp_podf) + 1;
-
-        return clk_get_rate(clk->parent) / (pred * podf);
-}
-
-static int clk_busy_wait(struct clk *clk)
-{
-        int timeout = 0x100000;
-        u32 bm;
-
-        if (clk == &axi_clk)
-                bm = BM_CDHIPR_AXI_PODF_BUSY;
-        else if (clk == &ahb_clk)
-                bm = BM_CDHIPR_AHB_PODF_BUSY;
-        else if (clk == &mmdc_ch0_axi_clk)
-                bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
-        else if (clk == &periph_clk)
-                bm = BM_CDHIPR_PERIPH_SEL_BUSY;
-        else if (clk == &arm_clk)
-                bm = BM_CDHIPR_ARM_PODF_BUSY;
-        else
-                return -EINVAL;
-
-        while ((readl_relaxed(CDHIPR) & bm) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                return -EBUSY;
-
-        return 0;
-}
-
-static int _clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        struct divider *d;
-        u32 val, div, max_div, pred = 0, podf;
-        int i, num;
-
-        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-                return ldb_di_clk_set_rate(clk, rate);
-
-        num = ARRAY_SIZE(dividers);
-        for (i = 0; i < num; i++)
-                if (dividers[i]->clk == clk) {
-                        d = dividers[i];
-                        break;
-                }
-        if (i == num)
-                return -EINVAL;
-
-        max_div = ((d->bm_pred >> d->bp_pred) + 1) *
-                  ((d->bm_podf >> d->bp_podf) + 1);
-
-        div = parent_rate / rate;
-        if (div == 0)
-                div++;
-
-        if ((parent_rate / div != rate) || div > max_div)
-                return -EINVAL;
-
-        if (d->bm_pred) {
-                calc_pred_podf_dividers(div, &pred, &podf);
-        } else {
-                pred = 1;
-                podf = div;
-        }
-
-        val = readl_relaxed(d->reg);
-        val &= ~(d->bm_pred | d->bm_podf);
-        val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
-        writel_relaxed(val, d->reg);
-
-        if (clk == &axi_clk || clk == &ahb_clk ||
-            clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
-                return clk_busy_wait(clk);
-
-        return 0;
-}
-
-static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        u32 div = parent_rate / rate;
-        u32 div_max, pred = 0, podf;
-        struct divider *d;
-        int i, num;
-
-        if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-                return ldb_di_clk_round_rate(clk, rate);
-
-        num = ARRAY_SIZE(dividers);
-        for (i = 0; i < num; i++)
-                if (dividers[i]->clk == clk) {
-                        d = dividers[i];
-                        break;
-                }
-        if (i == num)
-                return -EINVAL;
-
-        if (div == 0 || parent_rate % rate)
-                div++;
-
-        if (d->bm_pred) {
-                calc_pred_podf_dividers(div, &pred, &podf);
-                div = pred * podf;
-        } else {
-                div_max = (d->bm_podf >> d->bp_podf) + 1;
-                if (div > div_max)
-                        div = div_max;
-        }
-
-        return parent_rate / div;
-}
-
-struct multiplexer {
-        struct clk *clk;
-        void __iomem *reg;
-        u32 bp;
-        u32 bm;
-        int pnum;
-        struct clk *parents[];
-};
-
-static struct multiplexer axi_mux = {
-        .clk = &axi_clk,
-        .reg = CBCDR,
-        .bp = BP_CBCDR_AXI_SEL,
-        .bm = BM_CBCDR_AXI_SEL,
-        .parents = {
-                &periph_clk,
-                &pll2_pfd_400m,
-                &pll3_pfd_540m,
-                NULL
-        },
-};
-
-static struct multiplexer periph_mux = {
-        .clk = &periph_clk,
-        .reg = CBCDR,
-        .bp = BP_CBCDR_PERIPH_CLK_SEL,
-        .bm = BM_CBCDR_PERIPH_CLK_SEL,
-        .parents = {
-                &periph_pre_clk,
-                &periph_clk2_clk,
-                NULL
-        },
-};
-
-static struct multiplexer periph_pre_mux = {
-        .clk = &periph_pre_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
-        .bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
-        .parents = {
-                &pll2_bus,
-                &pll2_pfd_400m,
-                &pll2_pfd_352m,
-                &pll2_200m,
-                NULL
-        },
-};
-
-static struct multiplexer periph_clk2_mux = {
-        .clk = &periph_clk2_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_PERIPH_CLK2_SEL,
-        .bm = BM_CBCMR_PERIPH_CLK2_SEL,
-        .parents = {
-                &pll3_usb_otg,
-                &osc_clk,
-                NULL
-        },
-};
-
-static struct multiplexer periph2_mux = {
-        .clk = &periph2_clk,
-        .reg = CBCDR,
-        .bp = BP_CBCDR_PERIPH2_CLK_SEL,
-        .bm = BM_CBCDR_PERIPH2_CLK_SEL,
-        .parents = {
-                &periph2_pre_clk,
-                &periph2_clk2_clk,
-                NULL
-        },
-};
-
-static struct multiplexer periph2_pre_mux = {
-        .clk = &periph2_pre_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
-        .bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
-        .parents = {
-                &pll2_bus,
-                &pll2_pfd_400m,
-                &pll2_pfd_352m,
-                &pll2_200m,
-                NULL
-        },
-};
-
-static struct multiplexer periph2_clk2_mux = {
-        .clk = &periph2_clk2_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_PERIPH2_CLK2_SEL,
-        .bm = BM_CBCMR_PERIPH2_CLK2_SEL,
-        .parents = {
-                &pll3_usb_otg,
-                &osc_clk,
-                NULL
-        },
-};
-
-static struct multiplexer gpu2d_axi_mux = {
-        .clk = &gpu2d_axi_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_GPU2D_AXI_SEL,
-        .bm = BM_CBCMR_GPU2D_AXI_SEL,
-        .parents = {
-                &axi_clk,
-                &ahb_clk,
-                NULL
-        },
-};
-
-static struct multiplexer gpu3d_axi_mux = {
-        .clk = &gpu3d_axi_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_GPU3D_AXI_SEL,
-        .bm = BM_CBCMR_GPU3D_AXI_SEL,
-        .parents = {
-                &axi_clk,
-                &ahb_clk,
-                NULL
-        },
-};
-
-static struct multiplexer gpu3d_core_mux = {
-        .clk = &gpu3d_core_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_GPU3D_CORE_SEL,
-        .bm = BM_CBCMR_GPU3D_CORE_SEL,
-        .parents = {
-                &mmdc_ch0_axi_clk,
-                &pll3_usb_otg,
-                &pll2_pfd_594m,
-                &pll2_pfd_400m,
-                NULL
-        },
-};
-
-static struct multiplexer gpu3d_shader_mux = {
-        .clk = &gpu3d_shader_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_GPU3D_SHADER_SEL,
-        .bm = BM_CBCMR_GPU3D_SHADER_SEL,
-        .parents = {
-                &mmdc_ch0_axi_clk,
-                &pll3_usb_otg,
-                &pll2_pfd_594m,
-                &pll3_pfd_720m,
-                NULL
-        },
-};
-
-static struct multiplexer pcie_axi_mux = {
-        .clk = &pcie_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_PCIE_AXI_SEL,
-        .bm = BM_CBCMR_PCIE_AXI_SEL,
-        .parents = {
-                &axi_clk,
-                &ahb_clk,
-                NULL
-        },
-};
-
-static struct multiplexer vdo_axi_mux = {
-        .clk = &vdo_axi_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_VDO_AXI_SEL,
-        .bm = BM_CBCMR_VDO_AXI_SEL,
-        .parents = {
-                &axi_clk,
-                &ahb_clk,
-                NULL
-        },
-};
-
-static struct multiplexer vpu_axi_mux = {
-        .clk = &vpu_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_VPU_AXI_SEL,
-        .bm = BM_CBCMR_VPU_AXI_SEL,
-        .parents = {
-                &axi_clk,
-                &pll2_pfd_400m,
-                &pll2_pfd_352m,
-                NULL
-        },
-};
-
-static struct multiplexer gpu2d_core_mux = {
-        .clk = &gpu2d_core_clk,
-        .reg = CBCMR,
-        .bp = BP_CBCMR_GPU2D_CORE_SEL,
-        .bm = BM_CBCMR_GPU2D_CORE_SEL,
-        .parents = {
-                &axi_clk,
-                &pll3_usb_otg,
-                &pll2_pfd_352m,
-                &pll2_pfd_400m,
-                NULL
-        },
-};
-
-#define DEF_SSI_MUX(id)                                                 \
-        static struct multiplexer ssi##id##_mux = {                     \
-                .clk = &ssi##id##_clk,                                  \
-                .reg = CSCMR1,                                          \
-                .bp = BP_CSCMR1_SSI##id##_SEL,                          \
-                .bm = BM_CSCMR1_SSI##id##_SEL,                          \
-                .parents = {                                            \
-                        &pll3_pfd_508m,                                 \
-                        &pll3_pfd_454m,                                 \
-                        &pll4_audio,                                    \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_SSI_MUX(1);
-DEF_SSI_MUX(2);
-DEF_SSI_MUX(3);
-
-#define DEF_USDHC_MUX(id)                                               \
-        static struct multiplexer usdhc##id##_mux = {                   \
-                .clk = &usdhc##id##_clk,                                \
-                .reg = CSCMR1,                                          \
-                .bp = BP_CSCMR1_USDHC##id##_SEL,                        \
-                .bm = BM_CSCMR1_USDHC##id##_SEL,                        \
-                .parents = {                                            \
-                        &pll2_pfd_400m,                                 \
-                        &pll2_pfd_352m,                                 \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_USDHC_MUX(1);
-DEF_USDHC_MUX(2);
-DEF_USDHC_MUX(3);
-DEF_USDHC_MUX(4);
-
-static struct multiplexer emi_mux = {
-        .clk = &emi_clk,
-        .reg = CSCMR1,
-        .bp = BP_CSCMR1_EMI_SEL,
-        .bm = BM_CSCMR1_EMI_SEL,
-        .parents = {
-                &axi_clk,
-                &pll3_usb_otg,
-                &pll2_pfd_400m,
-                &pll2_pfd_352m,
-                NULL
-        },
-};
-
-static struct multiplexer emi_slow_mux = {
-        .clk = &emi_slow_clk,
-        .reg = CSCMR1,
-        .bp = BP_CSCMR1_EMI_SLOW_SEL,
-        .bm = BM_CSCMR1_EMI_SLOW_SEL,
-        .parents = {
-                &axi_clk,
-                &pll3_usb_otg,
-                &pll2_pfd_400m,
-                &pll2_pfd_352m,
-                NULL
-        },
-};
-
-static struct multiplexer esai_mux = {
-        .clk = &esai_clk,
-        .reg = CSCMR2,
-        .bp = BP_CSCMR2_ESAI_SEL,
-        .bm = BM_CSCMR2_ESAI_SEL,
-        .parents = {
-                &pll4_audio,
-                &pll3_pfd_508m,
-                &pll3_pfd_454m,
-                &pll3_usb_otg,
-                NULL
-        },
-};
-
-#define DEF_LDB_DI_MUX(id)                                              \
-        static struct multiplexer ldb_di##id##_mux = {                  \
-                .clk = &ldb_di##id##_clk,                               \
-                .reg = CS2CDR,                                          \
-                .bp = BP_CS2CDR_LDB_DI##id##_SEL,                       \
-                .bm = BM_CS2CDR_LDB_DI##id##_SEL,                       \
-                .parents = {                                            \
-                        &pll5_video,                                    \
-                        &pll2_pfd_352m,                                 \
-                        &pll2_pfd_400m,                                 \
-                        &pll3_pfd_540m,                                 \
-                        &pll3_usb_otg,                                  \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_LDB_DI_MUX(0);
-DEF_LDB_DI_MUX(1);
-
-static struct multiplexer enfc_mux = {
-        .clk = &enfc_clk,
-        .reg = CS2CDR,
-        .bp = BP_CS2CDR_ENFC_SEL,
-        .bm = BM_CS2CDR_ENFC_SEL,
-        .parents = {
-                &pll2_pfd_352m,
-                &pll2_bus,
-                &pll3_usb_otg,
-                &pll2_pfd_400m,
-                NULL
-        },
-};
-
-static struct multiplexer spdif_mux = {
-        .clk = &spdif_clk,
-        .reg = CDCDR,
-        .bp = BP_CDCDR_SPDIF_SEL,
-        .bm = BM_CDCDR_SPDIF_SEL,
-        .parents = {
-                &pll4_audio,
-                &pll3_pfd_508m,
-                &pll3_pfd_454m,
-                &pll3_usb_otg,
-                NULL
-        },
-};
-
-static struct multiplexer asrc_serial_mux = {
-        .clk = &asrc_serial_clk,
-        .reg = CDCDR,
-        .bp = BP_CDCDR_ASRC_SERIAL_SEL,
-        .bm = BM_CDCDR_ASRC_SERIAL_SEL,
-        .parents = {
-                &pll4_audio,
-                &pll3_pfd_508m,
-                &pll3_pfd_454m,
-                &pll3_usb_otg,
-                NULL
-        },
-};
-
-static struct multiplexer hsi_tx_mux = {
-        .clk = &hsi_tx_clk,
-        .reg = CDCDR,
-        .bp = BP_CDCDR_HSI_TX_SEL,
-        .bm = BM_CDCDR_HSI_TX_SEL,
-        .parents = {
-                &pll3_120m,
-                &pll2_pfd_400m,
-                NULL
-        },
-};
-
-#define DEF_IPU_DI_PRE_MUX(r, i, d)                                     \
-        static struct multiplexer ipu##i##_di##d##_pre_mux = {          \
-                .clk = &ipu##i##_di##d##_pre_clk,                       \
-                .reg = r,                                               \
-                .bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,                \
-                .bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,                \
-                .parents = {                                            \
-                        &mmdc_ch0_axi_clk,                              \
-                        &pll3_usb_otg,                                  \
-                        &pll5_video,                                    \
-                        &pll2_pfd_352m,                                 \
-                        &pll2_pfd_400m,                                 \
-                        &pll3_pfd_540m,                                 \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
-DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
-DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
-DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);
-
-#define DEF_IPU_DI_MUX(r, i, d)                                         \
-        static struct multiplexer ipu##i##_di##d##_mux = {              \
-                .clk = &ipu##i##_di##d##_clk,                           \
-                .reg = r,                                               \
-                .bp = BP_##r##_IPU##i##_DI##d##_SEL,                    \
-                .bm = BM_##r##_IPU##i##_DI##d##_SEL,                    \
-                .parents = {                                            \
-                        &ipu##i##_di##d##_pre_clk,                      \
-                        &dummy_clk,                                     \
-                        &dummy_clk,                                     \
-                        &ldb_di0_clk,                                   \
-                        &ldb_di1_clk,                                   \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
-DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
-DEF_IPU_DI_MUX(CSCDR2, 2, 0);
-DEF_IPU_DI_MUX(CSCDR2, 2, 1);
-
-#define DEF_IPU_MUX(id)                                                 \
-        static struct multiplexer ipu##id##_mux = {                     \
-                .clk = &ipu##id##_clk,                                  \
-                .reg = CSCDR3,                                          \
-                .bp = BP_CSCDR3_IPU##id##_HSP_SEL,                      \
-                .bm = BM_CSCDR3_IPU##id##_HSP_SEL,                      \
-                .parents = {                                            \
-                        &mmdc_ch0_axi_clk,                              \
-                        &pll2_pfd_400m,                                 \
-                        &pll3_120m,                                     \
-                        &pll3_pfd_540m,                                 \
-                        NULL                                            \
-                },                                                      \
-        }
-
-DEF_IPU_MUX(1);
-DEF_IPU_MUX(2);
-
-static struct multiplexer cko1_mux = {
-        .clk = &cko1_clk,
-        .reg = CCOSR,
-        .bp = BP_CCOSR_CKO1_SEL,
-        .bm = BM_CCOSR_CKO1_SEL,
-        .parents = {
-                &pll3_usb_otg,
-                &pll2_bus,
-                &pll1_sys,
-                &pll5_video,
-                &dummy_clk,
-                &axi_clk,
-                &enfc_clk,
-                &ipu1_di0_clk,
-                &ipu1_di1_clk,
-                &ipu2_di0_clk,
-                &ipu2_di1_clk,
-                &ahb_clk,
-                &ipg_clk,
-                &ipg_perclk,
-                &ckil_clk,
-                &pll4_audio,
-                NULL
-        },
-};
-
-static struct multiplexer *multiplexers[] = {
-        &axi_mux,
-        &periph_mux,
-        &periph_pre_mux,
-        &periph_clk2_mux,
-        &periph2_mux,
-        &periph2_pre_mux,
-        &periph2_clk2_mux,
-        &gpu2d_axi_mux,
-        &gpu3d_axi_mux,
-        &gpu3d_core_mux,
-        &gpu3d_shader_mux,
-        &pcie_axi_mux,
-        &vdo_axi_mux,
-        &vpu_axi_mux,
-        &gpu2d_core_mux,
-        &ssi1_mux,
-        &ssi2_mux,
-        &ssi3_mux,
-        &usdhc1_mux,
-        &usdhc2_mux,
-        &usdhc3_mux,
-        &usdhc4_mux,
-        &emi_mux,
-        &emi_slow_mux,
-        &esai_mux,
-        &ldb_di0_mux,
-        &ldb_di1_mux,
-        &enfc_mux,
-        &spdif_mux,
-        &asrc_serial_mux,
-        &hsi_tx_mux,
-        &ipu1_di0_pre_mux,
-        &ipu1_di0_mux,
-        &ipu1_di1_pre_mux,
-        &ipu1_di1_mux,
-        &ipu2_di0_pre_mux,
-        &ipu2_di0_mux,
-        &ipu2_di1_pre_mux,
-        &ipu2_di1_mux,
-        &ipu1_mux,
-        &ipu2_mux,
-        &cko1_mux,
-};
-
-static int _clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        struct multiplexer *m;
-        int i, num;
-        u32 val;
-
-        num = ARRAY_SIZE(multiplexers);
-        for (i = 0; i < num; i++)
-                if (multiplexers[i]->clk == clk) {
-                        m = multiplexers[i];
-                        break;
-                }
-        if (i == num)
-                return -EINVAL;
-
-        i = 0;
-        while (m->parents[i]) {
-                if (parent == m->parents[i])
-                        break;
-                i++;
-        }
-        if (!m->parents[i] || m->parents[i] == &dummy_clk)
-                return -EINVAL;
-
-        val = readl_relaxed(m->reg);
-        val &= ~m->bm;
-        val |= i << m->bp;
-        writel_relaxed(val, m->reg);
-
-        if (clk == &periph_clk)
-                return clk_busy_wait(clk);
-
-        return 0;
-}
-
-#define DEF_NG_CLK(name, p)                             \
-        static struct clk name = {                      \
-                .get_rate       = _clk_get_rate,        \
-                .set_rate       = _clk_set_rate,        \
-                .round_rate     = _clk_round_rate,      \
-                .set_parent     = _clk_set_parent,      \
-                .parent         = p,                    \
-        }
-
-DEF_NG_CLK(periph_clk2_clk,     &osc_clk);
-DEF_NG_CLK(periph_pre_clk,      &pll2_bus);
-DEF_NG_CLK(periph_clk,          &periph_pre_clk);
-DEF_NG_CLK(periph2_clk2_clk,    &osc_clk);
-DEF_NG_CLK(periph2_pre_clk,     &pll2_bus);
-DEF_NG_CLK(periph2_clk,         &periph2_pre_clk);
-DEF_NG_CLK(axi_clk,             &periph_clk);
-DEF_NG_CLK(emi_clk,             &axi_clk);
-DEF_NG_CLK(arm_clk,             &pll1_sw_clk);
-DEF_NG_CLK(ahb_clk,             &periph_clk);
-DEF_NG_CLK(ipg_clk,             &ahb_clk);
-DEF_NG_CLK(ipg_perclk,          &ipg_clk);
-DEF_NG_CLK(ipu1_di0_pre_clk,    &pll3_pfd_540m);
-DEF_NG_CLK(ipu1_di1_pre_clk,    &pll3_pfd_540m);
-DEF_NG_CLK(ipu2_di0_pre_clk,    &pll3_pfd_540m);
-DEF_NG_CLK(ipu2_di1_pre_clk,    &pll3_pfd_540m);
-DEF_NG_CLK(asrc_serial_clk,     &pll3_usb_otg);
-
-#define DEF_CLK(name, er, es, p, s)                     \
-        static struct clk name = {                      \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .enable         = _clk_enable,          \
-                .disable        = _clk_disable,         \
-                .get_rate       = _clk_get_rate,        \
-                .set_rate       = _clk_set_rate,        \
-                .round_rate     = _clk_round_rate,      \
-                .set_parent     = _clk_set_parent,      \
-                .parent         = p,                    \
-                .secondary      = s,                    \
-        }
-
-#define DEF_CLK_1B(name, er, es, p, s)                  \
-        static struct clk name = {                      \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .enable         = _clk_enable_1b,       \
-                .disable        = _clk_disable_1b,      \
-                .get_rate       = _clk_get_rate,        \
-                .set_rate       = _clk_set_rate,        \
-                .round_rate     = _clk_round_rate,      \
-                .set_parent     = _clk_set_parent,      \
-                .parent         = p,                    \
-                .secondary      = s,                    \
-        }
-
-DEF_CLK(aips_tz1_clk,     CCGR0, CG0,  &ahb_clk,          NULL);
-DEF_CLK(aips_tz2_clk,     CCGR0, CG1,  &ahb_clk,          NULL);
-DEF_CLK(apbh_dma_clk,     CCGR0, CG2,  &ahb_clk,          NULL);
-DEF_CLK(asrc_clk,         CCGR0, CG3,  &pll4_audio,       NULL);
-DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,     NULL);
-DEF_CLK(can1_clk,         CCGR0, CG7,  &pll3_usb_otg,     &can1_serial_clk);
-DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,     NULL);
-DEF_CLK(can2_clk,         CCGR0, CG9,  &pll3_usb_otg,     &can2_serial_clk);
-DEF_CLK(ecspi1_clk,       CCGR1, CG0,  &pll3_60m,         NULL);
-DEF_CLK(ecspi2_clk,       CCGR1, CG1,  &pll3_60m,         NULL);
-DEF_CLK(ecspi3_clk,       CCGR1, CG2,  &pll3_60m,         NULL);
-DEF_CLK(ecspi4_clk,       CCGR1, CG3,  &pll3_60m,         NULL);
-DEF_CLK(ecspi5_clk,       CCGR1, CG4,  &pll3_60m,         NULL);
-DEF_CLK(enet_clk,         CCGR1, CG5,  &ipg_clk,          NULL);
-DEF_CLK(esai_clk,         CCGR1, CG8,  &pll3_usb_otg,     NULL);
-DEF_CLK(gpt_serial_clk,   CCGR1, CG11, &ipg_perclk,       NULL);
-DEF_CLK(gpt_clk,          CCGR1, CG10, &ipg_perclk,       &gpt_serial_clk);
-DEF_CLK(gpu2d_core_clk,   CCGR1, CG12, &pll2_pfd_352m,    &gpu2d_axi_clk);
-DEF_CLK(gpu3d_core_clk,   CCGR1, CG13, &pll2_pfd_594m,    &gpu3d_axi_clk);
-DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,    &gpu3d_axi_clk);
-DEF_CLK(hdmi_iahb_clk,    CCGR2, CG0,  &ahb_clk,          NULL);
-DEF_CLK(hdmi_isfr_clk,    CCGR2, CG2,  &pll3_pfd_540m,    &hdmi_iahb_clk);
-DEF_CLK(i2c1_clk,         CCGR2, CG3,  &ipg_perclk,       NULL);
-DEF_CLK(i2c2_clk,         CCGR2, CG4,  &ipg_perclk,       NULL);
-DEF_CLK(i2c3_clk,         CCGR2, CG5,  &ipg_perclk,       NULL);
-DEF_CLK(iim_clk,          CCGR2, CG6,  &ipg_clk,          NULL);
-DEF_CLK(enfc_clk,         CCGR2, CG7,  &pll2_pfd_352m,    NULL);
-DEF_CLK(ipu1_clk,         CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
-DEF_CLK(ipu1_di0_clk,     CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
-DEF_CLK(ipu1_di1_clk,     CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
-DEF_CLK(ipu2_clk,         CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
-DEF_CLK(ipu2_di0_clk,     CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
-DEF_CLK(ipu2_di1_clk,     CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
-DEF_CLK(ldb_di0_clk,      CCGR3, CG6,  &pll3_pfd_540m,    NULL);
-DEF_CLK(ldb_di1_clk,      CCGR3, CG7,  &pll3_pfd_540m,    NULL);
-DEF_CLK(hsi_tx_clk,       CCGR3, CG8,  &pll2_pfd_400m,    NULL);
-DEF_CLK(mlb_clk,          CCGR3, CG9,  &pll6_mlb,         NULL);
-DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,          NULL);
-DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,       &mmdc_ch0_ipg_clk);
-DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,          NULL);
-DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,      &mmdc_ch1_ipg_clk);
-DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,          NULL);
-DEF_CLK(pwm1_clk,         CCGR4, CG8,  &ipg_perclk,       NULL);
-DEF_CLK(pwm2_clk,         CCGR4, CG9,  &ipg_perclk,       NULL);
-DEF_CLK(pwm3_clk,         CCGR4, CG10, &ipg_perclk,       NULL);
-DEF_CLK(pwm4_clk,         CCGR4, CG11, &ipg_perclk,       NULL);
-DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,       NULL);
-DEF_CLK(gpmi_bch_clk,     CCGR4, CG13, &usdhc4_clk,       &gpmi_bch_apb_clk);
-DEF_CLK(gpmi_apb_clk,     CCGR4, CG15, &usdhc3_clk,       &gpmi_bch_clk);
-DEF_CLK(gpmi_io_clk,      CCGR4, CG14, &enfc_clk,         &gpmi_apb_clk);
-DEF_CLK(sdma_clk,         CCGR5, CG3,  &ahb_clk,          NULL);
-DEF_CLK(spba_clk,         CCGR5, CG6,  &ipg_clk,          NULL);
-DEF_CLK(spdif_clk,        CCGR5, CG7,  &pll3_usb_otg,     &spba_clk);
-DEF_CLK(ssi1_clk,         CCGR5, CG9,  &pll3_pfd_508m,    NULL);
-DEF_CLK(ssi2_clk,         CCGR5, CG10, &pll3_pfd_508m,    NULL);
-DEF_CLK(ssi3_clk,         CCGR5, CG11, &pll3_pfd_508m,    NULL);
-DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,     NULL);
-DEF_CLK(uart_clk,         CCGR5, CG12, &pll3_80m,         &uart_serial_clk);
-DEF_CLK(usboh3_clk,       CCGR6, CG0,  &ipg_clk,          NULL);
-DEF_CLK(usdhc1_clk,       CCGR6, CG1,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc2_clk,       CCGR6, CG2,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc3_clk,       CCGR6, CG3,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc4_clk,       CCGR6, CG4,  &pll2_pfd_400m,    NULL);
-DEF_CLK(emi_slow_clk,     CCGR6, CG5,  &axi_clk,          NULL);
-DEF_CLK(vdo_axi_clk,      CCGR6, CG6,  &axi_clk,          NULL);
-DEF_CLK(vpu_clk,          CCGR6, CG7,  &axi_clk,          NULL);
-DEF_CLK_1B(cko1_clk,      CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
-
-static int pcie_clk_enable(struct clk *clk)
-{
-        u32 val;
-
-        val = readl_relaxed(PLL8_ENET);
-        val |= BM_PLL_ENET_EN_PCIE;
-        writel_relaxed(val, PLL8_ENET);
-
-        return _clk_enable(clk);
-}
-
-static void pcie_clk_disable(struct clk *clk)
-{
-        u32 val;
-
-        _clk_disable(clk);
-
-        val = readl_relaxed(PLL8_ENET);
-        val &= BM_PLL_ENET_EN_PCIE;
-        writel_relaxed(val, PLL8_ENET);
-}
-
-static struct clk pcie_clk = {
-        .enable_reg = CCGR4,
-        .enable_shift = CG0,
-        .enable = pcie_clk_enable,
-        .disable = pcie_clk_disable,
-        .set_parent = _clk_set_parent,
-        .parent = &axi_clk,
-        .secondary = &pll8_enet,
-};
-
-static int sata_clk_enable(struct clk *clk)
-{
-        u32 val;
-
-        val = readl_relaxed(PLL8_ENET);
-        val |= BM_PLL_ENET_EN_SATA;
-        writel_relaxed(val, PLL8_ENET);
-
-        return _clk_enable(clk);
-}
-
-static void sata_clk_disable(struct clk *clk)
-{
-        u32 val;
-
-        _clk_disable(clk);
-
-        val = readl_relaxed(PLL8_ENET);
-        val &= BM_PLL_ENET_EN_SATA;
-        writel_relaxed(val, PLL8_ENET);
-}
-
-static struct clk sata_clk = {
-        .enable_reg = CCGR5,
-        .enable_shift = CG2,
-        .enable = sata_clk_enable,
-        .disable = sata_clk_disable,
-        .parent = &ipg_clk,
-        .secondary = &pll8_enet,
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        }
-
-static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
-        _REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
-        _REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
-        _REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
-        _REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
-        _REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
-        _REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
-        _REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
-        _REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
-        _REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
-        _REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
-        _REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
-        _REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
-        _REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
-        _REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
-        _REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
-        _REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
-        _REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
-        _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
-        _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
-        _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
-        _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
-        _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
-        _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
-        _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
-        _REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
-        _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
-        _REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
-        _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
-        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
-        _REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
-        _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
-        _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
-        _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
-        _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
-        _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
-        _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
-        _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
-        _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
-        _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
-};
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        u32 val = readl_relaxed(CLPCR);
-
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                break;
-        default:
-                return -EINVAL;
-        }
-        writel_relaxed(val, CLPCR);
-
-        return 0;
-}
-
-static struct map_desc imx6q_clock_desc[] = {
-        imx_map_entry(MX6Q, CCM, MT_DEVICE),
-        imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
-};
-
-void __init imx6q_clock_map_io(void)
-{
-        iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
-}
-
-int __init mx6q_clocks_init(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-        int i, irq;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        external_low_reference = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        external_high_reference = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        oscillator_reference = rate;
-        }
-
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
-
-        /* only keep necessary clocks on */
-        writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,  CCGR0);
-        writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10, CCGR2);
-        writel_relaxed(0x3 << CG10 | 0x3 << CG12,               CCGR3);
-        writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,  CCGR4);
-        writel_relaxed(0x3 << CG0,                              CCGR5);
-        writel_relaxed(0,                                       CCGR6);
-        writel_relaxed(0,                                       CCGR7);
-
-        clk_enable(&uart_clk);
-        clk_enable(&mmdc_ch0_axi_clk);
-
-        clk_set_rate(&pll4_audio, FREQ_650M);
-        clk_set_rate(&pll5_video, FREQ_650M);
-        clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
-        clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
-        clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
-        clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
-        clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
-        clk_set_rate(&gpu3d_core_clk, FREQ_528M);
-        clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
-        clk_set_rate(&asrc_serial_clk, 1500000);
-        clk_set_rate(&enfc_clk, 11000000);
-
-        /*
-         * Before pinctrl API is available, we have to rely on the pad
-         * configuration set up by bootloader.  For usdhc example here,
-         * u-boot sets up the pads for 49.5 MHz case, and we have to lower
-         * the usdhc clock from 198 to 49.5 MHz to match the pad configuration.
-         *
-         * FIXME: This is should be removed after pinctrl API is available.
-         * At that time, usdhc driver can call pinctrl API to change pad
-         * configuration dynamically per different usdhc clock settings.
-         */
-        clk_set_rate(&usdhc1_clk, 49500000);
-        clk_set_rate(&usdhc2_clk, 49500000);
-        clk_set_rate(&usdhc3_clk, 49500000);
-        clk_set_rate(&usdhc4_clk, 49500000);
-
-        clk_set_parent(&cko1_clk, &ahb_clk);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(&gpt_clk, base, irq);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c
deleted file mode 100644
index 08470504a088..000000000000
--- a/arch/arm/mach-imx/clock-mx51-mx53.c
+++ /dev/null
@@ -1,1675 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-
-#include <asm/div64.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "crm-regs-imx5.h"
-
-/* External clock values passed-in by the board code */
-static unsigned long external_high_reference, external_low_reference;
-static unsigned long oscillator_reference, ckih2_reference;
-
-static struct clk osc_clk;
-static struct clk pll1_main_clk;
-static struct clk pll1_sw_clk;
-static struct clk pll2_sw_clk;
-static struct clk pll3_sw_clk;
-static struct clk mx53_pll4_sw_clk;
-static struct clk lp_apm_clk;
-static struct clk periph_apm_clk;
-static struct clk ahb_clk;
-static struct clk ipg_clk;
-static struct clk usboh3_clk;
-static struct clk emi_fast_clk;
-static struct clk ipu_clk;
-static struct clk mipi_hsc1_clk;
-static struct clk esdhc1_clk;
-static struct clk esdhc2_clk;
-static struct clk esdhc3_mx53_clk;
-
-#define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
-
-/* calculate best pre and post dividers to get the required divider */
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
-        u32 max_pre, u32 max_post)
-{
-        if (div >= max_pre * max_post) {
-                *pre = max_pre;
-                *post = max_post;
-        } else if (div >= max_pre) {
-                u32 min_pre, temp_pre, old_err, err;
-                min_pre = DIV_ROUND_UP(div, max_post);
-                old_err = max_pre;
-                for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
-                        err = div % temp_pre;
-                        if (err == 0) {
-                                *pre = temp_pre;
-                                break;
-                        }
-                        err = temp_pre - err;
-                        if (err < old_err) {
-                                old_err = err;
-                                *pre = temp_pre;
-                        }
-                }
-                *post = DIV_ROUND_UP(div, *pre);
-        } else {
-                *pre = div;
-                *post = 1;
-        }
-}
-
-static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
-{
-        u32 reg = __raw_readl(clk->enable_reg);
-
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        reg |= mode << clk->enable_shift;
-
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_ccgr_enable(struct clk *clk)
-{
-        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
-        return 0;
-}
-
-static void _clk_ccgr_disable(struct clk *clk)
-{
-        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
-}
-
-static int _clk_ccgr_enable_inrun(struct clk *clk)
-{
-        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-        return 0;
-}
-
-static void _clk_ccgr_disable_inwait(struct clk *clk)
-{
-        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-}
-
-/*
- * For the 4-to-1 muxed input clock
- */
-static inline u32 _get_mux(struct clk *parent, struct clk *m0,
-                           struct clk *m1, struct clk *m2, struct clk *m3)
-{
-        if (parent == m0)
-                return 0;
-        else if (parent == m1)
-                return 1;
-        else if (parent == m2)
-                return 2;
-        else if (parent == m3)
-                return 3;
-        else
-                BUG();
-
-        return -EINVAL;
-}
-
-static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
-{
-        if (pll == &pll1_main_clk)
-                return MX51_DPLL1_BASE;
-        else if (pll == &pll2_sw_clk)
-                return MX51_DPLL2_BASE;
-        else if (pll == &pll3_sw_clk)
-                return MX51_DPLL3_BASE;
-        else
-                BUG();
-
-        return NULL;
-}
-
-static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
-{
-        if (pll == &pll1_main_clk)
-                return MX53_DPLL1_BASE;
-        else if (pll == &pll2_sw_clk)
-                return MX53_DPLL2_BASE;
-        else if (pll == &pll3_sw_clk)
-                return MX53_DPLL3_BASE;
-        else if (pll == &mx53_pll4_sw_clk)
-                return MX53_DPLL4_BASE;
-        else
-                BUG();
-
-        return NULL;
-}
-
-static inline void __iomem *_get_pll_base(struct clk *pll)
-{
-        if (cpu_is_mx51())
-                return _mx51_get_pll_base(pll);
-        else
-                return _mx53_get_pll_base(pll);
-}
-
-static unsigned long clk_pll_get_rate(struct clk *clk)
-{
-        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
-        unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
-        void __iomem *pllbase;
-        s64 temp;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        pllbase = _get_pll_base(clk);
-
-        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-        pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-        dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
-        if (pll_hfsm == 0) {
-                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-        } else {
-                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
-                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
-                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
-        }
-        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-        mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
-        mfi = (mfi <= 5) ? 5 : mfi;
-        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-        mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
-        /* Sign extend to 32-bits */
-        if (mfn >= 0x04000000) {
-                mfn |= 0xFC000000;
-                mfn_abs = -mfn;
-        }
-
-        ref_clk = 2 * parent_rate;
-        if (dbl != 0)
-                ref_clk *= 2;
-
-        ref_clk /= (pdf + 1);
-        temp = (u64) ref_clk * mfn_abs;
-        do_div(temp, mfd + 1);
-        if (mfn < 0)
-                temp = -temp;
-        temp = (ref_clk * mfi) + temp;
-
-        return temp;
-}
-
-static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        void __iomem *pllbase;
-
-        long mfi, pdf, mfn, mfd = 999999;
-        s64 temp64;
-        unsigned long quad_parent_rate;
-        unsigned long pll_hfsm, dp_ctl;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        pllbase = _get_pll_base(clk);
-
-        quad_parent_rate = 4 * parent_rate;
-        pdf = mfi = -1;
-        while (++pdf < 16 && mfi < 5)
-                mfi = rate * (pdf+1) / quad_parent_rate;
-        if (mfi > 15)
-                return -EINVAL;
-        pdf--;
-
-        temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
-        do_div(temp64, quad_parent_rate/1000000);
-        mfn = (long)temp64;
-
-        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-        /* use dpdck0_2 */
-        __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
-        pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-        if (pll_hfsm == 0) {
-                reg = mfi << 4 | pdf;
-                __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
-                __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
-                __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
-        } else {
-                reg = mfi << 4 | pdf;
-                __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
-                __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
-                __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
-        }
-
-        return 0;
-}
-
-static int _clk_pll_enable(struct clk *clk)
-{
-        u32 reg;
-        void __iomem *pllbase;
-        int i = 0;
-
-        pllbase = _get_pll_base(clk);
-        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-        if (reg & MXC_PLL_DP_CTL_UPEN)
-                return 0;
-
-        reg |= MXC_PLL_DP_CTL_UPEN;
-        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
-        /* Wait for lock */
-        do {
-                reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-                if (reg & MXC_PLL_DP_CTL_LRF)
-                        break;
-
-                udelay(1);
-        } while (++i < MAX_DPLL_WAIT_TRIES);
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                pr_err("MX5: pll locking failed\n");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static void _clk_pll_disable(struct clk *clk)
-{
-        u32 reg;
-        void __iomem *pllbase;
-
-        pllbase = _get_pll_base(clk);
-        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
-        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg, step;
-
-        reg = __raw_readl(MXC_CCM_CCSR);
-
-        /* When switching from pll_main_clk to a bypass clock, first select a
-         * multiplexed clock in 'step_sel', then shift the glitchless mux
-         * 'pll1_sw_clk_sel'.
-         *
-         * When switching back, do it in reverse order
-         */
-        if (parent == &pll1_main_clk) {
-                /* Switch to pll1_main_clk */
-                reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-                __raw_writel(reg, MXC_CCM_CCSR);
-                /* step_clk mux switched to lp_apm, to save power. */
-                reg = __raw_readl(MXC_CCM_CCSR);
-                reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-                reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
-                                MXC_CCM_CCSR_STEP_SEL_OFFSET);
-        } else {
-                if (parent == &lp_apm_clk) {
-                        step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
-                } else  if (parent == &pll2_sw_clk) {
-                        step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
-                } else  if (parent == &pll3_sw_clk) {
-                        step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
-                } else
-                        return -EINVAL;
-
-                reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-                reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-
-                __raw_writel(reg, MXC_CCM_CCSR);
-                /* Switch to step_clk */
-                reg = __raw_readl(MXC_CCM_CCSR);
-                reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-        }
-        __raw_writel(reg, MXC_CCM_CCSR);
-        return 0;
-}
-
-static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
-{
-        u32 reg, div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(MXC_CCM_CCSR);
-
-        if (clk->parent == &pll2_sw_clk) {
-                div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
-                       MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
-        } else if (clk->parent == &pll3_sw_clk) {
-                div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
-                       MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
-        } else
-                div = 1;
-        return parent_rate / div;
-}
-
-static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CCSR);
-
-        if (parent == &pll2_sw_clk)
-                reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-        else
-                reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-
-        __raw_writel(reg, MXC_CCM_CCSR);
-        return 0;
-}
-
-static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        if (parent == &osc_clk)
-                reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
-        else
-                return -EINVAL;
-
-        __raw_writel(reg, MXC_CCM_CCSR);
-
-        return 0;
-}
-
-static unsigned long clk_cpu_get_rate(struct clk *clk)
-{
-        u32 cacrr, div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-        cacrr = __raw_readl(MXC_CCM_CACRR);
-        div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
-
-        return parent_rate / div;
-}
-
-static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, cpu_podf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-        cpu_podf = parent_rate / rate - 1;
-        /* use post divider to change freq */
-        reg = __raw_readl(MXC_CCM_CACRR);
-        reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
-        reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
-        __raw_writel(reg, MXC_CCM_CACRR);
-
-        return 0;
-}
-
-static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg, mux;
-        int i = 0;
-
-        mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
-
-        reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
-        reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
-        __raw_writel(reg, MXC_CCM_CBCMR);
-
-        /* Wait for lock */
-        do {
-                reg = __raw_readl(MXC_CCM_CDHIPR);
-                if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
-                        break;
-
-                udelay(1);
-        } while (++i < MAX_DPLL_WAIT_TRIES);
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                pr_err("MX5: Set parent for periph_apm clock failed\n");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-
-        if (parent == &pll2_sw_clk)
-                reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-        else if (parent == &periph_apm_clk)
-                reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-        else
-                return -EINVAL;
-
-        __raw_writel(reg, MXC_CCM_CBCDR);
-
-        return 0;
-}
-
-static struct clk main_bus_clk = {
-        .parent = &pll2_sw_clk,
-        .set_parent = _clk_main_bus_set_parent,
-};
-
-static unsigned long clk_ahb_get_rate(struct clk *clk)
-{
-        u32 reg, div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-               MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-        return parent_rate / div;
-}
-
-
-static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, div;
-        unsigned long parent_rate;
-        int i = 0;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
-        reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-        __raw_writel(reg, MXC_CCM_CBCDR);
-
-        /* Wait for lock */
-        do {
-                reg = __raw_readl(MXC_CCM_CDHIPR);
-                if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
-                        break;
-
-                udelay(1);
-        } while (++i < MAX_DPLL_WAIT_TRIES);
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                pr_err("MX5: clk_ahb_set_rate failed\n");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static unsigned long _clk_ahb_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-        if (div > 8)
-                div = 8;
-        else if (div == 0)
-                div++;
-        return parent_rate / div;
-}
-
-
-static int _clk_max_enable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_enable(clk);
-
-        /* Handshake with MAX when LPM is entered. */
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        if (cpu_is_mx51())
-                reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-        else if (cpu_is_mx53())
-                reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-static void _clk_max_disable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_disable_inwait(clk);
-
-        /* No Handshake with MAX when LPM is entered as its disabled. */
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        if (cpu_is_mx51())
-                reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-        else if (cpu_is_mx53())
-                reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static unsigned long clk_ipg_get_rate(struct clk *clk)
-{
-        u32 reg, div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-               MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
-
-        return parent_rate / div;
-}
-
-static unsigned long clk_ipg_per_get_rate(struct clk *clk)
-{
-        u32 reg, prediv1, prediv2, podf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
-                /* the main_bus_clk is the one before the DVFS engine */
-                reg = __raw_readl(MXC_CCM_CBCDR);
-                prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-                           MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
-                prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-                           MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
-                podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-                        MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
-                return parent_rate / (prediv1 * prediv2 * podf);
-        } else if (clk->parent == &ipg_clk)
-                return parent_rate;
-        else
-                BUG();
-}
-
-static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CBCMR);
-
-        reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-        reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-
-        if (parent == &ipg_clk)
-                reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-        else if (parent == &lp_apm_clk)
-                reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-        else if (parent != &main_bus_clk)
-                return -EINVAL;
-
-        __raw_writel(reg, MXC_CCM_CBCMR);
-
-        return 0;
-}
-
-#define clk_nfc_set_parent      NULL
-
-static unsigned long clk_nfc_get_rate(struct clk *clk)
-{
-        unsigned long rate;
-        u32 reg, div;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
-               MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
-        rate = clk_get_rate(clk->parent) / div;
-        WARN_ON(rate == 0);
-        return rate;
-}
-
-static unsigned long clk_nfc_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        u32 div;
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-
-        if (!rate)
-                return -EINVAL;
-
-        div = parent_rate / rate;
-
-        if (parent_rate % rate)
-                div++;
-
-        if (div > 8)
-                return -EINVAL;
-
-        return parent_rate / div;
-
-}
-
-static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, div;
-
-        div = clk_get_rate(clk->parent) / rate;
-        if (div == 0)
-                div++;
-        if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
-                return -EINVAL;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-        reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-        __raw_writel(reg, MXC_CCM_CBCDR);
-
-        while (__raw_readl(MXC_CCM_CDHIPR) &
-                        MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
-        }
-
-        return 0;
-}
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-        return external_high_reference;
-}
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-        return external_low_reference;
-}
-
-static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
-{
-        return oscillator_reference;
-}
-
-static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
-{
-        return ckih2_reference;
-}
-
-static unsigned long clk_emi_slow_get_rate(struct clk *clk)
-{
-        u32 reg, div;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
-               MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
-
-        return clk_get_rate(clk->parent) / div;
-}
-
-static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
-{
-        unsigned long rate;
-        u32 reg, div;
-
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
-                MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
-        rate = clk_get_rate(clk->parent) / div;
-
-        return rate;
-}
-
-/* External high frequency clock */
-static struct clk ckih_clk = {
-        .get_rate = get_high_reference_clock_rate,
-};
-
-static struct clk ckih2_clk = {
-        .get_rate = get_ckih2_reference_clock_rate,
-};
-
-static struct clk osc_clk = {
-        .get_rate = get_oscillator_reference_clock_rate,
-};
-
-/* External low frequency (32kHz) clock */
-static struct clk ckil_clk = {
-        .get_rate = get_low_reference_clock_rate,
-};
-
-static struct clk pll1_main_clk = {
-        .parent = &osc_clk,
-        .get_rate = clk_pll_get_rate,
-        .enable = _clk_pll_enable,
-        .disable = _clk_pll_disable,
-};
-
-/* Clock tree block diagram (WIP):
- *      CCM: Clock Controller Module
- *
- * PLL output -> |
- *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
- * PLL bypass -> |
- *
- */
-
-/* PLL1 SW supplies to ARM core */
-static struct clk pll1_sw_clk = {
-        .parent = &pll1_main_clk,
-        .set_parent = _clk_pll1_sw_set_parent,
-        .get_rate = clk_pll1_sw_get_rate,
-};
-
-/* PLL2 SW supplies to AXI/AHB/IP buses */
-static struct clk pll2_sw_clk = {
-        .parent = &osc_clk,
-        .get_rate = clk_pll_get_rate,
-        .set_rate = _clk_pll_set_rate,
-        .set_parent = _clk_pll2_sw_set_parent,
-        .enable = _clk_pll_enable,
-        .disable = _clk_pll_disable,
-};
-
-/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
-static struct clk pll3_sw_clk = {
-        .parent = &osc_clk,
-        .set_rate = _clk_pll_set_rate,
-        .get_rate = clk_pll_get_rate,
-        .enable = _clk_pll_enable,
-        .disable = _clk_pll_disable,
-};
-
-/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
-static struct clk mx53_pll4_sw_clk = {
-        .parent = &osc_clk,
-        .set_rate = _clk_pll_set_rate,
-        .enable = _clk_pll_enable,
-        .disable = _clk_pll_disable,
-};
-
-/* Low-power Audio Playback Mode clock */
-static struct clk lp_apm_clk = {
-        .parent = &osc_clk,
-        .set_parent = _clk_lp_apm_set_parent,
-};
-
-static struct clk periph_apm_clk = {
-        .parent = &pll1_sw_clk,
-        .set_parent = _clk_periph_apm_set_parent,
-};
-
-static struct clk cpu_clk = {
-        .parent = &pll1_sw_clk,
-        .get_rate = clk_cpu_get_rate,
-        .set_rate = clk_cpu_set_rate,
-};
-
-static struct clk ahb_clk = {
-        .parent = &main_bus_clk,
-        .get_rate = clk_ahb_get_rate,
-        .set_rate = _clk_ahb_set_rate,
-        .round_rate = _clk_ahb_round_rate,
-};
-
-static struct clk iim_clk = {
-        .parent = &ipg_clk,
-        .enable_reg = MXC_CCM_CCGR0,
-        .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
-};
-
-/* Main IP interface clock for access to registers */
-static struct clk ipg_clk = {
-        .parent = &ahb_clk,
-        .get_rate = clk_ipg_get_rate,
-};
-
-static struct clk ipg_perclk = {
-        .parent = &lp_apm_clk,
-        .get_rate = clk_ipg_per_get_rate,
-        .set_parent = _clk_ipg_per_set_parent,
-};
-
-static struct clk ahb_max_clk = {
-        .parent = &ahb_clk,
-        .enable_reg = MXC_CCM_CCGR0,
-        .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-        .enable = _clk_max_enable,
-        .disable = _clk_max_disable,
-};
-
-static struct clk aips_tz1_clk = {
-        .parent = &ahb_clk,
-        .secondary = &ahb_max_clk,
-        .enable_reg = MXC_CCM_CCGR0,
-        .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk aips_tz2_clk = {
-        .parent = &ahb_clk,
-        .secondary = &ahb_max_clk,
-        .enable_reg = MXC_CCM_CCGR0,
-        .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk gpc_dvfs_clk = {
-        .enable_reg = MXC_CCM_CCGR5,
-        .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable,
-};
-
-static struct clk gpt_32k_clk = {
-        .id = 0,
-        .parent = &ckil_clk,
-};
-
-static struct clk dummy_clk = {
-        .id = 0,
-};
-
-static struct clk emi_slow_clk = {
-        .parent = &pll2_sw_clk,
-        .enable_reg = MXC_CCM_CCGR5,
-        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable_inwait,
-        .get_rate = clk_emi_slow_get_rate,
-};
-
-static int clk_ipu_enable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_enable(clk);
-
-        /* Enable handshake with IPU when certain clock rates are changed */
-        reg = __raw_readl(MXC_CCM_CCDR);
-        reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
-        __raw_writel(reg, MXC_CCM_CCDR);
-
-        /* Enable handshake with IPU when LPM is entered */
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-static void clk_ipu_disable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_disable(clk);
-
-        /* Disable handshake with IPU whe dividers are changed */
-        reg = __raw_readl(MXC_CCM_CCDR);
-        reg |= MXC_CCM_CCDR_IPU_HS_MASK;
-        __raw_writel(reg, MXC_CCM_CCDR);
-
-        /* Disable handshake with IPU when LPM is entered */
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk ahbmux1_clk = {
-        .parent = &ahb_clk,
-        .secondary = &ahb_max_clk,
-        .enable_reg = MXC_CCM_CCGR0,
-        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk ipu_sec_clk = {
-        .parent = &emi_fast_clk,
-        .secondary = &ahbmux1_clk,
-};
-
-static struct clk ddr_hf_clk = {
-        .parent = &pll1_sw_clk,
-        .get_rate = _clk_ddr_hf_get_rate,
-};
-
-static struct clk ddr_clk = {
-        .parent = &ddr_hf_clk,
-};
-
-/* clock definitions for MIPI HSC unit which has been removed
- * from documentation, but not from hardware
- */
-static int _clk_hsc_enable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_enable(clk);
-        /* Handshake with IPU when certain clock rates are changed. */
-        reg = __raw_readl(MXC_CCM_CCDR);
-        reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
-        __raw_writel(reg, MXC_CCM_CCDR);
-
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-static void _clk_hsc_disable(struct clk *clk)
-{
-        u32 reg;
-
-        _clk_ccgr_disable(clk);
-        /* No handshake with HSC as its not enabled. */
-        reg = __raw_readl(MXC_CCM_CCDR);
-        reg |= MXC_CCM_CCDR_HSC_HS_MASK;
-        __raw_writel(reg, MXC_CCM_CCDR);
-
-        reg = __raw_readl(MXC_CCM_CLPCR);
-        reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-        __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk mipi_hsp_clk = {
-        .parent = &ipu_clk,
-        .enable_reg = MXC_CCM_CCGR4,
-        .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
-        .enable = _clk_hsc_enable,
-        .disable = _clk_hsc_disable,
-        .secondary = &mipi_hsc1_clk,
-};
-
-#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .get_rate       = pfx##_get_rate,       \
-                .set_rate       = pfx##_set_rate,       \
-                .round_rate     = pfx##_round_rate,     \
-                .set_parent     = pfx##_set_parent,     \
-                .enable         = _clk_ccgr_enable,     \
-                .disable        = _clk_ccgr_disable,    \
-                .parent         = p,                    \
-                .secondary      = s,                    \
-        }
-
-#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)    \
-        static struct clk name = {                      \
-                .id             = i,                    \
-                .enable_reg     = er,                   \
-                .enable_shift   = es,                   \
-                .get_rate       = pfx##_get_rate,       \
-                .set_rate       = pfx##_set_rate,       \
-                .set_parent     = pfx##_set_parent,     \
-                .enable         = _clk_max_enable,      \
-                .disable        = _clk_max_disable,     \
-                .parent         = p,                    \
-                .secondary      = s,                    \
-        }
-
-#define CLK_GET_RATE(name, nr, bitsname)                                \
-static unsigned long clk_##name##_get_rate(struct clk *clk)             \
-{                                                                       \
-        u32 reg, pred, podf;                                            \
-                                                                        \
-        reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
-        pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
-                >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
-        podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
-                >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
-                                                                        \
-        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
-                        (pred + 1) * (podf + 1));                       \
-}
-
-#define CLK_SET_PARENT(name, nr, bitsname)                              \
-static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
-{                                                                       \
-        u32 reg, mux;                                                   \
-                                                                        \
-        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
-                        &pll3_sw_clk, &lp_apm_clk);                     \
-        reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
-                ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
-        reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
-        __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
-                                                                        \
-        return 0;                                                       \
-}
-
-#define CLK_SET_RATE(name, nr, bitsname)                                \
-static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)   \
-{                                                                       \
-        u32 reg, div, parent_rate;                                      \
-        u32 pre = 0, post = 0;                                          \
-                                                                        \
-        parent_rate = clk_get_rate(clk->parent);                        \
-        div = parent_rate / rate;                                       \
-                                                                        \
-        if ((parent_rate / div) != rate)                                \
-                return -EINVAL;                                         \
-                                                                        \
-        __calc_pre_post_dividers(div, &pre, &post,                      \
-                (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
-                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
-                (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
-                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
-                                                                        \
-        /* Set sdhc1 clock divider */                                   \
-        reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
-                ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
-                | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
-        reg |= (post - 1) <<                                            \
-                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
-        reg |= (pre - 1) <<                                             \
-                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
-        __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
-                                                                        \
-        return 0;                                                       \
-}
-
-/* UART */
-CLK_GET_RATE(uart, 1, UART)
-CLK_SET_PARENT(uart, 1, UART)
-
-static struct clk uart_root_clk = {
-        .parent = &pll2_sw_clk,
-        .get_rate = clk_uart_get_rate,
-        .set_parent = clk_uart_set_parent,
-};
-
-/* USBOH3 */
-CLK_GET_RATE(usboh3, 1, USBOH3)
-CLK_SET_PARENT(usboh3, 1, USBOH3)
-
-static struct clk usboh3_clk = {
-        .parent = &pll2_sw_clk,
-        .get_rate = clk_usboh3_get_rate,
-        .set_parent = clk_usboh3_set_parent,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable,
-        .enable_reg = MXC_CCM_CCGR2,
-        .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-};
-
-static struct clk usb_ahb_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_ccgr_enable,
-        .disable = _clk_ccgr_disable,
-        .enable_reg = MXC_CCM_CCGR2,
-        .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-};
-
-static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-
-        if (parent == &pll3_sw_clk)
-                reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
-
-        __raw_writel(reg, MXC_CCM_CSCMR1);
-
-        return 0;
-}
-
-static struct clk usb_phy1_clk = {
-        .parent = &pll3_sw_clk,
-        .set_parent = clk_usb_phy1_set_parent,
-        .enable = _clk_ccgr_enable,
-        .enable_reg = MXC_CCM_CCGR2,
-        .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
-        .disable = _clk_ccgr_disable,
-};
-
-/* eCSPI */
-CLK_GET_RATE(ecspi, 2, CSPI)
-CLK_SET_PARENT(ecspi, 1, CSPI)
-
-static struct clk ecspi_main_clk = {
-        .parent = &pll3_sw_clk,
-        .get_rate = clk_ecspi_get_rate,
-        .set_parent = clk_ecspi_set_parent,
-};
-
-/* eSDHC */
-CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-
-/* mx51 specific */
-CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-
-static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CSCMR1);
-        if (parent == &esdhc1_clk)
-                reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-        else if (parent == &esdhc2_clk)
-                reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-        else
-                return -EINVAL;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
-
-        return 0;
-}
-
-static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CSCMR1);
-        if (parent == &esdhc1_clk)
-                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-        else if (parent == &esdhc2_clk)
-                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-        else
-                return -EINVAL;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
-
-        return 0;
-}
-
-/* mx53 specific */
-static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CSCMR1);
-        if (parent == &esdhc1_clk)
-                reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-        else if (parent == &esdhc3_mx53_clk)
-                reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-        else
-                return -EINVAL;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
-
-        return 0;
-}
-
-CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-
-static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_CSCMR1);
-        if (parent == &esdhc1_clk)
-                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-        else if (parent == &esdhc3_mx53_clk)
-                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-        else
-                return -EINVAL;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
-
-        return 0;
-}
-
-#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
-        static struct clk name = {                                      \
-                .id             = i,                                    \
-                .enable_reg     = er,                                   \
-                .enable_shift   = es,                                   \
-                .get_rate       = gr,                                   \
-                .set_rate       = sr,                                   \
-                .enable         = e,                                    \
-                .disable        = d,                                    \
-                .parent         = p,                                    \
-                .secondary      = s,                                    \
-        }
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
-        DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
-
-/* Shared peripheral bus arbiter */
-DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
-
-/* UART */
-DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
-        NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
-        NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
-        NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
-DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
-        NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
-DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
-        NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
-
-/* GPT */
-DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
-
-DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL, NULL, &ipg_perclk, NULL);
-
-/* I2C */
-DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
-        NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-        NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-        NULL, NULL, &ipg_perclk, NULL);
-
-/* FEC */
-DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
-
-/* NFC */
-DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
-        clk_nfc, &emi_slow_clk, NULL);
-
-/* SSI */
-DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
-DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
-        NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
-        NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
-DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
-        NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
-        NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
-
-/* eCSPI */
-DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-                &ipg_clk, &spba_clk);
-DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
-                NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
-DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
-                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-                &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
-                NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
-
-/* CSPI */
-DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-                NULL, NULL, &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
-                NULL, NULL, &ipg_clk, &cspi_ipg_clk);
-
-/* SDMA */
-DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
-                NULL, NULL, &ahb_clk, NULL);
-
-/* eSDHC */
-DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
-        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
-        clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
-DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
-        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-
-/* mx51 specific */
-DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
-        clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc3_clk = {
-        .id = 2,
-        .parent = &esdhc1_clk,
-        .set_parent = clk_esdhc3_set_parent,
-        .enable_reg = MXC_CCM_CCGR3,
-        .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
-        .enable  = _clk_max_enable,
-        .disable = _clk_max_disable,
-        .secondary = &esdhc3_ipg_clk,
-};
-static struct clk esdhc4_clk = {
-        .id = 3,
-        .parent = &esdhc1_clk,
-        .set_parent = clk_esdhc4_set_parent,
-        .enable_reg = MXC_CCM_CCGR3,
-        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-        .enable  = _clk_max_enable,
-        .disable = _clk_max_disable,
-        .secondary = &esdhc4_ipg_clk,
-};
-
-/* mx53 specific */
-static struct clk esdhc2_mx53_clk = {
-        .id = 2,
-        .parent = &esdhc1_clk,
-        .set_parent = clk_esdhc2_mx53_set_parent,
-        .enable_reg = MXC_CCM_CCGR3,
-        .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
-        .enable  = _clk_max_enable,
-        .disable = _clk_max_disable,
-        .secondary = &esdhc3_ipg_clk,
-};
-
-DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
-        clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc4_mx53_clk = {
-        .id = 3,
-        .parent = &esdhc1_clk,
-        .set_parent = clk_esdhc4_mx53_set_parent,
-        .enable_reg = MXC_CCM_CCGR3,
-        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-        .enable  = _clk_max_enable,
-        .disable = _clk_max_disable,
-        .secondary = &esdhc4_ipg_clk,
-};
-
-static struct clk sata_clk = {
-        .parent = &ipg_clk,
-        .enable = _clk_max_enable,
-        .enable_reg = MXC_CCM_CCGR4,
-        .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
-        .disable = _clk_max_disable,
-};
-
-static struct clk ahci_phy_clk = {
-        .parent = &usb_phy1_clk,
-};
-
-static struct clk ahci_dma_clk = {
-        .parent = &ahb_clk,
-};
-
-DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
-
-/* IPU */
-DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
-        NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
-
-DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
-                NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
-                &ddr_clk, NULL);
-
-DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
-                NULL, NULL, &pll3_sw_clk, NULL);
-DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
-                NULL, NULL, &pll3_sw_clk, NULL);
-
-/* PATA */
-DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
-                NULL, NULL, &ipg_clk, &spba_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c,   \
-       },
-
-static struct clk_lookup mx51_lookups[] = {
-        /* i.mx51 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-        /* i.mx51 has the i.mx27 type fec */
-        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
-        _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-        _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
-        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
-        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-        _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-        /* i.mx51 has the i.mx35 type sdma */
-        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
-        _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
-        _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
-        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-        /* i.mx51 has the i.mx35 type cspi */
-        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
-        _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
-        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-        _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
-        _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
-        _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
-        _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
-        _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
-        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-};
-
-static struct clk_lookup mx53_lookups[] = {
-        /* i.mx53 has the i.mx21 type uart */
-        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-        /* i.mx53 has the i.mx25 type fec */
-        _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
-        /* i.mx53 has the i.mx51 type ecspi */
-        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-        /* i.mx53 has the i.mx25 type cspi */
-        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
-        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-        /* i.mx53 has the i.mx35 type sdma */
-        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-        _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-        _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-        _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
-        _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
-        _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
-};
-
-static void clk_tree_init(void)
-{
-        u32 reg;
-
-        ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
-
-        /*
-         * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
-         * 8MHz, its derived from lp_apm.
-         *
-         * FIXME: Verify if true for all boards
-         */
-        reg = __raw_readl(MXC_CCM_CBCDR);
-        reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
-        reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
-        reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
-        reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
-        __raw_writel(reg, MXC_CCM_CBCDR);
-}
-
-int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2)
-{
-        int i;
-
-        external_low_reference = ckil;
-        external_high_reference = ckih1;
-        ckih2_reference = ckih2;
-        oscillator_reference = osc;
-
-        for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
-                clkdev_add(&mx51_lookups[i]);
-
-        clk_tree_init();
-
-        clk_enable(&cpu_clk);
-        clk_enable(&main_bus_clk);
-
-        clk_enable(&iim_clk);
-        imx_print_silicon_rev("i.MX51", mx51_revision());
-        clk_disable(&iim_clk);
-
-        /* move usb_phy_clk to 24MHz */
-        clk_set_parent(&usb_phy1_clk, &osc_clk);
-
-        /* set the usboh3_clk parent to pll2_sw_clk */
-        clk_set_parent(&usboh3_clk, &pll2_sw_clk);
-
-        /* Set SDHC parents to be PLL2 */
-        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-        clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
-
-        /* set SDHC root clock as 166.25MHZ*/
-        clk_set_rate(&esdhc1_clk, 166250000);
-        clk_set_rate(&esdhc2_clk, 166250000);
-
-        /* System timer */
-        mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-                MX51_INT_GPT);
-        return 0;
-}
-
-int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2)
-{
-        int i;
-
-        external_low_reference = ckil;
-        external_high_reference = ckih1;
-        ckih2_reference = ckih2;
-        oscillator_reference = osc;
-
-        for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
-                clkdev_add(&mx53_lookups[i]);
-
-        clk_tree_init();
-
-        clk_set_parent(&uart_root_clk, &pll3_sw_clk);
-        clk_enable(&cpu_clk);
-        clk_enable(&main_bus_clk);
-
-        clk_enable(&iim_clk);
-        imx_print_silicon_rev("i.MX53", mx53_revision());
-        clk_disable(&iim_clk);
-
-        /* Set SDHC parents to be PLL2 */
-        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-        clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
-
-        /* set SDHC root clock as 200MHZ*/
-        clk_set_rate(&esdhc1_clk, 200000000);
-        clk_set_rate(&esdhc3_mx53_clk, 200000000);
-
-        /* System timer */
-        mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-                MX53_INT_GPT);
-        return 0;
-}
-
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                   unsigned long *ckih1, unsigned long *ckih2)
-{
-        struct device_node *np;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        *ckil = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        *osc = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        *ckih1 = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                        *ckih2 = rate;
-        }
-}
-
-int __init mx51_clocks_init_dt(void)
-{
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
-}
-
-int __init mx53_clocks_init_dt(void)
-{
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
-}
-#endif
diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h
index 53141273df45..a1dfde53e335 100644
--- a/arch/arm/mach-imx/crmregs-imx3.h
+++ b/arch/arm/mach-imx/crmregs-imx3.h
@@ -24,48 +24,47 @@
 #define CKIH_CLK_FREQ_27MHZ     27000000
 #define CKIL_CLK_FREQ           32768
 
-#define MXC_CCM_BASE            (cpu_is_mx31() ? \
-MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
+extern void __iomem *mx3_ccm_base;
 
 /* Register addresses */
-#define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
-#define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
-#define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
-#define MX35_CCM_PDR2           (MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
-#define MX35_CCM_PDR3           (MXC_CCM_BASE + 0x10)
-#define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
-#define MX35_CCM_PDR4           (MXC_CCM_BASE + 0x14)
-#define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
-#define MX35_CCM_RCSR           (MXC_CCM_BASE + 0x18)
-#define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
-#define MX35_CCM_MPCTL          (MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
-#define MX35_CCM_PPCTL          (MXC_CCM_BASE + 0x20)
-#define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
-#define MX35_CCM_ACMR           (MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
-#define MX35_CCM_COSR           (MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
-#define MX35_CCM_CGR0           (MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
-#define MX35_CCM_CGR1           (MXC_CCM_BASE + 0x30)
-#define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
-#define MX35_CCM_CGR2           (MXC_CCM_BASE + 0x34)
-#define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
-#define MX35_CCM_CGR3           (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
-#define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
-#define MXC_CCM_LTR0            (MXC_CCM_BASE + 0x44)
-#define MXC_CCM_LTR1            (MXC_CCM_BASE + 0x48)
-#define MXC_CCM_LTR2            (MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_LTR3            (MXC_CCM_BASE + 0x50)
-#define MXC_CCM_LTBR0           (MXC_CCM_BASE + 0x54)
-#define MXC_CCM_LTBR1           (MXC_CCM_BASE + 0x58)
-#define MXC_CCM_PMCR0           (MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_PMCR1           (MXC_CCM_BASE + 0x60)
-#define MXC_CCM_PDR2            (MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCMR            0x00
+#define MXC_CCM_PDR0            0x04
+#define MXC_CCM_PDR1            0x08
+#define MX35_CCM_PDR2           0x0C
+#define MXC_CCM_RCSR            0x0C
+#define MX35_CCM_PDR3           0x10
+#define MXC_CCM_MPCTL           0x10
+#define MX35_CCM_PDR4           0x14
+#define MXC_CCM_UPCTL           0x14
+#define MX35_CCM_RCSR           0x18
+#define MXC_CCM_SRPCTL          0x18
+#define MX35_CCM_MPCTL          0x1C
+#define MXC_CCM_COSR            0x1C
+#define MX35_CCM_PPCTL          0x20
+#define MXC_CCM_CGR0            0x20
+#define MX35_CCM_ACMR           0x24
+#define MXC_CCM_CGR1            0x24
+#define MX35_CCM_COSR           0x28
+#define MXC_CCM_CGR2            0x28
+#define MX35_CCM_CGR0           0x2C
+#define MXC_CCM_WIMR            0x2C
+#define MX35_CCM_CGR1           0x30
+#define MXC_CCM_LDC             0x30
+#define MX35_CCM_CGR2           0x34
+#define MXC_CCM_DCVR0           0x34
+#define MX35_CCM_CGR3           0x38
+#define MXC_CCM_DCVR1           0x38
+#define MXC_CCM_DCVR2           0x3C
+#define MXC_CCM_DCVR3           0x40
+#define MXC_CCM_LTR0            0x44
+#define MXC_CCM_LTR1            0x48
+#define MXC_CCM_LTR2            0x4C
+#define MXC_CCM_LTR3            0x50
+#define MXC_CCM_LTBR0           0x54
+#define MXC_CCM_LTBR1           0x58
+#define MXC_CCM_PMCR0           0x5C
+#define MXC_CCM_PMCR1           0x60
+#define MXC_CCM_PDR2            0x64
 
 /* Register bit definitions */
 #define MXC_CCM_CCMR_WBEN                       (1 << 27)
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573964f0..5f577fbda2c8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -14,6 +14,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
 
         of_irq_init(imx51_irq_match);
 
+        pinctrl_provide_dummies();
+
         node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
         if (node) {
                 of_id = of_match_node(imx51_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279b3900..574eca4b89a5 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,6 +15,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
 
         of_irq_init(imx53_irq_match);
 
+        pinctrl_provide_dummies();
+
         node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
         if (node) {
                 of_id = of_match_node(imx53_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9af768..3df360a52c17 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <asm/smp_twd.h>
@@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 
 static void __init imx6q_init_machine(void)
 {
+        /*
+         * This should be removed when all imx6q boards have pinctrl
+         * states for devices defined in device tree.
+         */
+        pinctrl_provide_dummies();
+
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                                            ksz9021rn_phy_fixup);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2bded591d5c2..fcafd3dafb8c 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
@@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
                                                 MX1_GPIO_INT_PORTC, 0);
         mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
                                                 MX1_GPIO_INT_PORTD, 0);
+        pinctrl_provide_dummies();
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 14d540edfd1e..5f43905e5290 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,6 +20,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
         mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 
+        pinctrl_provide_dummies();
         imx_add_imx_dma();
         platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
                                         ARRAY_SIZE(imx21_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 153b457acdc0..6ff37140a4f8 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
@@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
         mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
         mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
 
+        pinctrl_provide_dummies();
         /* i.mx25 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
         /* i.mx25 has the i.mx31 type audmux */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 8cb3f5e3e569..25662558e018 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,6 +20,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
         mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 
+        pinctrl_provide_dummies();
         imx_add_imx_dma();
         /* imx27 has the imx21 type audmux */
         platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 74127389e7ab..967ed5b35a45 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/system_misc.h>
@@ -31,6 +32,10 @@
 #include <mach/iomux-v3.h>
 #include <mach/irqs.h>
 
+#include "crmregs-imx3.h"
+
+void __iomem *mx3_ccm_base;
+
 static void imx3_idle(void)
 {
         unsigned long reg = 0;
@@ -137,6 +142,7 @@ void __init imx31_init_early(void)
         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
         arch_ioremap_caller = imx3_ioremap_caller;
         arm_pm_idle = imx3_idle;
+        mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
 }
 
 void __init mx31_init_irq(void)
@@ -210,6 +216,7 @@ void __init imx35_init_early(void)
         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
         arm_pm_idle = imx3_idle;
         arch_ioremap_caller = imx3_ioremap_caller;
+        mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
 }
 
 void __init mx35_init_irq(void)
@@ -267,6 +274,7 @@ void __init imx35_soc_init(void)
         mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
         mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 
+        pinctrl_provide_dummies();
         if (to_version == 1) {
                 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
                         strlen(imx35_sdma_pdata.fw_name));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index e10f3914fcfe..8b4dc20c7c53 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -32,6 +33,7 @@ static void imx5_idle(void)
                 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
                 if (IS_ERR(gpc_dvfs_clk))
                         return;
+                clk_prepare(gpc_dvfs_clk);
         }
         clk_enable(gpc_dvfs_clk);
         mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
@@ -223,6 +225,7 @@ void __init imx53_soc_init(void)
         mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
         mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 
+        pinctrl_provide_dummies();
         /* i.mx53 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
 
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index b3752439632e..822103bdb709 100644
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -21,14 +21,14 @@
  */
 void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
 {
-        int reg = __raw_readl(MXC_CCM_CCMR);
+        int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR);
         reg &= ~MXC_CCM_CCMR_LPM_MASK;
 
         switch (mode) {
         case MX3_WAIT:
                 if (cpu_is_mx35())
                         reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
-                __raw_writel(reg, MXC_CCM_CCMR);
+                __raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
                 break;
         default:
                 pr_err("Unknown cpu power mode: %d\n", mode);
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e71169750..fb3496a52ef4 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -17,6 +17,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/memblock.h>
 
@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
         msm_map_msm8x60_io();
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id msm_dt_gic_match[] __initdata = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+#endif
+
 static void __init msm8x60_init_irq(void)
 {
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                 (void *)MSM_QGIC_CPU_BASE);
+        if (!of_have_populated_dt())
+                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                         (void *)MSM_QGIC_CPU_BASE);
+#ifdef CONFIG_OF
+        else
+                of_irq_init(msm_dt_gic_match);
+#endif
 
         /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
         writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
         {}
 };
 
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", },
-        {}
-};
-
 static void __init msm8x60_dt_init(void)
 {
-        irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
-                                GIC_SPI_START);
-
         if (of_machine_is_compatible("qcom,msm8660-surf")) {
                 printk(KERN_INFO "Init surf UART registers\n");
                 msm8x60_init_uart12dm();
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f9964a713..07d5383d68ee 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -9,11 +9,13 @@ config SOC_IMX23
         bool
         select CPU_ARM926T
         select HAVE_PWM
+        select PINCTRL_IMX23
 
 config SOC_IMX28
         bool
         select CPU_ARM926T
         select HAVE_PWM
+        select PINCTRL_IMX28
 
 comment "MXS platforms:"
 
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a567f1..6ce21a26412e 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,12 +1,9 @@
 # Common support
-obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
+obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
 
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
 
-obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
-obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
-
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
deleted file mode 100644
index e3ac52c34019..000000000000
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/jiffies.h>
-#include <linux/clkdev.h>
-
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#include <mach/mx23.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "regs-clkctrl-mx23.h"
-
-#define CLKCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
-#define DIGCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
-
-#define PARENT_RATE_SHIFT       8
-
-static int _raw_clk_enable(struct clk *clk)
-{
-        u32 reg;
-
-        if (clk->enable_reg) {
-                reg = __raw_readl(clk->enable_reg);
-                reg &= ~(1 << clk->enable_shift);
-                __raw_writel(reg, clk->enable_reg);
-        }
-
-        return 0;
-}
-
-static void _raw_clk_disable(struct clk *clk)
-{
-        u32 reg;
-
-        if (clk->enable_reg) {
-                reg = __raw_readl(clk->enable_reg);
-                reg |= 1 << clk->enable_shift;
-                __raw_writel(reg, clk->enable_reg);
-        }
-}
-
-/*
- * ref_xtal_clk
- */
-static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
-{
-        return 24000000;
-}
-
-static struct clk ref_xtal_clk = {
-        .get_rate = ref_xtal_clk_get_rate,
-};
-
-/*
- * pll_clk
- */
-static unsigned long pll_clk_get_rate(struct clk *clk)
-{
-        return 480000000;
-}
-
-static int pll_clk_enable(struct clk *clk)
-{
-        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
-                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
-
-        /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
-         * and is incorrect (excessive). Per definition of the PLLCTRL0
-         * POWER field, waiting at least 10us.
-         */
-        udelay(10);
-
-        return 0;
-}
-
-static void pll_clk_disable(struct clk *clk)
-{
-        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
-                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
-}
-
-static struct clk pll_clk = {
-         .get_rate = pll_clk_get_rate,
-         .enable = pll_clk_enable,
-         .disable = pll_clk_disable,
-         .parent = &ref_xtal_clk,
-};
-
-/*
- * ref_clk
- */
-#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        unsigned long parent_rate;                                      \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
-        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
-        parent_rate = clk_get_rate(clk->parent);                        \
-                                                                        \
-        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
-                        div, PARENT_RATE_SHIFT);                        \
-}
-
-_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
-_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
-_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
-_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
-
-#define _DEFINE_CLOCK_REF(name, er, es)                                 \
-        static struct clk name = {                                      \
-                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
-                .get_rate       = name##_get_rate,                      \
-                .enable         = _raw_clk_enable,                      \
-                .disable        = _raw_clk_disable,                     \
-                .parent         = &pll_clk,                             \
-        }
-
-_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
-_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
-_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
-_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
-
-/*
- * General clocks
- *
- * clk_get_rate
- */
-static unsigned long rtc_clk_get_rate(struct clk *clk)
-{
-        /* ref_xtal_clk is implemented as the only parent */
-        return clk_get_rate(clk->parent) / 768;
-}
-
-static unsigned long clk32k_clk_get_rate(struct clk *clk)
-{
-        return clk->parent->get_rate(clk->parent) / 750;
-}
-
-#define _CLK_GET_RATE(name, rs)                                         \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                        \
-        if (clk->parent == &ref_xtal_clk)                               \
-                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
-                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
-        else                                                            \
-                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
-                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
-                                                                        \
-        if (!div)                                                       \
-                return -EINVAL;                                         \
-                                                                        \
-        return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE(cpu_clk, CPU)
-_CLK_GET_RATE(emi_clk, EMI)
-
-#define _CLK_GET_RATE1(name, rs)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
-                                                                        \
-        if (!div)                                                       \
-                return -EINVAL;                                         \
-                                                                        \
-        return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE1(hbus_clk, HBUS)
-_CLK_GET_RATE1(xbus_clk, XBUS)
-_CLK_GET_RATE1(ssp_clk, SSP)
-_CLK_GET_RATE1(gpmi_clk, GPMI)
-_CLK_GET_RATE1(lcdif_clk, PIX)
-
-#define _CLK_GET_RATE_STUB(name)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        return clk_get_rate(clk->parent);                               \
-}
-
-_CLK_GET_RATE_STUB(uart_clk)
-_CLK_GET_RATE_STUB(audio_clk)
-_CLK_GET_RATE_STUB(pwm_clk)
-
-/*
- * clk_set_rate
- */
-static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, bm_busy, div_max, d, f, div, frac;
-        unsigned long diff, parent_rate, calc_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        if (clk->parent == &ref_xtal_clk) {
-                div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
-                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
-                div = DIV_ROUND_UP(parent_rate, rate);
-                if (div == 0 || div > div_max)
-                        return -EINVAL;
-        } else {
-                div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
-                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
-                rate >>= PARENT_RATE_SHIFT;
-                parent_rate >>= PARENT_RATE_SHIFT;
-                diff = parent_rate;
-                div = frac = 1;
-                for (d = 1; d <= div_max; d++) {
-                        f = parent_rate * 18 / d / rate;
-                        if ((parent_rate * 18 / d) % rate)
-                                f++;
-                        if (f < 18 || f > 35)
-                                continue;
-
-                        calc_rate = parent_rate * 18 / f / d;
-                        if (calc_rate > rate)
-                                continue;
-
-                        if (rate - calc_rate < diff) {
-                                frac = f;
-                                div = d;
-                                diff = rate - calc_rate;
-                        }
-
-                        if (diff == 0)
-                                break;
-                }
-
-                if (diff == parent_rate)
-                        return -EINVAL;
-
-                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-                reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
-                reg |= frac;
-                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-        }
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
-        reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
-        reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
-
-        mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
-
-        return 0;
-}
-
-#define _CLK_SET_RATE(name, dr)                                         \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        u32 reg, div_max, div;                                          \
-        unsigned long parent_rate;                                      \
-                                                                        \
-        parent_rate = clk_get_rate(clk->parent);                        \
-        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-                                                                        \
-        div = DIV_ROUND_UP(parent_rate, rate);                          \
-        if (div == 0 || div > div_max)                                  \
-                return -EINVAL;                                         \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
-        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
-        if (reg & (1 << clk->enable_shift)) {                           \
-                pr_err("%s: clock is gated\n", __func__);               \
-                return -EINVAL;                                         \
-        }                                                               \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                        \
-        mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);   \
-        return 0;                                                       \
-}
-
-_CLK_SET_RATE(xbus_clk, XBUS)
-_CLK_SET_RATE(ssp_clk, SSP)
-_CLK_SET_RATE(gpmi_clk, GPMI)
-_CLK_SET_RATE(lcdif_clk, PIX)
-
-#define _CLK_SET_RATE_STUB(name)                                        \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        return -EINVAL;                                                 \
-}
-
-_CLK_SET_RATE_STUB(emi_clk)
-_CLK_SET_RATE_STUB(uart_clk)
-_CLK_SET_RATE_STUB(audio_clk)
-_CLK_SET_RATE_STUB(pwm_clk)
-_CLK_SET_RATE_STUB(clk32k_clk)
-
-/*
- * clk_set_parent
- */
-#define _CLK_SET_PARENT(name, bit)                                      \
-static int name##_set_parent(struct clk *clk, struct clk *parent)       \
-{                                                                       \
-        if (parent != clk->parent) {                                    \
-                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
-                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
-                clk->parent = parent;                                   \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
-}
-
-_CLK_SET_PARENT(cpu_clk, CPU)
-_CLK_SET_PARENT(emi_clk, EMI)
-_CLK_SET_PARENT(ssp_clk, SSP)
-_CLK_SET_PARENT(gpmi_clk, GPMI)
-_CLK_SET_PARENT(lcdif_clk, PIX)
-
-#define _CLK_SET_PARENT_STUB(name)                                      \
-static int name##_set_parent(struct clk *clk, struct clk *parent)       \
-{                                                                       \
-        if (parent != clk->parent)                                      \
-                return -EINVAL;                                         \
-        else                                                            \
-                return 0;                                               \
-}
-
-_CLK_SET_PARENT_STUB(uart_clk)
-_CLK_SET_PARENT_STUB(audio_clk)
-_CLK_SET_PARENT_STUB(pwm_clk)
-_CLK_SET_PARENT_STUB(clk32k_clk)
-
-/*
- * clk definition
- */
-static struct clk cpu_clk = {
-        .get_rate = cpu_clk_get_rate,
-        .set_rate = cpu_clk_set_rate,
-        .set_parent = cpu_clk_set_parent,
-        .parent = &ref_cpu_clk,
-};
-
-static struct clk hbus_clk = {
-        .get_rate = hbus_clk_get_rate,
-        .parent = &cpu_clk,
-};
-
-static struct clk xbus_clk = {
-        .get_rate = xbus_clk_get_rate,
-        .set_rate = xbus_clk_set_rate,
-        .parent = &ref_xtal_clk,
-};
-
-static struct clk rtc_clk = {
-        .get_rate = rtc_clk_get_rate,
-        .parent = &ref_xtal_clk,
-};
-
-/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
-static struct clk usb_clk = {
-        .enable_reg = DIGCTRL_BASE_ADDR,
-        .enable_shift = 2,
-        .enable = _raw_clk_enable,
-        .disable = _raw_clk_disable,
-        .parent = &pll_clk,
-};
-
-#define _DEFINE_CLOCK(name, er, es, p)                                  \
-        static struct clk name = {                                      \
-                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
-                .get_rate       = name##_get_rate,                      \
-                .set_rate       = name##_set_rate,                      \
-                .set_parent     = name##_set_parent,                    \
-                .enable         = _raw_clk_enable,                      \
-                .disable        = _raw_clk_disable,                     \
-                .parent         = p,                                    \
-        }
-
-_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-
-static struct clk_lookup lookups[] = {
-        /* for amba bus driver */
-        _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
-        /* for amba-pl011 driver */
-        _REGISTER_CLOCK("duart", NULL, uart_clk)
-        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
-        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
-        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
-        _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
-        _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
-        _REGISTER_CLOCK(NULL, "usb", usb_clk)
-        _REGISTER_CLOCK(NULL, "audio", audio_clk)
-        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
-        _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
-        _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
-};
-
-static int clk_misc_init(void)
-{
-        u32 reg;
-        int ret;
-
-        /* Fix up parent per register setting */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
-        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
-                        &ref_xtal_clk : &ref_cpu_clk;
-        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
-                        &ref_xtal_clk : &ref_emi_clk;
-        ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
-                        &ref_xtal_clk : &ref_io_clk;
-        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
-                        &ref_xtal_clk : &ref_io_clk;
-        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
-                        &ref_xtal_clk : &ref_pix_clk;
-
-        /* Use int div over frac when both are available */
-        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
-        reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
-        reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
-
-        /*
-         * Set safe hbus clock divider. A divider of 3 ensure that
-         * the Vddd voltage required for the cpu clock is sufficiently
-         * high for the hbus clock.
-         */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-        reg &= BM_CLKCTRL_HBUS_DIV;
-        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-
-        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
-
-        /* Gate off cpu clock in WFI for power saving */
-        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
-
-        /*
-         * 480 MHz seems too high to be ssp clock source directly,
-         * so set frac to get a 288 MHz ref_io.
-         */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-        reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
-        reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-
-        return ret;
-}
-
-int __init mx23_clocks_init(void)
-{
-        clk_misc_init();
-
-        /*
-         * source ssp clock from ref_io than ref_xtal,
-         * as ref_xtal only provides 24 MHz as maximum.
-         */
-        clk_set_parent(&ssp_clk, &ref_io_clk);
-
-        clk_prepare_enable(&cpu_clk);
-        clk_prepare_enable(&hbus_clk);
-        clk_prepare_enable(&xbus_clk);
-        clk_prepare_enable(&emi_clk);
-        clk_prepare_enable(&uart_clk);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
deleted file mode 100644
index cea29c99e214..000000000000
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ /dev/null
@@ -1,803 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/jiffies.h>
-#include <linux/clkdev.h>
-#include <linux/spinlock.h>
-
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-#include <mach/digctl.h>
-
-#include "regs-clkctrl-mx28.h"
-
-#define CLKCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
-#define DIGCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
-
-#define PARENT_RATE_SHIFT       8
-
-static struct clk pll2_clk;
-static struct clk cpu_clk;
-static struct clk emi_clk;
-static struct clk saif0_clk;
-static struct clk saif1_clk;
-static struct clk clk32k_clk;
-static DEFINE_SPINLOCK(clkmux_lock);
-
-/*
- * HW_SAIF_CLKMUX_SEL:
- *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
- *              clock pins selected for SAIF1 input clocks.
- *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
- *              SAIF0 clock inputs selected for SAIF1 input clocks.
- *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
- *              clocks.
- *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
- *              clocks.
- */
-int mxs_saif_clkmux_select(unsigned int clkmux)
-{
-        if (clkmux > 0x3)
-                return -EINVAL;
-
-        spin_lock(&clkmux_lock);
-        __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
-                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
-        __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
-                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
-        spin_unlock(&clkmux_lock);
-
-        return 0;
-}
-
-static int _raw_clk_enable(struct clk *clk)
-{
-        u32 reg;
-
-        if (clk->enable_reg) {
-                reg = __raw_readl(clk->enable_reg);
-                reg &= ~(1 << clk->enable_shift);
-                __raw_writel(reg, clk->enable_reg);
-        }
-
-        return 0;
-}
-
-static void _raw_clk_disable(struct clk *clk)
-{
-        u32 reg;
-
-        if (clk->enable_reg) {
-                reg = __raw_readl(clk->enable_reg);
-                reg |= 1 << clk->enable_shift;
-                __raw_writel(reg, clk->enable_reg);
-        }
-}
-
-/*
- * ref_xtal_clk
- */
-static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
-{
-        return 24000000;
-}
-
-static struct clk ref_xtal_clk = {
-        .get_rate = ref_xtal_clk_get_rate,
-};
-
-/*
- * pll_clk
- */
-static unsigned long pll0_clk_get_rate(struct clk *clk)
-{
-        return 480000000;
-}
-
-static unsigned long pll1_clk_get_rate(struct clk *clk)
-{
-        return 480000000;
-}
-
-static unsigned long pll2_clk_get_rate(struct clk *clk)
-{
-        return 50000000;
-}
-
-#define _CLK_ENABLE_PLL(name, r, g)                                     \
-static int name##_enable(struct clk *clk)                               \
-{                                                                       \
-        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
-                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
-        udelay(10);                                                     \
-                                                                        \
-        if (clk == &pll2_clk)                                           \
-                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
-        else                                                            \
-                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
-                                                                        \
-        return 0;                                                       \
-}
-
-_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
-_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
-_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
-
-#define _CLK_DISABLE_PLL(name, r, g)                                    \
-static void name##_disable(struct clk *clk)                             \
-{                                                                       \
-        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
-                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
-                                                                        \
-        if (clk == &pll2_clk)                                           \
-                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
-        else                                                            \
-                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
-                                                                        \
-}
-
-_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
-_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
-_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
-
-#define _DEFINE_CLOCK_PLL(name)                                         \
-        static struct clk name = {                                      \
-                .get_rate       = name##_get_rate,                      \
-                .enable         = name##_enable,                        \
-                .disable        = name##_disable,                       \
-                .parent         = &ref_xtal_clk,                        \
-        }
-
-_DEFINE_CLOCK_PLL(pll0_clk);
-_DEFINE_CLOCK_PLL(pll1_clk);
-_DEFINE_CLOCK_PLL(pll2_clk);
-
-/*
- * ref_clk
- */
-#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        unsigned long parent_rate;                                      \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
-        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
-        parent_rate = clk_get_rate(clk->parent);                        \
-                                                                        \
-        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
-                        div, PARENT_RATE_SHIFT);                        \
-}
-
-_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
-_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
-_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
-_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
-_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
-_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
-
-#define _DEFINE_CLOCK_REF(name, er, es)                                 \
-        static struct clk name = {                                      \
-                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
-                .get_rate       = name##_get_rate,                      \
-                .enable         = _raw_clk_enable,                      \
-                .disable        = _raw_clk_disable,                     \
-                .parent         = &pll0_clk,                            \
-        }
-
-_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
-_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
-_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
-_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
-_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
-_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
-
-/*
- * General clocks
- *
- * clk_get_rate
- */
-static unsigned long lradc_clk_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 16;
-}
-
-static unsigned long rtc_clk_get_rate(struct clk *clk)
-{
-        /* ref_xtal_clk is implemented as the only parent */
-        return clk_get_rate(clk->parent) / 768;
-}
-
-static unsigned long clk32k_clk_get_rate(struct clk *clk)
-{
-        return clk->parent->get_rate(clk->parent) / 750;
-}
-
-static unsigned long spdif_clk_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 4;
-}
-
-#define _CLK_GET_RATE(name, rs)                                         \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                        \
-        if (clk->parent == &ref_xtal_clk)                               \
-                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
-                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
-        else                                                            \
-                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
-                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
-                                                                        \
-        if (!div)                                                       \
-                return -EINVAL;                                         \
-                                                                        \
-        return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE(cpu_clk, CPU)
-_CLK_GET_RATE(emi_clk, EMI)
-
-#define _CLK_GET_RATE1(name, rs)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        u32 reg, div;                                                   \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
-                                                                        \
-        if (!div)                                                       \
-                return -EINVAL;                                         \
-                                                                        \
-        if (clk == &saif0_clk || clk == &saif1_clk)                     \
-                return clk_get_rate(clk->parent) >> 16 * div;           \
-        else                                                            \
-                return clk_get_rate(clk->parent) / div;                 \
-}
-
-_CLK_GET_RATE1(hbus_clk, HBUS)
-_CLK_GET_RATE1(xbus_clk, XBUS)
-_CLK_GET_RATE1(ssp0_clk, SSP0)
-_CLK_GET_RATE1(ssp1_clk, SSP1)
-_CLK_GET_RATE1(ssp2_clk, SSP2)
-_CLK_GET_RATE1(ssp3_clk, SSP3)
-_CLK_GET_RATE1(gpmi_clk, GPMI)
-_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
-_CLK_GET_RATE1(saif0_clk, SAIF0)
-_CLK_GET_RATE1(saif1_clk, SAIF1)
-
-#define _CLK_GET_RATE_STUB(name)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                   \
-{                                                                       \
-        return clk_get_rate(clk->parent);                               \
-}
-
-_CLK_GET_RATE_STUB(uart_clk)
-_CLK_GET_RATE_STUB(pwm_clk)
-_CLK_GET_RATE_STUB(can0_clk)
-_CLK_GET_RATE_STUB(can1_clk)
-_CLK_GET_RATE_STUB(fec_clk)
-
-/*
- * clk_set_rate
- */
-/* fool compiler */
-#define BM_CLKCTRL_CPU_DIV      0
-#define BP_CLKCTRL_CPU_DIV      0
-#define BM_CLKCTRL_CPU_BUSY     0
-
-#define _CLK_SET_RATE(name, dr, fr, fs)                                 \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        u32 reg, bm_busy, div_max, d, f, div, frac;                     \
-        unsigned long diff, parent_rate, calc_rate;                     \
-                                                                        \
-        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-        bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
-                                                                        \
-        if (clk->parent == &ref_xtal_clk) {                             \
-                parent_rate = clk_get_rate(clk->parent);                \
-                div = DIV_ROUND_UP(parent_rate, rate);                  \
-                if (clk == &cpu_clk) {                                  \
-                        div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
-                                BP_CLKCTRL_CPU_DIV_XTAL;                \
-                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
-                }                                                       \
-                if (div == 0 || div > div_max)                          \
-                        return -EINVAL;                                 \
-        } else {                                                        \
-                /*                                                      \
-                 * hack alert: this block modifies clk->parent, too,    \
-                 * so the base to use it the grand parent.              \
-                 */                                                     \
-                parent_rate = clk_get_rate(clk->parent->parent);        \
-                rate >>= PARENT_RATE_SHIFT;                             \
-                parent_rate >>= PARENT_RATE_SHIFT;                      \
-                diff = parent_rate;                                     \
-                div = frac = 1;                                         \
-                if (clk == &cpu_clk) {                                  \
-                        div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
-                                BP_CLKCTRL_CPU_DIV_CPU;                 \
-                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
-                }                                                       \
-                for (d = 1; d <= div_max; d++) {                        \
-                        f = parent_rate * 18 / d / rate;                \
-                        if ((parent_rate * 18 / d) % rate)              \
-                                f++;                                    \
-                        if (f < 18 || f > 35)                           \
-                                continue;                               \
-                                                                        \
-                        calc_rate = parent_rate * 18 / f / d;           \
-                        if (calc_rate > rate)                           \
-                                continue;                               \
-                                                                        \
-                        if (rate - calc_rate < diff) {                  \
-                                frac = f;                               \
-                                div = d;                                \
-                                diff = rate - calc_rate;                \
-                        }                                               \
-                                                                        \
-                        if (diff == 0)                                  \
-                                break;                                  \
-                }                                                       \
-                                                                        \
-                if (diff == parent_rate)                                \
-                        return -EINVAL;                                 \
-                                                                        \
-                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
-                reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
-                reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
-                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
-        }                                                               \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-        if (clk == &cpu_clk) {                                          \
-                reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
-                reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
-        } else {                                                        \
-                reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
-                reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
-                if (reg & (1 << clk->enable_shift)) {                   \
-                        pr_err("%s: clock is gated\n", __func__);       \
-                        return -EINVAL;                                 \
-                }                                                       \
-        }                                                               \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                        \
-        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy);           \
-}
-
-_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
-_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
-_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
-_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
-_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
-_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
-_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
-
-#define _CLK_SET_RATE1(name, dr)                                        \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        u32 reg, div_max, div;                                          \
-        unsigned long parent_rate;                                      \
-                                                                        \
-        parent_rate = clk_get_rate(clk->parent);                        \
-        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-                                                                        \
-        div = DIV_ROUND_UP(parent_rate, rate);                          \
-        if (div == 0 || div > div_max)                                  \
-                return -EINVAL;                                         \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
-        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
-        if (reg & (1 << clk->enable_shift)) {                           \
-                pr_err("%s: clock is gated\n", __func__);               \
-                return -EINVAL;                                         \
-        }                                                               \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                        \
-        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
-}
-
-_CLK_SET_RATE1(xbus_clk, XBUS)
-
-/* saif clock uses 16 bits frac div */
-#define _CLK_SET_RATE_SAIF(name, rs)                                    \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        u16 div;                                                        \
-        u32 reg;                                                        \
-        u64 lrate;                                                      \
-        unsigned long parent_rate;                                      \
-                                                                        \
-        parent_rate = clk_get_rate(clk->parent);                        \
-        if (rate > parent_rate)                                         \
-                return -EINVAL;                                         \
-                                                                        \
-        lrate = (u64)rate << 16;                                        \
-        do_div(lrate, parent_rate);                                     \
-        div = (u16)lrate;                                               \
-                                                                        \
-        if (!div)                                                       \
-                return -EINVAL;                                         \
-                                                                        \
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-        reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
-        reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
-        if (reg & (1 << clk->enable_shift)) {                           \
-                pr_err("%s: clock is gated\n", __func__);               \
-                return -EINVAL;                                         \
-        }                                                               \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                        \
-        return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
-}
-
-_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
-_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
-
-#define _CLK_SET_RATE_STUB(name)                                        \
-static int name##_set_rate(struct clk *clk, unsigned long rate)         \
-{                                                                       \
-        return -EINVAL;                                                 \
-}
-
-_CLK_SET_RATE_STUB(emi_clk)
-_CLK_SET_RATE_STUB(uart_clk)
-_CLK_SET_RATE_STUB(pwm_clk)
-_CLK_SET_RATE_STUB(spdif_clk)
-_CLK_SET_RATE_STUB(clk32k_clk)
-_CLK_SET_RATE_STUB(can0_clk)
-_CLK_SET_RATE_STUB(can1_clk)
-_CLK_SET_RATE_STUB(fec_clk)
-
-/*
- * clk_set_parent
- */
-#define _CLK_SET_PARENT(name, bit)                                      \
-static int name##_set_parent(struct clk *clk, struct clk *parent)       \
-{                                                                       \
-        if (parent != clk->parent) {                                    \
-                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
-                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
-                clk->parent = parent;                                   \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
-}
-
-_CLK_SET_PARENT(cpu_clk, CPU)
-_CLK_SET_PARENT(emi_clk, EMI)
-_CLK_SET_PARENT(ssp0_clk, SSP0)
-_CLK_SET_PARENT(ssp1_clk, SSP1)
-_CLK_SET_PARENT(ssp2_clk, SSP2)
-_CLK_SET_PARENT(ssp3_clk, SSP3)
-_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
-_CLK_SET_PARENT(gpmi_clk, GPMI)
-_CLK_SET_PARENT(saif0_clk, SAIF0)
-_CLK_SET_PARENT(saif1_clk, SAIF1)
-
-#define _CLK_SET_PARENT_STUB(name)                                      \
-static int name##_set_parent(struct clk *clk, struct clk *parent)       \
-{                                                                       \
-        if (parent != clk->parent)                                      \
-                return -EINVAL;                                         \
-        else                                                            \
-                return 0;                                               \
-}
-
-_CLK_SET_PARENT_STUB(pwm_clk)
-_CLK_SET_PARENT_STUB(uart_clk)
-_CLK_SET_PARENT_STUB(clk32k_clk)
-_CLK_SET_PARENT_STUB(spdif_clk)
-_CLK_SET_PARENT_STUB(fec_clk)
-_CLK_SET_PARENT_STUB(can0_clk)
-_CLK_SET_PARENT_STUB(can1_clk)
-
-/*
- * clk definition
- */
-static struct clk cpu_clk = {
-        .get_rate = cpu_clk_get_rate,
-        .set_rate = cpu_clk_set_rate,
-        .set_parent = cpu_clk_set_parent,
-        .parent = &ref_cpu_clk,
-};
-
-static struct clk hbus_clk = {
-        .get_rate = hbus_clk_get_rate,
-        .parent = &cpu_clk,
-};
-
-static struct clk xbus_clk = {
-        .get_rate = xbus_clk_get_rate,
-        .set_rate = xbus_clk_set_rate,
-        .parent = &ref_xtal_clk,
-};
-
-static struct clk lradc_clk = {
-        .get_rate = lradc_clk_get_rate,
-        .parent = &clk32k_clk,
-};
-
-static struct clk rtc_clk = {
-        .get_rate = rtc_clk_get_rate,
-        .parent = &ref_xtal_clk,
-};
-
-/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
-static struct clk usb0_clk = {
-        .enable_reg = DIGCTRL_BASE_ADDR,
-        .enable_shift = 2,
-        .enable = _raw_clk_enable,
-        .disable = _raw_clk_disable,
-        .parent = &pll0_clk,
-};
-
-static struct clk usb1_clk = {
-        .enable_reg = DIGCTRL_BASE_ADDR,
-        .enable_shift = 16,
-        .enable = _raw_clk_enable,
-        .disable = _raw_clk_disable,
-        .parent = &pll1_clk,
-};
-
-#define _DEFINE_CLOCK(name, er, es, p)                                  \
-        static struct clk name = {                                      \
-                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
-                .get_rate       = name##_get_rate,                      \
-                .set_rate       = name##_set_rate,                      \
-                .set_parent     = name##_set_parent,                    \
-                .enable         = _raw_clk_enable,                      \
-                .disable        = _raw_clk_disable,                     \
-                .parent         = p,                                    \
-        }
-
-_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
-_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
-_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
-_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-
-static struct clk_lookup lookups[] = {
-        /* for amba bus driver */
-        _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
-        /* for amba-pl011 driver */
-        _REGISTER_CLOCK("duart", NULL, uart_clk)
-        _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
-        _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
-        _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
-        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
-        _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
-        _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
-        _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
-        _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
-        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-        _REGISTER_CLOCK("pll2", NULL, pll2_clk)
-        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
-        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
-        _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
-        _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
-        _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
-        _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
-        _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
-        _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
-        _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
-        _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
-        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
-        _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
-        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
-        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-        _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
-        _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
-        _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
-};
-
-static int clk_misc_init(void)
-{
-        u32 reg;
-        int ret;
-
-        /* Fix up parent per register setting */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
-        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
-                        &ref_xtal_clk : &ref_cpu_clk;
-        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
-                        &ref_xtal_clk : &ref_emi_clk;
-        ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
-                        &ref_xtal_clk : &ref_io0_clk;
-        ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
-                        &ref_xtal_clk : &ref_io0_clk;
-        ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
-                        &ref_xtal_clk : &ref_io1_clk;
-        ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
-                        &ref_xtal_clk : &ref_io1_clk;
-        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
-                        &ref_xtal_clk : &ref_pix_clk;
-        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
-                        &ref_xtal_clk : &ref_gpmi_clk;
-        saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
-                        &ref_xtal_clk : &pll0_clk;
-        saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
-                        &ref_xtal_clk : &pll0_clk;
-
-        /* Use int div over frac when both are available */
-        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
-        reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
-        reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
-        reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
-        reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
-        reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
-
-        /* SAIF has to use frac div for functional operation */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-        reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-        reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-
-        /*
-         * Set safe hbus clock divider. A divider of 3 ensure that
-         * the Vddd voltage required for the cpu clock is sufficiently
-         * high for the hbus clock.
-         */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-        reg &= BM_CLKCTRL_HBUS_DIV;
-        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-
-        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
-
-        /* Gate off cpu clock in WFI for power saving */
-        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
-
-        /*
-         * Extra fec clock setting
-         * The DENX M28 uses an external clock source
-         * and the clock output must not be enabled
-         */
-        if (!machine_is_m28evk()) {
-                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-                reg &= ~BM_CLKCTRL_ENET_SLEEP;
-                reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
-                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-        }
-
-        /*
-         * 480 MHz seems too high to be ssp clock source directly,
-         * so set frac0 to get a 288 MHz ref_io0.
-         */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
-        reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
-        reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
-
-        return ret;
-}
-
-int __init mx28_clocks_init(void)
-{
-        clk_misc_init();
-
-        /*
-         * source ssp clock from ref_io0 than ref_xtal,
-         * as ref_xtal only provides 24 MHz as maximum.
-         */
-        clk_set_parent(&ssp0_clk, &ref_io0_clk);
-        clk_set_parent(&ssp1_clk, &ref_io0_clk);
-        clk_set_parent(&ssp2_clk, &ref_io1_clk);
-        clk_set_parent(&ssp3_clk, &ref_io1_clk);
-
-        clk_prepare_enable(&cpu_clk);
-        clk_prepare_enable(&hbus_clk);
-        clk_prepare_enable(&xbus_clk);
-        clk_prepare_enable(&emi_clk);
-        clk_prepare_enable(&uart_clk);
-
-        clk_set_parent(&lcdif_clk, &ref_pix_clk);
-        clk_set_parent(&saif0_clk, &pll0_clk);
-        clk_set_parent(&saif1_clk, &pll0_clk);
-
-        /*
-         * Set an initial clock rate for the saif internal logic to work
-         * properly. This is important when working in EXTMASTER mode that
-         * uses the other saif's BITCLK&LRCLK but it still needs a basic
-         * clock which should be fast enough for the internal logic.
-         */
-        clk_set_rate(&saif0_clk, 24000000);
-        clk_set_rate(&saif1_clk, 24000000);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
deleted file mode 100644
index 97a6f4acc6cc..000000000000
--- a/arch/arm/mach-mxs/clock.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-/* #define DEBUG */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-
-#include <mach/clock.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-static void __clk_disable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        WARN_ON(!clk->usecount);
-
-        if (!(--clk->usecount)) {
-                if (clk->disable)
-                        clk->disable(clk);
-                __clk_disable(clk->parent);
-        }
-}
-
-static int __clk_enable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        if (clk->usecount++ == 0) {
-                __clk_enable(clk->parent);
-
-                if (clk->enable)
-                        clk->enable(clk);
-        }
-        return 0;
-}
-
-/*
- * The clk_enable/clk_disable could be called by drivers in atomic context,
- * so they should not really hold mutex.  Instead, clk_prepare/clk_unprepare
- * can hold a mutex, as the pair will only be called in non-atomic context.
- * Before migrating to common clk framework, we can have __clk_enable and
- * __clk_disable called in clk_prepare/clk_unprepare with mutex held and
- * leave clk_enable/clk_disable as the dummy functions.
- */
-int clk_prepare(struct clk *clk)
-{
-        int ret = 0;
-
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        mutex_lock(&clocks_mutex);
-        ret = __clk_enable(clk);
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_prepare);
-
-void clk_unprepare(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        mutex_lock(&clocks_mutex);
-        __clk_disable(clk);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unprepare);
-
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        /* nothing to do */
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return 0UL;
-
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-
-        return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
-                return 0;
-
-        return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret = -EINVAL;
-
-        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
-                return ret;
-
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_rate(clk, rate);
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -EINVAL;
-        struct clk *old;
-
-        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
-            IS_ERR(parent) || clk->set_parent == NULL)
-                return ret;
-
-        if (clk->usecount)
-                clk_prepare_enable(parent);
-
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_parent(clk, parent);
-        if (ret == 0) {
-                old = clk->parent;
-                clk->parent = parent;
-        } else {
-                old = parent;
-        }
-        mutex_unlock(&clocks_mutex);
-
-        if (clk->usecount)
-                clk_disable(old);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
-        struct clk *ret = NULL;
-
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
deleted file mode 100644
index 592c9ab5d760..000000000000
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_CLOCK_H__
-#define __MACH_MXS_CLOCK_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-
-struct module;
-
-struct clk {
-        int id;
-        /* Source clock this clk depends on */
-        struct clk *parent;
-        /* Reference count of clock enable/disable */
-        __s8 usecount;
-        /* Register bit position for clock's enable/disable control. */
-        u8 enable_shift;
-        /* Register address for clock's enable/disable control. */
-        void __iomem *enable_reg;
-        u32 flags;
-        /* get the current clock rate (always a fresh value) */
-        unsigned long (*get_rate) (struct clk *);
-        /* Function ptr to set the clock to a new rate. The rate must match a
-           supported rate returned from round_rate. Leave blank if clock is not
-           programmable */
-        int (*set_rate) (struct clk *, unsigned long);
-        /* Function ptr to round the requested clock rate to the nearest
-           supported rate that is less than or equal to the requested rate. */
-        unsigned long (*round_rate) (struct clk *, unsigned long);
-        /* Function ptr to enable the clock. Leave blank if clock can not
-           be gated. */
-        int (*enable) (struct clk *);
-        /* Function ptr to disable the clock. Leave blank if clock can not
-           be gated. */
-        void (*disable) (struct clk *);
-        /* Function ptr to set the parent clock of the clock. */
-        int (*set_parent) (struct clk *, struct clk *);
-};
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index c50c3ea28a9d..84af61cf6a62 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -11,19 +11,19 @@
 #ifndef __MACH_MXS_COMMON_H__
 #define __MACH_MXS_COMMON_H__
 
-struct clk;
-
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(struct clk *, int);
+extern void mxs_timer_init(int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
+extern void mx23_soc_init(void);
 extern int mx23_register_gpios(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
 extern void mx23_init_irq(void);
 
+extern void mx28_soc_init(void);
 extern int mx28_register_gpios(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
@@ -31,6 +31,4 @@ extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
-extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
-
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab571a6..5e90b9dcdef8 100644
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
 
 static void __init apx4devkit_init(void)
 {
+        mx28_soc_init();
+
         mxs_iomux_setup_multiple_pads(apx4devkit_pads,
                         ARRAY_SIZE(apx4devkit_pads));
 
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d79963611c..4c00c879b893 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
 
 static void __init m28evk_init(void)
 {
+        mx28_soc_init();
+
         mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
 
         mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57d2606..e7272a41939d 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
 {
         int ret;
 
+        mx23_soc_init();
+
         mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
 
         mx23_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c142f93c..dafd48e86c8c 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -226,7 +226,7 @@ static void __init mx28evk_fec_reset(void)
         struct clk *clk;
 
         /* Enable fec phy clock */
-        clk = clk_get_sys("pll2", NULL);
+        clk = clk_get_sys("enet_out", NULL);
         if (!IS_ERR(clk))
                 clk_prepare_enable(clk);
 
@@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
 {
         int ret;
 
+        mx28_soc_init();
+
         mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
 
         mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07b8713..6548965e4a76 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
 {
         int ret;
 
+        mx23_soc_init();
+
         mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
                         ARRAY_SIZE(stmp378x_dvb_pads));
 
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e655ee..8837029de1a4 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
 
 static void __init tx28_stk5v3_init(void)
 {
+        mx28_soc_init();
+
         mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
                         ARRAY_SIZE(tx28_stk5v3_pads));
 
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 50af5ceebf6d..67a384edcf5b 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,6 +13,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
@@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
 {
         icoll_init_irq();
 }
+
+void __init mx23_soc_init(void)
+{
+        pinctrl_provide_dummies();
+}
+
+void __init mx28_soc_init(void)
+{
+        pinctrl_provide_dummies();
+}
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
deleted file mode 100644
index 0ea5c9d0e2b2..000000000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * Freescale CLKCTRL Register Definitions
- *
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.48
- * Template revision: 26195
- */
-
-#ifndef __REGS_CLKCTRL_MX23_H__
-#define __REGS_CLKCTRL_MX23_H__
-
-
-#define HW_CLKCTRL_PLLCTRL0     (0x00000000)
-#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
-#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
-#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
-
-#define BP_CLKCTRL_PLLCTRL0_LFR_SEL     28
-#define BM_CLKCTRL_PLLCTRL0_LFR_SEL     0x30000000
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
-                (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_CP_SEL      24
-#define BM_CLKCTRL_PLLCTRL0_CP_SEL      0x03000000
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
-                (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_DIV_SEL     20
-#define BM_CLKCTRL_PLLCTRL0_DIV_SEL     0x00300000
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
-                (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
-#define BM_CLKCTRL_PLLCTRL0_POWER       0x00010000
-
-#define HW_CLKCTRL_PLLCTRL1     (0x00000010)
-
-#define BM_CLKCTRL_PLLCTRL1_LOCK        0x80000000
-#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK  0x40000000
-#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT  0
-#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT  0x0000FFFF
-#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_CPU  (0x00000020)
-#define HW_CLKCTRL_CPU_SET      (0x00000024)
-#define HW_CLKCTRL_CPU_CLR      (0x00000028)
-#define HW_CLKCTRL_CPU_TOG      (0x0000002c)
-
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
-#define BP_CLKCTRL_CPU_DIV_XTAL 16
-#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
-                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_DIV_CPU  0
-#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
-#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
-                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
-
-#define HW_CLKCTRL_HBUS (0x00000030)
-#define HW_CLKCTRL_HBUS_SET     (0x00000034)
-#define HW_CLKCTRL_HBUS_CLR     (0x00000038)
-#define HW_CLKCTRL_HBUS_TOG     (0x0000003c)
-
-#define BM_CLKCTRL_HBUS_BUSY    0x20000000
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x10000000
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE  0x00100000
-#define BP_CLKCTRL_HBUS_SLOW_DIV        16
-#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
-                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
-#define BP_CLKCTRL_HBUS_DIV     0
-#define BM_CLKCTRL_HBUS_DIV     0x0000001F
-#define BF_CLKCTRL_HBUS_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS (0x00000040)
-
-#define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
-#define BP_CLKCTRL_XBUS_DIV     0
-#define BM_CLKCTRL_XBUS_DIV     0x000003FF
-#define BF_CLKCTRL_XBUS_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
-
-#define HW_CLKCTRL_XTAL (0x00000050)
-#define HW_CLKCTRL_XTAL_SET     (0x00000054)
-#define HW_CLKCTRL_XTAL_CLR     (0x00000058)
-#define HW_CLKCTRL_XTAL_TOG     (0x0000005c)
-
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
-#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
-#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x08000000
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_DIV_UART        0
-#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
-#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
-                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
-
-#define HW_CLKCTRL_PIX  (0x00000060)
-
-#define BP_CLKCTRL_PIX_CLKGATE  31
-#define BM_CLKCTRL_PIX_CLKGATE  0x80000000
-#define BM_CLKCTRL_PIX_BUSY     0x20000000
-#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x00001000
-#define BP_CLKCTRL_PIX_DIV      0
-#define BM_CLKCTRL_PIX_DIV      0x00000FFF
-#define BF_CLKCTRL_PIX_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_PIX_DIV)
-
-#define HW_CLKCTRL_SSP  (0x00000070)
-
-#define BP_CLKCTRL_SSP_CLKGATE  31
-#define BM_CLKCTRL_SSP_CLKGATE  0x80000000
-#define BM_CLKCTRL_SSP_BUSY     0x20000000
-#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x00000200
-#define BP_CLKCTRL_SSP_DIV      0
-#define BM_CLKCTRL_SSP_DIV      0x000001FF
-#define BF_CLKCTRL_SSP_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SSP_DIV)
-
-#define HW_CLKCTRL_GPMI (0x00000080)
-
-#define BP_CLKCTRL_GPMI_CLKGATE 31
-#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
-#define BP_CLKCTRL_GPMI_DIV     0
-#define BM_CLKCTRL_GPMI_DIV     0x000003FF
-#define BF_CLKCTRL_GPMI_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
-
-#define HW_CLKCTRL_SPDIF        (0x00000090)
-
-#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-
-#define HW_CLKCTRL_EMI  (0x000000a0)
-
-#define BP_CLKCTRL_EMI_CLKGATE  31
-#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_DIV_XTAL 8
-#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
-                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_DIV_EMI  0
-#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
-#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
-                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
-
-#define HW_CLKCTRL_IR   (0x000000b0)
-
-#define BM_CLKCTRL_IR_CLKGATE   0x80000000
-#define BM_CLKCTRL_IR_AUTO_DIV  0x20000000
-#define BM_CLKCTRL_IR_IR_BUSY   0x10000000
-#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
-#define BP_CLKCTRL_IR_IROV_DIV  16
-#define BM_CLKCTRL_IR_IROV_DIV  0x01FF0000
-#define BF_CLKCTRL_IR_IROV_DIV(v)  \
-                (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
-#define BP_CLKCTRL_IR_IR_DIV    0
-#define BM_CLKCTRL_IR_IR_DIV    0x000003FF
-#define BF_CLKCTRL_IR_IR_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
-
-#define HW_CLKCTRL_SAIF (0x000000c0)
-
-#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
-#define BM_CLKCTRL_SAIF_BUSY    0x20000000
-#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x00010000
-#define BP_CLKCTRL_SAIF_DIV     0
-#define BM_CLKCTRL_SAIF_DIV     0x0000FFFF
-#define BF_CLKCTRL_SAIF_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
-
-#define HW_CLKCTRL_TV   (0x000000d0)
-
-#define BM_CLKCTRL_TV_CLK_TV108M_GATE   0x80000000
-#define BM_CLKCTRL_TV_CLK_TV_GATE       0x40000000
-
-#define HW_CLKCTRL_ETM  (0x000000e0)
-
-#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000040
-#define BP_CLKCTRL_ETM_DIV      0
-#define BM_CLKCTRL_ETM_DIV      0x0000003F
-#define BF_CLKCTRL_ETM_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
-
-#define HW_CLKCTRL_FRAC (0x000000f0)
-#define HW_CLKCTRL_FRAC_SET     (0x000000f4)
-#define HW_CLKCTRL_FRAC_CLR     (0x000000f8)
-#define HW_CLKCTRL_FRAC_TOG     (0x000000fc)
-
-#define BP_CLKCTRL_FRAC_CLKGATEIO       31
-#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
-#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
-#define BP_CLKCTRL_FRAC_IOFRAC  24
-#define BM_CLKCTRL_FRAC_IOFRAC  0x3F000000
-#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
-                (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
-#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x00800000
-#define BM_CLKCTRL_FRAC_PIX_STABLE      0x00400000
-#define BP_CLKCTRL_FRAC_PIXFRAC 16
-#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
-#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
-                (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
-#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x00008000
-#define BM_CLKCTRL_FRAC_EMI_STABLE      0x00004000
-#define BP_CLKCTRL_FRAC_EMIFRAC 8
-#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
-#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
-                (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATECPU      7
-#define BM_CLKCTRL_FRAC_CLKGATECPU      0x00000080
-#define BM_CLKCTRL_FRAC_CPU_STABLE      0x00000040
-#define BP_CLKCTRL_FRAC_CPUFRAC 0
-#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
-#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
-                (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
-
-#define HW_CLKCTRL_FRAC1        (0x00000100)
-#define HW_CLKCTRL_FRAC1_SET    (0x00000104)
-#define HW_CLKCTRL_FRAC1_CLR    (0x00000108)
-#define HW_CLKCTRL_FRAC1_TOG    (0x0000010c)
-
-#define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
-#define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
-
-#define HW_CLKCTRL_CLKSEQ       (0x00000110)
-#define HW_CLKCTRL_CLKSEQ_SET   (0x00000114)
-#define HW_CLKCTRL_CLKSEQ_CLR   (0x00000118)
-#define HW_CLKCTRL_CLKSEQ_TOG   (0x0000011c)
-
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00000080
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000040
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP    0x00000020
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000010
-#define BM_CLKCTRL_CLKSEQ_BYPASS_IR     0x00000008
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF   0x00000001
-
-#define HW_CLKCTRL_RESET        (0x00000120)
-
-#define BM_CLKCTRL_RESET_CHIP   0x00000002
-#define BM_CLKCTRL_RESET_DIG    0x00000001
-
-#define HW_CLKCTRL_STATUS       (0x00000130)
-
-#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
-                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-
-#define HW_CLKCTRL_VERSION      (0x00000140)
-
-#define BP_CLKCTRL_VERSION_MAJOR        24
-#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) \
-                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
-#define BP_CLKCTRL_VERSION_MINOR        16
-#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
-#define BF_CLKCTRL_VERSION_MINOR(v)  \
-                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
-#define BP_CLKCTRL_VERSION_STEP 0
-#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
-#define BF_CLKCTRL_VERSION_STEP(v)  \
-                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
-
-#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
deleted file mode 100644
index 7d1b061d7943..000000000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- * Freescale CLKCTRL Register Definitions
- *
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.48
- * Template revision: 26195
- */
-
-#ifndef __REGS_CLKCTRL_MX28_H__
-#define __REGS_CLKCTRL_MX28_H__
-
-#define HW_CLKCTRL_PLL0CTRL0    (0x00000000)
-#define HW_CLKCTRL_PLL0CTRL0_SET        (0x00000004)
-#define HW_CLKCTRL_PLL0CTRL0_CLR        (0x00000008)
-#define HW_CLKCTRL_PLL0CTRL0_TOG        (0x0000000c)
-
-#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL    28
-#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL    0x30000000
-#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
-                (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_CP_SEL     24
-#define BM_CLKCTRL_PLL0CTRL0_CP_SEL     0x03000000
-#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
-                (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL    20
-#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL    0x00300000
-#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
-                (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS        0x00040000
-#define BM_CLKCTRL_PLL0CTRL0_POWER      0x00020000
-
-#define HW_CLKCTRL_PLL0CTRL1    (0x00000010)
-
-#define BM_CLKCTRL_PLL0CTRL1_LOCK       0x80000000
-#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
-#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
-#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL1CTRL0    (0x00000020)
-#define HW_CLKCTRL_PLL1CTRL0_SET        (0x00000024)
-#define HW_CLKCTRL_PLL1CTRL0_CLR        (0x00000028)
-#define HW_CLKCTRL_PLL1CTRL0_TOG        (0x0000002c)
-
-#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
-#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL    28
-#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL    0x30000000
-#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
-                (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_CP_SEL     24
-#define BM_CLKCTRL_PLL1CTRL0_CP_SEL     0x03000000
-#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
-                (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL    20
-#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL    0x00300000
-#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
-                (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS        0x00040000
-#define BM_CLKCTRL_PLL1CTRL0_POWER      0x00020000
-
-#define HW_CLKCTRL_PLL1CTRL1    (0x00000030)
-
-#define BM_CLKCTRL_PLL1CTRL1_LOCK       0x80000000
-#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
-#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
-#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL2CTRL0    (0x00000040)
-#define HW_CLKCTRL_PLL2CTRL0_SET        (0x00000044)
-#define HW_CLKCTRL_PLL2CTRL0_CLR        (0x00000048)
-#define HW_CLKCTRL_PLL2CTRL0_TOG        (0x0000004c)
-
-#define BM_CLKCTRL_PLL2CTRL0_CLKGATE    0x80000000
-#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL    28
-#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL    0x30000000
-#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
-                (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B    0x04000000
-#define BP_CLKCTRL_PLL2CTRL0_CP_SEL     24
-#define BM_CLKCTRL_PLL2CTRL0_CP_SEL     0x03000000
-#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
-                (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_POWER      0x00800000
-
-#define HW_CLKCTRL_CPU  (0x00000050)
-#define HW_CLKCTRL_CPU_SET      (0x00000054)
-#define HW_CLKCTRL_CPU_CLR      (0x00000058)
-#define HW_CLKCTRL_CPU_TOG      (0x0000005c)
-
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
-#define BP_CLKCTRL_CPU_DIV_XTAL 16
-#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
-                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_DIV_CPU  0
-#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
-#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
-                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
-
-#define HW_CLKCTRL_HBUS (0x00000060)
-#define HW_CLKCTRL_HBUS_SET     (0x00000064)
-#define HW_CLKCTRL_HBUS_CLR     (0x00000068)
-#define HW_CLKCTRL_HBUS_TOG     (0x0000006c)
-
-#define BM_CLKCTRL_HBUS_ASM_BUSY        0x80000000
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x40000000
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x20000000
-#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE   0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
-#define BM_CLKCTRL_HBUS_ASM_ENABLE      0x00100000
-#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE   0x00080000
-#define BP_CLKCTRL_HBUS_SLOW_DIV        16
-#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
-                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
-#define BP_CLKCTRL_HBUS_DIV     0
-#define BM_CLKCTRL_HBUS_DIV     0x0000001F
-#define BF_CLKCTRL_HBUS_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS (0x00000070)
-
-#define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE   0x00000800
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
-#define BP_CLKCTRL_XBUS_DIV     0
-#define BM_CLKCTRL_XBUS_DIV     0x000003FF
-#define BF_CLKCTRL_XBUS_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
-
-#define HW_CLKCTRL_XTAL (0x00000080)
-#define HW_CLKCTRL_XTAL_SET     (0x00000084)
-#define HW_CLKCTRL_XTAL_CLR     (0x00000088)
-#define HW_CLKCTRL_XTAL_TOG     (0x0000008c)
-
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_DIV_UART        0
-#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
-#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
-                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
-
-#define HW_CLKCTRL_SSP0 (0x00000090)
-
-#define BP_CLKCTRL_SSP0_CLKGATE 31
-#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP0_BUSY    0x20000000
-#define BM_CLKCTRL_SSP0_DIV_FRAC_EN     0x00000200
-#define BP_CLKCTRL_SSP0_DIV     0
-#define BM_CLKCTRL_SSP0_DIV     0x000001FF
-#define BF_CLKCTRL_SSP0_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
-
-#define HW_CLKCTRL_SSP1 (0x000000a0)
-
-#define BP_CLKCTRL_SSP1_CLKGATE 31
-#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP1_BUSY    0x20000000
-#define BM_CLKCTRL_SSP1_DIV_FRAC_EN     0x00000200
-#define BP_CLKCTRL_SSP1_DIV     0
-#define BM_CLKCTRL_SSP1_DIV     0x000001FF
-#define BF_CLKCTRL_SSP1_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
-
-#define HW_CLKCTRL_SSP2 (0x000000b0)
-
-#define BP_CLKCTRL_SSP2_CLKGATE 31
-#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP2_BUSY    0x20000000
-#define BM_CLKCTRL_SSP2_DIV_FRAC_EN     0x00000200
-#define BP_CLKCTRL_SSP2_DIV     0
-#define BM_CLKCTRL_SSP2_DIV     0x000001FF
-#define BF_CLKCTRL_SSP2_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
-
-#define HW_CLKCTRL_SSP3 (0x000000c0)
-
-#define BP_CLKCTRL_SSP3_CLKGATE 31
-#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP3_BUSY    0x20000000
-#define BM_CLKCTRL_SSP3_DIV_FRAC_EN     0x00000200
-#define BP_CLKCTRL_SSP3_DIV     0
-#define BM_CLKCTRL_SSP3_DIV     0x000001FF
-#define BF_CLKCTRL_SSP3_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
-
-#define HW_CLKCTRL_GPMI (0x000000d0)
-
-#define BP_CLKCTRL_GPMI_CLKGATE 31
-#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
-#define BP_CLKCTRL_GPMI_DIV     0
-#define BM_CLKCTRL_GPMI_DIV     0x000003FF
-#define BF_CLKCTRL_GPMI_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
-
-#define HW_CLKCTRL_SPDIF        (0x000000e0)
-
-#define BP_CLKCTRL_SPDIF_CLKGATE        31
-#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-
-#define HW_CLKCTRL_EMI  (0x000000f0)
-
-#define BP_CLKCTRL_EMI_CLKGATE  31
-#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_DIV_XTAL 8
-#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
-                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_DIV_EMI  0
-#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
-#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
-                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
-
-#define HW_CLKCTRL_SAIF0        (0x00000100)
-
-#define BP_CLKCTRL_SAIF0_CLKGATE        31
-#define BM_CLKCTRL_SAIF0_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF0_BUSY   0x20000000
-#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN    0x00010000
-#define BP_CLKCTRL_SAIF0_DIV    0
-#define BM_CLKCTRL_SAIF0_DIV    0x0000FFFF
-#define BF_CLKCTRL_SAIF0_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
-
-#define HW_CLKCTRL_SAIF1        (0x00000110)
-
-#define BP_CLKCTRL_SAIF1_CLKGATE        31
-#define BM_CLKCTRL_SAIF1_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF1_BUSY   0x20000000
-#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN    0x00010000
-#define BP_CLKCTRL_SAIF1_DIV    0
-#define BM_CLKCTRL_SAIF1_DIV    0x0000FFFF
-#define BF_CLKCTRL_SAIF1_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
-
-#define HW_CLKCTRL_DIS_LCDIF    (0x00000120)
-
-#define BP_CLKCTRL_DIS_LCDIF_CLKGATE    31
-#define BM_CLKCTRL_DIS_LCDIF_CLKGATE    0x80000000
-#define BM_CLKCTRL_DIS_LCDIF_BUSY       0x20000000
-#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN        0x00002000
-#define BP_CLKCTRL_DIS_LCDIF_DIV        0
-#define BM_CLKCTRL_DIS_LCDIF_DIV        0x00001FFF
-#define BF_CLKCTRL_DIS_LCDIF_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
-
-#define HW_CLKCTRL_ETM  (0x00000130)
-
-#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000080
-#define BP_CLKCTRL_ETM_DIV      0
-#define BM_CLKCTRL_ETM_DIV      0x0000007F
-#define BF_CLKCTRL_ETM_DIV(v)  \
-                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
-
-#define HW_CLKCTRL_ENET (0x00000140)
-
-#define BM_CLKCTRL_ENET_SLEEP   0x80000000
-#define BP_CLKCTRL_ENET_DISABLE 30
-#define BM_CLKCTRL_ENET_DISABLE 0x40000000
-#define BM_CLKCTRL_ENET_STATUS  0x20000000
-#define BM_CLKCTRL_ENET_BUSY_TIME       0x08000000
-#define BP_CLKCTRL_ENET_DIV_TIME        21
-#define BM_CLKCTRL_ENET_DIV_TIME        0x07E00000
-#define BF_CLKCTRL_ENET_DIV_TIME(v)  \
-                (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
-#define BM_CLKCTRL_ENET_BUSY    0x08000000
-#define BP_CLKCTRL_ENET_DIV     21
-#define BM_CLKCTRL_ENET_DIV     0x07E00000
-#define BF_CLKCTRL_ENET_DIV(v)  \
-                (((v) << 21) & BM_CLKCTRL_ENET_DIV)
-#define BP_CLKCTRL_ENET_TIME_SEL        19
-#define BM_CLKCTRL_ENET_TIME_SEL        0x00180000
-#define BF_CLKCTRL_ENET_TIME_SEL(v)  \
-                (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
-#define BV_CLKCTRL_ENET_TIME_SEL__XTAL      0x0
-#define BV_CLKCTRL_ENET_TIME_SEL__PLL       0x1
-#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK  0x2
-#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_ENET_CLK_OUT_EN      0x00040000
-#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP        0x00020000
-#define BM_CLKCTRL_ENET_RESET_BY_SW     0x00010000
-
-#define HW_CLKCTRL_HSADC        (0x00000150)
-
-#define BM_CLKCTRL_HSADC_RESETB 0x40000000
-#define BP_CLKCTRL_HSADC_FREQDIV        28
-#define BM_CLKCTRL_HSADC_FREQDIV        0x30000000
-#define BF_CLKCTRL_HSADC_FREQDIV(v)  \
-                (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
-
-#define HW_CLKCTRL_FLEXCAN      (0x00000160)
-
-#define BP_CLKCTRL_FLEXCAN_STOP_CAN0    30
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN0    0x40000000
-#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS  0x20000000
-#define BP_CLKCTRL_FLEXCAN_STOP_CAN1    28
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN1    0x10000000
-#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS  0x08000000
-
-#define HW_CLKCTRL_FRAC0        (0x000001b0)
-#define HW_CLKCTRL_FRAC0_SET    (0x000001b4)
-#define HW_CLKCTRL_FRAC0_CLR    (0x000001b8)
-#define HW_CLKCTRL_FRAC0_TOG    (0x000001bc)
-
-#define BP_CLKCTRL_FRAC0_CLKGATEIO0     31
-#define BM_CLKCTRL_FRAC0_CLKGATEIO0     0x80000000
-#define BM_CLKCTRL_FRAC0_IO0_STABLE     0x40000000
-#define BP_CLKCTRL_FRAC0_IO0FRAC        24
-#define BM_CLKCTRL_FRAC0_IO0FRAC        0x3F000000
-#define BF_CLKCTRL_FRAC0_IO0FRAC(v)  \
-                (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATEIO1     23
-#define BM_CLKCTRL_FRAC0_CLKGATEIO1     0x00800000
-#define BM_CLKCTRL_FRAC0_IO1_STABLE     0x00400000
-#define BP_CLKCTRL_FRAC0_IO1FRAC        16
-#define BM_CLKCTRL_FRAC0_IO1FRAC        0x003F0000
-#define BF_CLKCTRL_FRAC0_IO1FRAC(v)  \
-                (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATEEMI     15
-#define BM_CLKCTRL_FRAC0_CLKGATEEMI     0x00008000
-#define BM_CLKCTRL_FRAC0_EMI_STABLE     0x00004000
-#define BP_CLKCTRL_FRAC0_EMIFRAC        8
-#define BM_CLKCTRL_FRAC0_EMIFRAC        0x00003F00
-#define BF_CLKCTRL_FRAC0_EMIFRAC(v)  \
-                (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATECPU     7
-#define BM_CLKCTRL_FRAC0_CLKGATECPU     0x00000080
-#define BM_CLKCTRL_FRAC0_CPU_STABLE     0x00000040
-#define BP_CLKCTRL_FRAC0_CPUFRAC        0
-#define BM_CLKCTRL_FRAC0_CPUFRAC        0x0000003F
-#define BF_CLKCTRL_FRAC0_CPUFRAC(v)  \
-                (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
-
-#define HW_CLKCTRL_FRAC1        (0x000001c0)
-#define HW_CLKCTRL_FRAC1_SET    (0x000001c4)
-#define HW_CLKCTRL_FRAC1_CLR    (0x000001c8)
-#define HW_CLKCTRL_FRAC1_TOG    (0x000001cc)
-
-#define BP_CLKCTRL_FRAC1_CLKGATEGPMI    23
-#define BM_CLKCTRL_FRAC1_CLKGATEGPMI    0x00800000
-#define BM_CLKCTRL_FRAC1_GPMI_STABLE    0x00400000
-#define BP_CLKCTRL_FRAC1_GPMIFRAC       16
-#define BM_CLKCTRL_FRAC1_GPMIFRAC       0x003F0000
-#define BF_CLKCTRL_FRAC1_GPMIFRAC(v)  \
-                (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
-#define BP_CLKCTRL_FRAC1_CLKGATEHSADC   15
-#define BM_CLKCTRL_FRAC1_CLKGATEHSADC   0x00008000
-#define BM_CLKCTRL_FRAC1_HSADC_STABLE   0x00004000
-#define BP_CLKCTRL_FRAC1_HSADCFRAC      8
-#define BM_CLKCTRL_FRAC1_HSADCFRAC      0x00003F00
-#define BF_CLKCTRL_FRAC1_HSADCFRAC(v)  \
-                (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
-#define BP_CLKCTRL_FRAC1_CLKGATEPIX     7
-#define BM_CLKCTRL_FRAC1_CLKGATEPIX     0x00000080
-#define BM_CLKCTRL_FRAC1_PIX_STABLE     0x00000040
-#define BP_CLKCTRL_FRAC1_PIXFRAC        0
-#define BM_CLKCTRL_FRAC1_PIXFRAC        0x0000003F
-#define BF_CLKCTRL_FRAC1_PIXFRAC(v)  \
-                (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
-
-#define HW_CLKCTRL_CLKSEQ       (0x000001d0)
-#define HW_CLKCTRL_CLKSEQ_SET   (0x000001d4)
-#define HW_CLKCTRL_CLKSEQ_CLR   (0x000001d8)
-#define HW_CLKCTRL_CLKSEQ_TOG   (0x000001dc)
-
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00040000
-#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF      0x00004000
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000080
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3   0x00000040
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2   0x00000020
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1   0x00000010
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0   0x00000008
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000004
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1  0x00000002
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0  0x00000001
-
-#define HW_CLKCTRL_RESET        (0x000001e0)
-
-#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE       0x00000020
-#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE  0x00000010
-#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE   0x00000008
-#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT  0x00000004
-#define BM_CLKCTRL_RESET_CHIP   0x00000002
-#define BM_CLKCTRL_RESET_DIG    0x00000001
-
-#define HW_CLKCTRL_STATUS       (0x000001f0)
-
-#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
-                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-
-#define HW_CLKCTRL_VERSION      (0x00000200)
-
-#define BP_CLKCTRL_VERSION_MAJOR        24
-#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) \
-                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
-#define BP_CLKCTRL_VERSION_MINOR        16
-#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
-#define BF_CLKCTRL_VERSION_MINOR(v)  \
-                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
-#define BP_CLKCTRL_VERSION_STEP 0
-#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
-#define BF_CLKCTRL_VERSION_STEP(v)  \
-                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
-
-#endif /* __REGS_CLKCTRL_MX28_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 80ac1fca8a00..30042e23bfa7 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -37,8 +37,6 @@
 #define MXS_MODULE_CLKGATE              (1 << 30)
 #define MXS_MODULE_SFTRST               (1 << 31)
 
-#define CLKCTRL_TIMEOUT         10      /* 10 ms */
-
 static void __iomem *mxs_clkctrl_reset_addr;
 
 /*
@@ -139,17 +137,3 @@ error:
         return -ETIMEDOUT;
 }
 EXPORT_SYMBOL(mxs_reset_block);
-
-int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
-{
-        unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
-        while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
-                                                + reg_offset) & mask) {
-                if (time_after(jiffies, timeout)) {
-                        pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
-                        return -ETIMEDOUT;
-                }
-        }
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 564a63279f18..02d36de9c4e8 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -20,6 +20,7 @@
  * MA 02110-1301, USA.
  */
 
+#include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clockchips.h>
@@ -243,8 +244,16 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxs_timer_init(struct clk *timer_clk, int irq)
+void __init mxs_timer_init(int irq)
 {
+        struct clk *timer_clk;
+
+        timer_clk = clk_get_sys("timrot", NULL);
+        if (IS_ERR(timer_clk)) {
+                pr_err("%s: failed to get clk\n", __func__);
+                return;
+        }
+
         clk_prepare_enable(timer_clk);
 
         /*
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index c54cef25895c..cbf51ae81855 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -17,6 +17,7 @@
  *
  * bit     23 - Input/Output (PXA2xx specific)
  * bit     24 - Wakeup Enable(PXA2xx specific)
+ * bit     25 - Keep Output  (PXA2xx specific)
  */
 
 #define MFP_DIR_IN              (0x0 << 23)
@@ -25,6 +26,12 @@
 #define MFP_DIR(x)              (((x) >> 23) & 0x1)
 
 #define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+
+/*
+ * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
+ * retain their last output level (low or high).
+ * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
+ */
 #define MFP_LPM_KEEP_OUTPUT     (0x1 << 25)
 
 #define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index b0a842887780..ef0426a159d4 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -33,6 +33,8 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPLR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5))
 #define GPDR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
+#define GPSR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
+#define GPCR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
 
 #define PWER_WE35       (1 << 24)
 
@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
 #ifdef CONFIG_PM
 static unsigned long saved_gafr[2][4];
 static unsigned long saved_gpdr[4];
+static unsigned long saved_gplr[4];
 static unsigned long saved_pgsr[4];
 
 static int pxa2xx_mfp_suspend(void)
@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
         }
 
         for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
-
                 saved_gafr[0][i] = GAFR_L(i);
                 saved_gafr[1][i] = GAFR_U(i);
                 saved_gpdr[i] = GPDR(i * 32);
+                saved_gplr[i] = GPLR(i * 32);
                 saved_pgsr[i] = PGSR(i);
 
-                GPDR(i * 32) = gpdr_lpm[i];
+                GPSR(i * 32) = PGSR(i);
+                GPCR(i * 32) = ~PGSR(i);
+        }
+
+        /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
+        for (i = 0; i < pxa_last_gpio; i++) {
+                if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
+                    ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
+                     (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
+                        GPDR(i) |= GPIO_bit(i);
+                else
+                        GPDR(i) &= ~GPIO_bit(i);
         }
+
         return 0;
 }
 
@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
         for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                 GAFR_L(i) = saved_gafr[0][i];
                 GAFR_U(i) = saved_gafr[1][i];
+                GPSR(i * 32) = saved_gplr[i];
+                GPCR(i * 32) = ~saved_gplr[i];
                 GPDR(i * 32) = saved_gpdr[i];
                 PGSR(i) = saved_pgsr[i];
         }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78edce7a..4726c246dcdc 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
         pxa_register_device(&pxa27x_device_i2c_power, info);
 }
 
+static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
+        .gpio_set_wake = gpio_set_wake,
+};
+
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
@@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
+                pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0f3a327ebcaa..b34287ab5afd 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
         help
           Compile in platform device definition for Samsung TouchScreen.
 
-# cpu-specific sections
-
-if CPU_S3C2410
-
 config S3C2410_DMA
         bool
         depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -127,6 +123,10 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
+# cpu-specific sections
+
+if CPU_S3C2410
+
 config S3C24XX_SIMTEC_NOR
         bool
         help
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index a8933de3d627..32395664e879 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 #include <linux/interrupt.h>
 
 #include <asm/hardware/vic.h>
@@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
 /* MoviNAND */
 static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
         .max_width              = 4,
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
 
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 7c524b4e415d..16be4c56abe3 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
 }
 
 static struct resource sa1100_rtc_resources[] = {
-        DEFINE_RES_MEM(0x90010000, 0x9001003f),
+        DEFINE_RES_MEM(0x90010000, 0x40),
         DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
         DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
 };
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-        bool "SPEAr300 Evaluation Board"
-        select MACH_SPEAR300
-        help
-          Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-        bool "SPEAr310 Evaluation Board"
-        select MACH_SPEAR310
-        help
-          Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-        bool "SPEAr320 Evaluation Board"
-        select MACH_SPEAR320
-        help
-          Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-        bool "SPEAr300"
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
         help
-          Supports ST SPEAr300 Machine
+          Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-        bool "SPEAr310"
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
         help
-          Supports ST SPEAr310 Machine
+          Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-        bool "SPEAr320"
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
         help
-          Supports ST SPEAr320 Machine
-
+          Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y   += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/clock.c
- *
- * SPEAr3xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/mach-types.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 32000,
-};
-
-/* 24 MHz oscillator clock */
-static struct clk osc_24m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 24000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-        .pclk = &osc_32k_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = RTC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from 24 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-        .mode_mask = PLL_MODE_MASK,
-        .mode_shift = PLL_MODE_SHIFT,
-        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-        .div_p_mask = PLL_DIV_P_MASK,
-        .div_p_shift = PLL_DIV_P_SHIFT,
-        .div_n_mask = PLL_DIV_N_MASK,
-        .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-        .mode_reg = PLL1_CTR,
-        .cfg_reg = PLL1_FRQ,
-        .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-        .flags = ENABLED_ON_INIT,
-        .pclk = &osc_24m_clk,
-        .en_reg = PLL1_CTR,
-        .en_reg_bit = PLL_ENABLE,
-        .calc_rate = &pll_calc_rate,
-        .recalc = &pll_clk_recalc,
-        .set_rate = &pll_clk_set_rate,
-        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-        .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-        {.div = 3}, /* == parent divided by 4 */
-        {.div = 2}, /* == parent divided by 3 */
-        {.div = 1}, /* == parent divided by 2 */
-        {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-        .eq_sel_mask = AUX_EQ_SEL_MASK,
-        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-        .eq1_mask = AUX_EQ1_SEL,
-        .eq2_mask = AUX_EQ2_SEL,
-        .xscale_sel_mask = AUX_XSCALE_MASK,
-        .xscale_sel_shift = AUX_XSCALE_SHIFT,
-        .yscale_sel_mask = AUX_YSCALE_MASK,
-        .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart synth configurations */
-static struct aux_clk_config uart_synth_config = {
-        .synth_reg = UART_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-        /* For PLL1 = 332 MHz */
-        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-        .en_reg = UART_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-        .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-        {
-                .pclk = &uart_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-        .pclk_info = uart_pclk_info,
-        .pclk_count = ARRAY_SIZE(uart_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart clock */
-static struct clk uart_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-        .synth_reg = FIRDA_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-        .en_reg = FIRDA_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-        .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-        {
-                .pclk = &firda_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-        .pclk_info = firda_pclk_info,
-        .pclk_count = ARRAY_SIZE(firda_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FIRDA_CLK_ENB,
-        .pclk_sel = &firda_pclk_sel,
-        .pclk_sel_shift = FIRDA_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-        .mscale_sel_mask = GPT_MSCALE_MASK,
-        .mscale_sel_shift = GPT_MSCALE_SHIFT,
-        .nscale_sel_mask = GPT_NSCALE_MASK,
-        .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-        /* For pll1 = 332 MHz */
-        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-        {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-        .synth_reg = PRSC1_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-        {
-                .pclk = &gpt0_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 timer clock */
-static struct clk gpt0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt0_pclk_sel,
-        .pclk_sel_shift = GPT0_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt1 synth clk configurations */
-static struct gpt_clk_config gpt1_synth_config = {
-        .synth_reg = PRSC2_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt1_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt1_synth_config,
-};
-
-static struct pclk_info gpt1_pclk_info[] = {
-        {
-                .pclk = &gpt1_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-        .pclk_info = gpt1_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPT1_CLK_ENB,
-        .pclk_sel = &gpt1_pclk_sel,
-        .pclk_sel_shift = GPT1_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk configurations */
-static struct gpt_clk_config gpt2_synth_config = {
-        .synth_reg = PRSC3_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt2_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt2_synth_config,
-};
-
-static struct pclk_info gpt2_pclk_info[] = {
-        {
-                .pclk = &gpt2_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-        .pclk_info = gpt2_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPT2_CLK_ENB,
-        .pclk_sel = &gpt2_pclk_sel,
-        .pclk_sel_shift = GPT2_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh clock */
-static struct clk usbh_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBD_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-        .mask = HCLK_PCLK_RATIO_MASK,
-        .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = I2C_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = DMA_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = JPEG_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GMAC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SMI_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* c3 clock */
-static struct clk c3_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = C3_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = ADC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* emi clock */
-static struct clk emi_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* ssp clock */
-static struct clk ssp0_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio clock */
-static struct clk gpio_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
-        defined(CONFIG_MACH_SPEAR320)
-/* fsmc clock */
-static struct clk fsmc_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* uart1 clock */
-static struct clk uart1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart2 clock */
-static struct clk uart2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
-/* common clocks to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
-/* clcd clock */
-static struct clk clcd_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll3_48m_clk,
-        .recalc = &follow_parent,
-};
-
-/* sdhci clock */
-static struct clk sdhci_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
-
-/* spear300 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR300
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* keyboard clock */
-static struct clk kbd_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-#endif
-
-/* spear310 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR310
-/* uart3 clock */
-static struct clk uart3_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart4 clock */
-static struct clk uart4_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart5 clock */
-static struct clk uart5_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* spear320 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR320
-/* can0 clock */
-static struct clk can0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* can1 clock */
-static struct clk can1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* i2c1 clock */
-static struct clk i2c1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* pwm clock */
-static struct clk pwm_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* array of all spear 3xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
-        /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-        /* clock derived from 24 MHz osc clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
-        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .dev_id = "uart",             .clk = &uart_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh_clk",         .clk = &usbh_clk},
-        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "c3",               .clk = &c3_clk},
-        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "gpio",             .clk = &gpio_clk},
-};
-
-/* array of all spear 300 clock lookups */
-#ifdef CONFIG_MACH_SPEAR300
-static struct clk_lookup spear300_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
-        { .dev_id = "keyboard",         .clk = &kbd_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-};
-#endif
-
-/* array of all spear 310 clock lookups */
-#ifdef CONFIG_MACH_SPEAR310
-static struct clk_lookup spear310_clk_lookups[] = {
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-        { .dev_id = "uart3",            .clk = &uart3_clk},
-        { .dev_id = "uart4",            .clk = &uart4_clk},
-        { .dev_id = "uart5",            .clk = &uart5_clk},
-};
-#endif
-
-/* array of all spear 320 clock lookups */
-#ifdef CONFIG_MACH_SPEAR320
-static struct clk_lookup spear320_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "pwm",              .clk = &pwm_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
-        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
-{
-        int i, cnt;
-        struct clk_lookup *lookups;
-
-        if (machine_is_spear300()) {
-                cnt = ARRAY_SIZE(spear300_clk_lookups);
-                lookups = spear300_clk_lookups;
-        } else if (machine_is_spear310()) {
-                cnt = ARRAY_SIZE(spear310_clk_lookups);
-                lookups = spear310_clk_lookups;
-        } else {
-                cnt = ARRAY_SIZE(spear320_clk_lookups);
-                lookups = spear320_clk_lookups;
-        }
-
-        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-                clk_register(&spear_clk_lookups[i]);
-
-        for (i = 0; i < cnt; i++)
-                clk_register(&lookups[i]);
-
-        clk_init();
-}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,189 +14,24 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/padmux.h>
-
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
+void __init spear_setup_of_timer(void);
 void __init spear3xx_clk_init(void);
-void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
-/* pad mux declarations */
-#define PMX_FIRDA_MASK          (1 << 14)
-#define PMX_I2C_MASK            (1 << 13)
-#define PMX_SSP_CS_MASK         (1 << 12)
-#define PMX_SSP_MASK            (1 << 11)
-#define PMX_MII_MASK            (1 << 10)
-#define PMX_GPIO_PIN0_MASK      (1 << 9)
-#define PMX_GPIO_PIN1_MASK      (1 << 8)
-#define PMX_GPIO_PIN2_MASK      (1 << 7)
-#define PMX_GPIO_PIN3_MASK      (1 << 6)
-#define PMX_GPIO_PIN4_MASK      (1 << 5)
-#define PMX_GPIO_PIN5_MASK      (1 << 4)
-#define PMX_UART0_MODEM_MASK    (1 << 3)
-#define PMX_UART0_MASK          (1 << 2)
-#define PMX_TIMER_3_4_MASK      (1 << 1)
-#define PMX_TIMER_1_2_MASK      (1 << 0)
-
-/* pad mux devices */
-extern struct pmx_dev spear3xx_pmx_firda;
-extern struct pmx_dev spear3xx_pmx_i2c;
-extern struct pmx_dev spear3xx_pmx_ssp_cs;
-extern struct pmx_dev spear3xx_pmx_ssp;
-extern struct pmx_dev spear3xx_pmx_mii;
-extern struct pmx_dev spear3xx_pmx_gpio_pin0;
-extern struct pmx_dev spear3xx_pmx_gpio_pin1;
-extern struct pmx_dev spear3xx_pmx_gpio_pin2;
-extern struct pmx_dev spear3xx_pmx_gpio_pin3;
-extern struct pmx_dev spear3xx_pmx_gpio_pin4;
-extern struct pmx_dev spear3xx_pmx_gpio_pin5;
-extern struct pmx_dev spear3xx_pmx_uart0_modem;
-extern struct pmx_dev spear3xx_pmx_uart0;
-extern struct pmx_dev spear3xx_pmx_timer_3_4;
-extern struct pmx_dev spear3xx_pmx_timer_1_2;
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* padmux plgpio devices */
-extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
-extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
-extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
-extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
-extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
-extern struct pmx_dev spear3xx_pmx_plgpio_28;
-extern struct pmx_dev spear3xx_pmx_plgpio_29;
-extern struct pmx_dev spear3xx_pmx_plgpio_30;
-extern struct pmx_dev spear3xx_pmx_plgpio_31;
-extern struct pmx_dev spear3xx_pmx_plgpio_32;
-extern struct pmx_dev spear3xx_pmx_plgpio_33;
-extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
-extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
-extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
-extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
-#endif
-
-/* spear300 declarations */
-#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
-/* pad mux modes */
-extern struct pmx_mode spear300_nand_mode;
-extern struct pmx_mode spear300_nor_mode;
-extern struct pmx_mode spear300_photo_frame_mode;
-extern struct pmx_mode spear300_lend_ip_phone_mode;
-extern struct pmx_mode spear300_hend_ip_phone_mode;
-extern struct pmx_mode spear300_lend_wifi_phone_mode;
-extern struct pmx_mode spear300_hend_wifi_phone_mode;
-extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
-extern struct pmx_mode spear300_ata_pabx_i2s_mode;
-extern struct pmx_mode spear300_caml_lcdw_mode;
-extern struct pmx_mode spear300_camu_lcd_mode;
-extern struct pmx_mode spear300_camu_wlcd_mode;
-extern struct pmx_mode spear300_caml_lcd_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear300_pmx_fsmc_2_chips;
-extern struct pmx_dev spear300_pmx_fsmc_4_chips;
-extern struct pmx_dev spear300_pmx_keyboard;
-extern struct pmx_dev spear300_pmx_clcd;
-extern struct pmx_dev spear300_pmx_telecom_gpio;
-extern struct pmx_dev spear300_pmx_telecom_tdm;
-extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev spear300_pmx_telecom_camera;
-extern struct pmx_dev spear300_pmx_telecom_dac;
-extern struct pmx_dev spear300_pmx_telecom_i2s;
-extern struct pmx_dev spear300_pmx_telecom_boot_pins;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
-extern struct pmx_dev spear300_pmx_gpio1;
-
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR300 */
-
-/* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
-/* pad mux devices */
-extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev spear310_pmx_emi_cs_2_3;
-extern struct pmx_dev spear310_pmx_uart1;
-extern struct pmx_dev spear310_pmx_uart2;
-extern struct pmx_dev spear310_pmx_uart3_4_5;
-extern struct pmx_dev spear310_pmx_fsmc;
-extern struct pmx_dev spear310_pmx_rs485_0_1;
-extern struct pmx_dev spear310_pmx_tdm0;
-
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR310 */
-
-/* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
-/* pad mux modes */
-extern struct pmx_mode spear320_auto_net_smii_mode;
-extern struct pmx_mode spear320_auto_net_mii_mode;
-extern struct pmx_mode spear320_auto_exp_mode;
-extern struct pmx_mode spear320_small_printers_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear320_pmx_clcd;
-extern struct pmx_dev spear320_pmx_emi;
-extern struct pmx_dev spear320_pmx_fsmc;
-extern struct pmx_dev spear320_pmx_spp;
-extern struct pmx_dev spear320_pmx_sdhci;
-extern struct pmx_dev spear320_pmx_i2s;
-extern struct pmx_dev spear320_pmx_uart1;
-extern struct pmx_dev spear320_pmx_uart1_modem;
-extern struct pmx_dev spear320_pmx_uart2;
-extern struct pmx_dev spear320_pmx_touchscreen;
-extern struct pmx_dev spear320_pmx_can;
-extern struct pmx_dev spear320_pmx_sdhci_led;
-extern struct pmx_dev spear320_pmx_pwm0;
-extern struct pmx_dev spear320_pmx_pwm1;
-extern struct pmx_dev spear320_pmx_pwm2;
-extern struct pmx_dev spear320_pmx_pwm3;
-extern struct pmx_dev spear320_pmx_ssp1;
-extern struct pmx_dev spear320_pmx_ssp2;
-extern struct pmx_dev spear320_pmx_mii1;
-extern struct pmx_dev spear320_pmx_smii0;
-extern struct pmx_dev spear320_pmx_smii1;
-extern struct pmx_dev spear320_pmx_i2c1;
-
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR320 */
-
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-/* SPEAr3xx IRQ definitions */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0             0
+/* FIXME: probe all these from DT */
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM           1
-#define SPEAR3XX_IRQ_CPU_GPT1_1                 2
-#define SPEAR3XX_IRQ_CPU_GPT1_2                 3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1               4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2               5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1               6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2               7
-#define SPEAR3XX_IRQ_BASIC_DMA                  8
-#define SPEAR3XX_IRQ_BASIC_SMI                  9
-#define SPEAR3XX_IRQ_BASIC_RTC                  10
-#define SPEAR3XX_IRQ_BASIC_GPIO                 11
-#define SPEAR3XX_IRQ_BASIC_WDT                  12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER             13
-#define SPEAR3XX_IRQ_SYS_ERROR                  14
-#define SPEAR3XX_IRQ_WAKEUP_RCV                 15
-#define SPEAR3XX_IRQ_JPEG                       16
-#define SPEAR3XX_IRQ_IRDA                       17
-#define SPEAR3XX_IRQ_ADC                        18
-#define SPEAR3XX_IRQ_UART                       19
-#define SPEAR3XX_IRQ_SSP                        20
-#define SPEAR3XX_IRQ_I2C                        21
-#define SPEAR3XX_IRQ_MAC_1                      22
-#define SPEAR3XX_IRQ_MAC_2                      23
-#define SPEAR3XX_IRQ_USB_DEV                    24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0               25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0               26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1               SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1               27
 #define SPEAR3XX_IRQ_GEN_RAS_1                  28
 #define SPEAR3XX_IRQ_GEN_RAS_2                  29
 #define SPEAR3XX_IRQ_GEN_RAS_3                  30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1             31
 #define SPEAR3XX_IRQ_VIC_END                    32
-
 #define SPEAR3XX_VIRQ_START                     SPEAR3XX_IRQ_VIC_END
 
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 9)
-#endif
-
-#define SPEAR300_GPIO1_INT_BASE                 (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT   102
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE                (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END                   (SPEAR3XX_PLGPIO_INT_BASE + \
-                                                        SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END   (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-
-#define SPEAR3XX_VIRQ_END       SPEAR3XX_GPIO_INT_END
-#define NR_IRQS                 SPEAR3XX_VIRQ_END
+#define NR_IRQS                 160
 
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          11
-#define GPT2_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB            3
-#define SSP_CLK_ENB             5
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FIRDA_CLK_ENB           10
-#define GPT1_CLK_ENB            11
-#define GPT2_CLK_ENB            12
-#define ADC_CLK_ENB             15
-#define RTC_CLK_ENB             17
-#define GPIO_CLK_ENB            18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH_CLK_ENB            25
-#define C3_CLK_ENB              31
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,26 @@
 #define __MACH_SPEAR3XX_H
 
 #include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-
-#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
-
-#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
+#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
@@ -78,4 +44,17 @@
 #define SPEAR_SYS_CTRL_BASE             SPEAR3XX_ICM3_SYS_CTRL_BASE
 #define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
 
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE     UL(0xFE000000)
+#define SPEAR320_CONTROL_REG            IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
+#define SPEAR320_EXT_CTRL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
+        #define SPEAR320_UARTX_PCLK_MASK                0x1
+        #define SPEAR320_UART2_PCLK_SHIFT               8
+        #define SPEAR320_UART3_PCLK_SHIFT               9
+        #define SPEAR320_UART4_PCLK_SHIFT               10
+        #define SPEAR320_UART5_PCLK_SHIFT               11
+        #define SPEAR320_UART6_PCLK_SHIFT               12
+        #define SPEAR320_RS485_PCLK_SHIFT               13
+
 #endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR300
-
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG       0x54
-#define SPEAR300_INT_STS_MASK_REG       0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-
-#define SPEAR300_CLCD_BASE              UL(0x60000000)
-#define SPEAR300_SDHCI_BASE             UL(0x70000000)
-#define SPEAR300_NAND_0_BASE            UL(0x80000000)
-#define SPEAR300_NAND_1_BASE            UL(0x84000000)
-#define SPEAR300_NAND_2_BASE            UL(0x88000000)
-#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE             UL(0x90000000)
-#define SPEAR300_NOR_1_BASE             UL(0x91000000)
-#define SPEAR300_NOR_2_BASE             UL(0x92000000)
-#define SPEAR300_NOR_3_BASE             UL(0x93000000)
-#define SPEAR300_FSMC_BASE              UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
-#define SPEAR300_GPIO_BASE              UL(0xA9000000)
-
-#endif /* __MACH_SPEAR300_H */
-
-#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR310
-
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-
-#define SPEAR310_NAND_BASE              UL(0x40000000)
-#define SPEAR310_FSMC_BASE              UL(0x44000000)
-#define SPEAR310_UART1_BASE             UL(0xB2000000)
-#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define SPEAR310_UART3_BASE             UL(0xB2100000)
-#define SPEAR310_UART4_BASE             UL(0xB2180000)
-#define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_HDLC_BASE              UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG       0x04
-#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-
-#endif /* __MACH_SPEAR310_H */
-
-#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR320
-
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-
-#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
-#define SPEAR320_FSMC_BASE              UL(0x4C000000)
-#define SPEAR320_NAND_BASE              UL(0x50000000)
-#define SPEAR320_I2S_BASE               UL(0x60000000)
-#define SPEAR320_SDHCI_BASE             UL(0x70000000)
-#define SPEAR320_CLCD_BASE              UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
-#define SPEAR320_CAN0_BASE              UL(0xA1000000)
-#define SPEAR320_CAN1_BASE              UL(0xA2000000)
-#define SPEAR320_UART1_BASE             UL(0xA3000000)
-#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define SPEAR320_SSP1_BASE              UL(0xA6000000)
-#define SPEAR320_I2C_BASE               UL(0xA7000000)
-#define SPEAR320_PWM_BASE               UL(0xA8000000)
-#define SPEAR320_SMII0_BASE             UL(0xAA000000)
-#define SPEAR320_SMII1_BASE             UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG               0x04
-#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-
-#endif /* __MACH_SPEAR320_H */
-
-#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,372 +3,62 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x00
-#define MODE_CONFIG_REG         0x04
-
-/* modes */
-#define NAND_MODE                       (1 << 0)
-#define NOR_MODE                        (1 << 1)
-#define PHOTO_FRAME_MODE                (1 << 2)
-#define LEND_IP_PHONE_MODE              (1 << 3)
-#define HEND_IP_PHONE_MODE              (1 << 4)
-#define LEND_WIFI_PHONE_MODE            (1 << 5)
-#define HEND_WIFI_PHONE_MODE            (1 << 6)
-#define ATA_PABX_WI2S_MODE              (1 << 7)
-#define ATA_PABX_I2S_MODE               (1 << 8)
-#define CAML_LCDW_MODE                  (1 << 9)
-#define CAMU_LCD_MODE                   (1 << 10)
-#define CAMU_WLCD_MODE                  (1 << 11)
-#define CAML_LCD_MODE                   (1 << 12)
-#define ALL_MODES                       0x1FFF
-
-struct pmx_mode spear300_nand_mode = {
-        .id = NAND_MODE,
-        .name = "nand mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear300_nor_mode = {
-        .id = NOR_MODE,
-        .name = "nor mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear300_photo_frame_mode = {
-        .id = PHOTO_FRAME_MODE,
-        .name = "photo frame mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear300_lend_ip_phone_mode = {
-        .id = LEND_IP_PHONE_MODE,
-        .name = "lend ip phone mode",
-        .mask = 0x03,
-};
-
-struct pmx_mode spear300_hend_ip_phone_mode = {
-        .id = HEND_IP_PHONE_MODE,
-        .name = "hend ip phone mode",
-        .mask = 0x04,
-};
-
-struct pmx_mode spear300_lend_wifi_phone_mode = {
-        .id = LEND_WIFI_PHONE_MODE,
-        .name = "lend wifi phone mode",
-        .mask = 0x05,
-};
-
-struct pmx_mode spear300_hend_wifi_phone_mode = {
-        .id = HEND_WIFI_PHONE_MODE,
-        .name = "hend wifi phone mode",
-        .mask = 0x06,
-};
-
-struct pmx_mode spear300_ata_pabx_wi2s_mode = {
-        .id = ATA_PABX_WI2S_MODE,
-        .name = "ata pabx wi2s mode",
-        .mask = 0x07,
-};
-
-struct pmx_mode spear300_ata_pabx_i2s_mode = {
-        .id = ATA_PABX_I2S_MODE,
-        .name = "ata pabx i2s mode",
-        .mask = 0x08,
-};
-
-struct pmx_mode spear300_caml_lcdw_mode = {
-        .id = CAML_LCDW_MODE,
-        .name = "caml lcdw mode",
-        .mask = 0x0C,
-};
-
-struct pmx_mode spear300_camu_lcd_mode = {
-        .id = CAMU_LCD_MODE,
-        .name = "camu lcd mode",
-        .mask = 0x0D,
-};
-
-struct pmx_mode spear300_camu_wlcd_mode = {
-        .id = CAMU_WLCD_MODE,
-        .name = "camu wlcd mode",
-        .mask = 0x0E,
-};
-
-struct pmx_mode spear300_caml_lcd_mode = {
-        .id = CAML_LCD_MODE,
-        .name = "caml lcd mode",
-        .mask = 0x0F,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_2_chips = {
-        .name = "fsmc_2_chips",
-        .modes = pmx_fsmc_2_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_4_chips = {
-        .name = "fsmc_4_chips",
-        .modes = pmx_fsmc_4_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
-                        CAML_LCD_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear300_pmx_keyboard = {
-        .name = "keyboard",
-        .modes = pmx_keyboard_modes,
-        .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
-        }, {
-                .ids = ATA_PABX_WI2S_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
-                        | PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_gpio = {
-        .name = "telecom_gpio",
-        .modes = pmx_telecom_gpio_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
-                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
-                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_tdm = {
-        .name = "telecom_tdm",
-        .modes = pmx_telecom_tdm_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
-                        | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
-                        CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
-        .name = "telecom_spi_cs_i2c_clk",
-        .modes = pmx_telecom_spi_cs_i2c_clk_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
-        {
-                .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_camera = {
-        .name = "telecom_camera",
-        .modes = pmx_telecom_camera_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
-        {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_dac = {
-        .name = "telecom_dac",
-        .modes = pmx_telecom_dac_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
-                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_i2s = {
-        .name = "telecom_i2s",
-        .modes = pmx_telecom_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_boot_pins = {
-        .name = "telecom_boot_pins",
-        .modes = pmx_telecom_boot_pins_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
-                        ATA_PABX_I2S_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
-        .name = "telecom_sdhci_4bit",
-        .modes = pmx_telecom_sdhci_4bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
-        .name = "telecom_sdhci_8bit",
-        .modes = pmx_telecom_sdhci_8bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_gpio1_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_gpio1 = {
-        .name = "arm gpio1",
-        .modes = pmx_gpio1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG       0x54
+#define SPEAR300_INT_STS_MASK_REG       0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
+
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
+
+
+/* SPEAr300 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = {
         },
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-        .gpio_base      = 8,
-        .irq_base       = SPEAR300_GPIO1_INT_BASE,
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-        int ret = 0;
+        int ret;
+
+        pl080_plat_data.slave_channels = spear300_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear300_auxdata_lookup, NULL);
 
         /* shared irq registration */
         shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
         if (shirq_ras1.regs.base) {
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ\n");
+                        pr_err("Error registering Shared IRQ\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear300_dt_board_compat[] = {
+        "st,spear300",
+        "st,spear300-evb",
+        NULL,
+};
 
-        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-        if (pmx_driver.base) {
-                ret = pmx_register(&pmx_driver);
-                if (ret)
-                        printk(KERN_ERR "padmux: registration failed. err no"
-                                        ": %d\n", ret);
-                /* Free Mapping, device selection already done */
-                iounmap(pmx_driver.base);
-        }
+static void __init spear300_map_io(void)
+{
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+        .map_io         =       spear300_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp_cs,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear300 specific devices */
-        &spear300_pmx_fsmc_2_chips,
-        &spear300_pmx_clcd,
-        &spear300_pmx_telecom_sdhci_4bit,
-        &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear300 specific devices */
-        &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear300 machine init function */
-        spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear300_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,141 +3,84 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x08
-
-/* devices */
-static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
-        .name = "emi_cs_0_1_4_5",
-        .modes = pmx_emi_cs_0_1_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_2_3 = {
-        .name = "emi_cs_2_3",
-        .modes = pmx_emi_cs_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart3_4_5 = {
-        .name = "uart3_4_5",
-        .modes = pmx_uart3_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_rs485_0_1 = {
-        .name = "rs485_0_1",
-        .modes = pmx_rs485_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_tdm0_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_tdm0 = {
-        .name = "tdm0",
-        .modes = pmx_tdm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
-        .enb_on_reset = 1,
-};
+#include <mach/spear.h>
+
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG       0x04
+#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
+
+/* SPEAr310 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
 
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear310 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart3_tx",
+                .dma_rx_param = "uart3_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart4_tx",
+                .dma_rx_param = "uart4_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart5_tx",
+                .dma_rx_param = "uart5_rx",
+        },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                        &spear310_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                        &spear310_uart_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                        &spear310_uart_data[2]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                        &spear310_uart_data[3]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                        &spear310_uart_data[4]),
+        {}
+};
+
+static void __init spear310_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear310_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear310_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 2 */
                 shirq_ras2.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras2);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                        pr_err("Error registering Shared IRQ 2\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+        "st,spear310",
+        "st,spear310-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear310_map_io(void)
+{
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+        .map_io         =       spear310_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_gpio_pin0,
-        &spear3xx_pmx_gpio_pin1,
-        &spear3xx_pmx_gpio_pin2,
-        &spear3xx_pmx_gpio_pin3,
-        &spear3xx_pmx_gpio_pin4,
-        &spear3xx_pmx_gpio_pin5,
-        &spear3xx_pmx_uart0,
-
-        /* spear310 specific devices */
-        &spear310_pmx_emi_cs_0_1_4_5,
-        &spear310_pmx_emi_cs_2_3,
-        &spear310_pmx_uart1,
-        &spear310_pmx_uart2,
-        &spear310_pmx_uart3_4_5,
-        &spear310_pmx_fsmc,
-        &spear310_pmx_rs485_0_1,
-        &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear310 machine init function */
-        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear310_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,386 +3,84 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x0C
-#define MODE_CONFIG_REG         0x10
-
-/* modes */
-#define AUTO_NET_SMII_MODE      (1 << 0)
-#define AUTO_NET_MII_MODE       (1 << 1)
-#define AUTO_EXP_MODE           (1 << 2)
-#define SMALL_PRINTERS_MODE     (1 << 3)
-#define ALL_MODES               0xF
-
-struct pmx_mode spear320_auto_net_smii_mode = {
-        .id = AUTO_NET_SMII_MODE,
-        .name = "Automation Networking SMII Mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear320_auto_net_mii_mode = {
-        .id = AUTO_NET_MII_MODE,
-        .name = "Automation Networking MII Mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear320_auto_exp_mode = {
-        .id = AUTO_EXP_MODE,
-        .name = "Automation Expanded Mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear320_small_printers_mode = {
-        .id = SMALL_PRINTERS_MODE,
-        .name = "Small Printers Mode",
-        .mask = 0x03,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_emi = {
-        .name = "emi",
-        .modes = pmx_emi_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_spp_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_spp = {
-        .name = "spp",
-        .modes = pmx_spp_modes,
-        .mode_count = ARRAY_SIZE(pmx_spp_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
-                        SMALL_PRINTERS_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci = {
-        .name = "sdhci",
-        .modes = pmx_sdhci_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2s_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2s = {
-        .name = "i2s",
-        .modes = pmx_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
-                        PMX_SSP_CS_MASK,
-        }, {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
-                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1_modem = {
-        .name = "uart1_modem",
-        .modes = pmx_uart1_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_touchscreen_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_touchscreen = {
-        .name = "touchscreen",
-        .modes = pmx_touchscreen_modes,
-        .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_can_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
-                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_can = {
-        .name = "can",
-        .modes = pmx_can_modes,
-        .mode_count = ARRAY_SIZE(pmx_can_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci_led = {
-        .name = "sdhci_led",
-        .modes = pmx_sdhci_led_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm0 = {
-        .name = "pwm0",
-        .modes = pmx_pwm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm1 = {
-        .name = "pwm1",
-        .modes = pmx_pwm1_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm2 = {
-        .name = "pwm2",
-        .modes = pmx_pwm2_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm3_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm3 = {
-        .name = "pwm3",
-        .modes = pmx_pwm3_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp1_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp1 = {
-        .name = "ssp1",
-        .modes = pmx_ssp1_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp2 = {
-        .name = "ssp2",
-        .modes = pmx_ssp2_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_mii1_modes[] = {
-        {
-                .ids = AUTO_NET_MII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_mii1 = {
-        .name = "mii1",
-        .modes = pmx_mii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii0 = {
-        .name = "smii0",
-        .modes = pmx_smii0_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii1 = {
-        .name = "smii1",
-        .modes = pmx_smii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2c1_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2c1 = {
-        .name = "i2c1",
-        .modes = pmx_i2c1_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG               0x04
+#define SPEAR320_INT_CLR_MASK_REG               0x04
+#define SPEAR320_INT_ENB_MASK_REG               0x08
+#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
+
+/* SPEAr320 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -508,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear320 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+        {
+                .bus_id = 1,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp1_tx",
+                .dma_rx_param = "ssp1_rx",
+                .num_chipselect = 2,
+        }, {
+                .bus_id = 2,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp2_tx",
+                .dma_rx_param = "ssp2_rx",
+                .num_chipselect = 2,
+        }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        },
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                        &spear320_ssp_data[0]),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                        &spear320_ssp_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                        &spear320_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                        &spear320_uart_data[1]),
+        {}
+};
+
+static void __init spear320_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear320_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear320_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
+
+static const char * const spear320_dt_board_compat[] = {
+        "st,spear320",
+        "st,spear320-evb",
+        NULL,
+};
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+struct map_desc spear320_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+                .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        },
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear320_map_io(void)
+{
+        iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+        .map_io         =       spear320_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear320 specific devices */
-        &spear320_pmx_fsmc,
-        &spear320_pmx_sdhci,
-        &spear320_pmx_i2s,
-        &spear320_pmx_uart1,
-        &spear320_pmx_uart2,
-        &spear320_pmx_can,
-        &spear320_pmx_pwm0,
-        &spear320_pmx_pwm1,
-        &spear320_pmx_pwm2,
-        &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear320 machine init function */
-        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear320_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-        .gpio_base      = 0,
-        .irq_base       = SPEAR3XX_GPIO_INT_BASE,
+#include <mach/spear.h>
+
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = pl08x_filter_id,
+        .dma_tx_param = "ssp0_tx",
+        .dma_rx_param = "ssp0_rx",
+        /*
+         * This is number of spi devices that can be connected to spi. There are
+         * two type of chipselects on which slave devices can work. One is chip
+         * select provided by spi masters other is controlled through external
+         * gpio's. We can't use chipselect provided from spi master (because as
+         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+         * this number now depends on number of gpios available for spi. each
+         * slave on each master requires a separate gpio pin.
+         */
+        .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
 };
 
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-        {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-        /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
 struct map_desc spear3xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -76,441 +83,15 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 void __init spear3xx_map_io(void)
 {
         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear3xx_clk_init();
 }
 
-/* pad multiplexing support */
-/* devices */
-static struct pmx_dev_mode pmx_firda_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_firda = {
-        .name = "firda",
-        .modes = pmx_firda_modes,
-        .mode_count = ARRAY_SIZE(pmx_firda_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_i2c_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_i2c = {
-        .name = "i2c",
-        .modes = pmx_i2c_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp_cs = {
-        .name = "ssp_chip_selects",
-        .modes = pmx_ssp_cs_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp = {
-        .name = "ssp",
-        .modes = pmx_ssp_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_mii_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_mii = {
-        .name = "mii",
-        .modes = pmx_mii_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin0 = {
-        .name = "gpio_pin0",
-        .modes = pmx_gpio_pin0_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin1 = {
-        .name = "gpio_pin1",
-        .modes = pmx_gpio_pin1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin2 = {
-        .name = "gpio_pin2",
-        .modes = pmx_gpio_pin2_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin3 = {
-        .name = "gpio_pin3",
-        .modes = pmx_gpio_pin3_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin4 = {
-        .name = "gpio_pin4",
-        .modes = pmx_gpio_pin4_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin5 = {
-        .name = "gpio_pin5",
-        .modes = pmx_gpio_pin5_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0_modem = {
-        .name = "uart0_modem",
-        .modes = pmx_uart0_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0 = {
-        .name = "uart0",
-        .modes = pmx_uart0_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_3_4 = {
-        .name = "timer_3_4",
-        .modes = pmx_timer_3_4_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_1_2 = {
-        .name = "timer_1_2",
-        .modes = pmx_timer_1_2_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
-        .enb_on_reset = 0,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
-static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
-        .name = "plgpio 0 and 1",
-        .modes = pmx_plgpio_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
-        .name = "plgpio 2 and 3",
-        .modes = pmx_plgpio_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
-        .name = "plgpio 4 and 5",
-        .modes = pmx_plgpio_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
-        .name = "plgpio 6 to 9",
-        .modes = pmx_plgpio_6_9_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
-        .name = "plgpio 10 to 27",
-        .modes = pmx_plgpio_10_27_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_28 = {
-        .name = "plgpio 28",
-        .modes = pmx_plgpio_28_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_29 = {
-        .name = "plgpio 29",
-        .modes = pmx_plgpio_29_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_30 = {
-        .name = "plgpio 30",
-        .modes = pmx_plgpio_30_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_31 = {
-        .name = "plgpio 31",
-        .modes = pmx_plgpio_31_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_32 = {
-        .name = "plgpio 32",
-        .modes = pmx_plgpio_32_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_33 = {
-        .name = "plgpio 33",
-        .modes = pmx_plgpio_33_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
-        .name = "plgpio 34 to 36",
-        .modes = pmx_plgpio_34_36_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
-        .name = "plgpio 37 to 42",
-        .modes = pmx_plgpio_37_42_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
-        .name = "plgpio 43, 44, 47 and 48",
-        .modes = pmx_plgpio_43_44_47_48_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
-        .name = "plgpio 45, 46, 49 and 50",
-        .modes = pmx_plgpio_45_46_49_50_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-        .enb_on_reset = 1,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
 static void __init spear3xx_timer_init(void)
 {
         char pclk_name[] = "pll3_48m_clk";
         struct clk *gpt_clk, *pclk;
 
+        spear3xx_clk_init();
+
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
         if (IS_ERR(gpt_clk)) {
@@ -530,9 +111,19 @@ static void __init spear3xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_of_timer();
 }
 
 struct sys_timer spear3xx_timer = {
         .init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
 #
 
 # common files
-obj-y   += clock.o spear6xx.o
+obj-y   += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/clock.c
- *
- * SPEAr6xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 32000,
-};
-
-/* 30 MHz oscillator clock */
-static struct clk osc_30m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 30000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-        .pclk = &osc_32k_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = RTC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from 30 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-        .mode_mask = PLL_MODE_MASK,
-        .mode_shift = PLL_MODE_SHIFT,
-        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-        .div_p_mask = PLL_DIV_P_MASK,
-        .div_p_shift = PLL_DIV_P_SHIFT,
-        .div_n_mask = PLL_DIV_N_MASK,
-        .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-        .mode_reg = PLL1_CTR,
-        .cfg_reg = PLL1_FRQ,
-        .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-        .flags = ENABLED_ON_INIT,
-        .pclk = &osc_30m_clk,
-        .en_reg = PLL1_CTR,
-        .en_reg_bit = PLL_ENABLE,
-        .calc_rate = &pll_calc_rate,
-        .recalc = &pll_clk_recalc,
-        .set_rate = &pll_clk_set_rate,
-        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-        .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_30m_clk,
-        .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_30m_clk,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-        {.div = 3}, /* == parent divided by 4 */
-        {.div = 2}, /* == parent divided by 3 */
-        {.div = 1}, /* == parent divided by 2 */
-        {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-        .eq_sel_mask = AUX_EQ_SEL_MASK,
-        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-        .eq1_mask = AUX_EQ1_SEL,
-        .eq2_mask = AUX_EQ2_SEL,
-        .xscale_sel_mask = AUX_XSCALE_MASK,
-        .xscale_sel_shift = AUX_XSCALE_SHIFT,
-        .yscale_sel_mask = AUX_YSCALE_MASK,
-        .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart configurations */
-static struct aux_clk_config uart_synth_config = {
-        .synth_reg = UART_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-        /* For PLL1 = 332 MHz */
-        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-        .en_reg = UART_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-        {
-                .pclk = &uart_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-        .pclk_info = uart_pclk_info,
-        .pclk_count = ARRAY_SIZE(uart_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart0 clock */
-static struct clk uart0_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART0_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* uart1 clock */
-static struct clk uart1_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART1_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-        .synth_reg = FIRDA_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-        .en_reg = FIRDA_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-        {
-                .pclk = &firda_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-        .pclk_info = firda_pclk_info,
-        .pclk_count = ARRAY_SIZE(firda_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FIRDA_CLK_ENB,
-        .pclk_sel = &firda_pclk_sel,
-        .pclk_sel_shift = FIRDA_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clcd configurations */
-static struct aux_clk_config clcd_synth_config = {
-        .synth_reg = CLCD_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk clcd_synth_clk = {
-        .en_reg = CLCD_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &clcd_synth_config,
-};
-
-/* clcd parents */
-static struct pclk_info clcd_pclk_info[] = {
-        {
-                .pclk = &clcd_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* clcd parent select structure */
-static struct pclk_sel clcd_pclk_sel = {
-        .pclk_info = clcd_pclk_info,
-        .pclk_count = ARRAY_SIZE(clcd_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = CLCD_CLK_MASK,
-};
-
-/* clcd clock */
-static struct clk clcd_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = CLCD_CLK_ENB,
-        .pclk_sel = &clcd_pclk_sel,
-        .pclk_sel_shift = CLCD_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-        .mscale_sel_mask = GPT_MSCALE_MASK,
-        .mscale_sel_shift = GPT_MSCALE_SHIFT,
-        .nscale_sel_mask = GPT_NSCALE_MASK,
-        .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-        /* For pll1 = 332 MHz */
-        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-        {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-        .synth_reg = PRSC1_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-        {
-                .pclk = &gpt0_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 ARM1 subsystem timer clock */
-static struct clk gpt0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt0_pclk_sel,
-        .pclk_sel_shift = GPT0_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-
-/* Note: gpt0 and gpt1 share same parent clocks */
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt1_pclk_sel,
-        .pclk_sel_shift = GPT1_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk config*/
-static struct gpt_clk_config gpt2_synth_config = {
-        .synth_reg = PRSC2_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt2_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt2_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt2_pclk_info[] = {
-        {
-                .pclk = &gpt2_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-        .pclk_info = gpt2_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt2_pclk_sel,
-        .pclk_sel_shift = GPT2_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt3 synth clk config*/
-static struct gpt_clk_config gpt3_synth_config = {
-        .synth_reg = PRSC3_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt3_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt3_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt3_pclk_info[] = {
-        {
-                .pclk = &gpt3_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt3_pclk_sel = {
-        .pclk_info = gpt3_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt3 timer clock */
-static struct clk gpt3_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt3_pclk_sel,
-        .pclk_sel_shift = GPT3_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh0 clock */
-static struct clk usbh0_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH0_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbh1 clock */
-static struct clk usbh1_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBD_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-        .mask = HCLK_PCLK_RATIO_MASK,
-        .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = I2C_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = DMA_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = JPEG_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GMAC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SMI_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* fsmc clock */
-static struct clk fsmc_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FSMC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = ADC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp0 clock */
-static struct clk ssp0_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP0_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP2_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio0 ARM subsystem clock */
-static struct clk gpio0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio2 clock */
-static struct clk gpio2_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO2_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-/* array of all spear 6xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
-        /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-        /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
-        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
-        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
-        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
-        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
-};
-
-void __init spear6xx_clk_init(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-                clk_register(&spear_clk_lookups[i]);
-
-        clk_init();
-}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    IRQ_CPU_GPT1_2
-
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
 
+void __init spear_setup_of_timer(void);
 void spear_restart(char, const char *);
-
-/* Add spear600 machine device structure declarations here */
+void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ                     0
-#define IRQ_INTRCOMM_CPU_1                      1
-#define IRQ_INTRCOMM_CPU_2                      2
-#define IRQ_INTRCOMM_RAS2A11_1                  3
-#define IRQ_INTRCOMM_RAS2A11_2                  4
-#define IRQ_INTRCOMM_RAS2A12_1                  5
-#define IRQ_INTRCOMM_RAS2A12_2                  6
-#define IRQ_GEN_RAS_0                           7
-#define IRQ_GEN_RAS_1                           8
-#define IRQ_GEN_RAS_2                           9
-#define IRQ_GEN_RAS_3                           10
-#define IRQ_GEN_RAS_4                           11
-#define IRQ_GEN_RAS_5                           12
-#define IRQ_GEN_RAS_6                           13
-#define IRQ_GEN_RAS_7                           14
-#define IRQ_GEN_RAS_8                           15
-#define IRQ_CPU_GPT1_1                          16
-#define IRQ_CPU_GPT1_2                          17
-#define IRQ_LOCAL_GPIO                          18
-#define IRQ_PLL_UNLOCK                          19
-#define IRQ_JPEG                                20
-#define IRQ_FSMC                                21
-#define IRQ_IRDA                                22
-#define IRQ_RESERVED                            23
-#define IRQ_UART_0                              24
-#define IRQ_UART_1                              25
-#define IRQ_SSP_1                               26
-#define IRQ_SSP_2                               27
-#define IRQ_I2C                                 28
-#define IRQ_GEN_RAS_9                           29
-#define IRQ_GEN_RAS_10                          30
-#define IRQ_GEN_RAS_11                          31
-
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1                         32
-#define IRQ_APPL_GPT1_2                         33
-#define IRQ_APPL_GPT2_1                         34
-#define IRQ_APPL_GPT2_2                         35
-#define IRQ_APPL_GPIO                           36
-#define IRQ_APPL_SSP                            37
-#define IRQ_APPL_ADC                            38
-#define IRQ_APPL_RESERVED                       39
-#define IRQ_AHB_EXP_MASTER                      40
-#define IRQ_DDR_CONTROLLER                      41
-#define IRQ_BASIC_DMA                           42
-#define IRQ_BASIC_RESERVED1                     43
-#define IRQ_BASIC_SMI                           44
-#define IRQ_BASIC_CLCD                          45
-#define IRQ_EXP_AHB_1                           46
-#define IRQ_EXP_AHB_2                           47
-#define IRQ_BASIC_GPT1_1                        48
-#define IRQ_BASIC_GPT1_2                        49
-#define IRQ_BASIC_RTC                           50
-#define IRQ_BASIC_GPIO                          51
-#define IRQ_BASIC_WDT                           52
-#define IRQ_BASIC_RESERVED                      53
-#define IRQ_AHB_EXP_SLAVE                       54
-#define IRQ_GMAC_1                              55
-#define IRQ_GMAC_2                              56
-#define IRQ_USB_DEV                             57
-#define IRQ_USB_H_OHCI_0                        58
-#define IRQ_USB_H_EHCI_0                        59
-#define IRQ_USB_H_OHCI_1                        60
-#define IRQ_USB_H_EHCI_1                        61
-#define IRQ_EXP_AHB_3                           62
-#define IRQ_EXP_AHB_4                           63
-
 #define IRQ_VIC_END                             64
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE     IRQ_VIC_END
-#define SPEAR_GPIO0_INT_BASE    SPEAR_GPIO_INT_BASE
-#define SPEAR_GPIO1_INT_BASE    (SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE    (SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END      (SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS            (SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#define VIRTUAL_IRQS                            24
+#define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
 
 #endif  /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT          2
-#define CLCD_CLK_MASK           0x3
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          10
-#define GPT2_CLK_SHIFT          11
-#define GPT3_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB           3
-#define UART1_CLK_ENB           4
-#define SSP0_CLK_ENB            5
-#define SSP1_CLK_ENB            6
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FSMC_CLK_ENB            9
-#define FIRDA_CLK_ENB           10
-#define GPT2_CLK_ENB            11
-#define GPT3_CLK_ENB            12
-#define GPIO2_CLK_ENB           13
-#define SSP2_CLK_ENB            14
-#define ADC_CLK_ENB             15
-#define GPT1_CLK_ENB            11
-#define RTC_CLK_ENB             17
-#define GPIO1_CLK_ENB           18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define CLCD_CLK_ENB            22
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH0_CLK_ENB           25
-#define USBH1_CLK_ENB           26
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
 #define __MACH_SPEAR6XX_H
 
 #include <asm/memory.h>
-#include <mach/spear600.h>
 
-#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-
+#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-
-#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
+#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
 
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR600
-
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-
-#endif /* __MACH_SPEAR600_H */
-
-#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
-/* Following will create static virtual/physical mappings */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
         {
-                .virtual        = VA_SPEAR6XX_ICM1_UART0_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
+                .bus_id = "ext0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+        .slave_channels = spear600_dma_info,
+        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xF0000000           0xF0000000
+ * 0xF1000000           0xF1000000
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .length         = 2 * SZ_16M,
+                .type           = MT_DEVICE
+        },      {
+                .virtual        = VA_SPEAR6XX_ICM1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
 void __init spear6xx_map_io(void)
 {
         iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear6xx_clk_init();
 }
 
 static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
         char pclk_name[] = "pll3_48m_clk";
         struct clk *gpt_clk, *pclk;
 
+        spear6xx_clk_init();
+
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
         if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_of_timer();
 }
 
 struct sys_timer spear6xx_timer = {
         .init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
+
 static void __init spear600_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1621ad07d284..33339745d432 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
 
         for (i = 0; i < U300_VIC_IRQS_END; i++)
                 set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
+        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
+                 mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
+                 mask[1], mask[1]);
 }
 
 
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index a38f80238ea9..cb04bd6ab3e7 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 1800000,
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 2500000,
                                 .max_uV = 2500000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                 .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
+                                REGULATOR_CHANGE_VOLTAGE,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ee78a26707eb..ec09c1e07b1a 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -12,101 +12,101 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-#define IRQ_U300_INTCON0_START          0
-#define IRQ_U300_INTCON1_START          32
+#define IRQ_U300_INTCON0_START          1
+#define IRQ_U300_INTCON1_START          33
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               0
-#define IRQ_U300_IRQ1_EXT               1
-#define IRQ_U300_DMA                    2
-#define IRQ_U300_VIDEO_ENC_0            3
-#define IRQ_U300_VIDEO_ENC_1            4
-#define IRQ_U300_AAIF_RX                5
-#define IRQ_U300_AAIF_TX                6
-#define IRQ_U300_AAIF_VGPIO             7
-#define IRQ_U300_AAIF_WAKEUP            8
-#define IRQ_U300_PCM_I2S0_FRAME         9
-#define IRQ_U300_PCM_I2S0_FIFO          10
-#define IRQ_U300_PCM_I2S1_FRAME         11
-#define IRQ_U300_PCM_I2S1_FIFO          12
-#define IRQ_U300_XGAM_GAMCON            13
-#define IRQ_U300_XGAM_CDI               14
-#define IRQ_U300_XGAM_CDICON            15
+#define IRQ_U300_IRQ0_EXT               1
+#define IRQ_U300_IRQ1_EXT               2
+#define IRQ_U300_DMA                    3
+#define IRQ_U300_VIDEO_ENC_0            4
+#define IRQ_U300_VIDEO_ENC_1            5
+#define IRQ_U300_AAIF_RX                6
+#define IRQ_U300_AAIF_TX                7
+#define IRQ_U300_AAIF_VGPIO             8
+#define IRQ_U300_AAIF_WAKEUP            9
+#define IRQ_U300_PCM_I2S0_FRAME         10
+#define IRQ_U300_PCM_I2S0_FIFO          11
+#define IRQ_U300_PCM_I2S1_FRAME         12
+#define IRQ_U300_PCM_I2S1_FIFO          13
+#define IRQ_U300_XGAM_GAMCON            14
+#define IRQ_U300_XGAM_CDI               15
+#define IRQ_U300_XGAM_CDICON            16
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
 /* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            16
+#define IRQ_U300_XGAM_MMIACC            17
 #endif
-#define IRQ_U300_XGAM_PDI               17
-#define IRQ_U300_XGAM_PDICON            18
-#define IRQ_U300_XGAM_GAMEACC           19
-#define IRQ_U300_XGAM_MCIDCT            20
-#define IRQ_U300_APEX                   21
-#define IRQ_U300_UART0                  22
-#define IRQ_U300_SPI                    23
-#define IRQ_U300_TIMER_APP_OS           24
-#define IRQ_U300_TIMER_APP_DD           25
-#define IRQ_U300_TIMER_APP_GP1          26
-#define IRQ_U300_TIMER_APP_GP2          27
-#define IRQ_U300_TIMER_OS               28
-#define IRQ_U300_TIMER_MS               29
-#define IRQ_U300_KEYPAD_KEYBF           30
-#define IRQ_U300_KEYPAD_KEYBR           31
+#define IRQ_U300_XGAM_PDI               18
+#define IRQ_U300_XGAM_PDICON            19
+#define IRQ_U300_XGAM_GAMEACC           20
+#define IRQ_U300_XGAM_MCIDCT            21
+#define IRQ_U300_APEX                   22
+#define IRQ_U300_UART0                  23
+#define IRQ_U300_SPI                    24
+#define IRQ_U300_TIMER_APP_OS           25
+#define IRQ_U300_TIMER_APP_DD           26
+#define IRQ_U300_TIMER_APP_GP1          27
+#define IRQ_U300_TIMER_APP_GP2          28
+#define IRQ_U300_TIMER_OS               29
+#define IRQ_U300_TIMER_MS               30
+#define IRQ_U300_KEYPAD_KEYBF           31
+#define IRQ_U300_KEYPAD_KEYBR           32
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             32
-#define IRQ_U300_GPIO_PORT1             33
-#define IRQ_U300_GPIO_PORT2             34
+#define IRQ_U300_GPIO_PORT0             33
+#define IRQ_U300_GPIO_PORT1             34
+#define IRQ_U300_GPIO_PORT2             35
 
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
     defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   35
-#define IRQ_U300_EVHIST                 36
-#define IRQ_U300_MSPRO                  37
-#define IRQ_U300_MMCSD_MCIINTR0         38
-#define IRQ_U300_MMCSD_MCIINTR1         39
-#define IRQ_U300_I2C0                   40
-#define IRQ_U300_I2C1                   41
-#define IRQ_U300_RTC                    42
-#define IRQ_U300_NFIF                   43
-#define IRQ_U300_NFIF2                  44
+#define IRQ_U300_WDOG                   36
+#define IRQ_U300_EVHIST                 37
+#define IRQ_U300_MSPRO                  38
+#define IRQ_U300_MMCSD_MCIINTR0         39
+#define IRQ_U300_MMCSD_MCIINTR1         40
+#define IRQ_U300_I2C0                   41
+#define IRQ_U300_I2C1                   42
+#define IRQ_U300_RTC                    43
+#define IRQ_U300_NFIF                   44
+#define IRQ_U300_NFIF2                  45
 #endif
 
 /* DB3150 and DB3200 have only 45 IRQs */
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               45
+#define U300_VIC_IRQS_END               46
 #endif
 
 /* The DB3350-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS335
-#define IRQ_U300_ISP_F0                 45
-#define IRQ_U300_ISP_F1                 46
-#define IRQ_U300_ISP_F2                 47
-#define IRQ_U300_ISP_F3                 48
-#define IRQ_U300_ISP_F4                 49
-#define IRQ_U300_GPIO_PORT3             50
-#define IRQ_U300_SYSCON_PLL_LOCK        51
-#define IRQ_U300_UART1                  52
-#define IRQ_U300_GPIO_PORT4             53
-#define IRQ_U300_GPIO_PORT5             54
-#define IRQ_U300_GPIO_PORT6             55
-#define U300_VIC_IRQS_END               56
+#define IRQ_U300_ISP_F0                 46
+#define IRQ_U300_ISP_F1                 47
+#define IRQ_U300_ISP_F2                 48
+#define IRQ_U300_ISP_F3                 49
+#define IRQ_U300_ISP_F4                 50
+#define IRQ_U300_GPIO_PORT3             51
+#define IRQ_U300_SYSCON_PLL_LOCK        52
+#define IRQ_U300_UART1                  53
+#define IRQ_U300_GPIO_PORT4             54
+#define IRQ_U300_GPIO_PORT5             55
+#define IRQ_U300_GPIO_PORT6             56
+#define U300_VIC_IRQS_END               57
 #endif
 
 /* The DB3210-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             35
-#define IRQ_U300_GPIO_PORT4             36
-#define IRQ_U300_WDOG                   37
-#define IRQ_U300_EVHIST                 38
-#define IRQ_U300_MSPRO                  39
-#define IRQ_U300_MMCSD_MCIINTR0         40
-#define IRQ_U300_MMCSD_MCIINTR1         41
-#define IRQ_U300_I2C0                   42
-#define IRQ_U300_I2C1                   43
-#define IRQ_U300_RTC                    44
-#define IRQ_U300_NFIF                   45
-#define IRQ_U300_NFIF2                  46
-#define IRQ_U300_SYSCON_PLL_LOCK        47
-#define U300_VIC_IRQS_END               48
+#define IRQ_U300_GPIO_PORT3             36
+#define IRQ_U300_GPIO_PORT4             37
+#define IRQ_U300_WDOG                   38
+#define IRQ_U300_EVHIST                 39
+#define IRQ_U300_MSPRO                  40
+#define IRQ_U300_MMCSD_MCIINTR0         41
+#define IRQ_U300_MMCSD_MCIINTR1         42
+#define IRQ_U300_I2C0                   43
+#define IRQ_U300_I2C1                   44
+#define IRQ_U300_RTC                    45
+#define IRQ_U300_NFIF                   46
+#define IRQ_U300_NFIF2                  47
+#define IRQ_U300_SYSCON_PLL_LOCK        48
+#define U300_VIC_IRQS_END               49
 #endif
 
 /* Maximum 8*7 GPIO lines */
@@ -117,6 +117,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS                         (IRQ_U300_GPIO_END)
+#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
index 2b2d51caf9d8..0127490218cd 100644
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
         return sprintf(buf, "0x%X\n", mbox_value);
 }
 
-static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
+static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
 
 static int mbox_show(struct seq_file *s, void *data)
 {
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ff1f7cc11f87..80741992a9fc 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
- * The test below covers all the write situations, including Java bytecodes
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
  */
-        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+#ifdef CONFIG_ARM_ERRATA_326103
+        ldr     ip, =0x4107b36
+        mrc     p15, 0, r3, c0, c0, 0           @ get processor id
+        teq     ip, r3, lsr #4                  @ r0 ARM1136?
+        bne     do_DataAbort
         tst     r5, #PSR_J_BIT                  @ Java?
+        tsteq   r5, #PSR_T_BIT                  @ Thumb?
         bne     do_DataAbort
-        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
-        ldreq   r3, [r4]                        @ read aborted ARM instruction
+        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+        ldr     r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
-        reveq   r3, r3
+        rev     r3, r3
 #endif
         do_ldrd_abort tmp=ip, insn=r3
         tst     r3, #1 << 20                    @ L = 0 -> write
         orreq   r1, r1, #1 << 11                @ yes.
+#endif
         b       do_DataAbort
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2aaa2f4..2a8e380501e8 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;       /* Bitmask of active ways */
 static u32 l2x0_size;
+static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -61,12 +62,7 @@ static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
 
-#ifdef CONFIG_PL310_ERRATA_753970
-        /* write to an unmmapped register */
-        writel_relaxed(0, base + L2X0_DUMMY_REG);
-#else
-        writel_relaxed(0, base + L2X0_CACHE_SYNC);
-#endif
+        writel_relaxed(0, base + sync_reg_offset);
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
 }
 
 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static inline void debug_writel(unsigned long val)
+{
+        if (outer_cache.set_debug)
+                outer_cache.set_debug(val);
+}
 
-#define debug_writel(val)       outer_cache.set_debug(val)
-
-static void l2x0_set_debug(unsigned long val)
+static void pl310_set_debug(unsigned long val)
 {
         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
 }
@@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
 {
 }
 
-#define l2x0_set_debug  NULL
+#define pl310_set_debug NULL
 #endif
 
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                 else
                         ways = 8;
                 type = "L310";
+#ifdef CONFIG_PL310_ERRATA_753970
+                /* Unmapped register. */
+                sync_reg_offset = L2X0_DUMMY_REG;
+#endif
+                outer_cache.set_debug = pl310_set_debug;
                 break;
         case L2X0_CACHE_ID_PART_L210:
                 ways = (aux >> 13) & 0xf;
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         outer_cache.flush_all = l2x0_flush_all;
         outer_cache.inv_all = l2x0_inv_all;
         outer_cache.disable = l2x0_disable;
-        outer_cache.set_debug = l2x0_set_debug;
 
         printk(KERN_INFO "%s cache controller enabled\n", type);
         printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 595079fa9d1d..8f5813bbffb5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
 #endif
 
 #ifndef CONFIG_SPARSEMEM
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
         struct memblock_region *reg;
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b86f8933ff91..2c7cf2f9c837 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
         }
 }
 
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
-        unsigned long phys, const struct mem_type *type)
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
+        unsigned long end, unsigned long phys, const struct mem_type *type)
 {
         pud_t *pud = pud_offset(pgd, addr);
         unsigned long next;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab173add..5079787273d2 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -41,6 +41,7 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 
+#ifndef CONFIG_COMMON_CLK
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 
@@ -200,6 +201,16 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
+#else
+
+/*
+ * Lock to protect the clock module (ccm) registers. Used
+ * on all i.MXs
+ */
+DEFINE_SPINLOCK(imx_ccm_lock);
+
+#endif /* CONFIG_COMMON_CLK */
+
 /*
  * Get the resulting clock rate from a PLL register value and the input
  * frequency. PLLs with this register layout can at least be found on
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 753a5988d85c..bd940c795cbb 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -23,6 +23,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/list.h>
 
+#ifndef CONFIG_COMMON_CLK
 struct module;
 
 struct clk {
@@ -59,6 +60,9 @@ struct clk {
 
 int clk_register(struct clk *clk);
 void clk_unregister(struct clk *clk);
+#endif /* CONFIG_COMMON_CLK */
+
+extern spinlock_t imx_ccm_lock;
 
 unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
 
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 7daf7c9a413b..99f958ca6cb8 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -25,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <asm/sched_clock.h>
@@ -282,6 +283,19 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
         uint32_t tctl_val;
+        struct clk *timer_ipg_clk;
+
+        if (!timer_clk) {
+                timer_clk = clk_get_sys("imx-gpt.0", "per");
+                if (IS_ERR(timer_clk)) {
+                        pr_err("i.MX timer: unable to get clk\n");
+                        return;
+                }
+
+                timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
+                if (!IS_ERR(timer_ipg_clk))
+                        clk_prepare_enable(timer_ipg_clk);
+        }
 
         clk_prepare_enable(timer_clk);
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ecdb3da0dea9..c58d896cd5c3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -916,6 +916,13 @@ void omap_start_dma(int lch)
                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
         l |= OMAP_DMA_CCR_EN;
 
+        /*
+         * As dma_write() uses IO accessors which are weakly ordered, there
+         * is no guarantee that data in coherent DMA memory will be visible
+         * to the DMA device.  Add a memory barrier here to ensure that any
+         * such data is visible prior to enabling DMA.
+         */
+        mb();
         p->dma_write(l, CCR, lch);
 
         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
@@ -965,6 +972,13 @@ void omap_stop_dma(int lch)
                 p->dma_write(l, CCR, lch);
         }
 
+        /*
+         * Ensure that data transferred by DMA is visible to any access
+         * after DMA has been disabled.  This is important for coherent
+         * DMA regions.
+         */
+        mb();
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
                 char dma_chan_link_map[dma_lch_count];
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 317e246ffc56..e834c5ef437c 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
 
+#include <plat/devs.h>
+
 struct platform_device;
 struct mmc_host;
 struct mmc_card;
@@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
 
 #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
 
+static inline void s3c_sdhci_setname(int id, char *name)
+{
+        switch (id) {
+#ifdef CONFIG_S3C_DEV_HSMMC
+        case 0:
+                s3c_device_hsmmc0.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        case 1:
+                s3c_device_hsmmc1.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        case 2:
+                s3c_device_hsmmc2.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+        case 3:
+                s3c_device_hsmmc3.name = name;
+                break;
+#endif
+        }
+}
+
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
         default ARCH_SPEAR3XX
 
 config ARCH_SPEAR3XX
-        bool "SPEAr3XX"
+        bool "ST SPEAr3xx with Device Tree"
         select ARM_VIC
         select CPU_ARM926T
+        select USE_OF
+        select PINCTRL
         help
           Supports for ARM's SPEAR3XX family
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..38f1235f4632 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y   := clock.o restart.o time.o
+obj-y   := restart.o time.o pl080.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644
index 67dd00381ea6..000000000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * arch/arm/plat-spear/clock.c
- *
- * Clock framework for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/bug.h>
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <plat/clock.h>
-
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(root_clks);
-#ifdef CONFIG_DEBUG_FS
-static LIST_HEAD(clocks);
-#endif
-
-static void propagate_rate(struct clk *, int on_init);
-#ifdef CONFIG_DEBUG_FS
-static int clk_debugfs_reparent(struct clk *);
-#endif
-
-static int generic_clk_enable(struct clk *clk)
-{
-        unsigned int val;
-
-        if (!clk->en_reg)
-                return -EFAULT;
-
-        val = readl(clk->en_reg);
-        if (unlikely(clk->flags & RESET_TO_ENABLE))
-                val &= ~(1 << clk->en_reg_bit);
-        else
-                val |= 1 << clk->en_reg_bit;
-
-        writel(val, clk->en_reg);
-
-        return 0;
-}
-
-static void generic_clk_disable(struct clk *clk)
-{
-        unsigned int val;
-
-        if (!clk->en_reg)
-                return;
-
-        val = readl(clk->en_reg);
-        if (unlikely(clk->flags & RESET_TO_ENABLE))
-                val |= 1 << clk->en_reg_bit;
-        else
-                val &= ~(1 << clk->en_reg_bit);
-
-        writel(val, clk->en_reg);
-}
-
-/* generic clk ops */
-static struct clkops generic_clkops = {
-        .enable = generic_clk_enable,
-        .disable = generic_clk_disable,
-};
-
-/* returns current programmed clocks clock info structure */
-static struct pclk_info *pclk_info_get(struct clk *clk)
-{
-        unsigned int val, i;
-        struct pclk_info *info = NULL;
-
-        val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
-                & clk->pclk_sel->pclk_sel_mask;
-
-        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-                if (clk->pclk_sel->pclk_info[i].pclk_val == val)
-                        info = &clk->pclk_sel->pclk_info[i];
-        }
-
-        return info;
-}
-
-/*
- * Set Update pclk, and pclk_info of clk and add clock sibling node to current
- * parents children list
- */
-static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        list_del(&clk->sibling);
-        list_add(&clk->sibling, &pclk_info->pclk->children);
-
-        clk->pclk = pclk_info->pclk;
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-#ifdef CONFIG_DEBUG_FS
-        clk_debugfs_reparent(clk);
-#endif
-}
-
-static void do_clk_disable(struct clk *clk)
-{
-        if (!clk)
-                return;
-
-        if (!clk->usage_count) {
-                WARN_ON(1);
-                return;
-        }
-
-        clk->usage_count--;
-
-        if (clk->usage_count == 0) {
-                /*
-                 * Surely, there are no active childrens or direct users
-                 * of this clock
-                 */
-                if (clk->pclk)
-                        do_clk_disable(clk->pclk);
-
-                if (clk->ops && clk->ops->disable)
-                        clk->ops->disable(clk);
-        }
-}
-
-static int do_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (!clk)
-                return -EFAULT;
-
-        if (clk->usage_count == 0) {
-                if (clk->pclk) {
-                        ret = do_clk_enable(clk->pclk);
-                        if (ret)
-                                goto err;
-                }
-                if (clk->ops && clk->ops->enable) {
-                        ret = clk->ops->enable(clk);
-                        if (ret) {
-                                if (clk->pclk)
-                                        do_clk_disable(clk->pclk);
-                                goto err;
-                        }
-                }
-                /*
-                 * Since the clock is going to be used for the first
-                 * time please reclac
-                 */
-                if (clk->recalc) {
-                        ret = clk->recalc(clk);
-                        if (ret)
-                                goto err;
-                }
-        }
-        clk->usage_count++;
-err:
-        return ret;
-}
-
-/*
- * clk_enable - inform the system when the clock source should be running.
- * @clk: clock source
- *
- * If the clock can not be enabled/disabled, this should return success.
- *
- * Returns success (0) or negative errno.
- */
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        ret = do_clk_enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/*
- * clk_disable - inform the system when the clock source is no longer required.
- * @clk: clock source
- *
- * Inform the system that a clock source is no longer required by
- * a driver and may be shut down.
- *
- * Implementation detail: if the clock source is shared between
- * multiple drivers, clk_enable() calls must be balanced by the
- * same number of clk_disable() calls for the clock source to be
- * disabled.
- */
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        do_clk_disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/**
- * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
- *               This is only valid once the clock source has been enabled.
- * @clk: clock source
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long flags, rate;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        rate = clk->rate;
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/**
- * clk_set_parent - set the parent clock source for this clock
- * @clk: clock source
- * @parent: parent clock source
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int i, found = 0, val = 0;
-        unsigned long flags;
-
-        if (!clk || !parent)
-                return -EFAULT;
-        if (clk->pclk == parent)
-                return 0;
-        if (!clk->pclk_sel)
-                return -EPERM;
-
-        /* check if requested parent is in clk parent list */
-        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-                if (clk->pclk_sel->pclk_info[i].pclk == parent) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (!found)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        /* reflect parent change in hardware */
-        val = readl(clk->pclk_sel->pclk_sel_reg);
-        val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
-        val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
-        writel(val, clk->pclk_sel->pclk_sel_reg);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        /* reflect parent change in software */
-        clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
-
-        propagate_rate(clk, 0);
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/**
- * clk_set_rate - set the clock rate for a clock source
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (!clk || !rate)
-                return -EFAULT;
-
-        if (clk->set_rate) {
-                spin_lock_irqsave(&clocks_lock, flags);
-                ret = clk->set_rate(clk, rate);
-                if (!ret)
-                        /* if successful -> propagate */
-                        propagate_rate(clk, 0);
-                spin_unlock_irqrestore(&clocks_lock, flags);
-        } else if (clk->pclk) {
-                u32 mult = clk->div_factor ? clk->div_factor : 1;
-                ret = clk_set_rate(clk->pclk, mult * rate);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* registers clock in platform clock framework */
-void clk_register(struct clk_lookup *cl)
-{
-        struct clk *clk;
-        unsigned long flags;
-
-        if (!cl || !cl->clk)
-                return;
-        clk = cl->clk;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        INIT_LIST_HEAD(&clk->children);
-        if (clk->flags & ALWAYS_ENABLED)
-                clk->ops = NULL;
-        else if (!clk->ops)
-                clk->ops = &generic_clkops;
-
-        /* root clock don't have any parents */
-        if (!clk->pclk && !clk->pclk_sel) {
-                list_add(&clk->sibling, &root_clks);
-        } else if (clk->pclk && !clk->pclk_sel) {
-                /* add clocks with only one parent to parent's children list */
-                list_add(&clk->sibling, &clk->pclk->children);
-        } else {
-                /* clocks with more than one parent */
-                struct pclk_info *pclk_info;
-
-                pclk_info = pclk_info_get(clk);
-                if (!pclk_info) {
-                        pr_err("CLKDEV: invalid pclk info of clk with"
-                                        " %s dev_id and %s con_id\n",
-                                        cl->dev_id, cl->con_id);
-                } else {
-                        clk->pclk = pclk_info->pclk;
-                        list_add(&clk->sibling, &pclk_info->pclk->children);
-                }
-        }
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        /* debugfs specific */
-#ifdef CONFIG_DEBUG_FS
-        list_add(&clk->node, &clocks);
-        clk->cl = cl;
-#endif
-
-        /* add clock to arm clockdev framework */
-        clkdev_add(cl);
-}
-
-/**
- * propagate_rate - recalculate and propagate all clocks to children
- * @pclk: parent clock required to be propogated
- * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
- *
- * Recalculates all children clocks
- */
-void propagate_rate(struct clk *pclk, int on_init)
-{
-        struct clk *clk, *_temp;
-        int ret = 0;
-
-        list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
-                if (clk->recalc) {
-                        ret = clk->recalc(clk);
-                        /*
-                         * recalc will return error if clk out is not programmed
-                         * In this case configure default rate.
-                         */
-                        if (ret && clk->set_rate)
-                                clk->set_rate(clk, 0);
-                }
-                propagate_rate(clk, on_init);
-
-                if (!on_init)
-                        continue;
-
-                /* Enable clks enabled on init, in software view */
-                if (clk->flags & ENABLED_ON_INIT)
-                        do_clk_enable(clk);
-        }
-}
-
-/**
- * round_rate_index - return closest programmable rate index in rate_config tbl
- * @clk: ptr to clock structure
- * @drate: desired rate
- * @rate: final rate will be returned in this variable only.
- *
- * Finds index in rate_config for highest clk rate which is less than
- * requested rate. If there is no clk rate lesser than requested rate then
- * -EINVAL is returned. This routine assumes that rate_config is written
- * in incrementing order of clk rates.
- * If drate passed is zero then default rate is programmed.
- */
-static int
-round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
-{
-        unsigned long tmp = 0, prev_rate = 0;
-        int index;
-
-        if (!clk->calc_rate)
-                return -EFAULT;
-
-        if (!drate)
-                return -EINVAL;
-
-        /*
-         * This loops ends on two conditions:
-         * - as soon as clk is found with rate greater than requested rate.
-         * - if all clks in rate_config are smaller than requested rate.
-         */
-        for (index = 0; index < clk->rate_config.count; index++) {
-                prev_rate = tmp;
-                tmp = clk->calc_rate(clk, index);
-                if (drate < tmp) {
-                        index--;
-                        break;
-                }
-        }
-        /* return if can't find suitable clock */
-        if (index < 0) {
-                index = -EINVAL;
-                *rate = 0;
-        } else if (index == clk->rate_config.count) {
-                /* program with highest clk rate possible */
-                index = clk->rate_config.count - 1;
-                *rate = tmp;
-        } else
-                *rate = prev_rate;
-
-        return index;
-}
-
-/**
- * clk_round_rate - adjust a rate to the exact rate a clock can provide
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns rounded clock rate in Hz, or negative errno.
- */
-long clk_round_rate(struct clk *clk, unsigned long drate)
-{
-        long rate = 0;
-        int index;
-
-        /*
-         * propagate call to parent who supports calc_rate. Similar approach is
-         * used in clk_set_rate.
-         */
-        if (!clk->calc_rate) {
-                u32 mult;
-                if (!clk->pclk)
-                        return clk->rate;
-
-                mult = clk->div_factor ? clk->div_factor : 1;
-                return clk_round_rate(clk->pclk, mult * drate) / mult;
-        }
-
-        index = round_rate_index(clk, drate, &rate);
-        if (index >= 0)
-                return rate;
-        else
-                return index;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/*All below functions are called with lock held */
-
-/*
- * Calculates pll clk rate for specific value of mode, m, n and p
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-unsigned long pll_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-        unsigned int mode;
-
-        mode = tbls[index].mode ? 256 : 1;
-        return (((2 * rate / 10000) * tbls[index].m) /
-                        (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
-}
-
-/*
- * calculates current programmed rate of pll1
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-int pll_clk_recalc(struct clk *clk)
-{
-        struct pll_clk_config *config = clk->private_data;
-        unsigned int num = 2, den = 0, val, mode = 0;
-
-        mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
-                config->masks->mode_mask;
-
-        val = readl(config->cfg_reg);
-        /* calculate denominator */
-        den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
-        den = 1 << den;
-        den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
-
-        /* calculate numerator & denominator */
-        if (!mode) {
-                /* Normal mode */
-                num *= (val >> config->masks->norm_fdbk_m_shift) &
-                        config->masks->norm_fdbk_m_mask;
-        } else {
-                /* Dithered mode */
-                num *= (val >> config->masks->dith_fdbk_m_shift) &
-                        config->masks->dith_fdbk_m_mask;
-                den *= 256;
-        }
-
-        if (!den)
-                return -EINVAL;
-
-        clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-        return 0;
-}
-
-/*
- * Configures new clock rate of pll
- */
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-        struct pll_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->mode_reg) &
-                ~(config->masks->mode_mask << config->masks->mode_shift);
-        val |= (tbls[i].mode & config->masks->mode_mask) <<
-                config->masks->mode_shift;
-        writel(val, config->mode_reg);
-
-        val = readl(config->cfg_reg) &
-                ~(config->masks->div_p_mask << config->masks->div_p_shift);
-        val |= (tbls[i].p & config->masks->div_p_mask) <<
-                config->masks->div_p_shift;
-        val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
-        val |= (tbls[i].n & config->masks->div_n_mask) <<
-                config->masks->div_n_shift;
-        val &= ~(config->masks->dith_fdbk_m_mask <<
-                        config->masks->dith_fdbk_m_shift);
-        if (tbls[i].mode)
-                val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
-                        config->masks->dith_fdbk_m_shift;
-        else
-                val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
-                        config->masks->norm_fdbk_m_shift;
-
-        writel(val, config->cfg_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates ahb, apb clk rate for specific value of div
- */
-unsigned long bus_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-
-        return rate / (tbls[index].div + 1);
-}
-
-/* calculates current programmed rate of ahb or apb bus */
-int bus_clk_recalc(struct clk *clk)
-{
-        struct bus_clk_config *config = clk->private_data;
-        unsigned int div;
-
-        div = ((readl(config->reg) >> config->masks->shift) &
-                        config->masks->mask) + 1;
-
-        if (!div)
-                return -EINVAL;
-
-        clk->rate = (unsigned long)clk->pclk->rate / div;
-        return 0;
-}
-
-/* Configures new clock rate of AHB OR APB bus */
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-        struct bus_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->reg) &
-                ~(config->masks->mask << config->masks->shift);
-        val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
-        writel(val, config->reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * gives rate for different values of eq, x and y
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2                EQ1
- * Fout2 = Fin * X/Y                    EQ2
- */
-unsigned long aux_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-        u8 eq = tbls[index].eq ? 1 : 2;
-
-        return (((rate/10000) * tbls[index].xscale) /
-                        (tbls[index].yscale * eq)) * 10000;
-}
-
-/*
- * calculates current programmed rate of auxiliary synthesizers
- * used by: UART, FIRDA
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2
- * Fout2 = Fin * X/Y
- *
- * Selection of eqn 1 or 2 is programmed in register
- */
-int aux_clk_recalc(struct clk *clk)
-{
-        struct aux_clk_config *config = clk->private_data;
-        unsigned int num = 1, den = 1, val, eqn;
-
-        val = readl(config->synth_reg);
-
-        eqn = (val >> config->masks->eq_sel_shift) &
-                config->masks->eq_sel_mask;
-        if (eqn == config->masks->eq1_mask)
-                den *= 2;
-
-        /* calculate numerator */
-        num = (val >> config->masks->xscale_sel_shift) &
-                config->masks->xscale_sel_mask;
-
-        /* calculate denominator */
-        den *= (val >> config->masks->yscale_sel_shift) &
-                config->masks->yscale_sel_mask;
-
-        if (!den)
-                return -EINVAL;
-
-        clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-        return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-        struct aux_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) &
-                ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
-        val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
-                config->masks->eq_sel_shift;
-        val &= ~(config->masks->xscale_sel_mask <<
-                        config->masks->xscale_sel_shift);
-        val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
-                config->masks->xscale_sel_shift;
-        val &= ~(config->masks->yscale_sel_mask <<
-                        config->masks->yscale_sel_shift);
-        val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
-                config->masks->yscale_sel_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates gpt clk rate for different values of mscale and nscale
- *
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-unsigned long gpt_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-
-        return rate / ((1 << (tbls[index].nscale + 1)) *
-                        (tbls[index].mscale + 1));
-}
-
-/*
- * calculates current programmed rate of gpt synthesizers
- * Fout from synthesizer can be given from below equations:
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-int gpt_clk_recalc(struct clk *clk)
-{
-        struct gpt_clk_config *config = clk->private_data;
-        unsigned int div = 1, val;
-
-        val = readl(config->synth_reg);
-        div += (val >> config->masks->mscale_sel_shift) &
-                config->masks->mscale_sel_mask;
-        div *= 1 << (((val >> config->masks->nscale_sel_shift) &
-                                config->masks->nscale_sel_mask) + 1);
-
-        if (!div)
-                return -EINVAL;
-
-        clk->rate = (unsigned long)clk->pclk->rate / div;
-        return 0;
-}
-
-/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-        struct gpt_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
-                        config->masks->mscale_sel_shift);
-        val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
-                config->masks->mscale_sel_shift;
-        val &= ~(config->masks->nscale_sel_mask <<
-                        config->masks->nscale_sel_shift);
-        val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
-                config->masks->nscale_sel_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates clcd clk rate for different values of div
- *
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *      0-13 (fractional part)
- *      14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-unsigned long clcd_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-
-        rate /= 1000;
-        rate <<= 12;
-        rate /= (2 * tbls[index].div);
-        rate >>= 12;
-        rate *= 1000;
-
-        return rate;
-}
-
-/*
- * calculates current programmed rate of clcd synthesizer
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *      0-13 (fractional part)
- *      14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-int clcd_clk_recalc(struct clk *clk)
-{
-        struct clcd_clk_config *config = clk->private_data;
-        unsigned int div = 1;
-        unsigned long prate;
-        unsigned int val;
-
-        val = readl(config->synth_reg);
-        div = (val >> config->masks->div_factor_shift) &
-                config->masks->div_factor_mask;
-
-        if (!div)
-                return -EINVAL;
-
-        prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
-
-        clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
-        clk->rate *= 1000;
-        return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-        struct clcd_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
-                        config->masks->div_factor_shift);
-        val |= (tbls[i].div & config->masks->div_factor_mask) <<
-                config->masks->div_factor_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Used for clocks that always have value as the parent clock divided by a
- * fixed divisor
- */
-int follow_parent(struct clk *clk)
-{
-        unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
-
-        clk->rate = clk->pclk->rate/div_factor;
-        return 0;
-}
-
-/**
- * recalc_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- */
-void recalc_root_clocks(void)
-{
-        struct clk *pclk;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        list_for_each_entry(pclk, &root_clks, sibling) {
-                if (pclk->recalc) {
-                        ret = pclk->recalc(pclk);
-                        /*
-                         * recalc will return error if clk out is not programmed
-                         * In this case configure default clock.
-                         */
-                        if (ret && pclk->set_rate)
-                                pclk->set_rate(pclk, 0);
-                }
-                propagate_rate(pclk, 1);
-                /* Enable clks enabled on init, in software view */
-                if (pclk->flags & ENABLED_ON_INIT)
-                        do_clk_enable(pclk);
-        }
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-
-void __init clk_init(void)
-{
-        recalc_root_clocks();
-}
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *      debugfs support to trace clock tree hierarchy and attributes
- */
-static struct dentry *clk_debugfs_root;
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d;
-        struct clk *pa = c->pclk;
-        char s[255];
-        char *p = s;
-
-        if (c) {
-                if (c->cl->con_id)
-                        p += sprintf(p, "%s", c->cl->con_id);
-                if (c->cl->dev_id)
-                        p += sprintf(p, "%s", c->cl->dev_id);
-        }
-        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-
-        d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
-                        (u32 *)&c->usage_count);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->pclk;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-late_initcall(clk_debugfs_init);
-
-static int clk_debugfs_reparent(struct clk *c)
-{
-        debugfs_remove(c->dent);
-        return clk_debugfs_register_one(c);
-}
-#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644
index 0062bafef12d..000000000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/clock.h
- *
- * Clock framework definitions for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_CLOCK_H
-#define __PLAT_CLOCK_H
-
-#include <linux/list.h>
-#include <linux/clkdev.h>
-#include <linux/types.h>
-
-/* clk structure flags */
-#define ALWAYS_ENABLED          (1 << 0) /* clock always enabled */
-#define RESET_TO_ENABLE         (1 << 1) /* reset register bit to enable clk */
-#define ENABLED_ON_INIT         (1 << 2) /* clocks enabled at init */
-
-/**
- * struct clkops - clock operations
- * @enable: pointer to clock enable function
- * @disable: pointer to clock disable function
- */
-struct clkops {
-        int (*enable) (struct clk *);
-        void (*disable) (struct clk *);
-};
-
-/**
- * struct pclk_info - parents info
- * @pclk: pointer to parent clk
- * @pclk_val: value to be written for selecting this parent
- */
-struct pclk_info {
-        struct clk *pclk;
-        u8 pclk_val;
-};
-
-/**
- * struct pclk_sel - parents selection configuration
- * @pclk_info: pointer to array of parent clock info
- * @pclk_count: number of parents
- * @pclk_sel_reg: register for selecting a parent
- * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
- */
-struct pclk_sel {
-        struct pclk_info *pclk_info;
-        u8 pclk_count;
-        void __iomem *pclk_sel_reg;
-        unsigned int pclk_sel_mask;
-};
-
-/**
- * struct rate_config - clk rate configurations
- * @tbls: array of device specific clk rate tables, in ascending order of rates
- * @count: size of tbls array
- * @default_index: default setting when originally disabled
- */
-struct rate_config {
-        void *tbls;
-        u8 count;
-        u8 default_index;
-};
-
-/**
- * struct clk - clock structure
- * @usage_count: num of users who enabled this clock
- * @flags: flags for clock properties
- * @rate: programmed clock rate in Hz
- * @en_reg: clk enable/disable reg
- * @en_reg_bit: clk enable/disable bit
- * @ops: clk enable/disable ops - generic_clkops selected if NULL
- * @recalc: pointer to clock rate recalculate function
- * @set_rate: pointer to clock set rate function
- * @calc_rate: pointer to clock get rate function for index
- * @rate_config: rate configuration information, used by set_rate
- * @div_factor: division factor to parent clock.
- * @pclk: current parent clk
- * @pclk_sel: pointer to parent selection structure
- * @pclk_sel_shift: register shift for selecting parent of this clock
- * @children: list for childrens or this clock
- * @sibling: node for list of clocks having same parents
- * @private_data: clock specific private data
- * @node: list to maintain clocks linearly
- * @cl: clocklook up associated with this clock
- * @dent: object for debugfs
- */
-struct clk {
-        unsigned int usage_count;
-        unsigned int flags;
-        unsigned long rate;
-        void __iomem *en_reg;
-        u8 en_reg_bit;
-        const struct clkops *ops;
-        int (*recalc) (struct clk *);
-        int (*set_rate) (struct clk *, unsigned long rate);
-        unsigned long (*calc_rate)(struct clk *, int index);
-        struct rate_config rate_config;
-        unsigned int div_factor;
-
-        struct clk *pclk;
-        struct pclk_sel *pclk_sel;
-        unsigned int pclk_sel_shift;
-
-        struct list_head children;
-        struct list_head sibling;
-        void *private_data;
-#ifdef CONFIG_DEBUG_FS
-        struct list_head node;
-        struct clk_lookup *cl;
-        struct dentry *dent;
-#endif
-};
-
-/* pll configuration structure */
-struct pll_clk_masks {
-        u32 mode_mask;
-        u32 mode_shift;
-
-        u32 norm_fdbk_m_mask;
-        u32 norm_fdbk_m_shift;
-        u32 dith_fdbk_m_mask;
-        u32 dith_fdbk_m_shift;
-        u32 div_p_mask;
-        u32 div_p_shift;
-        u32 div_n_mask;
-        u32 div_n_shift;
-};
-
-struct pll_clk_config {
-        void __iomem *mode_reg;
-        void __iomem *cfg_reg;
-        struct pll_clk_masks *masks;
-};
-
-/* pll clk rate config structure */
-struct pll_rate_tbl {
-        u8 mode;
-        u16 m;
-        u8 n;
-        u8 p;
-};
-
-/* ahb and apb bus configuration structure */
-struct bus_clk_masks {
-        u32 mask;
-        u32 shift;
-};
-
-struct bus_clk_config {
-        void __iomem *reg;
-        struct bus_clk_masks *masks;
-};
-
-/* ahb and apb clk bus rate config structure */
-struct bus_rate_tbl {
-        u8 div;
-};
-
-/* Aux clk configuration structure: applicable to UART and FIRDA */
-struct aux_clk_masks {
-        u32 eq_sel_mask;
-        u32 eq_sel_shift;
-        u32 eq1_mask;
-        u32 eq2_mask;
-        u32 xscale_sel_mask;
-        u32 xscale_sel_shift;
-        u32 yscale_sel_mask;
-        u32 yscale_sel_shift;
-};
-
-struct aux_clk_config {
-        void __iomem *synth_reg;
-        struct aux_clk_masks *masks;
-};
-
-/* aux clk rate config structure */
-struct aux_rate_tbl {
-        u16 xscale;
-        u16 yscale;
-        u8 eq;
-};
-
-/* GPT clk configuration structure */
-struct gpt_clk_masks {
-        u32 mscale_sel_mask;
-        u32 mscale_sel_shift;
-        u32 nscale_sel_mask;
-        u32 nscale_sel_shift;
-};
-
-struct gpt_clk_config {
-        void __iomem *synth_reg;
-        struct gpt_clk_masks *masks;
-};
-
-/* gpt clk rate config structure */
-struct gpt_rate_tbl {
-        u16 mscale;
-        u16 nscale;
-};
-
-/* clcd clk configuration structure */
-struct clcd_synth_masks {
-        u32 div_factor_mask;
-        u32 div_factor_shift;
-};
-
-struct clcd_clk_config {
-        void __iomem *synth_reg;
-        struct clcd_synth_masks *masks;
-};
-
-/* clcd clk rate config structure */
-struct clcd_rate_tbl {
-        u16 div;
-};
-
-/* platform specific clock functions */
-void __init clk_init(void);
-void clk_register(struct clk_lookup *cl);
-void recalc_root_clocks(void);
-
-/* clock recalc & set rate functions */
-int follow_parent(struct clk *clk);
-unsigned long pll_calc_rate(struct clk *clk, int index);
-int pll_clk_recalc(struct clk *clk);
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long bus_calc_rate(struct clk *clk, int index);
-int bus_clk_recalc(struct clk *clk);
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long gpt_calc_rate(struct clk *clk, int index);
-int gpt_clk_recalc(struct clk *clk);
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long aux_calc_rate(struct clk *clk, int index);
-int aux_clk_recalc(struct clk *clk);
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long clcd_calc_rate(struct clk *clk, int index);
-int clcd_clk_recalc(struct clk *clk);
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-
-#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
  */
 
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
                 .macro  addruart, rp, rv, tmp
                 mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/hardware.h
- *
- * Hardware definitions for SPEAr
- *
- * Copyright (C) 2010 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_HARDWARE_H
-#define __PLAT_HARDWARE_H
-
-#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.h
- *
- * SPEAr platform specific gpio pads muxing file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_PADMUX_H
-#define __PLAT_PADMUX_H
-
-#include <linux/types.h>
-
-/*
- * struct pmx_reg: configuration structure for mode reg and mux reg
- *
- * offset: offset of mode reg
- * mask: mask of mode reg
- */
-struct pmx_reg {
-        u32 offset;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev_mode: configuration structure every group of modes of a device
- *
- * ids: all modes for this configuration
- * mask: mask for supported mode
- */
-struct pmx_dev_mode {
-        u32 ids;
-        u32 mask;
-};
-
-/*
- * struct pmx_mode: mode definition structure
- *
- * name: mode name
- * mask: mode mask
- */
-struct pmx_mode {
-        char *name;
-        u32 id;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev: device definition structure
- *
- * name: device name
- * modes: device configuration array for different modes supported
- * mode_count: size of modes array
- * is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
- */
-struct pmx_dev {
-        char *name;
-        struct pmx_dev_mode *modes;
-        u8 mode_count;
-        bool is_active;
-        bool enb_on_reset;
-};
-
-/*
- * struct pmx_driver: driver definition structure
- *
- * mode: mode to be set
- * devs: array of pointer to pmx devices
- * devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
- * mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
- */
-struct pmx_driver {
-        struct pmx_mode *mode;
-        struct pmx_dev **devs;
-        u8 devs_count;
-        u32 *base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-};
-
-/* pmx functions */
-int pmx_register(struct pmx_driver *driver);
-
-#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.c
- *
- * SPEAr platform specific gpio pads muxing source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <plat/padmux.h>
-
-/*
- * struct pmx: pmx definition structure
- *
- * base: base address of configuration registers
- * mode_reg: mode configurations
- * mux_reg: muxing configurations
- * active_mode: pointer to current active mode
- */
-struct pmx {
-        u32 base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-        struct pmx_mode *active_mode;
-};
-
-static struct pmx *pmx;
-
-/**
- * pmx_mode_set - Enables an multiplexing mode
- * @mode - pointer to pmx mode
- *
- * It will set mode of operation in hardware.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_mode_set(struct pmx_mode *mode)
-{
-        u32 val;
-
-        if (!mode->name)
-                return -EFAULT;
-
-        pmx->active_mode = mode;
-
-        val = readl(pmx->base + pmx->mode_reg.offset);
-        val &= ~pmx->mode_reg.mask;
-        val |= mode->mask & pmx->mode_reg.mask;
-        writel(val, pmx->base + pmx->mode_reg.offset);
-
-        return 0;
-}
-
-/**
- * pmx_devs_enable - Enables list of devices
- * @devs - pointer to pmx device array
- * @count - number of devices to enable
- *
- * It will enable pads for all required peripherals once and only once.
- * If peripheral is not supported by current mode then request is rejected.
- * Conflicts between peripherals are not handled and peripherals will be
- * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
-{
-        u32 val, i, mask;
-
-        if (!count)
-                return -EINVAL;
-
-        val = readl(pmx->base + pmx->mux_reg.offset);
-        for (i = 0; i < count; i++) {
-                u8 j = 0;
-
-                if (!devs[i]->name || !devs[i]->modes) {
-                        printk(KERN_ERR "padmux: dev name or modes is null\n");
-                        continue;
-                }
-                /* check if peripheral exists in active mode */
-                if (pmx->active_mode) {
-                        bool found = false;
-                        for (j = 0; j < devs[i]->mode_count; j++) {
-                                if (devs[i]->modes[j].ids &
-                                                pmx->active_mode->id) {
-                                        found = true;
-                                        break;
-                                }
-                        }
-                        if (found == false) {
-                                printk(KERN_ERR "%s device not available in %s"\
-                                                "mode\n", devs[i]->name,
-                                                pmx->active_mode->name);
-                                continue;
-                        }
-                }
-
-                /* enable peripheral */
-                mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
-                if (devs[i]->enb_on_reset)
-                        val &= ~mask;
-                else
-                        val |= mask;
-
-                devs[i]->is_active = true;
-        }
-        writel(val, pmx->base + pmx->mux_reg.offset);
-        kfree(pmx);
-
-        /* this will ensure that multiplexing can't be changed now */
-        pmx = (struct pmx *)-1;
-
-        return 0;
-}
-
-/**
- * pmx_register - registers a platform requesting pad mux feature
- * @driver - pointer to driver structure containing driver specific parameters
- *
- * Also this must be called only once. This will allocate memory for pmx
- * structure, will call pmx_mode_set, will call pmx_devs_enable.
- * Returns -ve on Err otherwise 0
- */
-int pmx_register(struct pmx_driver *driver)
-{
-        int ret = 0;
-
-        if (pmx)
-                return -EPERM;
-        if (!driver->base || !driver->devs)
-                return -EFAULT;
-
-        pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
-        if (!pmx)
-                return -ENOMEM;
-
-        pmx->base = (u32)driver->base;
-        pmx->mode_reg.offset = driver->mode_reg.offset;
-        pmx->mode_reg.mask = driver->mode_reg.mask;
-        pmx->mux_reg.offset = driver->mux_reg.offset;
-        pmx->mux_reg.mask = driver->mux_reg.mask;
-
-        /* choose mode to enable */
-        if (driver->mode) {
-                ret = pmx_mode_set(driver->mode);
-                if (ret)
-                        goto pmx_fail;
-        }
-        ret = pmx_devs_enable(driver->devs, driver->devs_count);
-        if (ret)
-                goto pmx_fail;
-
-        return 0;
-
-pmx_fail:
-        return ret;
-}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..a56a067717c1
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+        unsigned char busy;
+        unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned int signal = cd->min_signal, val;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* Return if signal is already acquired by somebody else */
+        if (signals[signal].busy &&
+                        (signals[signal].val != cd->muxval)) {
+                spin_unlock_irqrestore(&lock, flags);
+                return -EBUSY;
+        }
+
+        /* If acquiring for the first time, configure it */
+        if (!signals[signal].busy) {
+                val = readl(DMA_CHN_CFG);
+
+                /*
+                 * Each request line has two bits in DMA_CHN_CFG register. To
+                 * goto the bits of current request line, do left shift of
+                 * value by 2 * signal number.
+                 */
+                val &= ~(0x3 << (signal * 2));
+                val |= cd->muxval << (signal * 2);
+                writel(val, DMA_CHN_CFG);
+        }
+
+        signals[signal].busy++;
+        signals[signal].val = cd->muxval;
+        spin_unlock_irqrestore(&lock, flags);
+
+        return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* if signal is not used */
+        if (!signals[cd->min_signal].busy)
+                BUG();
+
+        signals[cd->min_signal].busy--;
+
+        spin_unlock_irqrestore(&lock, flags);
+}
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..4471a232713a 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #include <mach/generic.h>
 
 void spear_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..03321af5de9f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,15 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
         .handler = spear_timer_interrupt
 };
 
-static void __init spear_clockevent_init(void)
+static void __init spear_clockevent_init(int irq)
 {
         u32 tick_rate;
 
@@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
 
         clockevents_register_device(&clkevt);
 
-        setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+        setup_irq(irq, &spear_timer_irq);
 }
 
-void __init spear_setup_timer(void)
+const static struct of_device_id timer_of_match[] __initconst = {
+        { .compatible = "st,spear-timer", },
+        { },
+};
+
+void __init spear_setup_of_timer(void)
 {
-        int ret;
+        struct device_node *np;
+        int irq, ret;
+
+        np = of_find_matching_node(NULL, timer_of_match);
+        if (!np) {
+                pr_err("%s: No timer passed via DT\n", __func__);
+                return;
+        }
 
-        if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
-                pr_err("%s:cannot get IO addr\n", __func__);
+        irq = irq_of_parse_and_map(np, 0);
+        if (!irq) {
+                pr_err("%s: No irq passed for timer via DT\n", __func__);
                 return;
         }
 
-        gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+        gpt_base = of_iomap(np, 0);
         if (!gpt_base) {
-                pr_err("%s:ioremap failed for gpt\n", __func__);
-                goto err_mem;
+                pr_err("%s: of iomap failed\n", __func__);
+                return;
         }
 
         gpt_clk = clk_get_sys("gpt0", NULL);
@@ -219,21 +233,19 @@ void __init spear_setup_timer(void)
                 goto err_iomap;
         }
 
-        ret = clk_enable(gpt_clk);
+        ret = clk_prepare_enable(gpt_clk);
         if (ret < 0) {
-                pr_err("%s:couldn't enable gpt clock\n", __func__);
-                goto err_clk;
+                pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
+                goto err_prepare_enable_clk;
         }
 
-        spear_clockevent_init();
+        spear_clockevent_init(irq);
         spear_clocksource_init();
 
         return;
 
-err_clk:
+err_prepare_enable_clk:
         clk_put(gpt_clk);
 err_iomap:
         iounmap(gpt_base);
-err_mem:
-        release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
 }
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 858748eaa144..bc683b8219b5 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -17,6 +17,8 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/user.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -529,6 +531,103 @@ void vfp_flush_hwstate(struct thread_info *thread)
 }
 
 /*
+ * Save the current VFP state into the provided structures and prepare
+ * for entry into a new function (signal handler).
+ */
+int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
+                                    struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        int err = 0;
+
+        /* Ensure that the saved hwstate is up-to-date. */
+        vfp_sync_hwstate(thread);
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
+                              sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __put_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+        /*
+         * Copy the exception registers.
+         */
+        __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
+        __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+        if (err)
+                return -EFAULT;
+
+        /* Ensure that VFP is disabled. */
+        vfp_flush_hwstate(thread);
+
+        /*
+         * As per the PCS, clear the length and stride bits for function
+         * entry.
+         */
+        hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
+
+        /*
+         * Disable VFP in the hwstate so that we can detect if it gets
+         * used.
+         */
+        hwstate->fpexc &= ~FPEXC_EN;
+        return 0;
+}
+
+/* Sanitise and restore the current VFP state from the provided structures. */
+int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
+                             struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        unsigned long fpexc;
+        int err = 0;
+
+        /*
+         * If VFP has been used, then disable it to avoid corrupting
+         * the new thread state.
+         */
+        if (hwstate->fpexc & FPEXC_EN)
+                vfp_flush_hwstate(thread);
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
+                                sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __get_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+        /*
+         * Sanitise and restore the exception registers.
+         */
+        __get_user_error(fpexc, &ufp_exc->fpexc, err);
+
+        /* Ensure the VFP is enabled. */
+        fpexc |= FPEXC_EN;
+
+        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
+        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
+        hwstate->fpexc = fpexc;
+
+        __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+        return err ? -EFAULT : 0;
+}
+
+/*
  * VFP hardware can lose all context when a CPU goes offline.
  * As we will be running in SMP mode with CPU hotplug, we will save the
  * hardware state at every thread switch.  We clear our held state when
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 1633a6f306c0..85038f54354d 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
         .name = "rtc-bfin",
         .id   = -1,
 };
-#endif
+#endif  /* CONFIG_RTC_DRV_BFIN */
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
@@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART0 */
 #ifdef CONFIG_SERIAL_BFIN_UART1
 static struct resource bfin_uart1_resources[] = {
         {
@@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART1 */
 #ifdef CONFIG_SERIAL_BFIN_UART2
 static struct resource bfin_uart2_resources[] = {
         {
@@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
                 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
         },
 };
-#endif
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART2 */
+#endif  /* CONFIG_SERIAL_BFIN */
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 #ifdef CONFIG_BFIN_SIR0
@@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
         .resource = bfin_sir0_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR0 */
 #ifdef CONFIG_BFIN_SIR1
 static struct resource bfin_sir1_resources[] = {
         {
@@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
         .resource = bfin_sir1_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR1 */
 #ifdef CONFIG_BFIN_SIR2
 static struct resource bfin_sir2_resources[] = {
         {
@@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
         .num_resources = ARRAY_SIZE(bfin_sir2_resources),
         .resource = bfin_sir2_resources,
 };
-#endif
-#endif
+#endif  /* CONFIG_BFIN_SIR2 */
+#endif  /* CONFIG_BFIN_SIR */
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT0_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 static struct resource bfin_sport1_uart_resources[] = {
         {
@@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT1_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 static struct resource bfin_sport2_uart_resources[] = {
         {
@@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT2_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
 static struct resource bfin_sport3_uart_resources[] = {
         {
@@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
                 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
         },
 };
-#endif
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT3_UART */
+#endif  /* CONFIG_SERIAL_BFIN_SPORT */
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 static unsigned short bfin_can_peripherals[] = {
@@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
                 .platform_data = &bfin_can_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_CAN_BFIN */
 
 /*
  *  USB-LAN EzExtender board
@@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
                 .platform_data  = &smc91x_info,
         },
 };
-#endif
+#endif  /* CONFIG_SMC91X */
 
 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
@@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
 };
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
+#endif  /* CONFIG_SPI_BFIN5XX */
 
 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 #include <linux/spi/ad7879.h>
@@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
         .gpio_export            = 1,    /* Export GPIO to gpiolib */
         .gpio_base              = -1,   /* Dynamic allocation */
 };
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879 */
 
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
@@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
                 .platform_data = &bfin_lq035q1_data,
         },
 };
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
@@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .controller_data = &spi_flash_chip_info,
                 .mode = SPI_MODE_3,
         },
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
         {
                 .modalias = "ad7879",
@@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .chip_select = 1,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879_SPI */
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
         {
                 .modalias = "bfin-lq035q1-spi",
@@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .chip_select = 2,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
         {
                 .modalias = "spidev",
@@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 1,
         },
-#endif
+#endif  /* CONFIG_SPI_SPIDEV */
 };
 
 /* SPI (0) */
@@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
                 },
 };
 
-#endif  /* spi master and devices */
-
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
         [0] = {
@@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
         .resource = bfin_twi1_resource,
 };
-#endif
-#endif
+#endif  /* CONFIG_BF542 */
+#endif  /* CONFIG_I2C_BLACKFIN_TWI */
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/gpio_keys.h>
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 37302218ca4a..0f2367cc5493 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
+#include <linux/module.h>
 
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);
diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c
index 18c4f0b0f4ba..ff02821bfb7e 100644
--- a/arch/hexagon/kernel/process.c
+++ b/arch/hexagon/kernel/process.c
@@ -1,7 +1,7 @@
 /*
  * Process creation support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
 void cpu_idle(void)
 {
         while (1) {
-                tick_nohz_stop_sched_tick(1);
+                tick_nohz_idle_enter();
                 local_irq_disable();
                 while (!need_resched()) {
                         idle_sleep();
@@ -97,7 +97,7 @@ void cpu_idle(void)
                         local_irq_disable();
                 }
                 local_irq_enable();
-                tick_nohz_restart_sched_tick();
+                tick_nohz_idle_exit();
                 schedule();
         }
 }
diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index 32342de1a79c..96c3b2c4dbad 100644
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -28,6 +28,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/user.h>
+#include <linux/elf.h>
 
 #include <asm/user.h>
 
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 9b44a9e2d05a..1298141874a3 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
  * SMP support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -28,6 +28,7 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/cpu.h>
 
 #include <asm/time.h>    /*  timer_interrupt  */
 #include <asm/hexagon_vm.h>
@@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
 
         printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
 
+        notify_cpu_starting(cpu);
+
+        ipi_call_lock();
         set_cpu_online(cpu, true);
+        ipi_call_unlock();
+
         local_irq_enable();
 
         cpu_idle();
diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c
index 6bee15c9c113..5d9b33b67935 100644
--- a/arch/hexagon/kernel/time.c
+++ b/arch/hexagon/kernel/time.c
@@ -28,6 +28,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/module.h>
 
 #include <asm/timer-regs.h>
 #include <asm/hexagon_vm.h>
diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index f212a453b527..5d39f42f7085 100644
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/binfmts.h>
 
 #include <asm/vdso.h>
 
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index e21507052066..9c717bf98ffe 100644
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
 
 static int ar933x_wmac_reset(void)
 {
-        ath79_device_reset_clear(AR933X_RESET_WMAC);
         ath79_device_reset_set(AR933X_RESET_WMAC);
+        ath79_device_reset_clear(AR933X_RESET_WMAC);
 
         return 0;
 }
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index a865c983c70a..5ad1a9c113c6 100644
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -45,7 +45,7 @@
 #define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
 
 /* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (x))
 
 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
 #define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 73c0d45798de..9b02cfba7449 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
                 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
         } while (0)
 
-
-static inline unsigned long get_current_pgd(void)
-{
-        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
-}
-
 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 185ca00c4c84..d5a338a1739c 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         sig = restore_sigcontext(&regs, &frame->sf_sc);
         if (sig < 0)
@@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
@@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
         if (ret)
                 return ret;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        block_sigmask(ka, sig);
 
         return ret;
 }
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 06b5da392e24..ac3b8d89aae5 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         sig = restore_sigcontext32(&regs, &frame->sf_sc);
         if (sig < 0)
@@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index ae29e894ab8d..86eb4b04631c 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
         sigset_from_compat(&newset, &uset);
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 4f004596a6e7..0b3393381a81 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
 
 static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
 {
-        if (!tty->count) {
+        if (tty->count == 1) {
                 del_timer_sync(&pdc_console_timer);
                 tty_port_tty_set(&tty_port, NULL);
         }
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
new file mode 100644
index 000000000000..1cf0b77b1efe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+message@42400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x42400 0x200>;
+        interrupts = <
+                0xb4 2 0 0
+                0xb5 2 0 0
+                0xb6 2 0 0
+                0xb7 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index fdedf7b1fe0f..71c30eb10056 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -53,6 +53,16 @@ timer@41100 {
                       3 0 3 0>;
 };
 
+message@41400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x41400 0x200>;
+        interrupts = <
+                0xb0 2 0 0
+                0xb1 2 0 0
+                0xb2 2 0 0
+                0xb3 2 0 0>;
+};
+
 msi@41600 {
         compatible = "fsl,mpic-msi";
         reg = <0x41600 0x80>;
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index e648af92ced1..0e40843a1c6e 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -18,10 +18,6 @@
 #include <linux/atomic.h>
 
 
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-        for ((i) = 0; (i) < NR_IRQS; ++(i))
-
 extern atomic_t ppc_n_lost_interrupts;
 
 /* This number is used when no interrupt has been assigned */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c65b9294376e..c9f698a994be 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -275,9 +275,6 @@ struct mpic
         unsigned int            isu_mask;
         /* Number of sources */
         unsigned int            num_sources;
-        /* default senses array */
-        unsigned char           *senses;
-        unsigned int            senses_count;
 
         /* vector numbers used for internal sources (ipi/timers) */
         unsigned int            ipi_vecs[4];
@@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                             phys_addr_t phys_addr);
 
-/* Set default sense codes
- *
- * @mpic:       controller
- * @senses:     array of sense codes
- * @count:      size of above array
- *
- * Optionally provide an array (indexed on hardware interrupt numbers
- * for this MPIC) of default sense codes for the chip. Those are linux
- * sense codes IRQ_TYPE_*
- *
- * The driver gets ownership of the pointer, don't dispose of it or
- * anything like that. __init only.
- */
-extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
-
 
 /* Initialize the controller. After this has been called, none of the above
  * should be called again for this mpic
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc9003e..326d33ca55cd 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#include <asm/smp.h>
 
 struct mpic_msgr {
         u32 __iomem *base;
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b86faa9107da..8a97aa7289d3 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,11 +15,6 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
 
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
-
 /* Machine State Register (MSR) Fields */
 #define MSR_GS          (1<<28) /* Guest state */
 #define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5ec1b2354ca6..43eb74fcedde 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -330,14 +330,10 @@ void migrate_irqs(void)
 
         alloc_cpumask_var(&mask, GFP_KERNEL);
 
-        for_each_irq(irq) {
+        for_each_irq_desc(irq, desc) {
                 struct irq_data *data;
                 struct irq_chip *chip;
 
-                desc = irq_to_desc(irq);
-                if (!desc)
-                        continue;
-
                 data = irq_desc_get_irq_data(desc);
                 if (irqd_is_per_cpu(data))
                         continue;
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index c957b1202bdc..5df777794403 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -23,14 +23,11 @@
 
 void machine_kexec_mask_interrupts(void) {
         unsigned int i;
+        struct irq_desc *desc;
 
-        for_each_irq(i) {
-                struct irq_desc *desc = irq_to_desc(i);
+        for_each_irq_desc(i, desc) {
                 struct irq_chip *chip;
 
-                if (!desc)
-                        continue;
-
                 chip = irq_desc_get_chip(desc);
                 if (!chip)
                         continue;
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9825f29d1faf..ec8a53fa9e8f 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
 }
 
 #ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+
 /* Checks wdt=x and wdt_period=xx command-line option */
 notrace int __init early_parse_wdt(char *p)
 {
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index af1ab5e9a691..5c3cf2d04e41 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -48,7 +48,13 @@
 /*
  * Assembly helpers from arch/powerpc/net/bpf_jit.S:
  */
-extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
+#define DECLARE_LOAD_FUNC(func) \
+        extern u8 func[], func##_negative_offset[], func##_positive_offset[]
+
+DECLARE_LOAD_FUNC(sk_load_word);
+DECLARE_LOAD_FUNC(sk_load_half);
+DECLARE_LOAD_FUNC(sk_load_byte);
+DECLARE_LOAD_FUNC(sk_load_byte_msh);
 
 #define FUNCTION_DESCR_SIZE     24
 
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index ff4506e85cce..55ba3855a97f 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -31,14 +31,13 @@
  * then branch directly to slow_path_XXX if required.  (In fact, could
  * load a spare GPR with the address of slow_path_generic and pass size
  * as an argument, making the call site a mtlr, li and bllr.)
- *
- * Technically, the "is addr < 0" check is unnecessary & slowing down
- * the ABS path, as it's statically checked on generation.
  */
         .globl  sk_load_word
 sk_load_word:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_word_neg
+        .globl  sk_load_word_positive_offset
+sk_load_word_positive_offset:
         /* Are we accessing past headlen? */
         subi    r_scratch1, r_HL, 4
         cmpd    r_scratch1, r_addr
@@ -51,7 +50,9 @@ sk_load_word:
         .globl  sk_load_half
 sk_load_half:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_half_neg
+        .globl  sk_load_half_positive_offset
+sk_load_half_positive_offset:
         subi    r_scratch1, r_HL, 2
         cmpd    r_scratch1, r_addr
         blt     bpf_slow_path_half
@@ -61,7 +62,9 @@ sk_load_half:
         .globl  sk_load_byte
 sk_load_byte:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_byte_neg
+        .globl  sk_load_byte_positive_offset
+sk_load_byte_positive_offset:
         cmpd    r_HL, r_addr
         ble     bpf_slow_path_byte
         lbzx    r_A, r_D, r_addr
@@ -69,22 +72,20 @@ sk_load_byte:
 
 /*
  * BPF_S_LDX_B_MSH: ldxb  4*([offset]&0xf)
- * r_addr is the offset value, already known positive
+ * r_addr is the offset value
  */
         .globl sk_load_byte_msh
 sk_load_byte_msh:
+        cmpdi   r_addr, 0
+        blt     bpf_slow_path_byte_msh_neg
+        .globl sk_load_byte_msh_positive_offset
+sk_load_byte_msh_positive_offset:
         cmpd    r_HL, r_addr
         ble     bpf_slow_path_byte_msh
         lbzx    r_X, r_D, r_addr
         rlwinm  r_X, r_X, 2, 32-4-2, 31-2
         blr
 
-bpf_error:
-        /* Entered with cr0 = lt */
-        li      r3, 0
-        /* Generated code will 'blt epilogue', returning 0. */
-        blr
-
 /* Call out to skb_copy_bits:
  * We'll need to back up our volatile regs first; we have
  * local variable space at r1+(BPF_PPC_STACK_BASIC).
@@ -136,3 +137,84 @@ bpf_slow_path_byte_msh:
         lbz     r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
         rlwinm  r_X, r_X, 2, 32-4-2, 31-2
         blr
+
+/* Call out to bpf_internal_load_pointer_neg_helper:
+ * We'll need to back up our volatile regs first; we have
+ * local variable space at r1+(BPF_PPC_STACK_BASIC).
+ * Allocate a new stack frame here to remain ABI-compliant in
+ * stashing LR.
+ */
+#define sk_negative_common(SIZE)                                \
+        mflr    r0;                                             \
+        std     r0, 16(r1);                                     \
+        /* R3 goes in parameter space of caller's frame */      \
+        std     r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        std     r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        std     r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        stdu    r1, -BPF_PPC_SLOWPATH_FRAME(r1);                \
+        /* R3 = r_skb, as passed */                             \
+        mr      r4, r_addr;                                     \
+        li      r5, SIZE;                                       \
+        bl      bpf_internal_load_pointer_neg_helper;           \
+        /* R3 != 0 on success */                                \
+        addi    r1, r1, BPF_PPC_SLOWPATH_FRAME;                 \
+        ld      r0, 16(r1);                                     \
+        ld      r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        ld      r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        mtlr    r0;                                             \
+        cmpldi  r3, 0;                                          \
+        beq     bpf_error_slow; /* cr0 = EQ */                  \
+        mr      r_addr, r3;                                     \
+        ld      r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        /* Great success! */
+
+bpf_slow_path_word_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_word_negative_offset
+sk_load_word_negative_offset:
+        sk_negative_common(4)
+        lwz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_half_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_half_negative_offset
+sk_load_half_negative_offset:
+        sk_negative_common(2)
+        lhz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_byte_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_negative_offset
+sk_load_byte_negative_offset:
+        sk_negative_common(1)
+        lbz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_byte_msh_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_msh_negative_offset
+sk_load_byte_msh_negative_offset:
+        sk_negative_common(1)
+        lbz     r_X, 0(r_addr)
+        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+        blr
+
+bpf_error_slow:
+        /* fabricate a cr0 = lt */
+        li      r_scratch1, -1
+        cmpdi   r_scratch1, 0
+bpf_error:
+        /* Entered with cr0 = lt */
+        li      r3, 0
+        /* Generated code will 'blt epilogue', returning 0. */
+        blr
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 73619d3aeb6c..2dc8b1484845 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
         PPC_BLR();
 }
 
+#define CHOOSE_LOAD_FUNC(K, func) \
+        ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
+
 /* Assemble the body code between the prologue & epilogue. */
 static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                               struct codegen_context *ctx,
@@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
 
                         /*** Absolute loads from packet header/data ***/
                 case BPF_S_LD_W_ABS:
-                        func = sk_load_word;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_word);
                         goto common_load;
                 case BPF_S_LD_H_ABS:
-                        func = sk_load_half;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_half);
                         goto common_load;
                 case BPF_S_LD_B_ABS:
-                        func = sk_load_byte;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte);
                 common_load:
-                        /*
-                         * Load from [K].  Reference with the (negative)
-                         * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
-                         */
+                        /* Load from [K]. */
                         ctx->seen |= SEEN_DATAREF;
-                        if ((int)K < 0)
-                                return -ENOTSUPP;
                         PPC_LI64(r_scratch1, func);
                         PPC_MTLR(r_scratch1);
                         PPC_LI32(r_addr, K);
@@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                 common_load_ind:
                         /*
                          * Load from [X + K].  Negative offsets are tested for
-                         * in the helper functions, and result in a 'ret 0'.
+                         * in the helper functions.
                          */
                         ctx->seen |= SEEN_DATAREF | SEEN_XREG;
                         PPC_LI64(r_scratch1, func);
@@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                         break;
 
                 case BPF_S_LDX_B_MSH:
-                        /*
-                         * x86 version drops packet (RET 0) when K<0, whereas
-                         * interpreter does allow K<0 (__load_pointer, special
-                         * ancillary data).  common_load returns ENOTSUPP if K<0,
-                         * so we fall back to interpreter & filter works.
-                         */
-                        func = sk_load_byte_msh;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh);
                         goto common_load;
                         break;
 
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 9fef5302adc1..67dac22b4363 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
         { .compatible = "fsl,qe", },
         { .compatible = "fsl,cpm2", },
         { .compatible = "fsl,srio", },
+        /* So that the DMA channel nodes can be probed individually: */
+        { .compatible = "fsl,eloplus-dma", },
+        /* For the PMC driver */
+        { .compatible = "fsl,mpc8548-guts", },
+        /* Probably unnecessary? */
+        { .compatible = "gpio-leds", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 9a6f04406e0d..d208ebccb91c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -399,12 +399,6 @@ static int __init board_fixups(void)
 machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
 
-static struct of_device_id mpc85xx_ids[] = {
-        { .compatible = "fsl,mpc8548-guts", },
-        { .compatible = "gpio-leds", },
-        {},
-};
-
 static int __init mpc85xx_publish_devices(void)
 {
         if (machine_is(mpc8568_mds))
@@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-        mpc85xx_common_publish_devices();
-        of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
-
-        return 0;
+        return mpc85xx_common_publish_devices();
 }
 
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e74b7cde9aee..f700c81a1321 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
         pr_info("Freescale P1022 DS reference board\n");
 }
 
-static struct of_device_id __initdata p1022_ds_ids[] = {
-        /* So that the DMA channel nodes can be probed individually: */
-        { .compatible = "fsl,eloplus-dma", },
-        {},
-};
-
-static int __init p1022_ds_publish_devices(void)
-{
-        mpc85xx_common_publish_devices();
-        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
-}
-machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index d09f3e8e6867..85825b5401e5 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
                 pr_devel("axon_msi: woff %x roff %x msi %x\n",
                           write_offset, msic->read_offset, msi);
 
-                if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
+                if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
                         generic_handle_irq(msi);
                         msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
                 } else {
@@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         if (rc)
                 return rc;
 
-        /* We rely on being able to stash a virq in a u16 */
-        BUILD_BUG_ON(NR_IRQS > 65536);
-
         list_for_each_entry(entry, &dev->msi_list, list) {
                 virq = irq_create_direct_mapping(msic->irq_domain);
                 if (virq == NO_IRQ) {
@@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
         }
         memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
 
-        msic->irq_domain = irq_domain_add_nomap(dn, 0, &msic_host_ops, msic);
+        /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
+        msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
         if (!msic->irq_domain) {
                 printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
                        dn->full_name);
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index f9a48af335cb..8c6dc42ecf65 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
 {
         int     i;
 
-        for (i = 1; i < NR_IRQS; i++)
+        for (i = 1; i < nr_irqs; i++)
                 beat_destruct_irq_plug(i);
 }
diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c
index 996c5ff7824b..03685a329d7d 100644
--- a/arch/powerpc/platforms/powermac/low_i2c.c
+++ b/arch/powerpc/platforms/powermac/low_i2c.c
@@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
         unsigned long flags;
 
         spin_lock_irqsave(&host->lock, flags);
+
+        /*
+         * If the timer is pending, that means we raced with the
+         * irq, in which case we just return
+         */
+        if (timer_pending(&host->timeout_timer))
+                goto skip;
+
         kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
         if (host->state != state_idle) {
                 host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
                 add_timer(&host->timeout_timer);
         }
+ skip:
         spin_unlock_irqrestore(&host->lock, flags);
 }
 
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 66ad93de1d55..c4e630576ff2 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -57,9 +57,9 @@ static int max_real_irqs;
 
 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
 
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+/* The max irq number this driver deals with is 128; see max_irqs */
+static DECLARE_BITMAP(ppc_lost_interrupts, 128);
+static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
 static int pmac_irq_cascade = -1;
 static struct irq_domain *pmac_pic_host;
 
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index aadbe4f6d537..178a5f300bc9 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -30,9 +30,9 @@ config PPC_SPLPAR
           two or more partitions.
 
 config EEH
-        bool "PCI Extended Error Handling (EEH)" if EXPERT
+        bool
         depends on PPC_PSERIES && PCI
-        default y if !EXPERT
+        default y
 
 config PSERIES_MSI
        bool
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 309d38ef7322..a75e37dc41aa 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
         pr_debug("EEH: Adding device %s\n", pci_name(dev));
 
         dn = pci_device_to_OF_node(dev);
-        edev = pci_dev_to_eeh_dev(dev);
+        edev = of_node_to_eeh_dev(dn);
         if (edev->pdev == dev) {
                 pr_debug("EEH: Already referenced !\n");
                 return;
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index d3be961e2ae7..10386b676d87 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -51,8 +51,7 @@
 static intctl_cpm2_t __iomem *cpm2_intctl;
 
 static struct irq_domain *cpm2_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
 
 static const u_char irq_to_siureg[] = {
         1, 1, 1, 1, 1, 1, 1, 1,
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index d5f5416be310..b724622c3a0b 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -18,69 +18,45 @@
 extern int cpm_get_irq(struct pt_regs *regs);
 
 static struct irq_domain *mpc8xx_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long mpc8xx_cached_irq_mask;
 static sysconf8xx_t __iomem *siu_reg;
 
-int cpm_get_irq(struct pt_regs *regs);
+static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
+{
+        return 0x80000000 >> irqd_to_hwirq(d);
+}
 
 static void mpc8xx_unmask_irq(struct irq_data *d)
 {
-        int     bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_mask_irq(struct irq_data *d)
 {
-        int     bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_ack(struct irq_data *d)
 {
-        int     bit;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
+        out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
 }
 
 static void mpc8xx_end_irq(struct irq_data *d)
 {
-        int bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        if (flow_type & IRQ_TYPE_EDGE_FALLING) {
-                irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
+        /* only external IRQ senses are programmable */
+        if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
                 unsigned int siel = in_be32(&siu_reg->sc_siel);
-
-                /* only external IRQ senses are programmable */
-                if ((hw & 1) == 0) {
-                        siel |= (0x80000000 >> hw);
-                        out_be32(&siu_reg->sc_siel, siel);
-                        __irq_set_handler_locked(d->irq, handle_edge_irq);
-                }
+                siel |= mpc8xx_irqd_to_bit(d);
+                out_be32(&siu_reg->sc_siel, siel);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         }
         return 0;
 }
@@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
                 IRQ_TYPE_EDGE_FALLING,
         };
 
+        if (intspec[0] > 0x1f)
+                return 0;
+
         *out_hwirq = intspec[0];
         if (intsize > 1 && intspec[1] < 4)
                 *out_flags = map_pic_senses[intspec[1]];
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9ac71ebd2c40..395af1347749 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
 }
 
 /* Determine if the linux irq is an IPI */
-static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
-
         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 
 /* Determine if the linux irq is a timer */
-static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
-
         return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 }
 
@@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         if (src >= mpic->num_sources)
                 return -EINVAL;
 
+        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+
+        /* We don't support "none" type */
         if (flow_type == IRQ_TYPE_NONE)
-                if (mpic->senses && src < mpic->senses_count)
-                        flow_type = mpic->senses[src];
-        if (flow_type == IRQ_TYPE_NONE)
-                flow_type = IRQ_TYPE_LEVEL_LOW;
+                flow_type = IRQ_TYPE_DEFAULT;
+
+        /* Default: read HW settings */
+        if (flow_type == IRQ_TYPE_DEFAULT) {
+                switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
+                               MPIC_INFO(VECPRI_SENSE_MASK))) {
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_EDGE_RISING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_EDGE_FALLING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_LEVEL_HIGH;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_LEVEL_LOW;
+                                break;
+                }
+        }
 
+        /* Apply to irq desc */
         irqd_set_trigger_type(d, flow_type);
 
+        /* Apply to HW */
         if (mpic_is_ht_interrupt(mpic, src))
                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
                         MPIC_VECPRI_SENSE_EDGE;
         else
                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 
-        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
                         MPIC_INFO(VECPRI_SENSE_MASK));
         vnew |= vecpri;
@@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 
         /* Set default irq type */
-        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
 
         /* If the MPIC was reset, then all vectors have already been
          * initialized.  Otherwise, a per source lazy initialization
@@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                 mpic->num_sources = isu_first + mpic->isu_size;
 }
 
-void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
-{
-        mpic->senses = senses;
-        mpic->senses_count = count;
-}
-
 void __init mpic_init(struct mpic *mpic)
 {
         int i, cpu;
@@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                 return;
 
         raw_spin_lock_irqsave(&mpic_lock, flags);
-        if (mpic_is_ipi(mpic, irq)) {
+        if (mpic_is_ipi(mpic, src)) {
                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                         ~MPIC_VECPRI_PRIORITY_MASK;
                 mpic_ipi_write(src - mpic->ipi_vecs[0],
                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
-        } else if (mpic_is_tm(mpic, irq)) {
+        } else if (mpic_is_tm(mpic, src)) {
                 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
                         ~MPIC_VECPRI_PRIORITY_MASK;
                 mpic_tm_write(src - mpic->timer_vecs[0],
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 6e7fa386e76a..483d8fa72e8b 100644
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -27,6 +27,7 @@
 
 static struct mpic_msgr **mpic_msgrs;
 static unsigned int mpic_msgr_count;
+static DEFINE_RAW_SPINLOCK(msgrs_lock);
 
 static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
 {
@@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
         if (reg_num >= mpic_msgr_count)
                 return ERR_PTR(-ENODEV);
 
-        raw_spin_lock_irqsave(&msgr->lock, flags);
-        if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
-                msgr = mpic_msgrs[reg_num];
+        raw_spin_lock_irqsave(&msgrs_lock, flags);
+        msgr = mpic_msgrs[reg_num];
+        if (msgr->in_use == MSGR_FREE)
                 msgr->in_use = MSGR_INUSE;
-        }
-        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+        raw_spin_unlock_irqrestore(&msgrs_lock, flags);
 
         return msgr;
 }
@@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
 
                 reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
                 msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
-                msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+                msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
                 msgr->in_use = MSGR_FREE;
                 msgr->num = i;
                 raw_spin_lock_init(&msgr->lock);
diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c
index 49a3ece1c6b3..702256a1ca11 100644
--- a/arch/powerpc/sysdev/scom.c
+++ b/arch/powerpc/sysdev/scom.c
@@ -22,6 +22,7 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <asm/debug.h>
 #include <asm/prom.h>
 #include <asm/scom.h>
 
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index ea5e204e3450..cd1d18db92c6 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
 {
         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
         unsigned int irq, virq;
+        struct irq_desc *desc;
 
         /* If we used to be the default server, move to the new "boot_cpuid" */
         if (hw_cpu == xics_default_server)
@@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
         /* Allow IPIs again... */
         icp_ops->set_priority(DEFAULT_PRIORITY);
 
-        for_each_irq(virq) {
-                struct irq_desc *desc;
+        for_each_irq_desc(virq, desc) {
                 struct irq_chip *chip;
                 long server;
                 unsigned long flags;
@@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
                 /* We can't set affinity on ISA interrupts */
                 if (virq < NUM_ISA_INTERRUPTS)
                         continue;
-                desc = irq_to_desc(virq);
                 /* We only need to migrate enabled IRQS */
-                if (!desc || !desc->action)
+                if (!desc->action)
                         continue;
                 if (desc->irq_data.domain != xics_host)
                         continue;
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 37f2f4a55231..f4c1c20bcdf6 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
 
-#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+#define ATOMIC_INIT(i)  { (i) }
 
 #define atomic_read(v)          (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)         ((v)->counter = (i))
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 324eef93c900..e99b104d967a 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address)
         pte_t *pte_k;
 
         /* Make sure we are in vmalloc/module/P3 area: */
-        if (!(address >= VMALLOC_START && address < P3_ADDR_MAX))
+        if (!(address >= P3SEG && address < P3_ADDR_MAX))
                 return -1;
 
         /*
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 5d5a635530bd..32e6cbe8dff3 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -47,8 +47,8 @@ struct pci_controller {
  */
 #define PCI_DMA_BUS_IS_PHYS     1
 
-int __devinit tile_pci_init(void);
-int __devinit pcibios_init(void);
+int __init tile_pci_init(void);
+int __init pcibios_init(void);
 
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index a1bb59eecc18..b56d12bf5900 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
  *
  * Returns the number of controllers discovered.
  */
-int __devinit tile_pci_init(void)
+int __init tile_pci_init(void)
 {
         int i;
 
@@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
  * The controllers have been set up by the time we get here, by a call to
  * tile_pci_init.
  */
-int __devinit pcibios_init(void)
+int __init pcibios_init(void)
 {
         int i;
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d14cc6b79ad..c9866b0b77d8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -81,7 +81,7 @@ config X86
         select CLKEVT_I8253
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_IOMAP
-        select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
+        select DCACHE_WORD_ACCESS
 
 config INSTRUCTION_DECODER
         def_bool (KPROBES || PERF_EVENTS)
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index a0559930a180..c85e3ac99bba 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -33,6 +33,9 @@
         __HEAD
 ENTRY(startup_32)
 #ifdef CONFIG_EFI_STUB
+        jmp     preferred_addr
+
+        .balign 0x10
         /*
          * We don't need the return address, so set up the stack so
          * efi_main() can find its arugments.
@@ -41,12 +44,17 @@ ENTRY(startup_32)
 
         call    efi_main
         cmpl    $0, %eax
-        je      preferred_addr
         movl    %eax, %esi
-        call    1f
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
         popl    %eax
-        subl    $1b, %eax
+        subl    $3b, %eax
         subl    BP_pref_address(%esi), %eax
         add     BP_code32_start(%esi), %eax
         leal    preferred_addr(%eax), %eax
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 558d76ce23bc..87e03a13d8e3 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -200,18 +200,28 @@ ENTRY(startup_64)
          * entire text+data+bss and hopefully all of memory.
          */
 #ifdef CONFIG_EFI_STUB
-        pushq   %rsi
+        /*
+         * The entry point for the PE/COFF executable is 0x210, so only
+         * legacy boot loaders will execute this jmp.
+         */
+        jmp     preferred_addr
+
+        .org 0x210
         mov     %rcx, %rdi
         mov     %rdx, %rsi
         call    efi_main
-        popq    %rsi
-        cmpq    $0,%rax
-        je      preferred_addr
         movq    %rax,%rsi
-        call    1f
+        cmpq    $0,%rax
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
         popq    %rax
-        subq    $1b, %rax
+        subq    $3b, %rax
         subq    BP_pref_address(%rsi), %rax
         add     BP_code32_start(%esi), %eax
         leaq    preferred_addr(%rax), %rax
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index d3c0b0277666..fb7117a4ade1 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -403,13 +403,11 @@ static void print_absolute_symbols(void)
         for (i = 0; i < ehdr.e_shnum; i++) {
                 struct section *sec = &secs[i];
                 char *sym_strtab;
-                Elf32_Sym *sh_symtab;
                 int j;
 
                 if (sec->shdr.sh_type != SHT_SYMTAB) {
                         continue;
                 }
-                sh_symtab = sec->symtab;
                 sym_strtab = sec->link->strtab;
                 for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
                         Elf32_Sym *sym;
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ed549767a231..24443a332083 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -205,8 +205,13 @@ int main(int argc, char ** argv)
         put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
 
 #ifdef CONFIG_X86_32
-        /* Address of entry point */
-        put_unaligned_le32(i, &buf[pe_header + 0x28]);
+        /*
+         * Address of entry point.
+         *
+         * The EFI stub entry point is +16 bytes from the start of
+         * the .text section.
+         */
+        put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
 
         /* .text size */
         put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
@@ -217,9 +222,11 @@ int main(int argc, char ** argv)
         /*
          * Address of entry point. startup_32 is at the beginning and
          * the 64-bit entry point (startup_64) is always 512 bytes
-         * after.
+         * after. The EFI stub entry point is 16 bytes after that, as
+         * the first instruction allows legacy loaders to jump over
+         * the EFI stub initialisation
          */
-        put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
+        put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
 
         /* .text size */
         put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 4824fb45560f..07b3a68d2d29 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -294,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
 
         /* OK, This is the point of no return */
         set_personality(PER_LINUX);
-        set_thread_flag(TIF_IA32);
-        current->mm->context.ia32_compat = 1;
+        set_personality_ia32(false);
 
         setup_new_exec(bprm);
 
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 3427b7798dbc..7ef7c3020e5c 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -7,9 +7,9 @@
 #else
 # ifdef __i386__
 #  include "posix_types_32.h"
-# elif defined(__LP64__)
-#  include "posix_types_64.h"
-# else
+# elif defined(__ILP32__)
 #  include "posix_types_x32.h"
+# else
+#  include "posix_types_64.h"
 # endif
 #endif
diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h
index 4a085383af27..5ca71c065eef 100644
--- a/arch/x86/include/asm/sigcontext.h
+++ b/arch/x86/include/asm/sigcontext.h
@@ -257,7 +257,7 @@ struct sigcontext {
         __u64 oldmask;
         __u64 cr2;
         struct _fpstate __user *fpstate;        /* zero when no FPU context */
-#ifndef __LP64__
+#ifdef __ILP32__
         __u32 __fpstate_pad;
 #endif
         __u64 reserved1[8];
diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h
index fc1aa5535646..34c47b3341c0 100644
--- a/arch/x86/include/asm/siginfo.h
+++ b/arch/x86/include/asm/siginfo.h
@@ -2,7 +2,13 @@
 #define _ASM_X86_SIGINFO_H
 
 #ifdef __x86_64__
-# define __ARCH_SI_PREAMBLE_SIZE        (4 * sizeof(int))
+# ifdef __ILP32__ /* x32 */
+typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
+#  define __ARCH_SI_CLOCK_T             __kernel_si_clock_t
+#  define __ARCH_SI_ATTRIBUTES          __attribute__((aligned(8)))
+# else /* x86-64 */
+#  define __ARCH_SI_PREAMBLE_SIZE       (4 * sizeof(int))
+# endif
 #endif
 
 #include <asm-generic/siginfo.h>
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 37cdc9d99bb1..4437001d8e3d 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -63,10 +63,10 @@
 #else
 # ifdef __i386__
 #  include <asm/unistd_32.h>
-# elif defined(__LP64__)
-#  include <asm/unistd_64.h>
-# else
+# elif defined(__ILP32__)
 #  include <asm/unistd_x32.h>
+# else
+#  include <asm/unistd_64.h>
 # endif
 #endif
 
diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h
index 6fe6767b7124..e58f03b206c3 100644
--- a/arch/x86/include/asm/word-at-a-time.h
+++ b/arch/x86/include/asm/word-at-a-time.h
@@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a)
         return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80);
 }
 
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, dummy;
+
+        asm(
+                "1:\tmov %2,%0\n"
+                "2:\n"
+                ".section .fixup,\"ax\"\n"
+                "3:\t"
+                "lea %2,%1\n\t"
+                "and %3,%1\n\t"
+                "mov (%1),%0\n\t"
+                "leal %2,%%ecx\n\t"
+                "andl %4,%%ecx\n\t"
+                "shll $3,%%ecx\n\t"
+                "shr %%cl,%0\n\t"
+                "jmp 2b\n"
+                ".previous\n"
+                _ASM_EXTABLE(1b, 3b)
+                :"=&r" (ret),"=&c" (dummy)
+                :"m" (*(unsigned long *)addr),
+                 "i" (-sizeof(unsigned long)),
+                 "i" (sizeof(unsigned long)-1));
+        return ret;
+}
+
 #endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index baaca8defec8..764b66a4cf89 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi;
 
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
-extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
 
 #endif
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 103b6ab368d3..146a49c763a4 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
 static char temp_stack[4096];
 #endif
 
+asmlinkage void acpi_enter_s3(void)
+{
+        acpi_enter_sleep_state(3, wake_sleep_flags);
+}
 /**
  * acpi_suspend_lowlevel - save kernel state
  *
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 416d4be13fef..d68677a2a010 100644
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -3,12 +3,16 @@
  */
 
 #include <asm/trampoline.h>
+#include <linux/linkage.h>
 
 extern unsigned long saved_video_mode;
 extern long saved_magic;
 
 extern int wakeup_pmode_return;
 
+extern u8 wake_sleep_flags;
+extern asmlinkage void acpi_enter_s3(void);
+
 extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
 
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 13ab720573e3..72610839f03b 100644
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -74,9 +74,7 @@ restore_registers:
 ENTRY(do_suspend_lowlevel)
         call    save_processor_state
         call    save_registers
-        pushl   $3
-        call    acpi_enter_sleep_state
-        addl    $4, %esp
+        call    acpi_enter_s3
 
 #       In case of S3 failure, we'll emerge here.  Jump
 #       to ret_point to recover
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 8ea5164cbd04..014d1d28c397 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
         movq    %rsi, saved_rsi
 
         addq    $8, %rsp
-        movl    $3, %edi
-        xorl    %eax, %eax
-        call    acpi_enter_sleep_state
+        call    acpi_enter_s3
         /* in case something went wrong, restore the machine status and go on */
         jmp     resume_point
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 11544d8f1e97..edc24480469f 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1637,9 +1637,11 @@ static int __init apic_verify(void)
         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 
         /* The BIOS may have set up the APIC at some other address */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (l & MSR_IA32_APICBASE_ENABLE)
-                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+        if (boot_cpu_data.x86 >= 6) {
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                if (l & MSR_IA32_APICBASE_ENABLE)
+                        mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+        }
 
         pr_info("Found and enabled local APIC!\n");
         return 0;
@@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr)
          * MSR. This can only be done in software for Intel P6 or later
          * and AMD K7 (Model > 1) or later.
          */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-                l &= ~MSR_IA32_APICBASE_BASE;
-                l |= MSR_IA32_APICBASE_ENABLE | addr;
-                wrmsr(MSR_IA32_APICBASE, l, h);
-                enabled_via_apicbase = 1;
+        if (boot_cpu_data.x86 >= 6) {
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                        pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                        l &= ~MSR_IA32_APICBASE_BASE;
+                        l |= MSR_IA32_APICBASE_ENABLE | addr;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                        enabled_via_apicbase = 1;
+                }
         }
         return apic_verify();
 }
@@ -2209,10 +2213,12 @@ static void lapic_resume(void)
                  * FIXME! This will be wrong if we ever support suspend on
                  * SMP! We'll need to do this as part of the CPU restore!
                  */
-                rdmsr(MSR_IA32_APICBASE, l, h);
-                l &= ~MSR_IA32_APICBASE_BASE;
-                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-                wrmsr(MSR_IA32_APICBASE, l, h);
+                if (boot_cpu_data.x86 >= 6) {
+                        rdmsr(MSR_IA32_APICBASE, l, h);
+                        l &= ~MSR_IA32_APICBASE_BASE;
+                        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                }
         }
 
         maxlvt = lapic_get_maxlvt();
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 899803e03214..23e75422e013 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -207,8 +207,11 @@ static void __init map_csrs(void)
 
 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 {
-        c->phys_proc_id = node;
-        per_cpu(cpu_llc_id, smp_processor_id()) = node;
+
+        if (c->phys_proc_id != node) {
+                c->phys_proc_id = node;
+                per_cpu(cpu_llc_id, smp_processor_id()) = node;
+        }
 }
 
 static int __init numachip_system_init(void)
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 8a778db45e3a..991e315f4227 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         if (x2apic_phys)
                 return x2apic_enabled();
+        else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
+                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
+                x2apic_enabled()) {
+                printk(KERN_DEBUG "System requires x2apic physical mode\n");
+                return 1;
+        }
         else
                 return 0;
 }
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 0a44b90602b0..146bb6218eec 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -26,7 +26,8 @@
  *      contact AMD for precise details and a CPU swap.
  *
  *      See     http://www.multimania.com/poulot/k6bug.html
- *              http://www.amd.com/K6/k6docs/revgd.html
+ *      and     section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
+ *              (Publication # 21266  Issue Date: August 1998)
  *
  *      The following test is erm.. interesting. AMD neglected to up
  *      the chip setting when fixing the bug but they also tweaked some
@@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                                 "system stability may be impaired when more than 32 MB are used.\n");
                 else
                         printk(KERN_CONT "probably OK (after B9730xxxx).\n");
-                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
         }
 
         /* K6 with old style WHCR */
@@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
                 node = per_cpu(cpu_llc_id, cpu);
 
         /*
-         * If core numbers are inconsistent, it's likely a multi-fabric platform,
-         * so invoke platform-specific handler
+         * On multi-fabric platform (e.g. Numascale NumaChip) a
+         * platform-specific handler needs to be called to fixup some
+         * IDs of the CPU.
          */
-        if (c->phys_proc_id != node)
+        if (x86_cpuinit.fixup_cpu_id)
                 x86_cpuinit.fixup_cpu_id(c, node);
 
         if (!node_online(node)) {
@@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 }
         }
 
+        /* re-enable TopologyExtensions if switched off by BIOS */
+        if ((c->x86 == 0x15) &&
+            (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
+            !cpu_has(c, X86_FEATURE_TOPOEXT)) {
+                u64 val;
+
+                if (!rdmsrl_amd_safe(0xc0011005, &val)) {
+                        val |= 1ULL << 54;
+                        wrmsrl_amd_safe(0xc0011005, val);
+                        rdmsrl(0xc0011005, val);
+                        if (val & (1ULL << 54)) {
+                                set_cpu_cap(c, X86_FEATURE_TOPOEXT);
+                                printk(KERN_INFO FW_INFO "CPU: Re-enabling "
+                                  "disabled Topology Extensions Support\n");
+                        }
+                }
+        }
+
         cpu_detect_cache_sizes(c);
 
         /* Multi core CPU? */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 67e258362a3d..cf79302198a6 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void)
 #endif /* ! CONFIG_KGDB */
 
 /*
- * Prints an error where the NUMA and configured core-number mismatch and the
- * platform didn't override this to fix it up
- */
-void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
-{
-        pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
-}
-
-/*
  * cpu_init() initializes state that is per-CPU. Some data is already
  * initialized (naturally) in the bootstrap process, such as the GDT
  * and IDT. We reload them nevertheless, this function acts as a
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed98a64..b8f3653dddbc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
         /*  check if @slot is already used or the index is already disabled */
         ret = amd_get_l3_disable_slot(nb, slot);
         if (ret >= 0)
-                return -EINVAL;
+                return -EEXIST;
 
         if (index > nb->l3_cache.indices)
                 return -EINVAL;
 
         /* check whether the other slot has disabled the same index already */
         if (index == amd_get_l3_disable_slot(nb, !slot))
-                return -EINVAL;
+                return -EEXIST;
 
         amd_l3_disable_index(nb, cpu, slot, index);
 
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
         err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
         if (err) {
                 if (err == -EEXIST)
-                        printk(KERN_WARNING "L3 disable slot %d in use!\n",
-                                            slot);
+                        pr_warning("L3 slot %d in use/index already disabled!\n",
+                                   slot);
                 return err;
         }
         return count;
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 7734bcbb5a3a..2d6e6498c176 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
         if (tsk_used_math(tsk)) {
                 if (HAVE_HWFP && tsk == current)
                         unlazy_fpu(tsk);
+                tsk->thread.fpu.last_cpu = ~0;
                 return 0;
         }
 
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 73465aab28f8..8a2ce8fd41c0 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
 
-        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
-                pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
-                return -1;
-        }
-
         csig->rev = c->microcode;
         pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 
@@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
 
 struct microcode_ops * __init init_amd_microcode(void)
 {
+        struct cpuinfo_x86 *c = &cpu_data(0);
+
+        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+                pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
+                return NULL;
+        }
+
         patch = (void *)get_zeroed_page(GFP_KERNEL);
         if (!patch)
                 return NULL;
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 87a0f8688301..c9bda6d6035c 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
         if (err)
                 return err;
 
-        if (microcode_init_cpu(cpu) == UCODE_ERROR) {
-                sysfs_remove_group(&dev->kobj, &mc_attr_group);
+        if (microcode_init_cpu(cpu) == UCODE_ERROR)
                 return -EINVAL;
-        }
 
         return err;
 }
@@ -528,11 +526,11 @@ static int __init microcode_init(void)
                 microcode_ops = init_intel_microcode();
         else if (c->x86_vendor == X86_VENDOR_AMD)
                 microcode_ops = init_amd_microcode();
-
-        if (!microcode_ops) {
+        else
                 pr_err("no support for this CPU vendor\n");
+
+        if (!microcode_ops)
                 return -ENODEV;
-        }
 
         microcode_pdev = platform_device_register_simple("microcode", -1,
                                                          NULL, 0);
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index e9f265fd79ae..9cf71d0b2d37 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = {
 struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
         .early_percpu_clock_init        = x86_init_noop,
         .setup_percpu_clockev           = setup_secondary_APIC_clock,
-        .fixup_cpu_id                   = x86_default_fixup_cpu_id,
 };
 
 static void default_nmi_init(void) { };
diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
index 66d377e334f7..646e3b5b4bb6 100644
--- a/arch/x86/platform/geode/net5501.c
+++ b/arch/x86/platform/geode/net5501.c
@@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = {
                 .name = "net5501:1",
                 .gpio = 6,
                 .default_trigger = "default-on",
-                .active_low = 1,
+                .active_low = 0,
         },
 };
 
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index e0a37233c0af..e31bcd8f2eee 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
                 } else
                         i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
         }
-        intel_scu_notifier_post(SCU_AVAILABLE, 0L);
+        intel_scu_notifier_post(SCU_AVAILABLE, NULL);
 }
 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
 
@@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
 {
         int i;
 
-        intel_scu_notifier_post(SCU_DOWN, 0L);
+        intel_scu_notifier_post(SCU_DOWN, NULL);
 
         for (i = 0; i < ipc_next_dev; i++)
                 platform_device_del(ipc_devs[i]);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 4f51bebac02c..a8f8844b8d32 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 
 static bool __init xen_check_mwait(void)
 {
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
+        !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
         struct xen_platform_op op = {
                 .cmd                    = XENPF_set_processor_pminfo,
                 .u.set_pminfo.id        = -1,
@@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void)
         /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
         if ((cx & xsave_mask) != xsave_mask)
                 cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
-
         if (xen_check_mwait())
                 cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 5fac6919b957..0503c0c493a9 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
 static void __init xen_filter_cpu_maps(void)
 {
         int i, rc;
+        unsigned int subtract = 0;
 
         if (!xen_initial_domain())
                 return;
@@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
                 } else {
                         set_cpu_possible(i, false);
                         set_cpu_present(i, false);
+                        subtract++;
                 }
         }
+#ifdef CONFIG_HOTPLUG_CPU
+        /* This is akin to using 'nr_cpus' on the Linux command line.
+         * Which is OK as when we use 'dom0_max_vcpus=X' we can only
+         * have up to X, while nr_cpu_ids is greater than X. This
+         * normally is not a problem, except when CPU hotplugging
+         * is involved and then there might be more than X CPUs
+         * in the guest - which will not work as there is no
+         * hypercall to expand the max number of VCPUs an already
+         * running guest has. So cap it up to X. */
+        if (subtract)
+                nr_cpu_ids = nr_cpu_ids - subtract;
+#endif
+
 }
 
 static void __init xen_smp_prepare_boot_cpu(void)
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 79d7362ad6d1..3e45aa000718 100644
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
 
         /* check for unmasked and pending */
         cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
-        jz 1f
+        jnz 1f
 2:      call check_events
 1:
 ENDPATCH(xen_restore_fl_direct)
diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h
index 26664cef8f11..91695a135498 100644
--- a/arch/xtensa/include/asm/hardirq.h
+++ b/arch/xtensa/include/asm/hardirq.h
@@ -11,9 +11,6 @@
 #ifndef _XTENSA_HARDIRQ_H
 #define _XTENSA_HARDIRQ_H
 
-void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
 #include <asm-generic/hardirq.h>
 
 #endif  /* _XTENSA_HARDIRQ_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index d04cd3a625fa..4beb43c087d3 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 #include <asm/byteorder.h>
 #include <asm/page.h>
+#include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include <linux/types.h>
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index b69b000349fc..d78869a00b11 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
 
         if (signr > 0) {
+                int ret;
 
                 /* Are we from a system call? */