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authorArnd Bergmann <arnd@arndb.de>2012-05-16 10:35:25 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-16 10:35:25 -0400
commit3c0dec5f58b3c7b3627715126d1bf9b030a076f0 (patch)
tree4bf8f56fca3bf6be109209b116fc8e32cb2e0f9e /arch
parentfcd8d84a585f3578a9ebdd27e757495a27415322 (diff)
parent7e0fa1b5fa91d9aa456d102c273b2cf0f2e95d39 (diff)
Merge branch 'clk-next' of git://git.linaro.org/people/mturquette/linux into next/clock
* 'clk-next' of git://git.linaro.org/people/mturquette/linux: clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ARM: Orion: SDIO: Add support for clk. ARM: Orion: NAND: Add support for clk, if there is one. ARM: Orion: EHCI: Add support for enabling clocks ARM: Orion: SATA: Add per channel clk/clkdev support. ARM: Orion: UART: Get the clock rate via clk_get_rate(). ARM: Orion: WDT: Add clk/clkdev support ARM: Orion: Eth: Add clk/clkdev support. ARM: Orion: SPI: Add clk/clkdev support. ARM: Orion: Add clocks using the generic clk infrastructure. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-dove/common.c39
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/board-dreamplug.c1
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c3
-rw-r--r--arch/arm/mach-kirkwood/common.c274
-rw-r--r--arch/arm/mach-kirkwood/common.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h16
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/pcie.c25
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.c1
-rw-r--r--arch/arm/mach-mv78xx0/common.c45
-rw-r--r--arch/arm/mach-orion5x/common.c27
-rw-r--r--arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c1
-rw-r--r--arch/arm/plat-orion/common.c104
-rw-r--r--arch/arm/plat-orion/include/plat/common.h34
-rw-r--r--arch/arm/plat-orion/include/plat/orion_wdt.h18
-rw-r--r--arch/arm/plat-orion/pcie.c4
20 files changed, 381 insertions, 217 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0fc52784ebc..0a166b52600d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1142,6 +1142,7 @@ config PLAT_ORION
1142 bool 1142 bool
1143 select CLKSRC_MMIO 1143 select CLKSRC_MMIO
1144 select GENERIC_IRQ_CHIP 1144 select GENERIC_IRQ_CHIP
1145 select COMMON_CLK
1145 1146
1146config PLAT_PXA 1147config PLAT_PXA
1147 bool 1148 bool
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index bda7aca04ca0..0ab0f81b661d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -13,7 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/clk.h> 16#include <linux/clk-provider.h>
17#include <linux/ata_platform.h> 17#include <linux/ata_platform.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <asm/page.h> 19#include <asm/page.h>
@@ -68,6 +68,19 @@ void __init dove_map_io(void)
68} 68}
69 69
70/***************************************************************************** 70/*****************************************************************************
71 * CLK tree
72 ****************************************************************************/
73static struct clk *tclk;
74
75static void __init clk_init(void)
76{
77 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
78 get_tclk());
79
80 orion_clkdev_init(tclk);
81}
82
83/*****************************************************************************
71 * EHCI0 84 * EHCI0
72 ****************************************************************************/ 85 ****************************************************************************/
73void __init dove_ehci0_init(void) 86void __init dove_ehci0_init(void)
@@ -89,8 +102,7 @@ void __init dove_ehci1_init(void)
89void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 102void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
90{ 103{
91 orion_ge00_init(eth_data, 104 orion_ge00_init(eth_data,
92 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 105 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0);
93 0, get_tclk());
94} 106}
95 107
96/***************************************************************************** 108/*****************************************************************************
@@ -116,7 +128,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
116void __init dove_uart0_init(void) 128void __init dove_uart0_init(void)
117{ 129{
118 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 130 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
119 IRQ_DOVE_UART_0, get_tclk()); 131 IRQ_DOVE_UART_0, tclk);
120} 132}
121 133
122/***************************************************************************** 134/*****************************************************************************
@@ -125,7 +137,7 @@ void __init dove_uart0_init(void)
125void __init dove_uart1_init(void) 137void __init dove_uart1_init(void)
126{ 138{
127 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 139 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
128 IRQ_DOVE_UART_1, get_tclk()); 140 IRQ_DOVE_UART_1, tclk);
129} 141}
130 142
131/***************************************************************************** 143/*****************************************************************************
@@ -134,7 +146,7 @@ void __init dove_uart1_init(void)
134void __init dove_uart2_init(void) 146void __init dove_uart2_init(void)
135{ 147{
136 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 148 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
137 IRQ_DOVE_UART_2, get_tclk()); 149 IRQ_DOVE_UART_2, tclk);
138} 150}
139 151
140/***************************************************************************** 152/*****************************************************************************
@@ -143,7 +155,7 @@ void __init dove_uart2_init(void)
143void __init dove_uart3_init(void) 155void __init dove_uart3_init(void)
144{ 156{
145 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 157 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
146 IRQ_DOVE_UART_3, get_tclk()); 158 IRQ_DOVE_UART_3, tclk);
147} 159}
148 160
149/***************************************************************************** 161/*****************************************************************************
@@ -151,12 +163,12 @@ void __init dove_uart3_init(void)
151 ****************************************************************************/ 163 ****************************************************************************/
152void __init dove_spi0_init(void) 164void __init dove_spi0_init(void)
153{ 165{
154 orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk()); 166 orion_spi_init(DOVE_SPI0_PHYS_BASE);
155} 167}
156 168
157void __init dove_spi1_init(void) 169void __init dove_spi1_init(void)
158{ 170{
159 orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk()); 171 orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
160} 172}
161 173
162/***************************************************************************** 174/*****************************************************************************
@@ -272,18 +284,17 @@ void __init dove_sdio1_init(void)
272 284
273void __init dove_init(void) 285void __init dove_init(void)
274{ 286{
275 int tclk;
276
277 tclk = get_tclk();
278
279 printk(KERN_INFO "Dove 88AP510 SoC, "); 287 printk(KERN_INFO "Dove 88AP510 SoC, ");
280 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); 288 printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
281 289
282#ifdef CONFIG_CACHE_TAUROS2 290#ifdef CONFIG_CACHE_TAUROS2
283 tauros2_init(); 291 tauros2_init();
284#endif 292#endif
285 dove_setup_cpu_mbus(); 293 dove_setup_cpu_mbus();
286 294
295 /* Setup root of clk tree */
296 clk_init();
297
287 /* internal devices that every board has */ 298 /* internal devices that every board has */
288 dove_rtc_init(); 299 dove_rtc_init();
289 dove_xor0_init(); 300 dove_xor0_init();
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index ea77ae430b2d..bc2867f11346 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -20,7 +20,6 @@
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/spi/orion_spi.h>
24#include <linux/spi/flash.h> 23#include <linux/spi/flash.h>
25#include <linux/gpio.h> 24#include <linux/gpio.h>
26#include <asm/mach-types.h> 25#include <asm/mach-types.h>
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 985453994dd3..55e357ab2923 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -27,7 +27,6 @@
27#include <linux/mtd/physmap.h> 27#include <linux/mtd/physmap.h>
28#include <linux/spi/flash.h> 28#include <linux/spi/flash.h>
29#include <linux/spi/spi.h> 29#include <linux/spi/spi.h>
30#include <linux/spi/orion_spi.h>
31#include <asm/mach-types.h> 30#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 32#include <asm/mach/map.h>
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1c672d9e6656..87856b5a397d 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -42,6 +42,9 @@ static void __init kirkwood_dt_init(void)
42 kirkwood_l2_init(); 42 kirkwood_l2_init();
43#endif 43#endif
44 44
45 /* Setup root of clk tree */
46 kirkwood_clk_init();
47
45 /* internal devices that every board has */ 48 /* internal devices that every board has */
46 kirkwood_wdt_init(); 49 kirkwood_wdt_init();
47 kirkwood_xor0_init(); 50 kirkwood_xor0_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae881f2f..25fb3fd418ef 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,8 @@
15#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
16#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18#include <linux/clk-provider.h>
19#include <linux/spinlock.h>
18#include <net/dsa.h> 20#include <net/dsa.h>
19#include <asm/page.h> 21#include <asm/page.h>
20#include <asm/timex.h> 22#include <asm/timex.h>
@@ -31,6 +33,7 @@
31#include <plat/common.h> 33#include <plat/common.h>
32#include <plat/time.h> 34#include <plat/time.h>
33#include <plat/addr-map.h> 35#include <plat/addr-map.h>
36#include <plat/mv_xor.h>
34#include "common.h" 37#include "common.h"
35 38
36/***************************************************************************** 39/*****************************************************************************
@@ -60,20 +63,188 @@ void __init kirkwood_map_io(void)
60 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); 63 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
61} 64}
62 65
63/* 66/*****************************************************************************
64 * Default clock control bits. Any bit _not_ set in this variable 67 * CLK tree
65 * will be cleared from the hardware after platform devices have been 68 ****************************************************************************/
66 * registered. Some reserved bits must be set to 1. 69
67 */ 70static void disable_sata0(void)
68unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; 71{
72 /* Disable PLL and IVREF */
73 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
74 /* Disable PHY */
75 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
76}
77
78static void disable_sata1(void)
79{
80 /* Disable PLL and IVREF */
81 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
82 /* Disable PHY */
83 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
84}
85
86static void disable_pcie0(void)
87{
88 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
89 while (1)
90 if (readl(PCIE_STATUS) & 0x1)
91 break;
92 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
93}
94
95static void disable_pcie1(void)
96{
97 u32 dev, rev;
98
99 kirkwood_pcie_id(&dev, &rev);
100
101 if (dev == MV88F6282_DEV_ID) {
102 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
103 while (1)
104 if (readl(PCIE1_STATUS) & 0x1)
105 break;
106 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
107 }
108}
109
110/* An extended version of the gated clk. This calls fn() before
111 * disabling the clock. We use this to turn off PHYs etc. */
112struct clk_gate_fn {
113 struct clk_gate gate;
114 void (*fn)(void);
115};
69 116
117#define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
118#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
119
120static void clk_gate_fn_disable(struct clk_hw *hw)
121{
122 struct clk_gate *gate = to_clk_gate(hw);
123 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
124
125 if (gate_fn->fn)
126 gate_fn->fn();
127
128 clk_gate_ops.disable(hw);
129}
130
131static struct clk_ops clk_gate_fn_ops;
132
133static struct clk __init *clk_register_gate_fn(struct device *dev,
134 const char *name,
135 const char *parent_name, unsigned long flags,
136 void __iomem *reg, u8 bit_idx,
137 u8 clk_gate_flags, spinlock_t *lock,
138 void (*fn)(void))
139{
140 struct clk_gate_fn *gate_fn;
141 struct clk *clk;
142 struct clk_init_data init;
143
144 gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
145 if (!gate_fn) {
146 pr_err("%s: could not allocate gated clk\n", __func__);
147 return ERR_PTR(-ENOMEM);
148 }
149
150 init.name = name;
151 init.ops = &clk_gate_fn_ops;
152 init.flags = flags;
153 init.parent_names = (parent_name ? &parent_name : NULL);
154 init.num_parents = (parent_name ? 1 : 0);
155
156 /* struct clk_gate assignments */
157 gate_fn->gate.reg = reg;
158 gate_fn->gate.bit_idx = bit_idx;
159 gate_fn->gate.flags = clk_gate_flags;
160 gate_fn->gate.lock = lock;
161 gate_fn->gate.hw.init = &init;
162
163 /* ops is the gate ops, but with our disable function */
164 if (clk_gate_fn_ops.disable != clk_gate_fn_disable) {
165 clk_gate_fn_ops = clk_gate_ops;
166 clk_gate_fn_ops.disable = clk_gate_fn_disable;
167 }
168
169 clk = clk_register(dev, &gate_fn->gate.hw);
170
171 if (IS_ERR(clk))
172 kfree(gate_fn);
173
174 return clk;
175}
176
177static DEFINE_SPINLOCK(gating_lock);
178static struct clk *tclk;
179
180static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
181{
182 return clk_register_gate(NULL, name, "tclk", 0,
183 (void __iomem *)CLOCK_GATING_CTRL,
184 bit_idx, 0, &gating_lock);
185}
186
187static struct clk __init *kirkwood_register_gate_fn(const char *name,
188 u8 bit_idx,
189 void (*fn)(void))
190{
191 return clk_register_gate_fn(NULL, name, "tclk", 0,
192 (void __iomem *)CLOCK_GATING_CTRL,
193 bit_idx, 0, &gating_lock, fn);
194}
195
196void __init kirkwood_clk_init(void)
197{
198 struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;
199 struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
200
201 tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
202 CLK_IS_ROOT, kirkwood_tclk);
203
204 runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
205 ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
206 ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
207 sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
208 disable_sata0);
209 sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
210 disable_sata1);
211 usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
212 sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
213 crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
214 xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
215 xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
216 pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
217 disable_pcie0);
218 pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
219 disable_pcie1);
220 audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
221 kirkwood_register_gate("tdm", CGC_BIT_TDM);
222 kirkwood_register_gate("tsu", CGC_BIT_TSU);
223
224 /* clkdev entries, mapping clks to devices */
225 orion_clkdev_add(NULL, "orion_spi.0", runit);
226 orion_clkdev_add(NULL, "orion_spi.1", runit);
227 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
228 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
229 orion_clkdev_add(NULL, "orion_wdt", tclk);
230 orion_clkdev_add("0", "sata_mv.0", sata0);
231 orion_clkdev_add("1", "sata_mv.0", sata1);
232 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
233 orion_clkdev_add(NULL, "orion_nand", runit);
234 orion_clkdev_add(NULL, "mvsdio", sdio);
235 orion_clkdev_add(NULL, "mv_crypto", crypto);
236 orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
237 orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
238 orion_clkdev_add("0", "pcie", pex0);
239 orion_clkdev_add("1", "pcie", pex1);
240 orion_clkdev_add(NULL, "kirkwood-i2s", audio);
241}
70 242
71/***************************************************************************** 243/*****************************************************************************
72 * EHCI0 244 * EHCI0
73 ****************************************************************************/ 245 ****************************************************************************/
74void __init kirkwood_ehci_init(void) 246void __init kirkwood_ehci_init(void)
75{ 247{
76 kirkwood_clk_ctrl |= CGC_USB0;
77 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); 248 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
78} 249}
79 250
@@ -83,11 +254,9 @@ void __init kirkwood_ehci_init(void)
83 ****************************************************************************/ 254 ****************************************************************************/
84void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) 255void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
85{ 256{
86 kirkwood_clk_ctrl |= CGC_GE0;
87
88 orion_ge00_init(eth_data, 257 orion_ge00_init(eth_data,
89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, 258 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); 259 IRQ_KIRKWOOD_GE00_ERR);
91} 260}
92 261
93 262
@@ -96,12 +265,9 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
96 ****************************************************************************/ 265 ****************************************************************************/
97void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) 266void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
98{ 267{
99
100 kirkwood_clk_ctrl |= CGC_GE1;
101
102 orion_ge01_init(eth_data, 268 orion_ge01_init(eth_data,
103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, 269 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); 270 IRQ_KIRKWOOD_GE01_ERR);
105} 271}
106 272
107 273
@@ -143,7 +309,6 @@ static struct platform_device kirkwood_nand_flash = {
143void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, 309void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
144 int chip_delay) 310 int chip_delay)
145{ 311{
146 kirkwood_clk_ctrl |= CGC_RUNIT;
147 kirkwood_nand_data.parts = parts; 312 kirkwood_nand_data.parts = parts;
148 kirkwood_nand_data.nr_parts = nr_parts; 313 kirkwood_nand_data.nr_parts = nr_parts;
149 kirkwood_nand_data.chip_delay = chip_delay; 314 kirkwood_nand_data.chip_delay = chip_delay;
@@ -153,7 +318,6 @@ void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
153void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, 318void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
154 int (*dev_ready)(struct mtd_info *)) 319 int (*dev_ready)(struct mtd_info *))
155{ 320{
156 kirkwood_clk_ctrl |= CGC_RUNIT;
157 kirkwood_nand_data.parts = parts; 321 kirkwood_nand_data.parts = parts;
158 kirkwood_nand_data.nr_parts = nr_parts; 322 kirkwood_nand_data.nr_parts = nr_parts;
159 kirkwood_nand_data.dev_ready = dev_ready; 323 kirkwood_nand_data.dev_ready = dev_ready;
@@ -174,10 +338,6 @@ static void __init kirkwood_rtc_init(void)
174 ****************************************************************************/ 338 ****************************************************************************/
175void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) 339void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
176{ 340{
177 kirkwood_clk_ctrl |= CGC_SATA0;
178 if (sata_data->n_ports > 1)
179 kirkwood_clk_ctrl |= CGC_SATA1;
180
181 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); 341 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
182} 342}
183 343
@@ -220,7 +380,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
220 mvsdio_data->clock = 100000000; 380 mvsdio_data->clock = 100000000;
221 else 381 else
222 mvsdio_data->clock = 200000000; 382 mvsdio_data->clock = 200000000;
223 kirkwood_clk_ctrl |= CGC_SDIO;
224 kirkwood_sdio.dev.platform_data = mvsdio_data; 383 kirkwood_sdio.dev.platform_data = mvsdio_data;
225 platform_device_register(&kirkwood_sdio); 384 platform_device_register(&kirkwood_sdio);
226} 385}
@@ -231,8 +390,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
231 ****************************************************************************/ 390 ****************************************************************************/
232void __init kirkwood_spi_init() 391void __init kirkwood_spi_init()
233{ 392{
234 kirkwood_clk_ctrl |= CGC_RUNIT; 393 orion_spi_init(SPI_PHYS_BASE);
235 orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
236} 394}
237 395
238 396
@@ -252,7 +410,7 @@ void __init kirkwood_i2c_init(void)
252void __init kirkwood_uart0_init(void) 410void __init kirkwood_uart0_init(void)
253{ 411{
254 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 412 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
255 IRQ_KIRKWOOD_UART_0, kirkwood_tclk); 413 IRQ_KIRKWOOD_UART_0, tclk);
256} 414}
257 415
258 416
@@ -262,7 +420,7 @@ void __init kirkwood_uart0_init(void)
262void __init kirkwood_uart1_init(void) 420void __init kirkwood_uart1_init(void)
263{ 421{
264 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 422 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
265 IRQ_KIRKWOOD_UART_1, kirkwood_tclk); 423 IRQ_KIRKWOOD_UART_1, tclk);
266} 424}
267 425
268/***************************************************************************** 426/*****************************************************************************
@@ -270,7 +428,6 @@ void __init kirkwood_uart1_init(void)
270 ****************************************************************************/ 428 ****************************************************************************/
271void __init kirkwood_crypto_init(void) 429void __init kirkwood_crypto_init(void)
272{ 430{
273 kirkwood_clk_ctrl |= CGC_CRYPTO;
274 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, 431 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
275 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); 432 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
276} 433}
@@ -281,8 +438,6 @@ void __init kirkwood_crypto_init(void)
281 ****************************************************************************/ 438 ****************************************************************************/
282void __init kirkwood_xor0_init(void) 439void __init kirkwood_xor0_init(void)
283{ 440{
284 kirkwood_clk_ctrl |= CGC_XOR0;
285
286 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, 441 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
287 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); 442 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
288} 443}
@@ -293,8 +448,6 @@ void __init kirkwood_xor0_init(void)
293 ****************************************************************************/ 448 ****************************************************************************/
294void __init kirkwood_xor1_init(void) 449void __init kirkwood_xor1_init(void)
295{ 450{
296 kirkwood_clk_ctrl |= CGC_XOR1;
297
298 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, 451 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
299 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); 452 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
300} 453}
@@ -305,7 +458,7 @@ void __init kirkwood_xor1_init(void)
305 ****************************************************************************/ 458 ****************************************************************************/
306void __init kirkwood_wdt_init(void) 459void __init kirkwood_wdt_init(void)
307{ 460{
308 orion_wdt_init(kirkwood_tclk); 461 orion_wdt_init();
309} 462}
310 463
311 464
@@ -381,7 +534,6 @@ static struct platform_device kirkwood_pcm_device = {
381 534
382void __init kirkwood_audio_init(void) 535void __init kirkwood_audio_init(void)
383{ 536{
384 kirkwood_clk_ctrl |= CGC_AUDIO;
385 platform_device_register(&kirkwood_i2s_device); 537 platform_device_register(&kirkwood_i2s_device);
386 platform_device_register(&kirkwood_pcm_device); 538 platform_device_register(&kirkwood_pcm_device);
387} 539}
@@ -465,6 +617,9 @@ void __init kirkwood_init(void)
465 kirkwood_l2_init(); 617 kirkwood_l2_init();
466#endif 618#endif
467 619
620 /* Setup root of clk tree */
621 kirkwood_clk_init();
622
468 /* internal devices that every board has */ 623 /* internal devices that every board has */
469 kirkwood_rtc_init(); 624 kirkwood_rtc_init();
470 kirkwood_wdt_init(); 625 kirkwood_wdt_init();
@@ -477,61 +632,6 @@ void __init kirkwood_init(void)
477#endif 632#endif
478} 633}
479 634
480static int __init kirkwood_clock_gate(void)
481{
482 unsigned int curr = readl(CLOCK_GATING_CTRL);
483 u32 dev, rev;
484
485 kirkwood_pcie_id(&dev, &rev);
486 printk(KERN_DEBUG "Gating clock of unused units\n");
487 printk(KERN_DEBUG "before: 0x%08x\n", curr);
488
489 /* Make sure those units are accessible */
490 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
491
492 /* For SATA: first shutdown the phy */
493 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
494 /* Disable PLL and IVREF */
495 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
496 /* Disable PHY */
497 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
498 }
499 if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
500 /* Disable PLL and IVREF */
501 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
502 /* Disable PHY */
503 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
504 }
505
506 /* For PCIe: first shutdown the phy */
507 if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
508 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
509 while (1)
510 if (readl(PCIE_STATUS) & 0x1)
511 break;
512 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
513 }
514
515 /* For PCIe 1: first shutdown the phy */
516 if (dev == MV88F6282_DEV_ID) {
517 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
518 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
519 while (1)
520 if (readl(PCIE1_STATUS) & 0x1)
521 break;
522 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
523 }
524 } else /* keep this bit set for devices that don't have PCIe1 */
525 kirkwood_clk_ctrl |= CGC_PEX1;
526
527 /* Now gate clock the required units */
528 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
529 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
530
531 return 0;
532}
533late_initcall(kirkwood_clock_gate);
534
535void kirkwood_restart(char mode, const char *cmd) 635void kirkwood_restart(char mode, const char *cmd)
536{ 636{
537 /* 637 /*
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fa8e7689c436..0729b11a3e2a 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -50,6 +50,7 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
50void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); 50void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *));
51void kirkwood_audio_init(void); 51void kirkwood_audio_init(void);
52void kirkwood_restart(char, const char *); 52void kirkwood_restart(char, const char *);
53void kirkwood_clk_init(void);
53 54
54/* board init functions for boards not fully converted to fdt */ 55/* board init functions for boards not fully converted to fdt */
55#ifdef CONFIG_MACH_DREAMPLUG_DT 56#ifdef CONFIG_MACH_DREAMPLUG_DT
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 957bd7997d7e..3eee37a3b501 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -43,6 +43,22 @@
43#define L2_WRITETHROUGH 0x00000010 43#define L2_WRITETHROUGH 0x00000010
44 44
45#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) 45#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
46#define CGC_BIT_GE0 (0)
47#define CGC_BIT_PEX0 (2)
48#define CGC_BIT_USB0 (3)
49#define CGC_BIT_SDIO (4)
50#define CGC_BIT_TSU (5)
51#define CGC_BIT_DUNIT (6)
52#define CGC_BIT_RUNIT (7)
53#define CGC_BIT_XOR0 (8)
54#define CGC_BIT_AUDIO (9)
55#define CGC_BIT_SATA0 (14)
56#define CGC_BIT_SATA1 (15)
57#define CGC_BIT_XOR1 (16)
58#define CGC_BIT_CRYPTO (17)
59#define CGC_BIT_PEX1 (18)
60#define CGC_BIT_GE1 (19)
61#define CGC_BIT_TDM (20)
46#define CGC_GE0 (1 << 0) 62#define CGC_GE0 (1 << 0)
47#define CGC_PEX0 (1 << 2) 63#define CGC_PEX0 (1 << 2)
48#define CGC_USB0 (1 << 3) 64#define CGC_USB0 (1 << 3)
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 85f6169c2484..6d8364a97810 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -23,7 +23,6 @@
23#include <linux/gpio_keys.h> 23#include <linux/gpio_keys.h>
24#include <linux/spi/flash.h> 24#include <linux/spi/flash.h>
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/orion_spi.h>
27#include <net/dsa.h> 26#include <net/dsa.h>
28#include <asm/mach-types.h> 27#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index f56a0118c1bb..f26d6cff8bab 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,6 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/clk.h>
14#include <video/vga.h> 15#include <video/vga.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
16#include <asm/mach/pci.h> 17#include <asm/mach/pci.h>
@@ -19,6 +20,23 @@
19#include <plat/addr-map.h> 20#include <plat/addr-map.h>
20#include "common.h" 21#include "common.h"
21 22
23static void kirkwood_enable_pcie_clk(const char *port)
24{
25 struct clk *clk;
26
27 clk = clk_get_sys("pcie", port);
28 if (IS_ERR(clk)) {
29 printk(KERN_ERR "PCIE clock %s missing\n", port);
30 return;
31 }
32 clk_prepare_enable(clk);
33 clk_put(clk);
34}
35
36/* This function is called very early in the boot when probing the
37 hardware to determine what we actually are, and what rate tclk is
38 ticking at. Hence calling kirkwood_enable_pcie_clk() is not
39 possible since the clk tree has not been created yet. */
22void kirkwood_enable_pcie(void) 40void kirkwood_enable_pcie(void)
23{ 41{
24 u32 curr = readl(CLOCK_GATING_CTRL); 42 u32 curr = readl(CLOCK_GATING_CTRL);
@@ -26,7 +44,7 @@ void kirkwood_enable_pcie(void)
26 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL); 44 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
27} 45}
28 46
29void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 47void kirkwood_pcie_id(u32 *dev, u32 *rev)
30{ 48{
31 kirkwood_enable_pcie(); 49 kirkwood_enable_pcie();
32 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); 50 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
@@ -163,7 +181,6 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
163 181
164static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) 182static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
165{ 183{
166 extern unsigned int kirkwood_clk_ctrl;
167 struct pcie_port *pp; 184 struct pcie_port *pp;
168 int index; 185 int index;
169 186
@@ -182,11 +199,11 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
182 199
183 switch (index) { 200 switch (index) {
184 case 0: 201 case 0:
185 kirkwood_clk_ctrl |= CGC_PEX0; 202 kirkwood_enable_pcie_clk("0");
186 pcie0_ioresources_init(pp); 203 pcie0_ioresources_init(pp);
187 break; 204 break;
188 case 1: 205 case 1:
189 kirkwood_clk_ctrl |= CGC_PEX1; 206 kirkwood_enable_pcie_clk("1");
190 pcie1_ioresources_init(pp); 207 pcie1_ioresources_init(pp);
191 break; 208 break;
192 default: 209 default:
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index fd2c9c8b6831..f742a66a7045 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -16,7 +16,6 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/spi/flash.h> 17#include <linux/spi/flash.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <asm/mach-types.h> 19#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
22#include <mach/kirkwood.h> 21#include <mach/kirkwood.h>
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index f9d2a11b7f96..bad738e44044 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -16,7 +16,6 @@
16#include <linux/mtd/physmap.h> 16#include <linux/mtd/physmap.h>
17#include <linux/spi/flash.h> 17#include <linux/spi/flash.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <linux/i2c.h> 19#include <linux/i2c.h>
21#include <linux/mv643xx_eth.h> 20#include <linux/mv643xx_eth.h>
22#include <linux/ata_platform.h> 21#include <linux/ata_platform.h>
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index 24294b2bc469..8943ede29b44 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -4,7 +4,6 @@
4#include <linux/mtd/physmap.h> 4#include <linux/mtd/physmap.h>
5#include <linux/spi/flash.h> 5#include <linux/spi/flash.h>
6#include <linux/spi/spi.h> 6#include <linux/spi/spi.h>
7#include <linux/spi/orion_spi.h>
8#include <linux/serial_reg.h> 7#include <linux/serial_reg.h>
9#include <mach/kirkwood.h> 8#include <mach/kirkwood.h>
10#include "common.h" 9#include "common.h"
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index a5dcf766a3f9..b4c53b846c9c 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,6 +13,7 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
16#include <linux/clk-provider.h>
16#include <linux/ethtool.h> 17#include <linux/ethtool.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18#include <asm/mach/time.h> 19#include <asm/mach/time.h>
@@ -103,24 +104,24 @@ static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
103 104
104static int get_tclk(void) 105static int get_tclk(void)
105{ 106{
106 int tclk; 107 int tclk_freq;
107 108
108 /* 109 /*
109 * TCLK tick rate is configured by DEV_A[2:0] strap pins. 110 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
110 */ 111 */
111 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { 112 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
112 case 1: 113 case 1:
113 tclk = 166666667; 114 tclk_freq = 166666667;
114 break; 115 break;
115 case 3: 116 case 3:
116 tclk = 200000000; 117 tclk_freq = 200000000;
117 break; 118 break;
118 default: 119 default:
119 panic("unknown TCLK PLL setting: %.8x\n", 120 panic("unknown TCLK PLL setting: %.8x\n",
120 readl(SAMPLE_AT_RESET_HIGH)); 121 readl(SAMPLE_AT_RESET_HIGH));
121 } 122 }
122 123
123 return tclk; 124 return tclk_freq;
124} 125}
125 126
126 127
@@ -166,6 +167,19 @@ void __init mv78xx0_map_io(void)
166 167
167 168
168/***************************************************************************** 169/*****************************************************************************
170 * CLK tree
171 ****************************************************************************/
172static struct clk *tclk;
173
174static void __init clk_init(void)
175{
176 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
177 get_tclk());
178
179 orion_clkdev_init(tclk);
180}
181
182/*****************************************************************************
169 * EHCI 183 * EHCI
170 ****************************************************************************/ 184 ****************************************************************************/
171void __init mv78xx0_ehci0_init(void) 185void __init mv78xx0_ehci0_init(void)
@@ -199,7 +213,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
199{ 213{
200 orion_ge00_init(eth_data, 214 orion_ge00_init(eth_data,
201 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 215 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
202 IRQ_MV78XX0_GE_ERR, get_tclk()); 216 IRQ_MV78XX0_GE_ERR);
203} 217}
204 218
205 219
@@ -210,7 +224,7 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
210{ 224{
211 orion_ge01_init(eth_data, 225 orion_ge01_init(eth_data,
212 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 226 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
213 NO_IRQ, get_tclk()); 227 NO_IRQ);
214} 228}
215 229
216 230
@@ -234,7 +248,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
234 248
235 orion_ge10_init(eth_data, 249 orion_ge10_init(eth_data,
236 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 250 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
237 NO_IRQ, get_tclk()); 251 NO_IRQ);
238} 252}
239 253
240 254
@@ -258,7 +272,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
258 272
259 orion_ge11_init(eth_data, 273 orion_ge11_init(eth_data,
260 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 274 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
261 NO_IRQ, get_tclk()); 275 NO_IRQ);
262} 276}
263 277
264/***************************************************************************** 278/*****************************************************************************
@@ -285,7 +299,7 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
285void __init mv78xx0_uart0_init(void) 299void __init mv78xx0_uart0_init(void)
286{ 300{
287 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 301 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
288 IRQ_MV78XX0_UART_0, get_tclk()); 302 IRQ_MV78XX0_UART_0, tclk);
289} 303}
290 304
291 305
@@ -295,7 +309,7 @@ void __init mv78xx0_uart0_init(void)
295void __init mv78xx0_uart1_init(void) 309void __init mv78xx0_uart1_init(void)
296{ 310{
297 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 311 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
298 IRQ_MV78XX0_UART_1, get_tclk()); 312 IRQ_MV78XX0_UART_1, tclk);
299} 313}
300 314
301 315
@@ -305,7 +319,7 @@ void __init mv78xx0_uart1_init(void)
305void __init mv78xx0_uart2_init(void) 319void __init mv78xx0_uart2_init(void)
306{ 320{
307 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, 321 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
308 IRQ_MV78XX0_UART_2, get_tclk()); 322 IRQ_MV78XX0_UART_2, tclk);
309} 323}
310 324
311/***************************************************************************** 325/*****************************************************************************
@@ -314,7 +328,7 @@ void __init mv78xx0_uart2_init(void)
314void __init mv78xx0_uart3_init(void) 328void __init mv78xx0_uart3_init(void)
315{ 329{
316 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, 330 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
317 IRQ_MV78XX0_UART_3, get_tclk()); 331 IRQ_MV78XX0_UART_3, tclk);
318} 332}
319 333
320/***************************************************************************** 334/*****************************************************************************
@@ -378,25 +392,26 @@ void __init mv78xx0_init(void)
378 int hclk; 392 int hclk;
379 int pclk; 393 int pclk;
380 int l2clk; 394 int l2clk;
381 int tclk;
382 395
383 core_index = mv78xx0_core_index(); 396 core_index = mv78xx0_core_index();
384 hclk = get_hclk(); 397 hclk = get_hclk();
385 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); 398 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
386 tclk = get_tclk();
387 399
388 printk(KERN_INFO "%s ", mv78xx0_id()); 400 printk(KERN_INFO "%s ", mv78xx0_id());
389 printk("core #%d, ", core_index); 401 printk("core #%d, ", core_index);
390 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); 402 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
391 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); 403 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
392 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); 404 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
393 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); 405 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
394 406
395 mv78xx0_setup_cpu_mbus(); 407 mv78xx0_setup_cpu_mbus();
396 408
397#ifdef CONFIG_CACHE_FEROCEON_L2 409#ifdef CONFIG_CACHE_FEROCEON_L2
398 feroceon_l2_init(is_l2_writethrough()); 410 feroceon_l2_init(is_l2_writethrough());
399#endif 411#endif
412
413 /* Setup root of clk tree */
414 clk_init();
400} 415}
401 416
402void mv78xx0_restart(char mode, const char *cmd) 417void mv78xx0_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 24481666d2cd..fd36e020d09d 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -18,6 +18,7 @@
18#include <linux/mv643xx_i2c.h> 18#include <linux/mv643xx_i2c.h>
19#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/clk-provider.h>
21#include <net/dsa.h> 22#include <net/dsa.h>
22#include <asm/page.h> 23#include <asm/page.h>
23#include <asm/setup.h> 24#include <asm/setup.h>
@@ -70,6 +71,19 @@ void __init orion5x_map_io(void)
70 71
71 72
72/***************************************************************************** 73/*****************************************************************************
74 * CLK tree
75 ****************************************************************************/
76static struct clk *tclk;
77
78static void __init clk_init(void)
79{
80 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
81 orion5x_tclk);
82
83 orion_clkdev_init(tclk);
84}
85
86/*****************************************************************************
73 * EHCI0 87 * EHCI0
74 ****************************************************************************/ 88 ****************************************************************************/
75void __init orion5x_ehci0_init(void) 89void __init orion5x_ehci0_init(void)
@@ -95,7 +109,7 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
95{ 109{
96 orion_ge00_init(eth_data, 110 orion_ge00_init(eth_data,
97 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 111 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
98 IRQ_ORION5X_ETH_ERR, orion5x_tclk); 112 IRQ_ORION5X_ETH_ERR);
99} 113}
100 114
101 115
@@ -132,7 +146,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
132 ****************************************************************************/ 146 ****************************************************************************/
133void __init orion5x_spi_init() 147void __init orion5x_spi_init()
134{ 148{
135 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); 149 orion_spi_init(SPI_PHYS_BASE);
136} 150}
137 151
138 152
@@ -142,7 +156,7 @@ void __init orion5x_spi_init()
142void __init orion5x_uart0_init(void) 156void __init orion5x_uart0_init(void)
143{ 157{
144 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 158 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
145 IRQ_ORION5X_UART0, orion5x_tclk); 159 IRQ_ORION5X_UART0, tclk);
146} 160}
147 161
148/***************************************************************************** 162/*****************************************************************************
@@ -151,7 +165,7 @@ void __init orion5x_uart0_init(void)
151void __init orion5x_uart1_init(void) 165void __init orion5x_uart1_init(void)
152{ 166{
153 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 167 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
154 IRQ_ORION5X_UART1, orion5x_tclk); 168 IRQ_ORION5X_UART1, tclk);
155} 169}
156 170
157/***************************************************************************** 171/*****************************************************************************
@@ -179,7 +193,7 @@ static void __init orion5x_crypto_init(void)
179 ****************************************************************************/ 193 ****************************************************************************/
180void __init orion5x_wdt_init(void) 194void __init orion5x_wdt_init(void)
181{ 195{
182 orion_wdt_init(orion5x_tclk); 196 orion_wdt_init();
183} 197}
184 198
185 199
@@ -276,6 +290,9 @@ void __init orion5x_init(void)
276 */ 290 */
277 orion5x_setup_cpu_mbus_bridge(); 291 orion5x_setup_cpu_mbus_bridge();
278 292
293 /* Setup root of clk tree */
294 clk_init();
295
279 /* 296 /*
280 * Don't issue "Wait for Interrupt" instruction if we are 297 * Don't issue "Wait for Interrupt" instruction if we are
281 * running on D0 5281 silicon. 298 * running on D0 5281 silicon.
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 2c5fab00d205..7b97a9a211ed 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -16,7 +16,6 @@
16#include <linux/mtd/physmap.h> 16#include <linux/mtd/physmap.h>
17#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <linux/spi/flash.h> 19#include <linux/spi/flash.h>
21#include <linux/ethtool.h> 20#include <linux/ethtool.h>
22#include <net/dsa.h> 21#include <net/dsa.h>
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 74daf5ed1432..61fd837624a8 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -14,15 +14,41 @@
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
17#include <linux/clk.h>
18#include <linux/clkdev.h>
17#include <linux/mv643xx_eth.h> 19#include <linux/mv643xx_eth.h>
18#include <linux/mv643xx_i2c.h> 20#include <linux/mv643xx_i2c.h>
19#include <net/dsa.h> 21#include <net/dsa.h>
20#include <linux/spi/orion_spi.h>
21#include <plat/orion_wdt.h>
22#include <plat/mv_xor.h> 22#include <plat/mv_xor.h>
23#include <plat/ehci-orion.h> 23#include <plat/ehci-orion.h>
24#include <mach/bridge-regs.h> 24#include <mach/bridge-regs.h>
25 25
26/* Create a clkdev entry for a given device/clk */
27void __init orion_clkdev_add(const char *con_id, const char *dev_id,
28 struct clk *clk)
29{
30 struct clk_lookup *cl;
31
32 cl = clkdev_alloc(clk, con_id, dev_id);
33 if (cl)
34 clkdev_add(cl);
35}
36
37/* Create clkdev entries for all orion platforms except kirkwood.
38 Kirkwood has gated clocks for some of its peripherals, so creates
39 its own clkdev entries. For all the other orion devices, create
40 clkdev entries to the tclk. */
41void __init orion_clkdev_init(struct clk *tclk)
42{
43 orion_clkdev_add(NULL, "orion_spi.0", tclk);
44 orion_clkdev_add(NULL, "orion_spi.1", tclk);
45 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
46 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
47 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
48 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
49 orion_clkdev_add(NULL, "orion_wdt", tclk);
50}
51
26/* Fill in the resources structure and link it into the platform 52/* Fill in the resources structure and link it into the platform
27 device structure. There is always a memory region, and nearly 53 device structure. There is always a memory region, and nearly
28 always an interrupt.*/ 54 always an interrupt.*/
@@ -49,6 +75,12 @@ static void fill_resources(struct platform_device *device,
49/***************************************************************************** 75/*****************************************************************************
50 * UART 76 * UART
51 ****************************************************************************/ 77 ****************************************************************************/
78static unsigned long __init uart_get_clk_rate(struct clk *clk)
79{
80 clk_prepare_enable(clk);
81 return clk_get_rate(clk);
82}
83
52static void __init uart_complete( 84static void __init uart_complete(
53 struct platform_device *orion_uart, 85 struct platform_device *orion_uart,
54 struct plat_serial8250_port *data, 86 struct plat_serial8250_port *data,
@@ -56,12 +88,12 @@ static void __init uart_complete(
56 unsigned int membase, 88 unsigned int membase,
57 resource_size_t mapbase, 89 resource_size_t mapbase,
58 unsigned int irq, 90 unsigned int irq,
59 unsigned int uartclk) 91 struct clk *clk)
60{ 92{
61 data->mapbase = mapbase; 93 data->mapbase = mapbase;
62 data->membase = (void __iomem *)membase; 94 data->membase = (void __iomem *)membase;
63 data->irq = irq; 95 data->irq = irq;
64 data->uartclk = uartclk; 96 data->uartclk = uart_get_clk_rate(clk);
65 orion_uart->dev.platform_data = data; 97 orion_uart->dev.platform_data = data;
66 98
67 fill_resources(orion_uart, resources, mapbase, 0xff, irq); 99 fill_resources(orion_uart, resources, mapbase, 0xff, irq);
@@ -90,10 +122,10 @@ static struct platform_device orion_uart0 = {
90void __init orion_uart0_init(unsigned int membase, 122void __init orion_uart0_init(unsigned int membase,
91 resource_size_t mapbase, 123 resource_size_t mapbase,
92 unsigned int irq, 124 unsigned int irq,
93 unsigned int uartclk) 125 struct clk *clk)
94{ 126{
95 uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, 127 uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
96 membase, mapbase, irq, uartclk); 128 membase, mapbase, irq, clk);
97} 129}
98 130
99/***************************************************************************** 131/*****************************************************************************
@@ -118,10 +150,10 @@ static struct platform_device orion_uart1 = {
118void __init orion_uart1_init(unsigned int membase, 150void __init orion_uart1_init(unsigned int membase,
119 resource_size_t mapbase, 151 resource_size_t mapbase,
120 unsigned int irq, 152 unsigned int irq,
121 unsigned int uartclk) 153 struct clk *clk)
122{ 154{
123 uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, 155 uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
124 membase, mapbase, irq, uartclk); 156 membase, mapbase, irq, clk);
125} 157}
126 158
127/***************************************************************************** 159/*****************************************************************************
@@ -146,10 +178,10 @@ static struct platform_device orion_uart2 = {
146void __init orion_uart2_init(unsigned int membase, 178void __init orion_uart2_init(unsigned int membase,
147 resource_size_t mapbase, 179 resource_size_t mapbase,
148 unsigned int irq, 180 unsigned int irq,
149 unsigned int uartclk) 181 struct clk *clk)
150{ 182{
151 uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, 183 uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
152 membase, mapbase, irq, uartclk); 184 membase, mapbase, irq, clk);
153} 185}
154 186
155/***************************************************************************** 187/*****************************************************************************
@@ -174,10 +206,10 @@ static struct platform_device orion_uart3 = {
174void __init orion_uart3_init(unsigned int membase, 206void __init orion_uart3_init(unsigned int membase,
175 resource_size_t mapbase, 207 resource_size_t mapbase,
176 unsigned int irq, 208 unsigned int irq,
177 unsigned int uartclk) 209 struct clk *clk)
178{ 210{
179 uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, 211 uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
180 membase, mapbase, irq, uartclk); 212 membase, mapbase, irq, clk);
181} 213}
182 214
183/***************************************************************************** 215/*****************************************************************************
@@ -203,13 +235,11 @@ void __init orion_rtc_init(unsigned long mapbase,
203 ****************************************************************************/ 235 ****************************************************************************/
204static __init void ge_complete( 236static __init void ge_complete(
205 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, 237 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
206 int tclk,
207 struct resource *orion_ge_resource, unsigned long irq, 238 struct resource *orion_ge_resource, unsigned long irq,
208 struct platform_device *orion_ge_shared, 239 struct platform_device *orion_ge_shared,
209 struct mv643xx_eth_platform_data *eth_data, 240 struct mv643xx_eth_platform_data *eth_data,
210 struct platform_device *orion_ge) 241 struct platform_device *orion_ge)
211{ 242{
212 orion_ge_shared_data->t_clk = tclk;
213 orion_ge_resource->start = irq; 243 orion_ge_resource->start = irq;
214 orion_ge_resource->end = irq; 244 orion_ge_resource->end = irq;
215 eth_data->shared = orion_ge_shared; 245 eth_data->shared = orion_ge_shared;
@@ -260,12 +290,11 @@ static struct platform_device orion_ge00 = {
260void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 290void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
261 unsigned long mapbase, 291 unsigned long mapbase,
262 unsigned long irq, 292 unsigned long irq,
263 unsigned long irq_err, 293 unsigned long irq_err)
264 int tclk)
265{ 294{
266 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, 295 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
267 mapbase + 0x2000, SZ_16K - 1, irq_err); 296 mapbase + 0x2000, SZ_16K - 1, irq_err);
268 ge_complete(&orion_ge00_shared_data, tclk, 297 ge_complete(&orion_ge00_shared_data,
269 orion_ge00_resources, irq, &orion_ge00_shared, 298 orion_ge00_resources, irq, &orion_ge00_shared,
270 eth_data, &orion_ge00); 299 eth_data, &orion_ge00);
271} 300}
@@ -313,12 +342,11 @@ static struct platform_device orion_ge01 = {
313void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 342void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
314 unsigned long mapbase, 343 unsigned long mapbase,
315 unsigned long irq, 344 unsigned long irq,
316 unsigned long irq_err, 345 unsigned long irq_err)
317 int tclk)
318{ 346{
319 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, 347 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
320 mapbase + 0x2000, SZ_16K - 1, irq_err); 348 mapbase + 0x2000, SZ_16K - 1, irq_err);
321 ge_complete(&orion_ge01_shared_data, tclk, 349 ge_complete(&orion_ge01_shared_data,
322 orion_ge01_resources, irq, &orion_ge01_shared, 350 orion_ge01_resources, irq, &orion_ge01_shared,
323 eth_data, &orion_ge01); 351 eth_data, &orion_ge01);
324} 352}
@@ -366,12 +394,11 @@ static struct platform_device orion_ge10 = {
366void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 394void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
367 unsigned long mapbase, 395 unsigned long mapbase,
368 unsigned long irq, 396 unsigned long irq,
369 unsigned long irq_err, 397 unsigned long irq_err)
370 int tclk)
371{ 398{
372 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, 399 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
373 mapbase + 0x2000, SZ_16K - 1, irq_err); 400 mapbase + 0x2000, SZ_16K - 1, irq_err);
374 ge_complete(&orion_ge10_shared_data, tclk, 401 ge_complete(&orion_ge10_shared_data,
375 orion_ge10_resources, irq, &orion_ge10_shared, 402 orion_ge10_resources, irq, &orion_ge10_shared,
376 eth_data, &orion_ge10); 403 eth_data, &orion_ge10);
377} 404}
@@ -419,12 +446,11 @@ static struct platform_device orion_ge11 = {
419void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 446void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
420 unsigned long mapbase, 447 unsigned long mapbase,
421 unsigned long irq, 448 unsigned long irq,
422 unsigned long irq_err, 449 unsigned long irq_err)
423 int tclk)
424{ 450{
425 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, 451 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
426 mapbase + 0x2000, SZ_16K - 1, irq_err); 452 mapbase + 0x2000, SZ_16K - 1, irq_err);
427 ge_complete(&orion_ge11_shared_data, tclk, 453 ge_complete(&orion_ge11_shared_data,
428 orion_ge11_resources, irq, &orion_ge11_shared, 454 orion_ge11_resources, irq, &orion_ge11_shared,
429 eth_data, &orion_ge11); 455 eth_data, &orion_ge11);
430} 456}
@@ -521,44 +547,32 @@ void __init orion_i2c_1_init(unsigned long mapbase,
521/***************************************************************************** 547/*****************************************************************************
522 * SPI 548 * SPI
523 ****************************************************************************/ 549 ****************************************************************************/
524static struct orion_spi_info orion_spi_plat_data;
525static struct resource orion_spi_resources; 550static struct resource orion_spi_resources;
526 551
527static struct platform_device orion_spi = { 552static struct platform_device orion_spi = {
528 .name = "orion_spi", 553 .name = "orion_spi",
529 .id = 0, 554 .id = 0,
530 .dev = {
531 .platform_data = &orion_spi_plat_data,
532 },
533}; 555};
534 556
535static struct orion_spi_info orion_spi_1_plat_data;
536static struct resource orion_spi_1_resources; 557static struct resource orion_spi_1_resources;
537 558
538static struct platform_device orion_spi_1 = { 559static struct platform_device orion_spi_1 = {
539 .name = "orion_spi", 560 .name = "orion_spi",
540 .id = 1, 561 .id = 1,
541 .dev = {
542 .platform_data = &orion_spi_1_plat_data,
543 },
544}; 562};
545 563
546/* Note: The SPI silicon core does have interrupts. However the 564/* Note: The SPI silicon core does have interrupts. However the
547 * current Linux software driver does not use interrupts. */ 565 * current Linux software driver does not use interrupts. */
548 566
549void __init orion_spi_init(unsigned long mapbase, 567void __init orion_spi_init(unsigned long mapbase)
550 unsigned long tclk)
551{ 568{
552 orion_spi_plat_data.tclk = tclk;
553 fill_resources(&orion_spi, &orion_spi_resources, 569 fill_resources(&orion_spi, &orion_spi_resources,
554 mapbase, SZ_512 - 1, NO_IRQ); 570 mapbase, SZ_512 - 1, NO_IRQ);
555 platform_device_register(&orion_spi); 571 platform_device_register(&orion_spi);
556} 572}
557 573
558void __init orion_spi_1_init(unsigned long mapbase, 574void __init orion_spi_1_init(unsigned long mapbase)
559 unsigned long tclk)
560{ 575{
561 orion_spi_1_plat_data.tclk = tclk;
562 fill_resources(&orion_spi_1, &orion_spi_1_resources, 576 fill_resources(&orion_spi_1, &orion_spi_1_resources,
563 mapbase, SZ_512 - 1, NO_IRQ); 577 mapbase, SZ_512 - 1, NO_IRQ);
564 platform_device_register(&orion_spi_1); 578 platform_device_register(&orion_spi_1);
@@ -567,24 +581,18 @@ void __init orion_spi_1_init(unsigned long mapbase,
567/***************************************************************************** 581/*****************************************************************************
568 * Watchdog 582 * Watchdog
569 ****************************************************************************/ 583 ****************************************************************************/
570static struct orion_wdt_platform_data orion_wdt_data;
571
572static struct resource orion_wdt_resource = 584static struct resource orion_wdt_resource =
573 DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28); 585 DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28);
574 586
575static struct platform_device orion_wdt_device = { 587static struct platform_device orion_wdt_device = {
576 .name = "orion_wdt", 588 .name = "orion_wdt",
577 .id = -1, 589 .id = -1,
578 .dev = {
579 .platform_data = &orion_wdt_data,
580 },
581 .resource = &orion_wdt_resource,
582 .num_resources = 1, 590 .num_resources = 1,
591 .resource = &orion_wdt_resource,
583}; 592};
584 593
585void __init orion_wdt_init(unsigned long tclk) 594void __init orion_wdt_init(void)
586{ 595{
587 orion_wdt_data.tclk = tclk;
588 platform_device_register(&orion_wdt_device); 596 platform_device_register(&orion_wdt_device);
589} 597}
590 598
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index a7fa005a5a0e..e00fdb213609 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -16,22 +16,22 @@ struct dsa_platform_data;
16void __init orion_uart0_init(unsigned int membase, 16void __init orion_uart0_init(unsigned int membase,
17 resource_size_t mapbase, 17 resource_size_t mapbase,
18 unsigned int irq, 18 unsigned int irq,
19 unsigned int uartclk); 19 struct clk *clk);
20 20
21void __init orion_uart1_init(unsigned int membase, 21void __init orion_uart1_init(unsigned int membase,
22 resource_size_t mapbase, 22 resource_size_t mapbase,
23 unsigned int irq, 23 unsigned int irq,
24 unsigned int uartclk); 24 struct clk *clk);
25 25
26void __init orion_uart2_init(unsigned int membase, 26void __init orion_uart2_init(unsigned int membase,
27 resource_size_t mapbase, 27 resource_size_t mapbase,
28 unsigned int irq, 28 unsigned int irq,
29 unsigned int uartclk); 29 struct clk *clk);
30 30
31void __init orion_uart3_init(unsigned int membase, 31void __init orion_uart3_init(unsigned int membase,
32 resource_size_t mapbase, 32 resource_size_t mapbase,
33 unsigned int irq, 33 unsigned int irq,
34 unsigned int uartclk); 34 struct clk *clk);
35 35
36void __init orion_rtc_init(unsigned long mapbase, 36void __init orion_rtc_init(unsigned long mapbase,
37 unsigned long irq); 37 unsigned long irq);
@@ -39,29 +39,26 @@ void __init orion_rtc_init(unsigned long mapbase,
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 unsigned long mapbase, 40 unsigned long mapbase,
41 unsigned long irq, 41 unsigned long irq,
42 unsigned long irq_err, 42 unsigned long irq_err);
43 int tclk);
44 43
45void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 44void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
46 unsigned long mapbase, 45 unsigned long mapbase,
47 unsigned long irq, 46 unsigned long irq,
48 unsigned long irq_err, 47 unsigned long irq_err);
49 int tclk);
50 48
51void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 49void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
52 unsigned long mapbase, 50 unsigned long mapbase,
53 unsigned long irq, 51 unsigned long irq,
54 unsigned long irq_err, 52 unsigned long irq_err);
55 int tclk);
56 53
57void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 54void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
58 unsigned long mapbase, 55 unsigned long mapbase,
59 unsigned long irq, 56 unsigned long irq,
60 unsigned long irq_err, 57 unsigned long irq_err);
61 int tclk);
62 58
63void __init orion_ge00_switch_init(struct dsa_platform_data *d, 59void __init orion_ge00_switch_init(struct dsa_platform_data *d,
64 int irq); 60 int irq);
61
65void __init orion_i2c_init(unsigned long mapbase, 62void __init orion_i2c_init(unsigned long mapbase,
66 unsigned long irq, 63 unsigned long irq,
67 unsigned long freq_m); 64 unsigned long freq_m);
@@ -70,13 +67,11 @@ void __init orion_i2c_1_init(unsigned long mapbase,
70 unsigned long irq, 67 unsigned long irq,
71 unsigned long freq_m); 68 unsigned long freq_m);
72 69
73void __init orion_spi_init(unsigned long mapbase, 70void __init orion_spi_init(unsigned long mapbase);
74 unsigned long tclk);
75 71
76void __init orion_spi_1_init(unsigned long mapbase, 72void __init orion_spi_1_init(unsigned long mapbase);
77 unsigned long tclk);
78 73
79void __init orion_wdt_init(unsigned long tclk); 74void __init orion_wdt_init(void);
80 75
81void __init orion_xor0_init(unsigned long mapbase_low, 76void __init orion_xor0_init(unsigned long mapbase_low,
82 unsigned long mapbase_high, 77 unsigned long mapbase_high,
@@ -106,4 +101,9 @@ void __init orion_crypto_init(unsigned long mapbase,
106 unsigned long srambase, 101 unsigned long srambase,
107 unsigned long sram_size, 102 unsigned long sram_size,
108 unsigned long irq); 103 unsigned long irq);
104
105void __init orion_clkdev_add(const char *con_id, const char *dev_id,
106 struct clk *clk);
107
108void __init orion_clkdev_init(struct clk *tclk);
109#endif 109#endif
diff --git a/arch/arm/plat-orion/include/plat/orion_wdt.h b/arch/arm/plat-orion/include/plat/orion_wdt.h
deleted file mode 100644
index 665c362a2fba..000000000000
--- a/arch/arm/plat-orion/include/plat/orion_wdt.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * arch/arm/plat-orion/include/plat/orion_wdt.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __PLAT_ORION_WDT_H
10#define __PLAT_ORION_WDT_H
11
12struct orion_wdt_platform_data {
13 u32 tclk; /* no <linux/clk.h> support yet */
14};
15
16
17#endif
18
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 86dbb5bdb172..f20a321088a2 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -52,12 +52,12 @@
52#define PCIE_DEBUG_SOFT_RESET (1<<20) 52#define PCIE_DEBUG_SOFT_RESET (1<<20)
53 53
54 54
55u32 __init orion_pcie_dev_id(void __iomem *base) 55u32 orion_pcie_dev_id(void __iomem *base)
56{ 56{
57 return readl(base + PCIE_DEV_ID_OFF) >> 16; 57 return readl(base + PCIE_DEV_ID_OFF) >> 16;
58} 58}
59 59
60u32 __init orion_pcie_rev(void __iomem *base) 60u32 orion_pcie_rev(void __iomem *base)
61{ 61{
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; 62 return readl(base + PCIE_DEV_REV_OFF) & 0xff;
63} 63}