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-rw-r--r--arch/cris/arch-v32/kernel/time.c4
-rw-r--r--arch/m68k/platform/68328/timers.c4
-rw-r--r--arch/m68k/platform/coldfire/dma_timer.c5
-rw-r--r--arch/m68k/platform/coldfire/pit.c4
-rw-r--r--arch/m68k/platform/coldfire/sltimers.c4
-rw-r--r--arch/m68k/platform/coldfire/timers.c4
-rw-r--r--arch/parisc/kernel/time.c6
-rw-r--r--arch/um/kernel/time.c6
-rw-r--r--arch/x86/include/asm/mach_timer.h2
-rw-r--r--arch/x86/include/asm/tsc.h2
-rw-r--r--arch/x86/kernel/tsc.c6
-rw-r--r--arch/x86/kernel/tsc_sync.c4
-rw-r--r--arch/xtensa/kernel/time.c13
13 files changed, 18 insertions, 46 deletions
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index bb978ede8985..6773fc83a670 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -47,14 +47,12 @@ static struct clocksource cont_rotime = {
47 .rating = 300, 47 .rating = 300,
48 .read = read_cont_rotime, 48 .read = read_cont_rotime,
49 .mask = CLOCKSOURCE_MASK(32), 49 .mask = CLOCKSOURCE_MASK(32),
50 .shift = 10,
51 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
52}; 51};
53 52
54static int __init etrax_init_cont_rotime(void) 53static int __init etrax_init_cont_rotime(void)
55{ 54{
56 cont_rotime.mult = clocksource_khz2mult(100000, cont_rotime.shift); 55 clocksource_register_khz(&cont_rotime, 100000);
57 clocksource_register(&cont_rotime);
58 return 0; 56 return 0;
59} 57}
60arch_initcall(etrax_init_cont_rotime); 58arch_initcall(etrax_init_cont_rotime);
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c
index 309f725995bf..f2678866067b 100644
--- a/arch/m68k/platform/68328/timers.c
+++ b/arch/m68k/platform/68328/timers.c
@@ -93,7 +93,6 @@ static struct clocksource m68328_clk = {
93 .name = "timer", 93 .name = "timer",
94 .rating = 250, 94 .rating = 250,
95 .read = m68328_read_clk, 95 .read = m68328_read_clk,
96 .shift = 20,
97 .mask = CLOCKSOURCE_MASK(32), 96 .mask = CLOCKSOURCE_MASK(32),
98 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 97 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
99}; 98};
@@ -115,8 +114,7 @@ void hw_timer_init(void)
115 114
116 /* Enable timer 1 */ 115 /* Enable timer 1 */
117 TCTL |= TCTL_TEN; 116 TCTL |= TCTL_TEN;
118 m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift); 117 clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
119 clocksource_register(&m68328_clk);
120} 118}
121 119
122/***************************************************************************/ 120/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/dma_timer.c b/arch/m68k/platform/coldfire/dma_timer.c
index a5f562823d7a..235ad57c4707 100644
--- a/arch/m68k/platform/coldfire/dma_timer.c
+++ b/arch/m68k/platform/coldfire/dma_timer.c
@@ -44,7 +44,6 @@ static struct clocksource clocksource_cf_dt = {
44 .rating = 200, 44 .rating = 200,
45 .read = cf_dt_get_cycles, 45 .read = cf_dt_get_cycles,
46 .mask = CLOCKSOURCE_MASK(32), 46 .mask = CLOCKSOURCE_MASK(32),
47 .shift = 20,
48 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
49}; 48};
50 49
@@ -60,9 +59,7 @@ static int __init init_cf_dt_clocksource(void)
60 __raw_writeb(0x00, DTER0); 59 __raw_writeb(0x00, DTER0);
61 __raw_writel(0x00000000, DTRR0); 60 __raw_writel(0x00000000, DTRR0);
62 __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); 61 __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
63 clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ, 62 return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
64 clocksource_cf_dt.shift);
65 return clocksource_register(&clocksource_cf_dt);
66} 63}
67 64
68arch_initcall(init_cf_dt_clocksource); 65arch_initcall(init_cf_dt_clocksource);
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index c2b980926bec..02663d25822d 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -144,7 +144,6 @@ static struct clocksource pit_clk = {
144 .name = "pit", 144 .name = "pit",
145 .rating = 100, 145 .rating = 100,
146 .read = pit_read_clk, 146 .read = pit_read_clk,
147 .shift = 20,
148 .mask = CLOCKSOURCE_MASK(32), 147 .mask = CLOCKSOURCE_MASK(32),
149}; 148};
150 149
@@ -162,8 +161,7 @@ void hw_timer_init(void)
162 161
163 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); 162 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
164 163
165 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); 164 clocksource_register_hz(&pit_clk, FREQ);
166 clocksource_register(&pit_clk);
167} 165}
168 166
169/***************************************************************************/ 167/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 6a85daf9a7fd..b7f822b552bb 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -114,7 +114,6 @@ static struct clocksource mcfslt_clk = {
114 .name = "slt", 114 .name = "slt",
115 .rating = 250, 115 .rating = 250,
116 .read = mcfslt_read_clk, 116 .read = mcfslt_read_clk,
117 .shift = 20,
118 .mask = CLOCKSOURCE_MASK(32), 117 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 118 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120}; 119};
@@ -136,8 +135,7 @@ void hw_timer_init(void)
136 135
137 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq); 136 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
138 137
139 mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift); 138 clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
140 clocksource_register(&mcfslt_clk);
141 139
142#ifdef CONFIG_HIGHPROFILE 140#ifdef CONFIG_HIGHPROFILE
143 mcfslt_profile_init(); 141 mcfslt_profile_init();
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 60242f65fea9..0d90da32fcdb 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -88,7 +88,6 @@ static struct clocksource mcftmr_clk = {
88 .name = "tmr", 88 .name = "tmr",
89 .rating = 250, 89 .rating = 250,
90 .read = mcftmr_read_clk, 90 .read = mcftmr_read_clk,
91 .shift = 20,
92 .mask = CLOCKSOURCE_MASK(32), 91 .mask = CLOCKSOURCE_MASK(32),
93 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 92 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
94}; 93};
@@ -109,8 +108,7 @@ void hw_timer_init(void)
109 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 108 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
110 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); 109 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
111 110
112 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift); 111 clocksource_register_hz(&mcftmr_clk, FREQ);
113 clocksource_register(&mcftmr_clk);
114 112
115 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq); 113 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
116 114
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 45b7389d77aa..7c0774397b89 100644
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -198,8 +198,6 @@ static struct clocksource clocksource_cr16 = {
198 .rating = 300, 198 .rating = 300,
199 .read = read_cr16, 199 .read = read_cr16,
200 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 200 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
201 .mult = 0, /* to be set */
202 .shift = 22,
203 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 201 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
204}; 202};
205 203
@@ -270,7 +268,5 @@ void __init time_init(void)
270 268
271 /* register at clocksource framework */ 269 /* register at clocksource framework */
272 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 270 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
273 clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, 271 clocksource_register_khz(&clocksource_cr16, current_cr16_khz);
274 clocksource_cr16.shift);
275 clocksource_register(&clocksource_cr16);
276} 272}
diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
index a08d9fab81f2..82a6e22f1f35 100644
--- a/arch/um/kernel/time.c
+++ b/arch/um/kernel/time.c
@@ -75,8 +75,6 @@ static struct clocksource itimer_clocksource = {
75 .rating = 300, 75 .rating = 300,
76 .read = itimer_read, 76 .read = itimer_read,
77 .mask = CLOCKSOURCE_MASK(64), 77 .mask = CLOCKSOURCE_MASK(64),
78 .mult = 1000,
79 .shift = 0,
80 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 78 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
81}; 79};
82 80
@@ -94,9 +92,9 @@ static void __init setup_itimer(void)
94 clockevent_delta2ns(60 * HZ, &itimer_clockevent); 92 clockevent_delta2ns(60 * HZ, &itimer_clockevent);
95 itimer_clockevent.min_delta_ns = 93 itimer_clockevent.min_delta_ns =
96 clockevent_delta2ns(1, &itimer_clockevent); 94 clockevent_delta2ns(1, &itimer_clockevent);
97 err = clocksource_register(&itimer_clocksource); 95 err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
98 if (err) { 96 if (err) {
99 printk(KERN_ERR "clocksource_register returned %d\n", err); 97 printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
100 return; 98 return;
101 } 99 }
102 clockevents_register_device(&itimer_clockevent); 100 clockevents_register_device(&itimer_clockevent);
diff --git a/arch/x86/include/asm/mach_timer.h b/arch/x86/include/asm/mach_timer.h
index 853728519ae9..88d0c3c74c13 100644
--- a/arch/x86/include/asm/mach_timer.h
+++ b/arch/x86/include/asm/mach_timer.h
@@ -15,7 +15,7 @@
15 15
16#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ 16#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
17#define CALIBRATE_LATCH \ 17#define CALIBRATE_LATCH \
18 ((CLOCK_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000) 18 ((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
19 19
20static inline void mach_prepare_counter(void) 20static inline void mach_prepare_counter(void)
21{ 21{
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 83e2efd181e2..15d99153a96d 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,6 +51,8 @@ extern int unsynchronized_tsc(void);
51extern int check_tsc_unstable(void); 51extern int check_tsc_unstable(void);
52extern unsigned long native_calibrate_tsc(void); 52extern unsigned long native_calibrate_tsc(void);
53 53
54extern int tsc_clocksource_reliable;
55
54/* 56/*
55 * Boot-time check whether the TSCs are synchronized across 57 * Boot-time check whether the TSCs are synchronized across
56 * all CPUs/cores: 58 * all CPUs/cores:
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index db483369f10b..2c9cf0fd78f5 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -35,7 +35,7 @@ static int __read_mostly tsc_unstable;
35 erroneous rdtsc usage on !cpu_has_tsc processors */ 35 erroneous rdtsc usage on !cpu_has_tsc processors */
36static int __read_mostly tsc_disabled = -1; 36static int __read_mostly tsc_disabled = -1;
37 37
38static int tsc_clocksource_reliable; 38int tsc_clocksource_reliable;
39/* 39/*
40 * Scheduler clock - returns current time in nanosec units. 40 * Scheduler clock - returns current time in nanosec units.
41 */ 41 */
@@ -178,11 +178,11 @@ static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
178} 178}
179 179
180#define CAL_MS 10 180#define CAL_MS 10
181#define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) 181#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
182#define CAL_PIT_LOOPS 1000 182#define CAL_PIT_LOOPS 1000
183 183
184#define CAL2_MS 50 184#define CAL2_MS 50
185#define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) 185#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
186#define CAL2_PIT_LOOPS 5000 186#define CAL2_PIT_LOOPS 5000
187 187
188 188
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 0aa5fed8b9e6..9eba29b46cb7 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -113,7 +113,7 @@ void __cpuinit check_tsc_sync_source(int cpu)
113 if (unsynchronized_tsc()) 113 if (unsynchronized_tsc())
114 return; 114 return;
115 115
116 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { 116 if (tsc_clocksource_reliable) {
117 if (cpu == (nr_cpu_ids-1) || system_state != SYSTEM_BOOTING) 117 if (cpu == (nr_cpu_ids-1) || system_state != SYSTEM_BOOTING)
118 pr_info( 118 pr_info(
119 "Skipped synchronization checks as TSC is reliable.\n"); 119 "Skipped synchronization checks as TSC is reliable.\n");
@@ -172,7 +172,7 @@ void __cpuinit check_tsc_sync_target(void)
172{ 172{
173 int cpus = 2; 173 int cpus = 2;
174 174
175 if (unsynchronized_tsc() || boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 175 if (unsynchronized_tsc() || tsc_clocksource_reliable)
176 return; 176 return;
177 177
178 /* 178 /*
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index f3e5eb43f71c..ac62f9cf1e10 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -41,14 +41,6 @@ static struct clocksource ccount_clocksource = {
41 .rating = 200, 41 .rating = 200,
42 .read = ccount_read, 42 .read = ccount_read,
43 .mask = CLOCKSOURCE_MASK(32), 43 .mask = CLOCKSOURCE_MASK(32),
44 /*
45 * With a shift of 22 the lower limit of the cpu clock is
46 * 1MHz, where NSEC_PER_CCOUNT is 1000 or a bit less than
47 * 2^10: Since we have 32 bits and the multiplicator can
48 * already take up as much as 10 bits, this leaves us with
49 * remaining upper 22 bits.
50 */
51 .shift = 22,
52}; 44};
53 45
54static irqreturn_t timer_interrupt(int irq, void *dev_id); 46static irqreturn_t timer_interrupt(int irq, void *dev_id);
@@ -66,10 +58,7 @@ void __init time_init(void)
66 printk("%d.%02d MHz\n", (int)ccount_per_jiffy/(1000000/HZ), 58 printk("%d.%02d MHz\n", (int)ccount_per_jiffy/(1000000/HZ),
67 (int)(ccount_per_jiffy/(10000/HZ))%100); 59 (int)(ccount_per_jiffy/(10000/HZ))%100);
68#endif 60#endif
69 ccount_clocksource.mult = 61 clocksource_register_hz(&ccount_clocksource, CCOUNT_PER_JIFFY * HZ);
70 clocksource_hz2mult(CCOUNT_PER_JIFFY * HZ,
71 ccount_clocksource.shift);
72 clocksource_register(&ccount_clocksource);
73 62
74 /* Initialize the linux timer interrupt. */ 63 /* Initialize the linux timer interrupt. */
75 64