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-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts188
-rw-r--r--arch/arm/mach-vexpress/Makefile.boot3
2 files changed, 190 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
new file mode 100644
index 000000000000..4890a81c5467
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -0,0 +1,188 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
40
41 cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <1>;
45 };
46
47/* A7s disabled till big.LITTLE patches are available...
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <0x100>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0x101>;
58 };
59
60 cpu4: cpu@4 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0x102>;
64 };
65*/
66 };
67
68 memory@80000000 {
69 device_type = "memory";
70 reg = <0 0x80000000 0 0x40000000>;
71 };
72
73 wdt@2a490000 {
74 compatible = "arm,sp805", "arm,primecell";
75 reg = <0 0x2a490000 0 0x1000>;
76 interrupts = <98>;
77 };
78
79 hdlcd@2b000000 {
80 compatible = "arm,hdlcd";
81 reg = <0 0x2b000000 0 0x1000>;
82 interrupts = <0 85 4>;
83 };
84
85 memory-controller@2b0a0000 {
86 compatible = "arm,pl341", "arm,primecell";
87 reg = <0 0x2b0a0000 0 0x1000>;
88 };
89
90 gic: interrupt-controller@2c001000 {
91 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
94 interrupt-controller;
95 reg = <0 0x2c001000 0 0x1000>,
96 <0 0x2c002000 0 0x1000>,
97 <0 0x2c004000 0 0x2000>,
98 <0 0x2c006000 0 0x2000>;
99 interrupts = <1 9 0xf04>;
100 };
101
102 memory-controller@7ffd0000 {
103 compatible = "arm,pl354", "arm,primecell";
104 reg = <0 0x7ffd0000 0 0x1000>;
105 interrupts = <0 86 4>,
106 <0 87 4>;
107 };
108
109 dma@7ff00000 {
110 compatible = "arm,pl330", "arm,primecell";
111 reg = <0 0x7ff00000 0 0x1000>;
112 interrupts = <0 92 4>,
113 <0 88 4>,
114 <0 89 4>,
115 <0 90 4>,
116 <0 91 4>;
117 };
118
119 timer {
120 compatible = "arm,armv7-timer";
121 interrupts = <1 13 0xf08>,
122 <1 14 0xf08>,
123 <1 11 0xf08>,
124 <1 10 0xf08>;
125 };
126
127 pmu {
128 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
129 interrupts = <0 68 4>,
130 <0 69 4>;
131 };
132
133 motherboard {
134 ranges = <0 0 0 0x08000000 0x04000000>,
135 <1 0 0 0x14000000 0x04000000>,
136 <2 0 0 0x18000000 0x04000000>,
137 <3 0 0 0x1c000000 0x04000000>,
138 <4 0 0 0x0c000000 0x04000000>,
139 <5 0 0 0x10000000 0x04000000>;
140
141 interrupt-map-mask = <0 0 63>;
142 interrupt-map = <0 0 0 &gic 0 0 4>,
143 <0 0 1 &gic 0 1 4>,
144 <0 0 2 &gic 0 2 4>,
145 <0 0 3 &gic 0 3 4>,
146 <0 0 4 &gic 0 4 4>,
147 <0 0 5 &gic 0 5 4>,
148 <0 0 6 &gic 0 6 4>,
149 <0 0 7 &gic 0 7 4>,
150 <0 0 8 &gic 0 8 4>,
151 <0 0 9 &gic 0 9 4>,
152 <0 0 10 &gic 0 10 4>,
153 <0 0 11 &gic 0 11 4>,
154 <0 0 12 &gic 0 12 4>,
155 <0 0 13 &gic 0 13 4>,
156 <0 0 14 &gic 0 14 4>,
157 <0 0 15 &gic 0 15 4>,
158 <0 0 16 &gic 0 16 4>,
159 <0 0 17 &gic 0 17 4>,
160 <0 0 18 &gic 0 18 4>,
161 <0 0 19 &gic 0 19 4>,
162 <0 0 20 &gic 0 20 4>,
163 <0 0 21 &gic 0 21 4>,
164 <0 0 22 &gic 0 22 4>,
165 <0 0 23 &gic 0 23 4>,
166 <0 0 24 &gic 0 24 4>,
167 <0 0 25 &gic 0 25 4>,
168 <0 0 26 &gic 0 26 4>,
169 <0 0 27 &gic 0 27 4>,
170 <0 0 28 &gic 0 28 4>,
171 <0 0 29 &gic 0 29 4>,
172 <0 0 30 &gic 0 30 4>,
173 <0 0 31 &gic 0 31 4>,
174 <0 0 32 &gic 0 32 4>,
175 <0 0 33 &gic 0 33 4>,
176 <0 0 34 &gic 0 34 4>,
177 <0 0 35 &gic 0 35 4>,
178 <0 0 36 &gic 0 36 4>,
179 <0 0 37 &gic 0 37 4>,
180 <0 0 38 &gic 0 38 4>,
181 <0 0 39 &gic 0 39 4>,
182 <0 0 40 &gic 0 40 4>,
183 <0 0 41 &gic 0 41 4>,
184 <0 0 42 &gic 0 42 4>;
185 };
186};
187
188/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 909f85ebf5f4..318d308dfb93 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000
6 6
7dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ 7dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
8 vexpress-v2p-ca9.dtb \ 8 vexpress-v2p-ca9.dtb \
9 vexpress-v2p-ca15-tc1.dtb 9 vexpress-v2p-ca15-tc1.dtb \
10 vexpress-v2p-ca15_a7.dtb
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 08:21:58 -0500