diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kernel/cpu/perf_counter.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index f5853718d4d3..1df421042b2a 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c | |||
@@ -37,7 +37,7 @@ struct cpu_hw_counters { | |||
37 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | 37 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
38 | unsigned long interrupts; | 38 | unsigned long interrupts; |
39 | u64 throttle_ctrl; | 39 | u64 throttle_ctrl; |
40 | u64 active_mask; | 40 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
41 | int enabled; | 41 | int enabled; |
42 | }; | 42 | }; |
43 | 43 | ||
@@ -291,7 +291,7 @@ static void pmc_amd_restore_all(u64 ctrl) | |||
291 | return; | 291 | return; |
292 | 292 | ||
293 | for (idx = 0; idx < nr_counters_generic; idx++) { | 293 | for (idx = 0; idx < nr_counters_generic; idx++) { |
294 | if (test_bit(idx, (unsigned long *)&cpuc->active_mask)) { | 294 | if (test_bit(idx, cpuc->active_mask)) { |
295 | u64 val; | 295 | u64 val; |
296 | 296 | ||
297 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | 297 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
@@ -377,7 +377,7 @@ static void pmc_amd_enable(int idx, u64 config) | |||
377 | { | 377 | { |
378 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | 378 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
379 | 379 | ||
380 | set_bit(idx, (unsigned long *)&cpuc->active_mask); | 380 | set_bit(idx, cpuc->active_mask); |
381 | if (cpuc->enabled) | 381 | if (cpuc->enabled) |
382 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | 382 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
383 | 383 | ||
@@ -401,7 +401,7 @@ static void pmc_amd_disable(int idx, u64 config) | |||
401 | { | 401 | { |
402 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | 402 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
403 | 403 | ||
404 | clear_bit(idx, (unsigned long *)&cpuc->active_mask); | 404 | clear_bit(idx, cpuc->active_mask); |
405 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | 405 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
406 | 406 | ||
407 | } | 407 | } |