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-rw-r--r--arch/arm/mach-s3c2410/include/mach/system-reset.h2
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-watchdog.h41
-rw-r--r--arch/arm/plat-s3c/include/plat/uncompress.h2
3 files changed, 43 insertions, 2 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index 43535a0e7186..7613d0a384ba 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -13,7 +13,7 @@
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16#include <asm/plat-s3c/regs-watchdog.h> 16#include <plat/regs-watchdog.h>
17#include <mach/regs-clock.h> 17#include <mach/regs-clock.h>
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H
16
17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
18
19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
41
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
index 4df006b9cc10..8a8a927292e0 100644
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -28,7 +28,7 @@ static void arch_detect_cpu(void);
28/* defines for UART registers */ 28/* defines for UART registers */
29 29
30#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
31#include <asm/plat-s3c/regs-watchdog.h> 31#include <plat/regs-watchdog.h>
32 32
33/* working in physical space... */ 33/* working in physical space... */
34#undef S3C2410_WDOGREG 34#undef S3C2410_WDOGREG