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-rw-r--r--arch/mips/Kconfig18
-rw-r--r--arch/mips/Makefile11
-rw-r--r--arch/mips/configs/atlas_defconfig2
-rw-r--r--arch/mips/configs/bigsur_defconfig2
-rw-r--r--arch/mips/configs/capcella_defconfig2
-rw-r--r--arch/mips/configs/cobalt_defconfig1
-rw-r--r--arch/mips/configs/db1000_defconfig2
-rw-r--r--arch/mips/configs/db1100_defconfig2
-rw-r--r--arch/mips/configs/db1200_defconfig2
-rw-r--r--arch/mips/configs/db1500_defconfig2
-rw-r--r--arch/mips/configs/db1550_defconfig2
-rw-r--r--arch/mips/configs/ddb5477_defconfig2
-rw-r--r--arch/mips/configs/decstation_defconfig2
-rw-r--r--arch/mips/configs/e55_defconfig2
-rw-r--r--arch/mips/configs/emma2rh_defconfig2
-rw-r--r--arch/mips/configs/excite_defconfig2
-rw-r--r--arch/mips/configs/fulong_defconfig1
-rw-r--r--arch/mips/configs/ip22_defconfig2
-rw-r--r--arch/mips/configs/ip27_defconfig2
-rw-r--r--arch/mips/configs/ip32_defconfig2
-rw-r--r--arch/mips/configs/jazz_defconfig2
-rw-r--r--arch/mips/configs/jmr3927_defconfig2
-rw-r--r--arch/mips/configs/malta_defconfig2
-rw-r--r--arch/mips/configs/mipssim_defconfig2
-rw-r--r--arch/mips/configs/mpc30x_defconfig2
-rw-r--r--arch/mips/configs/msp71xx_defconfig2
-rw-r--r--arch/mips/configs/ocelot_defconfig919
-rw-r--r--arch/mips/configs/pb1100_defconfig2
-rw-r--r--arch/mips/configs/pb1500_defconfig2
-rw-r--r--arch/mips/configs/pb1550_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig2
-rw-r--r--arch/mips/configs/qemu_defconfig2
-rw-r--r--arch/mips/configs/rbhma4200_defconfig1
-rw-r--r--arch/mips/configs/rbhma4500_defconfig1
-rw-r--r--arch/mips/configs/rm200_defconfig2
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig2
-rw-r--r--arch/mips/configs/sead_defconfig2
-rw-r--r--arch/mips/configs/tb0219_defconfig2
-rw-r--r--arch/mips/configs/tb0226_defconfig2
-rw-r--r--arch/mips/configs/tb0287_defconfig2
-rw-r--r--arch/mips/configs/workpad_defconfig2
-rw-r--r--arch/mips/configs/wrppmc_defconfig2
-rw-r--r--arch/mips/configs/yosemite_defconfig2
-rw-r--r--arch/mips/defconfig2
-rw-r--r--arch/mips/gt64120/momenco_ocelot/Makefile7
-rw-r--r--arch/mips/gt64120/momenco_ocelot/dbg_io.c121
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c95
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot-platform.c46
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot_pld.h30
-rw-r--r--arch/mips/gt64120/momenco_ocelot/prom.c71
-rw-r--r--arch/mips/gt64120/momenco_ocelot/reset.c47
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c365
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-ocelot.c75
-rw-r--r--arch/mips/pci/pci-ocelot.c107
56 files changed, 0 insertions, 1993 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3513e226837b..1d9a65e4c5cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -227,24 +227,6 @@ config MIPS_SIM
227 This option enables support for MIPS Technologies MIPSsim software 227 This option enables support for MIPS Technologies MIPSsim software
228 emulator. 228 emulator.
229 229
230config MOMENCO_OCELOT
231 bool "Momentum Ocelot board"
232 select DMA_NONCOHERENT
233 select HW_HAS_PCI
234 select IRQ_CPU
235 select IRQ_CPU_RM7K
236 select PCI_GT64XXX_PCI0
237 select RM7000_CPU_SCACHE
238 select SWAP_IO_SPACE
239 select SYS_HAS_CPU_RM7000
240 select SYS_SUPPORTS_32BIT_KERNEL
241 select SYS_SUPPORTS_64BIT_KERNEL
242 select SYS_SUPPORTS_BIG_ENDIAN
243 select SYS_SUPPORTS_KGDB
244 help
245 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
246 Momentum Computer <http://www.momenco.com/>.
247
248config DDB5477 230config DDB5477
249 bool "NEC DDB Vrc-5477" 231 bool "NEC DDB Vrc-5477"
250 select DDB5XXX_COMMON 232 select DDB5XXX_COMMON
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 6ac8bdae612a..2bd0a86e2f9c 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -337,17 +337,6 @@ cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-mipssim
337load-$(CONFIG_MIPS_SIM) += 0x80100000 337load-$(CONFIG_MIPS_SIM) += 0x80100000
338 338
339# 339#
340# Momentum Ocelot board
341#
342# The Ocelot setup.o must be linked early - it does the ioremap() for the
343# mips_io_port_base.
344#
345core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
346 arch/mips/gt64120/momenco_ocelot/
347cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
348load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
349
350#
351# PMC-Sierra MSP SOCs 340# PMC-Sierra MSP SOCs
352# 341#
353core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/ 342core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 129e2c961fec..28d36961f0ca 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -32,8 +32,6 @@ CONFIG_MIPS_ATLAS=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index dc3e1bf4e42e..98dd3196b7c3 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 4c7031222e64..5ffbd3885c14 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index c8c05785a86d..410b441c5ca8 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -18,7 +18,6 @@ CONFIG_MIPS_COBALT=y
18# CONFIG_MIPS_SEAD is not set 18# CONFIG_MIPS_SEAD is not set
19# CONFIG_WR_PPMC is not set 19# CONFIG_WR_PPMC is not set
20# CONFIG_MIPS_SIM is not set 20# CONFIG_MIPS_SIM is not set
21# CONFIG_MOMENCO_OCELOT is not set
22# CONFIG_PNX8550_JBS is not set 21# CONFIG_PNX8550_JBS is not set
23# CONFIG_PNX8550_STB810 is not set 22# CONFIG_PNX8550_STB810 is not set
24# CONFIG_DDB5477 is not set 23# CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index ec60beb888b2..7c515d7e189f 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_DB1000=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index f3c25f08bfad..9460d6587a65 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_DB1100=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 6d400befbacc..dc3985fadbd2 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_DB1200=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 82aea6e08823..d56931762279 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_DB1500=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 82697714a9e3..2348486cc4cd 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_DB1550=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index a42ab9ae7d4b..90123c69c11c 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index d6e3fffbc80d..37d3bc5fdba3 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -32,8 +32,6 @@ CONFIG_MACH_DECSTATION=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 78f5004fb721..629737830d29 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index b29bff0f56c3..ec54880a2ec9 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 69810592aa6b..801f5ac8b849 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -33,8 +33,6 @@ CONFIG_BASLER_EXCITE=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig
index 6ab94d8cf08b..feacaf073777 100644
--- a/arch/mips/configs/fulong_defconfig
+++ b/arch/mips/configs/fulong_defconfig
@@ -19,7 +19,6 @@ CONFIG_LEMOTE_FULONG=y
19# CONFIG_MIPS_SEAD is not set 19# CONFIG_MIPS_SEAD is not set
20# CONFIG_WR_PPMC is not set 20# CONFIG_WR_PPMC is not set
21# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
22# CONFIG_MOMENCO_OCELOT is not set
23# CONFIG_PNX8550_JBS is not set 22# CONFIG_PNX8550_JBS is not set
24# CONFIG_PNX8550_STB810 is not set 23# CONFIG_PNX8550_STB810 is not set
25# CONFIG_DDB5477 is not set 24# CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 405c9f505a77..5d2d29a0e062 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index a9dcbcf563cb..82131929cdb4 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index a040459bec11..849f9c932b3f 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 8a0b4ac5283d..49487493eb1d 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -32,8 +32,6 @@ CONFIG_MACH_JAZZ=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 9a25e770abd8..1e6d3cb6cde2 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 546cb243fd09..b17eb6f33724 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -32,8 +32,6 @@ CONFIG_MIPS_MALTA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 6abad6f88313..2d94569f0547 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33CONFIG_MIPS_SIM=y 33CONFIG_MIPS_SIM=y
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 4981ce425d82..090eb2fa0564 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index adca5f7ba533..7296f0c8b1ec 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
deleted file mode 100644
index e1db1fb80cd0..000000000000
--- a/arch/mips/configs/ocelot_defconfig
+++ /dev/null
@@ -1,919 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:36 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set
29# CONFIG_MIPS_ATLAS is not set
30# CONFIG_MIPS_MALTA is not set
31# CONFIG_MIPS_SEAD is not set
32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35CONFIG_MOMENCO_OCELOT=y
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set
40# CONFIG_DDB5477 is not set
41# CONFIG_MACH_VR41XX is not set
42# CONFIG_PMC_YOSEMITE is not set
43# CONFIG_QEMU is not set
44# CONFIG_MARKEINS is not set
45# CONFIG_SGI_IP22 is not set
46# CONFIG_SGI_IP27 is not set
47# CONFIG_SGI_IP32 is not set
48# CONFIG_SIBYTE_BIGSUR is not set
49# CONFIG_SIBYTE_SWARM is not set
50# CONFIG_SIBYTE_SENTOSA is not set
51# CONFIG_SIBYTE_RHONE is not set
52# CONFIG_SIBYTE_CARMEL is not set
53# CONFIG_SIBYTE_PTSWARM is not set
54# CONFIG_SIBYTE_LITTLESUR is not set
55# CONFIG_SIBYTE_CRHINE is not set
56# CONFIG_SIBYTE_CRHONE is not set
57# CONFIG_SNI_RM is not set
58# CONFIG_TOSHIBA_JMR3927 is not set
59# CONFIG_TOSHIBA_RBTX4927 is not set
60# CONFIG_TOSHIBA_RBTX4938 is not set
61CONFIG_RWSEM_GENERIC_SPINLOCK=y
62# CONFIG_ARCH_HAS_ILOG2_U32 is not set
63# CONFIG_ARCH_HAS_ILOG2_U64 is not set
64CONFIG_GENERIC_FIND_NEXT_BIT=y
65CONFIG_GENERIC_HWEIGHT=y
66CONFIG_GENERIC_CALIBRATE_DELAY=y
67CONFIG_GENERIC_TIME=y
68CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
69# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
70CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y
72CONFIG_CPU_BIG_ENDIAN=y
73# CONFIG_CPU_LITTLE_ENDIAN is not set
74CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
75CONFIG_IRQ_CPU=y
76CONFIG_IRQ_CPU_RM7K=y
77CONFIG_MIPS_GT64120=y
78CONFIG_SWAP_IO_SPACE=y
79# CONFIG_SYSCLK_75 is not set
80# CONFIG_SYSCLK_83 is not set
81CONFIG_SYSCLK_100=y
82CONFIG_MIPS_L1_CACHE_SHIFT=5
83
84#
85# CPU selection
86#
87# CONFIG_CPU_MIPS32_R1 is not set
88# CONFIG_CPU_MIPS32_R2 is not set
89# CONFIG_CPU_MIPS64_R1 is not set
90# CONFIG_CPU_MIPS64_R2 is not set
91# CONFIG_CPU_R3000 is not set
92# CONFIG_CPU_TX39XX is not set
93# CONFIG_CPU_VR41XX is not set
94# CONFIG_CPU_R4300 is not set
95# CONFIG_CPU_R4X00 is not set
96# CONFIG_CPU_TX49XX is not set
97# CONFIG_CPU_R5000 is not set
98# CONFIG_CPU_R5432 is not set
99# CONFIG_CPU_R6000 is not set
100# CONFIG_CPU_NEVADA is not set
101# CONFIG_CPU_R8000 is not set
102# CONFIG_CPU_R10000 is not set
103CONFIG_CPU_RM7000=y
104# CONFIG_CPU_RM9000 is not set
105# CONFIG_CPU_SB1 is not set
106CONFIG_SYS_HAS_CPU_RM7000=y
107CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
108CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
109CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
110CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
111
112#
113# Kernel type
114#
115CONFIG_32BIT=y
116# CONFIG_64BIT is not set
117CONFIG_PAGE_SIZE_4KB=y
118# CONFIG_PAGE_SIZE_8KB is not set
119# CONFIG_PAGE_SIZE_16KB is not set
120# CONFIG_PAGE_SIZE_64KB is not set
121CONFIG_BOARD_SCACHE=y
122CONFIG_RM7000_CPU_SCACHE=y
123CONFIG_CPU_HAS_PREFETCH=y
124CONFIG_MIPS_MT_DISABLED=y
125# CONFIG_MIPS_MT_SMP is not set
126# CONFIG_MIPS_MT_SMTC is not set
127# CONFIG_MIPS_VPE_LOADER is not set
128# CONFIG_64BIT_PHYS_ADDR is not set
129CONFIG_CPU_HAS_LLSC=y
130CONFIG_CPU_HAS_SYNC=y
131CONFIG_GENERIC_HARDIRQS=y
132CONFIG_GENERIC_IRQ_PROBE=y
133CONFIG_CPU_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_SELECT_MEMORY_MODEL=y
136CONFIG_FLATMEM_MANUAL=y
137# CONFIG_DISCONTIGMEM_MANUAL is not set
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_FLATMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141# CONFIG_SPARSEMEM_STATIC is not set
142CONFIG_SPLIT_PTLOCK_CPUS=4
143# CONFIG_RESOURCES_64BIT is not set
144CONFIG_ZONE_DMA_FLAG=1
145# CONFIG_HZ_48 is not set
146# CONFIG_HZ_100 is not set
147# CONFIG_HZ_128 is not set
148# CONFIG_HZ_250 is not set
149# CONFIG_HZ_256 is not set
150CONFIG_HZ_1000=y
151# CONFIG_HZ_1024 is not set
152CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
153CONFIG_HZ=1000
154CONFIG_PREEMPT_NONE=y
155# CONFIG_PREEMPT_VOLUNTARY is not set
156# CONFIG_PREEMPT is not set
157# CONFIG_KEXEC is not set
158CONFIG_LOCKDEP_SUPPORT=y
159CONFIG_STACKTRACE_SUPPORT=y
160CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
161
162#
163# Code maturity level options
164#
165CONFIG_EXPERIMENTAL=y
166CONFIG_BROKEN_ON_SMP=y
167CONFIG_INIT_ENV_ARG_LIMIT=32
168
169#
170# General setup
171#
172CONFIG_LOCALVERSION=""
173CONFIG_LOCALVERSION_AUTO=y
174CONFIG_SWAP=y
175CONFIG_SYSVIPC=y
176# CONFIG_IPC_NS is not set
177CONFIG_SYSVIPC_SYSCTL=y
178# CONFIG_POSIX_MQUEUE is not set
179# CONFIG_BSD_PROCESS_ACCT is not set
180# CONFIG_TASKSTATS is not set
181# CONFIG_UTS_NS is not set
182# CONFIG_AUDIT is not set
183# CONFIG_IKCONFIG is not set
184CONFIG_SYSFS_DEPRECATED=y
185CONFIG_RELAY=y
186# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
187CONFIG_SYSCTL=y
188CONFIG_EMBEDDED=y
189CONFIG_SYSCTL_SYSCALL=y
190CONFIG_KALLSYMS=y
191# CONFIG_KALLSYMS_EXTRA_PASS is not set
192# CONFIG_HOTPLUG is not set
193CONFIG_PRINTK=y
194CONFIG_BUG=y
195CONFIG_ELF_CORE=y
196CONFIG_BASE_FULL=y
197CONFIG_FUTEX=y
198CONFIG_EPOLL=y
199CONFIG_SHMEM=y
200CONFIG_SLAB=y
201CONFIG_VM_EVENT_COUNTERS=y
202CONFIG_RT_MUTEXES=y
203# CONFIG_TINY_SHMEM is not set
204CONFIG_BASE_SMALL=0
205# CONFIG_SLOB is not set
206
207#
208# Loadable module support
209#
210# CONFIG_MODULES is not set
211
212#
213# Block layer
214#
215CONFIG_BLOCK=y
216# CONFIG_LBD is not set
217# CONFIG_BLK_DEV_IO_TRACE is not set
218# CONFIG_LSF is not set
219
220#
221# IO Schedulers
222#
223CONFIG_IOSCHED_NOOP=y
224CONFIG_IOSCHED_AS=y
225CONFIG_IOSCHED_DEADLINE=y
226CONFIG_IOSCHED_CFQ=y
227CONFIG_DEFAULT_AS=y
228# CONFIG_DEFAULT_DEADLINE is not set
229# CONFIG_DEFAULT_CFQ is not set
230# CONFIG_DEFAULT_NOOP is not set
231CONFIG_DEFAULT_IOSCHED="anticipatory"
232
233#
234# Bus options (PCI, PCMCIA, EISA, ISA, TC)
235#
236CONFIG_HW_HAS_PCI=y
237# CONFIG_PCI is not set
238CONFIG_MMU=y
239
240#
241# PCCARD (PCMCIA/CardBus) support
242#
243
244#
245# PCI Hotplug Support
246#
247
248#
249# Executable file formats
250#
251CONFIG_BINFMT_ELF=y
252# CONFIG_BINFMT_MISC is not set
253CONFIG_TRAD_SIGNALS=y
254
255#
256# Power management options
257#
258CONFIG_PM=y
259# CONFIG_PM_LEGACY is not set
260# CONFIG_PM_DEBUG is not set
261# CONFIG_PM_SYSFS_DEPRECATED is not set
262
263#
264# Networking
265#
266CONFIG_NET=y
267
268#
269# Networking options
270#
271# CONFIG_NETDEBUG is not set
272# CONFIG_PACKET is not set
273CONFIG_UNIX=y
274CONFIG_XFRM=y
275CONFIG_XFRM_USER=y
276# CONFIG_XFRM_SUB_POLICY is not set
277CONFIG_XFRM_MIGRATE=y
278CONFIG_NET_KEY=y
279CONFIG_NET_KEY_MIGRATE=y
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282# CONFIG_IP_ADVANCED_ROUTER is not set
283CONFIG_IP_FIB_HASH=y
284CONFIG_IP_PNP=y
285# CONFIG_IP_PNP_DHCP is not set
286CONFIG_IP_PNP_BOOTP=y
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_ARPD is not set
291# CONFIG_SYN_COOKIES is not set
292# CONFIG_INET_AH is not set
293# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set
295# CONFIG_INET_XFRM_TUNNEL is not set
296# CONFIG_INET_TUNNEL is not set
297CONFIG_INET_XFRM_MODE_TRANSPORT=y
298CONFIG_INET_XFRM_MODE_TUNNEL=y
299CONFIG_INET_XFRM_MODE_BEET=y
300CONFIG_INET_DIAG=y
301CONFIG_INET_TCP_DIAG=y
302# CONFIG_TCP_CONG_ADVANCED is not set
303CONFIG_TCP_CONG_CUBIC=y
304CONFIG_DEFAULT_TCP_CONG="cubic"
305CONFIG_TCP_MD5SIG=y
306# CONFIG_IPV6 is not set
307# CONFIG_INET6_XFRM_TUNNEL is not set
308# CONFIG_INET6_TUNNEL is not set
309CONFIG_NETWORK_SECMARK=y
310# CONFIG_NETFILTER is not set
311
312#
313# DCCP Configuration (EXPERIMENTAL)
314#
315# CONFIG_IP_DCCP is not set
316
317#
318# SCTP Configuration (EXPERIMENTAL)
319#
320# CONFIG_IP_SCTP is not set
321
322#
323# TIPC Configuration (EXPERIMENTAL)
324#
325# CONFIG_TIPC is not set
326# CONFIG_ATM is not set
327# CONFIG_BRIDGE is not set
328# CONFIG_VLAN_8021Q is not set
329# CONFIG_DECNET is not set
330# CONFIG_LLC2 is not set
331# CONFIG_IPX is not set
332# CONFIG_ATALK is not set
333# CONFIG_X25 is not set
334# CONFIG_LAPB is not set
335# CONFIG_ECONET is not set
336# CONFIG_WAN_ROUTER is not set
337
338#
339# QoS and/or fair queueing
340#
341# CONFIG_NET_SCHED is not set
342
343#
344# Network testing
345#
346# CONFIG_NET_PKTGEN is not set
347# CONFIG_HAMRADIO is not set
348# CONFIG_IRDA is not set
349# CONFIG_BT is not set
350CONFIG_IEEE80211=y
351# CONFIG_IEEE80211_DEBUG is not set
352CONFIG_IEEE80211_CRYPT_WEP=y
353CONFIG_IEEE80211_CRYPT_CCMP=y
354CONFIG_IEEE80211_SOFTMAC=y
355# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
356CONFIG_WIRELESS_EXT=y
357
358#
359# Device Drivers
360#
361
362#
363# Generic Driver Options
364#
365CONFIG_STANDALONE=y
366CONFIG_PREVENT_FIRMWARE_BUILD=y
367# CONFIG_SYS_HYPERVISOR is not set
368
369#
370# Connector - unified userspace <-> kernelspace linker
371#
372CONFIG_CONNECTOR=y
373CONFIG_PROC_EVENTS=y
374
375#
376# Memory Technology Devices (MTD)
377#
378# CONFIG_MTD is not set
379
380#
381# Parallel port support
382#
383# CONFIG_PARPORT is not set
384
385#
386# Plug and Play support
387#
388# CONFIG_PNPACPI is not set
389
390#
391# Block devices
392#
393# CONFIG_BLK_DEV_COW_COMMON is not set
394# CONFIG_BLK_DEV_LOOP is not set
395# CONFIG_BLK_DEV_NBD is not set
396# CONFIG_BLK_DEV_RAM is not set
397# CONFIG_BLK_DEV_INITRD is not set
398CONFIG_CDROM_PKTCDVD=y
399CONFIG_CDROM_PKTCDVD_BUFFERS=8
400# CONFIG_CDROM_PKTCDVD_WCACHE is not set
401CONFIG_ATA_OVER_ETH=y
402
403#
404# Misc devices
405#
406
407#
408# ATA/ATAPI/MFM/RLL support
409#
410# CONFIG_IDE is not set
411
412#
413# SCSI device support
414#
415CONFIG_RAID_ATTRS=y
416# CONFIG_SCSI is not set
417# CONFIG_SCSI_NETLINK is not set
418
419#
420# Serial ATA (prod) and Parallel ATA (experimental) drivers
421#
422# CONFIG_ATA is not set
423
424#
425# Multi-device support (RAID and LVM)
426#
427# CONFIG_MD is not set
428
429#
430# Fusion MPT device support
431#
432# CONFIG_FUSION is not set
433
434#
435# IEEE 1394 (FireWire) support
436#
437
438#
439# I2O device support
440#
441
442#
443# Network device support
444#
445CONFIG_NETDEVICES=y
446# CONFIG_DUMMY is not set
447# CONFIG_BONDING is not set
448# CONFIG_EQUALIZER is not set
449# CONFIG_TUN is not set
450
451#
452# PHY device support
453#
454CONFIG_PHYLIB=y
455
456#
457# MII PHY device drivers
458#
459CONFIG_MARVELL_PHY=y
460CONFIG_DAVICOM_PHY=y
461CONFIG_QSEMI_PHY=y
462CONFIG_LXT_PHY=y
463CONFIG_CICADA_PHY=y
464CONFIG_VITESSE_PHY=y
465CONFIG_SMSC_PHY=y
466# CONFIG_BROADCOM_PHY is not set
467# CONFIG_FIXED_PHY is not set
468
469#
470# Ethernet (10 or 100Mbit)
471#
472CONFIG_NET_ETHERNET=y
473# CONFIG_MII is not set
474# CONFIG_DM9000 is not set
475
476#
477# Ethernet (1000 Mbit)
478#
479
480#
481# Ethernet (10000 Mbit)
482#
483
484#
485# Token Ring devices
486#
487
488#
489# Wireless LAN (non-hamradio)
490#
491# CONFIG_NET_RADIO is not set
492
493#
494# Wan interfaces
495#
496# CONFIG_WAN is not set
497# CONFIG_PPP is not set
498# CONFIG_SLIP is not set
499# CONFIG_SHAPER is not set
500# CONFIG_NETCONSOLE is not set
501# CONFIG_NETPOLL is not set
502# CONFIG_NET_POLL_CONTROLLER is not set
503
504#
505# ISDN subsystem
506#
507# CONFIG_ISDN is not set
508
509#
510# Telephony Support
511#
512# CONFIG_PHONE is not set
513
514#
515# Input device support
516#
517CONFIG_INPUT=y
518# CONFIG_INPUT_FF_MEMLESS is not set
519
520#
521# Userland interfaces
522#
523CONFIG_INPUT_MOUSEDEV=y
524CONFIG_INPUT_MOUSEDEV_PSAUX=y
525CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
526CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
527# CONFIG_INPUT_JOYDEV is not set
528# CONFIG_INPUT_TSDEV is not set
529# CONFIG_INPUT_EVDEV is not set
530# CONFIG_INPUT_EVBUG is not set
531
532#
533# Input Device Drivers
534#
535# CONFIG_INPUT_KEYBOARD is not set
536# CONFIG_INPUT_MOUSE is not set
537# CONFIG_INPUT_JOYSTICK is not set
538# CONFIG_INPUT_TOUCHSCREEN is not set
539# CONFIG_INPUT_MISC is not set
540
541#
542# Hardware I/O ports
543#
544CONFIG_SERIO=y
545# CONFIG_SERIO_I8042 is not set
546CONFIG_SERIO_SERPORT=y
547# CONFIG_SERIO_LIBPS2 is not set
548CONFIG_SERIO_RAW=y
549# CONFIG_GAMEPORT is not set
550
551#
552# Character devices
553#
554CONFIG_VT=y
555CONFIG_VT_CONSOLE=y
556CONFIG_HW_CONSOLE=y
557CONFIG_VT_HW_CONSOLE_BINDING=y
558# CONFIG_SERIAL_NONSTANDARD is not set
559
560#
561# Serial drivers
562#
563CONFIG_SERIAL_8250=y
564CONFIG_SERIAL_8250_CONSOLE=y
565CONFIG_SERIAL_8250_NR_UARTS=4
566CONFIG_SERIAL_8250_RUNTIME_UARTS=4
567# CONFIG_SERIAL_8250_EXTENDED is not set
568
569#
570# Non-8250 serial port support
571#
572CONFIG_SERIAL_CORE=y
573CONFIG_SERIAL_CORE_CONSOLE=y
574CONFIG_UNIX98_PTYS=y
575CONFIG_LEGACY_PTYS=y
576CONFIG_LEGACY_PTY_COUNT=256
577
578#
579# IPMI
580#
581# CONFIG_IPMI_HANDLER is not set
582
583#
584# Watchdog Cards
585#
586# CONFIG_WATCHDOG is not set
587# CONFIG_HW_RANDOM is not set
588# CONFIG_RTC is not set
589# CONFIG_GEN_RTC is not set
590# CONFIG_DTLK is not set
591# CONFIG_R3964 is not set
592# CONFIG_RAW_DRIVER is not set
593
594#
595# TPM devices
596#
597# CONFIG_TCG_TPM is not set
598
599#
600# I2C support
601#
602# CONFIG_I2C is not set
603
604#
605# SPI support
606#
607# CONFIG_SPI is not set
608# CONFIG_SPI_MASTER is not set
609
610#
611# Dallas's 1-wire bus
612#
613# CONFIG_W1 is not set
614
615#
616# Hardware Monitoring support
617#
618# CONFIG_HWMON is not set
619# CONFIG_HWMON_VID is not set
620
621#
622# Multimedia devices
623#
624# CONFIG_VIDEO_DEV is not set
625
626#
627# Digital Video Broadcasting Devices
628#
629# CONFIG_DVB is not set
630
631#
632# Graphics support
633#
634# CONFIG_FIRMWARE_EDID is not set
635# CONFIG_FB is not set
636
637#
638# Console display driver support
639#
640# CONFIG_VGA_CONSOLE is not set
641CONFIG_DUMMY_CONSOLE=y
642# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
643
644#
645# Sound
646#
647# CONFIG_SOUND is not set
648
649#
650# HID Devices
651#
652# CONFIG_HID is not set
653
654#
655# USB support
656#
657# CONFIG_USB_ARCH_HAS_HCD is not set
658# CONFIG_USB_ARCH_HAS_OHCI is not set
659# CONFIG_USB_ARCH_HAS_EHCI is not set
660
661#
662# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
663#
664
665#
666# USB Gadget Support
667#
668# CONFIG_USB_GADGET is not set
669
670#
671# MMC/SD Card support
672#
673# CONFIG_MMC is not set
674
675#
676# LED devices
677#
678# CONFIG_NEW_LEDS is not set
679
680#
681# LED drivers
682#
683
684#
685# LED Triggers
686#
687
688#
689# InfiniBand support
690#
691
692#
693# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
694#
695
696#
697# Real Time Clock
698#
699# CONFIG_RTC_CLASS is not set
700
701#
702# DMA Engine support
703#
704# CONFIG_DMA_ENGINE is not set
705
706#
707# DMA Clients
708#
709
710#
711# DMA Devices
712#
713
714#
715# Auxiliary Display support
716#
717
718#
719# Virtualization
720#
721
722#
723# File systems
724#
725CONFIG_EXT2_FS=y
726# CONFIG_EXT2_FS_XATTR is not set
727# CONFIG_EXT2_FS_XIP is not set
728# CONFIG_EXT3_FS is not set
729# CONFIG_EXT4DEV_FS is not set
730# CONFIG_REISERFS_FS is not set
731# CONFIG_JFS_FS is not set
732CONFIG_FS_POSIX_ACL=y
733# CONFIG_XFS_FS is not set
734# CONFIG_GFS2_FS is not set
735# CONFIG_OCFS2_FS is not set
736# CONFIG_MINIX_FS is not set
737# CONFIG_ROMFS_FS is not set
738CONFIG_INOTIFY=y
739CONFIG_INOTIFY_USER=y
740# CONFIG_QUOTA is not set
741CONFIG_DNOTIFY=y
742# CONFIG_AUTOFS_FS is not set
743# CONFIG_AUTOFS4_FS is not set
744CONFIG_FUSE_FS=y
745CONFIG_GENERIC_ACL=y
746
747#
748# CD-ROM/DVD Filesystems
749#
750# CONFIG_ISO9660_FS is not set
751# CONFIG_UDF_FS is not set
752
753#
754# DOS/FAT/NT Filesystems
755#
756# CONFIG_MSDOS_FS is not set
757# CONFIG_VFAT_FS is not set
758# CONFIG_NTFS_FS is not set
759
760#
761# Pseudo filesystems
762#
763CONFIG_PROC_FS=y
764CONFIG_PROC_KCORE=y
765CONFIG_PROC_SYSCTL=y
766CONFIG_SYSFS=y
767CONFIG_TMPFS=y
768CONFIG_TMPFS_POSIX_ACL=y
769# CONFIG_HUGETLB_PAGE is not set
770CONFIG_RAMFS=y
771CONFIG_CONFIGFS_FS=y
772
773#
774# Miscellaneous filesystems
775#
776# CONFIG_ADFS_FS is not set
777# CONFIG_AFFS_FS is not set
778# CONFIG_ECRYPT_FS is not set
779# CONFIG_HFS_FS is not set
780# CONFIG_HFSPLUS_FS is not set
781# CONFIG_BEFS_FS is not set
782# CONFIG_BFS_FS is not set
783# CONFIG_EFS_FS is not set
784# CONFIG_CRAMFS is not set
785# CONFIG_VXFS_FS is not set
786# CONFIG_HPFS_FS is not set
787# CONFIG_QNX4FS_FS is not set
788# CONFIG_SYSV_FS is not set
789# CONFIG_UFS_FS is not set
790
791#
792# Network File Systems
793#
794CONFIG_NFS_FS=y
795# CONFIG_NFS_V3 is not set
796# CONFIG_NFS_V4 is not set
797# CONFIG_NFS_DIRECTIO is not set
798CONFIG_NFSD=y
799# CONFIG_NFSD_V3 is not set
800# CONFIG_NFSD_TCP is not set
801CONFIG_ROOT_NFS=y
802CONFIG_LOCKD=y
803CONFIG_EXPORTFS=y
804CONFIG_NFS_COMMON=y
805CONFIG_SUNRPC=y
806# CONFIG_RPCSEC_GSS_KRB5 is not set
807# CONFIG_RPCSEC_GSS_SPKM3 is not set
808# CONFIG_SMB_FS is not set
809# CONFIG_CIFS is not set
810# CONFIG_NCP_FS is not set
811# CONFIG_CODA_FS is not set
812# CONFIG_AFS_FS is not set
813# CONFIG_9P_FS is not set
814
815#
816# Partition Types
817#
818# CONFIG_PARTITION_ADVANCED is not set
819CONFIG_MSDOS_PARTITION=y
820
821#
822# Native Language Support
823#
824# CONFIG_NLS is not set
825
826#
827# Distributed Lock Manager
828#
829CONFIG_DLM=y
830CONFIG_DLM_TCP=y
831# CONFIG_DLM_SCTP is not set
832# CONFIG_DLM_DEBUG is not set
833
834#
835# Profiling support
836#
837# CONFIG_PROFILING is not set
838
839#
840# Kernel hacking
841#
842CONFIG_TRACE_IRQFLAGS_SUPPORT=y
843# CONFIG_PRINTK_TIME is not set
844CONFIG_ENABLE_MUST_CHECK=y
845# CONFIG_MAGIC_SYSRQ is not set
846# CONFIG_UNUSED_SYMBOLS is not set
847# CONFIG_DEBUG_FS is not set
848# CONFIG_HEADERS_CHECK is not set
849# CONFIG_DEBUG_KERNEL is not set
850CONFIG_LOG_BUF_SHIFT=14
851CONFIG_CROSSCOMPILE=y
852CONFIG_CMDLINE=""
853CONFIG_SYS_SUPPORTS_KGDB=y
854
855#
856# Security options
857#
858CONFIG_KEYS=y
859CONFIG_KEYS_DEBUG_PROC_KEYS=y
860# CONFIG_SECURITY is not set
861
862#
863# Cryptographic options
864#
865CONFIG_CRYPTO=y
866CONFIG_CRYPTO_ALGAPI=y
867CONFIG_CRYPTO_BLKCIPHER=y
868CONFIG_CRYPTO_HASH=y
869CONFIG_CRYPTO_MANAGER=y
870CONFIG_CRYPTO_HMAC=y
871CONFIG_CRYPTO_XCBC=y
872CONFIG_CRYPTO_NULL=y
873CONFIG_CRYPTO_MD4=y
874CONFIG_CRYPTO_MD5=y
875CONFIG_CRYPTO_SHA1=y
876CONFIG_CRYPTO_SHA256=y
877CONFIG_CRYPTO_SHA512=y
878CONFIG_CRYPTO_WP512=y
879CONFIG_CRYPTO_TGR192=y
880CONFIG_CRYPTO_GF128MUL=y
881CONFIG_CRYPTO_ECB=y
882CONFIG_CRYPTO_CBC=y
883CONFIG_CRYPTO_PCBC=y
884CONFIG_CRYPTO_LRW=y
885CONFIG_CRYPTO_DES=y
886CONFIG_CRYPTO_FCRYPT=y
887CONFIG_CRYPTO_BLOWFISH=y
888CONFIG_CRYPTO_TWOFISH=y
889CONFIG_CRYPTO_TWOFISH_COMMON=y
890CONFIG_CRYPTO_SERPENT=y
891CONFIG_CRYPTO_AES=y
892CONFIG_CRYPTO_CAST5=y
893CONFIG_CRYPTO_CAST6=y
894CONFIG_CRYPTO_TEA=y
895CONFIG_CRYPTO_ARC4=y
896CONFIG_CRYPTO_KHAZAD=y
897CONFIG_CRYPTO_ANUBIS=y
898CONFIG_CRYPTO_DEFLATE=y
899CONFIG_CRYPTO_MICHAEL_MIC=y
900CONFIG_CRYPTO_CRC32C=y
901CONFIG_CRYPTO_CAMELLIA=y
902
903#
904# Hardware crypto devices
905#
906
907#
908# Library routines
909#
910CONFIG_BITREVERSE=y
911# CONFIG_CRC_CCITT is not set
912CONFIG_CRC16=y
913CONFIG_CRC32=y
914CONFIG_LIBCRC32C=y
915CONFIG_ZLIB_INFLATE=y
916CONFIG_ZLIB_DEFLATE=y
917CONFIG_PLIST=y
918CONFIG_HAS_IOMEM=y
919CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 0028aef0af9d..cb4ad4f87e89 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_PB1100=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 8a1d5888739c..0d2c945ac81e 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_PB1500=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 5581ad2ca411..2d7df49d191a 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -33,8 +33,6 @@ CONFIG_MIPS_PB1550=y
33# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_G is not set
38# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 821c1cee5639..18996ed7be25 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38CONFIG_PNX8550_JBS=y 36CONFIG_PNX8550_JBS=y
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 0e8bd92b38cf..9bbc09e5b86d 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39CONFIG_PNX8550_STB810=y 37CONFIG_PNX8550_STB810=y
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 703de002e372..5df7cc3ba001 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig
index 20a38526d483..3da990353295 100644
--- a/arch/mips/configs/rbhma4200_defconfig
+++ b/arch/mips/configs/rbhma4200_defconfig
@@ -30,7 +30,6 @@ CONFIG_MIPS=y
30# CONFIG_MIPS_SEAD is not set 30# CONFIG_MIPS_SEAD is not set
31# CONFIG_WR_PPMC is not set 31# CONFIG_WR_PPMC is not set
32# CONFIG_MIPS_SIM is not set 32# CONFIG_MIPS_SIM is not set
33# CONFIG_MOMENCO_OCELOT is not set
34# CONFIG_MIPS_XXS1500 is not set 33# CONFIG_MIPS_XXS1500 is not set
35# CONFIG_PNX8550_JBS is not set 34# CONFIG_PNX8550_JBS is not set
36# CONFIG_PNX8550_STB810 is not set 35# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index 5dbb250f71c7..badf679e3f52 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -20,7 +20,6 @@ CONFIG_ZONE_DMA=y
20# CONFIG_MIPS_SEAD is not set 20# CONFIG_MIPS_SEAD is not set
21# CONFIG_WR_PPMC is not set 21# CONFIG_WR_PPMC is not set
22# CONFIG_MIPS_SIM is not set 22# CONFIG_MIPS_SIM is not set
23# CONFIG_MOMENCO_OCELOT is not set
24# CONFIG_PNX8550_JBS is not set 23# CONFIG_PNX8550_JBS is not set
25# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
26# CONFIG_DDB5477 is not set 25# CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index a5dc5cb97aae..091f41d13ddd 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 98a914092258..21cc7eaae5c5 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 69c08b24c82a..1f0122877731 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -32,8 +32,6 @@ CONFIG_MIPS_SEAD=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index 5d4fc0e4f729..9b2fe199db90 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 1b92b48de051..3e9f41d98ad3 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 5b77c7a5d83a..94511f9dc8f3 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 94a4f94a8b24..0fcb6e52c30d 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index e38bd9b0eadc..f58418c5f1e7 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32CONFIG_WR_PPMC=y 32CONFIG_WR_PPMC=y
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index f342d8c887b8..850d4e8570cb 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index b3b6e58058f6..fee0f9f948b3 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -32,8 +32,6 @@ CONFIG_ZONE_DMA=y
32# CONFIG_WR_PPMC is not set 32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_G is not set
37# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
38# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
39# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile
deleted file mode 100644
index 1df5fe23c642..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for Momentum's Ocelot board.
3#
4
5obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o
6
7obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
deleted file mode 100644
index 2585d9dbda33..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/irq.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51asmlinkage void plat_irq_dispatch(void)
52{
53 unsigned int pending = read_c0_status() & read_c0_cause();
54
55 if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(2);
57 else if (pending & STATUSF_IP3) /* int1 hardware line */
58 do_IRQ(3);
59 else if (pending & STATUSF_IP4) /* int2 hardware line */
60 do_IRQ(4);
61 else if (pending & STATUSF_IP5) /* int3 hardware line */
62 do_IRQ(5);
63 else if (pending & STATUSF_IP6) /* int4 hardware line */
64 do_IRQ(6);
65 else if (pending & STATUSF_IP7) /* cpu timer */
66 do_IRQ(7);
67 else {
68 /*
69 * Now look at the extended interrupts
70 */
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72
73 if (pending & STATUSF_IP8) /* int6 hardware line */
74 do_IRQ(8);
75 else if (pending & STATUSF_IP9) /* int7 hardware line */
76 do_IRQ(9);
77 else if (pending & STATUSF_IP10) /* int8 hardware line */
78 do_IRQ(10);
79 else if (pending & STATUSF_IP11) /* int9 hardware line */
80 do_IRQ(11);
81 }
82}
83
84void __init arch_init_irq(void)
85{
86 /*
87 * Clear all of the interrupts while we change the able around a bit.
88 * int-handler is not on bootstrap
89 */
90 clear_c0_status(ST0_IM);
91 local_irq_disable();
92
93 mips_cpu_irq_init();
94 rm7k_cpu_irq_init();
95}
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
deleted file mode 100644
index 81d9031a5a2a..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * A NS16552 DUART with a 20MHz crystal.
9 *
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
16
17static struct plat_serial8250_port uart8250_data[] = {
18 {
19 .mapbase = 0xe0001020,
20 .irq = 4,
21 .uartclk = 20000000,
22 .iotype = UPIO_MEM,
23 .flags = OCELOT_UART_FLAGS,
24 .regshift = 2,
25 },
26 { },
27};
28
29static struct platform_device uart8250_device = {
30 .name = "serial8250",
31 .id = PLAT8250_DEV_PLATFORM,
32 .dev = {
33 .platform_data = uart8250_data,
34 },
35};
36
37static int __init uart8250_init(void)
38{
39 return platform_device_register(&uart8250_device);
40}
41
42module_init(uart8250_init);
43
44MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
45MODULE_LICENSE("GPL");
46MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
deleted file mode 100644
index 11f02c402b2a..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xe0020000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
27#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
28
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
deleted file mode 100644
index c71c85276c74..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/prom.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/bootmem.h>
14
15#include <asm/addrspace.h>
16#include <asm/bootinfo.h>
17#include <asm/pmon.h>
18
19struct callvectors* debug_vectors;
20
21extern unsigned long gt64120_base;
22
23const char *get_system_type(void)
24{
25 return "Momentum Ocelot";
26}
27
28/* [jsun@junsun.net] PMON passes arguments in C main() style */
29void __init prom_init(void)
30{
31 int argc = fw_arg0;
32 char **arg = (char **) fw_arg1;
33 char **env = (char **) fw_arg2;
34 struct callvectors *cv = (struct callvectors *) fw_arg3;
35 int i;
36
37 /* save the PROM vectors for debugging use */
38 debug_vectors = cv;
39
40 /* arg[0] is "g", the rest is boot parameters */
41 arcs_cmdline[0] = '\0';
42 for (i = 1; i < argc; i++) {
43 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
44 >= sizeof(arcs_cmdline))
45 break;
46 strcat(arcs_cmdline, arg[i]);
47 strcat(arcs_cmdline, " ");
48 }
49
50 mips_machgroup = MACH_GROUP_MOMENCO;
51 mips_machtype = MACH_MOMENCO_OCELOT;
52
53 while (*env) {
54 if (strncmp("gtbase", *env, 6) == 0) {
55 gt64120_base = simple_strtol(*env + strlen("gtbase="),
56 NULL, 16);
57 break;
58 }
59 *env++;
60 }
61
62 debug_vectors->printf("Booting Linux kernel...\n");
63
64 /* All the boards have at least 64MiB. If there's more, we
65 detect and register it later */
66 add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
67}
68
69void __init prom_free_prom_memory(void)
70{
71}
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c
deleted file mode 100644
index 3fd499adf4cf..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/reset.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
deleted file mode 100644
index 98b6fb38096d..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot (CP7000) - board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 *
38 */
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/types.h>
42#include <linux/mm.h>
43#include <linux/swap.h>
44#include <linux/ioport.h>
45#include <linux/sched.h>
46#include <linux/interrupt.h>
47#include <linux/pci.h>
48#include <linux/timex.h>
49#include <linux/vmalloc.h>
50#include <linux/pm.h>
51
52#include <asm/time.h>
53#include <asm/bootinfo.h>
54#include <asm/page.h>
55#include <asm/io.h>
56#include <asm/irq.h>
57#include <asm/pci.h>
58#include <asm/processor.h>
59#include <asm/reboot.h>
60#include <asm/traps.h>
61#include <linux/bootmem.h>
62#include <linux/initrd.h>
63#include <asm/gt64120.h>
64#include "ocelot_pld.h"
65
66unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
67
68/* These functions are used for rebooting or halting the machine*/
69extern void momenco_ocelot_restart(char *command);
70extern void momenco_ocelot_halt(void);
71extern void momenco_ocelot_power_off(void);
72
73extern void momenco_ocelot_irq_setup(void);
74
75static char reset_reason;
76
77#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
78
79static void __init setup_l3cache(unsigned long size);
80
81/* setup code for a handoff from a version 1 PMON 2000 PROM */
82static void PMON_v1_setup(void)
83{
84 /* A wired TLB entry for the GT64120A and the serial port. The
85 GT64120A is going to be hit on every IRQ anyway - there's
86 absolutely no point in letting it be a random TLB entry, as
87 it'll just cause needless churning of the TLB. And we use
88 the other half for the serial port, which is just a PITA
89 otherwise :)
90
91 Device Physical Virtual
92 GT64120 Internal Regs 0x24000000 0xe0000000
93 UARTs (CS2) 0x2d000000 0xe0001000
94 */
95 add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
96
97 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
98 in the CS[012] region. We can't use ioremap() yet. The NVRAM
99 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
100
101 Ocelot PLD (CS0) 0x2c000000 0xe0020000
102 NVRAM 0x2c800000 0xe0030000
103 */
104
105 add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
106
107 /* Relocate the CS3/BootCS region */
108 GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
109
110 /* Relocate CS[012] */
111 GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
112
113 /* Relocate the GT64120A itself... */
114 GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
115 mb();
116 gt64120_base = 0xe0000000;
117
118 /* ...and the PCI0 view of it. */
119 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
120 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
121 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
122 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
123}
124
125/* setup code for a handoff from a version 2 PMON 2000 PROM */
126void PMON_v2_setup()
127{
128 /* A wired TLB entry for the GT64120A and the serial port. The
129 GT64120A is going to be hit on every IRQ anyway - there's
130 absolutely no point in letting it be a random TLB entry, as
131 it'll just cause needless churning of the TLB. And we use
132 the other half for the serial port, which is just a PITA
133 otherwise :)
134
135 Device Physical Virtual
136 GT64120 Internal Regs 0xf4000000 0xe0000000
137 UARTs (CS2) 0xfd000000 0xe0001000
138 */
139 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
140
141 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
142 in the CS[012] region. We can't use ioremap() yet. The NVRAM
143 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
144
145 Ocelot PLD (CS0) 0xfc000000 0xe0020000
146 NVRAM 0xfc800000 0xe0030000
147 */
148 add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
149
150 gt64120_base = 0xe0000000;
151}
152
153void __init plat_mem_setup(void)
154{
155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
156 unsigned int tmpword;
157
158 _machine_restart = momenco_ocelot_restart;
159 _machine_halt = momenco_ocelot_halt;
160 pm_power_off = momenco_ocelot_power_off;
161
162 /*
163 * initrd_start = (unsigned long)ocelot_initrd_start;
164 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
165 * initrd_below_start_ok = 1;
166 */
167
168 /* do handoff reconfiguration */
169 if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
170 PMON_v1_setup();
171 else
172 PMON_v2_setup();
173
174 /* Turn off the Bit-Error LED */
175 OCELOT_PLD_WRITE(0x80, INTCLR);
176
177 /* Relocate all the PCI1 stuff, not that we use it */
178 GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
179 GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
180 GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
181
182 /* Relocate PCI0 I/O and Mem0 */
183 GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
184 GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
185
186 /* Relocate PCI0 Mem1 */
187 GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
188
189 /* For the initial programming, we assume 512MB configuration */
190 /* Relocate the CPU's view of the RAM... */
191 GT_WRITE(GT_SCS10LD_OFS, 0);
192 GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
193 GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
194 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
195
196 GT_WRITE(GT_SCS1LD_OFS, 0xff);
197 GT_WRITE(GT_SCS1HD_OFS, 0x00);
198 GT_WRITE(GT_SCS0LD_OFS, 0);
199 GT_WRITE(GT_SCS0HD_OFS, 0xff);
200 GT_WRITE(GT_SCS3LD_OFS, 0xff);
201 GT_WRITE(GT_SCS3HD_OFS, 0x00);
202 GT_WRITE(GT_SCS2LD_OFS, 0);
203 GT_WRITE(GT_SCS2HD_OFS, 0xff);
204
205 /* ...and the PCI0 view of it. */
206 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
207 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
208 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
209 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
210 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
211 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
212
213 tmpword = OCELOT_PLD_READ(BOARDREV);
214 if (tmpword < 26)
215 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
216 else
217 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
218
219 tmpword = OCELOT_PLD_READ(PLD1_ID);
220 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
221 tmpword = OCELOT_PLD_READ(PLD2_ID);
222 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
223 tmpword = OCELOT_PLD_READ(RESET_STATUS);
224 printk("Reset reason: 0x%x\n", tmpword);
225 reset_reason = tmpword;
226 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
227
228 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
229 printk("Board Status register: 0x%02x\n", tmpword);
230 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
231 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
232 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
233 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
234 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
235
236 if (tmpword&12)
237 l3func((1<<(((tmpword&12) >> 2)+20)));
238
239 switch(tmpword &3) {
240 case 3:
241 /* 512MiB */
242 /* Decoders are allready set -- just add the
243 * appropriate region */
244 add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
245 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
246 break;
247 case 2:
248 /* 256MiB -- two banks of 128MiB */
249 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
250 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
251 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
252
253 GT_WRITE(GT_SCS0HD_OFS, 0x7f);
254 GT_WRITE(GT_SCS2LD_OFS, 0x80);
255 GT_WRITE(GT_SCS2HD_OFS, 0xff);
256
257 /* reconfigure the PCI0 interface view of memory */
258 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
259 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
260 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
261 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
262
263 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
264 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
265 break;
266 case 1:
267 /* 128MiB -- 64MiB per bank */
268 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
269 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
270 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
271
272 GT_WRITE(GT_SCS0HD_OFS, 0x3f);
273 GT_WRITE(GT_SCS2LD_OFS, 0x40);
274 GT_WRITE(GT_SCS2HD_OFS, 0x7f);
275
276 /* reconfigure the PCI0 interface view of memory */
277 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
278 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
279 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
280 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
281
282 /* add the appropriate region */
283 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
284 break;
285 case 0:
286 /* 64MiB */
287 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
288 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
289 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
290
291 GT_WRITE(GT_SCS0HD_OFS, 0x1f);
292 GT_WRITE(GT_SCS2LD_OFS, 0x20);
293 GT_WRITE(GT_SCS2HD_OFS, 0x3f);
294
295 /* reconfigure the PCI0 interface view of memory */
296 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
297 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
298 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
299 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
300
301 break;
302 }
303
304 /* Fix up the DiskOnChip mapping */
305 GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
306}
307
308extern int rm7k_tcache_enabled;
309/*
310 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
311 */
312#define Page_Invalidate_T 0x16
313static void __init setup_l3cache(unsigned long size)
314{
315 int register i;
316 unsigned long tmp;
317
318 printk("Enabling L3 cache...");
319
320 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
321 tmp = GT_READ(GT_CPU_OFS);
322 GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
323
324 /* Enable the L3 cache in the CPU */
325 set_c0_config(1<<12 /* CONF_TE */);
326
327 /* Clear the cache */
328 write_c0_taglo(0);
329 write_c0_taghi(0);
330
331 for (i=0; i < size; i+= 4096) {
332 __asm__ __volatile__ (
333 ".set noreorder\n\t"
334 ".set mips3\n\t"
335 "cache %1, (%0)\n\t"
336 ".set mips0\n\t"
337 ".set reorder"
338 :
339 : "r" (KSEG0ADDR(i)),
340 "i" (Page_Invalidate_T));
341 }
342
343 /* Let the RM7000 MM code know that the tertiary cache is enabled */
344 rm7k_tcache_enabled = 1;
345
346 printk("Done\n");
347}
348
349
350/* This needs to be one of the first initcalls, because no I/O port access
351 can work before this */
352
353static int io_base_ioremap(void)
354{
355 void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
356
357 if (!io_remap_range) {
358 panic("Could not ioremap I/O port range");
359 }
360 set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
361
362 return 0;
363}
364
365module_init(io_base_ioremap);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c58bd3d036f4..8be9f2b9db26 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o 28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
30obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
31obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 30obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
32obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 31obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
33obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 32obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c
deleted file mode 100644
index 99629bd047ce..000000000000
--- a/arch/mips/pci/fixup-ocelot.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/gt64120/momenco_ocelot/pci.c
6 * Board-specific PCI routines for gt64120 controller.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <asm/pci.h>
18
19
20void __devinit pcibios_fixup_bus(struct pci_bus *bus)
21{
22 struct pci_bus *current_bus = bus;
23 struct pci_dev *devices;
24 struct list_head *devices_link;
25 u16 cmd;
26
27 list_for_each(devices_link, &(current_bus->devices)) {
28
29 devices = pci_dev_b(devices_link);
30 if (devices == NULL)
31 continue;
32
33 if (PCI_SLOT(devices->devfn) == 1) {
34 /*
35 * Slot 1 is primary ether port, i82559
36 * we double-check against that assumption
37 */
38 if ((devices->vendor != 0x8086) ||
39 (devices->device != 0x1209)) {
40 panic("pcibios_fixup_bus: found "
41 "unexpected PCI device in slot 1.");
42 }
43 devices->irq = 2; /* irq_nr is 2 for INT0 */
44 } else if (PCI_SLOT(devices->devfn) == 2) {
45 /*
46 * Slot 2 is secondary ether port, i21143
47 * we double-check against that assumption
48 */
49 if ((devices->vendor != 0x1011) ||
50 (devices->device != 0x19)) {
51 panic("galileo_pcibios_fixup_bus: "
52 "found unexpected PCI device in slot 2.");
53 }
54 devices->irq = 3; /* irq_nr is 3 for INT1 */
55 } else if (PCI_SLOT(devices->devfn) == 4) {
56 /* PMC Slot 1 */
57 devices->irq = 8; /* irq_nr is 8 for INT6 */
58 } else if (PCI_SLOT(devices->devfn) == 5) {
59 /* PMC Slot 1 */
60 devices->irq = 9; /* irq_nr is 9 for INT7 */
61 } else {
62 /* We don't have assign interrupts for other devices. */
63 devices->irq = 0xff;
64 }
65
66 /* Assign an interrupt number for the device */
67 bus->ops->write_byte(devices, PCI_INTERRUPT_LINE,
68 devices->irq);
69
70 /* enable master */
71 bus->ops->read_word(devices, PCI_COMMAND, &cmd);
72 cmd |= PCI_COMMAND_MASTER;
73 bus->ops->write_word(devices, PCI_COMMAND, cmd);
74 }
75}
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
deleted file mode 100644
index 1421d34535ef..000000000000
--- a/arch/mips/pci/pci-ocelot.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo Evaluation Boards PCI support.
4 *
5 * The general-purpose functions to read/write and configure the GT64120A's
6 * PCI registers (function names start with pci0 or pci1) are either direct
7 * copies of functions written by Galileo Technology, or are modifications
8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
9 * are Copyright - Galileo Technology.
10 *
11 * Other functions are derived from other MIPS PCI implementations, or were
12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38#include <linux/init.h>
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h>
42#include <linux/slab.h>
43#include <linux/cache.h>
44#include <asm/pci.h>
45#include <asm/io.h>
46#include <asm/gt64120.h>
47
48static inline unsigned int pci0ReadConfigReg(unsigned int offset)
49{
50 unsigned int DataForRegCf8;
51 unsigned int data;
52
53 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
54 (PCI_FUNC(device->devfn) << 8) |
55 (offset & ~0x3)) | 0x80000000;
56 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
57 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
58
59 return data;
60}
61
62static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
63{
64 unsigned int DataForRegCf8;
65
66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
67 (PCI_FUNC(device->devfn) << 8) |
68 (offset & ~0x3)) | 0x80000000;
69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
70 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
71}
72
73static struct resource ocelot_mem_resource = {
74 .start = GT_PCI_MEM_BASE,
75 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1,
76};
77
78static struct resource ocelot_io_resource = {
79 .start = GT_PCI_IO_BASE,
80 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
81};
82
83static struct pci_controller ocelot_pci_controller = {
84 .pci_ops = gt64xxx_pci0_ops,
85 .mem_resource = &ocelot_mem_resource,
86 .io_resource = &ocelot_io_resource,
87};
88
89static int __init ocelot_pcibios_init(void)
90{
91 u32 tmp;
92
93 GT_READ(GT_PCI0_CMD_OFS, &tmp);
94 GT_READ(GT_PCI0_BARE_OFS, &tmp);
95
96 /*
97 * You have to enable bus mastering to configure any other
98 * card on the bus.
99 */
100 tmp = pci0ReadConfigReg(PCI_COMMAND);
101 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
102 pci0WriteConfigReg(PCI_COMMAND, tmp);
103
104 register_pci_controller(&ocelot_pci_controller);
105}
106
107arch_initcall(ocelot_pcibios_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 01:12:13 -0500