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-rw-r--r--arch/cris/arch-v10/drivers/eeprom.c6
-rw-r--r--arch/cris/arch-v10/drivers/i2c.c2
-rw-r--r--arch/cris/arch-v10/kernel/kgdb.c2
-rw-r--r--arch/ia64/hp/common/sba_iommu.c8
-rw-r--r--arch/sh64/lib/dbg.c2
5 files changed, 10 insertions, 10 deletions
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
index 6e1f191a71e3..284ebfda03f0 100644
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ b/arch/cris/arch-v10/drivers/eeprom.c
@@ -1,7 +1,7 @@
1/*!***************************************************************************** 1/*!*****************************************************************************
2*! 2*!
3*! Implements an interface for i2c compatible eeproms to run under linux. 3*! Implements an interface for i2c compatible eeproms to run under Linux.
4*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by 4*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by
5*! Johan.Adolfsson@axis.com 5*! Johan.Adolfsson@axis.com
6*! 6*!
7*! Probing results: 7*! Probing results:
@@ -51,7 +51,7 @@
51*! Revision 1.8 2001/06/15 13:24:29 jonashg 51*! Revision 1.8 2001/06/15 13:24:29 jonashg
52*! * Added verification of pointers from userspace in read and write. 52*! * Added verification of pointers from userspace in read and write.
53*! * Made busy counter volatile. 53*! * Made busy counter volatile.
54*! * Added define for inital write delay. 54*! * Added define for initial write delay.
55*! * Removed warnings by using loff_t instead of unsigned long. 55*! * Removed warnings by using loff_t instead of unsigned long.
56*! 56*!
57*! Revision 1.7 2001/06/14 15:26:54 jonashg 57*! Revision 1.7 2001/06/14 15:26:54 jonashg
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
index 6114596c3b33..092c724a645f 100644
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ b/arch/cris/arch-v10/drivers/i2c.c
@@ -47,7 +47,7 @@
47*! Update Port B register and shadow even when running with hardware support 47*! Update Port B register and shadow even when running with hardware support
48*! to avoid glitches when reading bits 48*! to avoid glitches when reading bits
49*! Never set direction to out in i2c_inbyte 49*! Never set direction to out in i2c_inbyte
50*! Removed incorrect clock togling at end of i2c_inbyte 50*! Removed incorrect clock toggling at end of i2c_inbyte
51*! 51*!
52*! Revision 1.8 2002/08/13 06:31:53 starvik 52*! Revision 1.8 2002/08/13 06:31:53 starvik
53*! Made SDA and SCL line configurable 53*! Made SDA and SCL line configurable
diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c
index 34528da98817..07628a13c6c4 100644
--- a/arch/cris/arch-v10/kernel/kgdb.c
+++ b/arch/cris/arch-v10/kernel/kgdb.c
@@ -33,7 +33,7 @@
33*! 33*!
34*! Revision 1.2 2002/11/19 14:35:24 starvik 34*! Revision 1.2 2002/11/19 14:35:24 starvik
35*! Changes from linux 2.4 35*! Changes from linux 2.4
36*! Changed struct initializer syntax to the currently prefered notation 36*! Changed struct initializer syntax to the currently preferred notation
37*! 37*!
38*! Revision 1.1 2001/12/17 13:59:27 bjornw 38*! Revision 1.1 2001/12/17 13:59:27 bjornw
39*! Initial revision 39*! Initial revision
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index db8e1fcfa047..14691cda05c3 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -75,7 +75,7 @@
75** If a device prefetches beyond the end of a valid pdir entry, it will cause 75** If a device prefetches beyond the end of a valid pdir entry, it will cause
76** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should 76** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
77** disconnect on 4k boundaries and prevent such issues. If the device is 77** disconnect on 4k boundaries and prevent such issues. If the device is
78** particularly agressive, this option will keep the entire pdir valid such 78** particularly aggressive, this option will keep the entire pdir valid such
79** that prefetching will hit a valid address. This could severely impact 79** that prefetching will hit a valid address. This could severely impact
80** error containment, and is therefore off by default. The page that is 80** error containment, and is therefore off by default. The page that is
81** used for spill-over is poisoned, so that should help debugging somewhat. 81** used for spill-over is poisoned, so that should help debugging somewhat.
@@ -258,10 +258,10 @@ static u64 prefetch_spill_page;
258 258
259/* 259/*
260** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up 260** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
261** (or rather not merge) DMA's into managable chunks. 261** (or rather not merge) DMAs into manageable chunks.
262** On parisc, this is more of the software/tuning constraint 262** On parisc, this is more of the software/tuning constraint
263** rather than the HW. I/O MMU allocation alogorithms can be 263** rather than the HW. I/O MMU allocation algorithms can be
264** faster with smaller size is (to some degree). 264** faster with smaller sizes (to some degree).
265*/ 265*/
266#define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size) 266#define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
267 267
diff --git a/arch/sh64/lib/dbg.c b/arch/sh64/lib/dbg.c
index 1326f45f31eb..4310fc87444e 100644
--- a/arch/sh64/lib/dbg.c
+++ b/arch/sh64/lib/dbg.c
@@ -383,7 +383,7 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
383/* ======================================================================= */ 383/* ======================================================================= */
384 384
385/* 385/*
386** Depending on <base> scan the MMU, Data or Instrction side 386** Depending on <base> scan the MMU, Data or Instruction side
387** looking for a valid mapping matching Eaddr & asid. 387** looking for a valid mapping matching Eaddr & asid.
388** Return -1 if not found or the TLB id entry otherwise. 388** Return -1 if not found or the TLB id entry otherwise.
389** Note: it works only for 4k pages! 389** Note: it works only for 4k pages!