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-rw-r--r--arch/arm/Kconfig17
-rw-r--r--arch/arm/Kconfig.debug1
-rw-r--r--arch/arm/boot/dts/atlas6-evb.dts78
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi668
-rw-r--r--arch/arm/configs/multi_v7_defconfig6
-rw-r--r--arch/arm/include/asm/smp_twd.h8
-rw-r--r--arch/arm/include/debug/sirf.S (renamed from arch/arm/mach-prima2/include/mach/uart.h)29
-rw-r--r--arch/arm/kernel/smp_twd.c17
-rw-r--r--arch/arm/mach-highbank/highbank.c5
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c5
-rw-r--r--arch/arm/mach-omap2/timer.c2
-rw-r--r--arch/arm/mach-prima2/Kconfig22
-rw-r--r--arch/arm/mach-prima2/Makefile5
-rw-r--r--arch/arm/mach-prima2/common.c37
-rw-r--r--arch/arm/mach-prima2/common.h4
-rw-r--r--arch/arm/mach-prima2/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/debug-macro.S29
-rw-r--r--arch/arm/mach-prima2/include/mach/entry-macro.S22
-rw-r--r--arch/arm/mach-prima2/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/irqs.h17
-rw-r--r--arch/arm/mach-prima2/include/mach/map.h18
-rw-r--r--arch/arm/mach-prima2/include/mach/timex.h14
-rw-r--r--arch/arm/mach-prima2/include/mach/uncompress.h41
-rw-r--r--arch/arm/mach-prima2/irq.c129
-rw-r--r--arch/arm/mach-prima2/lluart.c14
-rw-r--r--arch/arm/mach-prima2/platsmp.c1
-rw-r--r--arch/arm/mach-prima2/timer-marco.c316
-rw-r--r--arch/arm/mach-prima2/timer-prima2.c241
-rw-r--r--arch/arm/mach-spear/spear13xx.c4
-rw-r--r--arch/arm/mach-ux500/timer.c3
-rw-r--r--arch/arm/mach-vexpress/v2m.c6
31 files changed, 859 insertions, 930 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e2c7ecf0d1ca..6423b587fa23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -49,7 +49,6 @@ config ARM
49 select HAVE_REGS_AND_STACK_ACCESS_API 49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS 50 select HAVE_SYSCALL_TRACEPOINTS
51 select HAVE_UID16 51 select HAVE_UID16
52 select HAVE_VIRT_TO_BUS
53 select KTIME_SCALAR 52 select KTIME_SCALAR
54 select PERF_USE_VMALLOC 53 select PERF_USE_VMALLOC
55 select RTC_LIB 54 select RTC_LIB
@@ -404,21 +403,6 @@ config ARCH_GEMINI
404 help 403 help
405 Support for the Cortina Systems Gemini family SoCs 404 Support for the Cortina Systems Gemini family SoCs
406 405
407config ARCH_SIRF
408 bool "CSR SiRF"
409 select ARCH_REQUIRE_GPIOLIB
410 select AUTO_ZRELADDR
411 select COMMON_CLK
412 select GENERIC_CLOCKEVENTS
413 select GENERIC_IRQ_CHIP
414 select MIGHT_HAVE_CACHE_L2X0
415 select NO_IOPORT
416 select PINCTRL
417 select PINCTRL_SIRF
418 select USE_OF
419 help
420 Support for CSR SiRFprimaII/Marco/Polo platforms
421
422config ARCH_EBSA110 406config ARCH_EBSA110
423 bool "EBSA-110" 407 bool "EBSA-110"
424 select ARCH_USES_GETTIMEOFFSET 408 select ARCH_USES_GETTIMEOFFSET
@@ -1557,6 +1541,7 @@ config HAVE_ARM_ARCH_TIMER
1557config HAVE_ARM_TWD 1541config HAVE_ARM_TWD
1558 bool 1542 bool
1559 depends on SMP 1543 depends on SMP
1544 select CLKSRC_OF if OF
1560 help 1545 help
1561 This options enables support for the ARM timer and watchdog unit 1546 This options enables support for the ARM timer and watchdog unit
1562 1547
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5115ff9e8a2a..fd17127b4188 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -608,6 +608,7 @@ config DEBUG_LL_INCLUDE
608 default "debug/nomadik.S" if DEBUG_NOMADIK_UART 608 default "debug/nomadik.S" if DEBUG_NOMADIK_UART
609 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 609 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
610 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART 610 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
611 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
611 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 612 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
612 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 613 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
613 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ 614 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts
new file mode 100644
index 000000000000..ab042ca8dea1
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6-evb.dts
@@ -0,0 +1,78 @@
1/*
2 * DTS file for CSR SiRFatlas6 Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "atlas6.dtsi"
12
13/ {
14 model = "CSR SiRFatlas6 Evaluation Board";
15 compatible = "sirf,atlas6-cb", "sirf,atlas6";
16
17 memory {
18 reg = <0x00000000 0x20000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart@b0060000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins_a>;
26 };
27 spi@b00d0000 {
28 status = "okay";
29 pinctrl-names = "default";
30 pinctrl-0 = <&spi0_pins_a>;
31 spi@0 {
32 compatible = "spidev";
33 reg = <0>;
34 spi-max-frequency = <1000000>;
35 };
36 };
37 spi@b0170000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi1_pins_a>;
40 };
41 i2c0: i2c@b00e0000 {
42 status = "okay";
43 pinctrl-names = "default";
44 pinctrl-0 = <&i2c0_pins_a>;
45 lcd@40 {
46 compatible = "sirf,lcd";
47 reg = <0x40>;
48 };
49 };
50
51 };
52 disp-iobg {
53 lcd@90010000 {
54 status = "okay";
55 pinctrl-names = "default";
56 pinctrl-0 = <&lcd_24pins_a>;
57 };
58 };
59 };
60 display: display@0 {
61 panels {
62 panel0: panel@0 {
63 panel-name = "Innolux TFT";
64 hactive = <800>;
65 vactive = <480>;
66 left_margin = <20>;
67 right_margin = <234>;
68 upper_margin = <3>;
69 lower_margin = <41>;
70 hsync_len = <3>;
71 vsync_len = <2>;
72 pixclock = <33264000>;
73 sync = <3>;
74 timing = <0x88>;
75 };
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
new file mode 100644
index 000000000000..7d1a27949c13
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -0,0 +1,668 @@
1/*
2 * DTS file for CSR SiRFatlas6 SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas6";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
30 };
31 };
32
33 axi {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges = <0x40000000 0x40000000 0x80000000>;
38
39 intc: interrupt-controller@80020000 {
40 #interrupt-cells = <1>;
41 interrupt-controller;
42 compatible = "sirf,prima2-intc";
43 reg = <0x80020000 0x1000>;
44 };
45
46 sys-iobg {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges = <0x88000000 0x88000000 0x40000>;
51
52 clks: clock-controller@88000000 {
53 compatible = "sirf,atlas6-clkc";
54 reg = <0x88000000 0x1000>;
55 interrupts = <3>;
56 #clock-cells = <1>;
57 };
58
59 reset-controller@88010000 {
60 compatible = "sirf,prima2-rstc";
61 reg = <0x88010000 0x1000>;
62 };
63
64 rsc-controller@88020000 {
65 compatible = "sirf,prima2-rsc";
66 reg = <0x88020000 0x1000>;
67 };
68 };
69
70 mem-iobg {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0x90000000 0x90000000 0x10000>;
75
76 memory-controller@90000000 {
77 compatible = "sirf,prima2-memc";
78 reg = <0x90000000 0x10000>;
79 interrupts = <27>;
80 clocks = <&clks 5>;
81 };
82 };
83
84 disp-iobg {
85 compatible = "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges = <0x90010000 0x90010000 0x30000>;
89
90 lcd@90010000 {
91 compatible = "sirf,prima2-lcd";
92 reg = <0x90010000 0x20000>;
93 interrupts = <30>;
94 clocks = <&clks 34>;
95 display=<&display>;
96 /* later transfer to pwm */
97 bl-gpio = <&gpio 7 0>;
98 default-panel = <&panel0>;
99 };
100
101 vpp@90020000 {
102 compatible = "sirf,prima2-vpp";
103 reg = <0x90020000 0x10000>;
104 interrupts = <31>;
105 clocks = <&clks 35>;
106 };
107 };
108
109 graphics-iobg {
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 ranges = <0x98000000 0x98000000 0x8000000>;
114
115 graphics@98000000 {
116 compatible = "powervr,sgx510";
117 reg = <0x98000000 0x8000000>;
118 interrupts = <6>;
119 clocks = <&clks 32>;
120 };
121 };
122
123 dsp-iobg {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0xa8000000 0xa8000000 0x2000000>;
128
129 dspif@a8000000 {
130 compatible = "sirf,prima2-dspif";
131 reg = <0xa8000000 0x10000>;
132 interrupts = <9>;
133 };
134
135 gps@a8010000 {
136 compatible = "sirf,prima2-gps";
137 reg = <0xa8010000 0x10000>;
138 interrupts = <7>;
139 clocks = <&clks 9>;
140 };
141
142 dsp@a9000000 {
143 compatible = "sirf,prima2-dsp";
144 reg = <0xa9000000 0x1000000>;
145 interrupts = <8>;
146 clocks = <&clks 8>;
147 };
148 };
149
150 peri-iobg {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0xb0000000 0xb0000000 0x180000>,
155 <0x56000000 0x56000000 0x1b00000>;
156
157 timer@b0020000 {
158 compatible = "sirf,prima2-tick";
159 reg = <0xb0020000 0x1000>;
160 interrupts = <0>;
161 };
162
163 nand@b0030000 {
164 compatible = "sirf,prima2-nand";
165 reg = <0xb0030000 0x10000>;
166 interrupts = <41>;
167 clocks = <&clks 26>;
168 };
169
170 audio@b0040000 {
171 compatible = "sirf,prima2-audio";
172 reg = <0xb0040000 0x10000>;
173 interrupts = <35>;
174 clocks = <&clks 27>;
175 };
176
177 uart0: uart@b0050000 {
178 cell-index = <0>;
179 compatible = "sirf,prima2-uart";
180 reg = <0xb0050000 0x1000>;
181 interrupts = <17>;
182 fifosize = <128>;
183 clocks = <&clks 13>;
184 };
185
186 uart1: uart@b0060000 {
187 cell-index = <1>;
188 compatible = "sirf,prima2-uart";
189 reg = <0xb0060000 0x1000>;
190 interrupts = <18>;
191 fifosize = <32>;
192 clocks = <&clks 14>;
193 };
194
195 uart2: uart@b0070000 {
196 cell-index = <2>;
197 compatible = "sirf,prima2-uart";
198 reg = <0xb0070000 0x1000>;
199 interrupts = <19>;
200 fifosize = <128>;
201 clocks = <&clks 15>;
202 };
203
204 usp0: usp@b0080000 {
205 cell-index = <0>;
206 compatible = "sirf,prima2-usp";
207 reg = <0xb0080000 0x10000>;
208 interrupts = <20>;
209 clocks = <&clks 28>;
210 };
211
212 usp1: usp@b0090000 {
213 cell-index = <1>;
214 compatible = "sirf,prima2-usp";
215 reg = <0xb0090000 0x10000>;
216 interrupts = <21>;
217 clocks = <&clks 29>;
218 };
219
220 dmac0: dma-controller@b00b0000 {
221 cell-index = <0>;
222 compatible = "sirf,prima2-dmac";
223 reg = <0xb00b0000 0x10000>;
224 interrupts = <12>;
225 clocks = <&clks 24>;
226 };
227
228 dmac1: dma-controller@b0160000 {
229 cell-index = <1>;
230 compatible = "sirf,prima2-dmac";
231 reg = <0xb0160000 0x10000>;
232 interrupts = <13>;
233 clocks = <&clks 25>;
234 };
235
236 vip@b00C0000 {
237 compatible = "sirf,prima2-vip";
238 reg = <0xb00C0000 0x10000>;
239 clocks = <&clks 31>;
240 };
241
242 spi0: spi@b00d0000 {
243 cell-index = <0>;
244 compatible = "sirf,prima2-spi";
245 reg = <0xb00d0000 0x10000>;
246 interrupts = <15>;
247 sirf,spi-num-chipselects = <1>;
248 cs-gpios = <&gpio 0 0>;
249 sirf,spi-dma-rx-channel = <25>;
250 sirf,spi-dma-tx-channel = <20>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 clocks = <&clks 19>;
254 status = "disabled";
255 };
256
257 spi1: spi@b0170000 {
258 cell-index = <1>;
259 compatible = "sirf,prima2-spi";
260 reg = <0xb0170000 0x10000>;
261 interrupts = <16>;
262 clocks = <&clks 20>;
263 status = "disabled";
264 };
265
266 i2c0: i2c@b00e0000 {
267 cell-index = <0>;
268 compatible = "sirf,prima2-i2c";
269 reg = <0xb00e0000 0x10000>;
270 interrupts = <24>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 clocks = <&clks 17>;
274 };
275
276 i2c1: i2c@b00f0000 {
277 cell-index = <1>;
278 compatible = "sirf,prima2-i2c";
279 reg = <0xb00f0000 0x10000>;
280 interrupts = <25>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clocks = <&clks 18>;
284 };
285
286 tsc@b0110000 {
287 compatible = "sirf,prima2-tsc";
288 reg = <0xb0110000 0x10000>;
289 interrupts = <33>;
290 clocks = <&clks 16>;
291 };
292
293 gpio: pinctrl@b0120000 {
294 #gpio-cells = <2>;
295 #interrupt-cells = <2>;
296 compatible = "sirf,atlas6-pinctrl";
297 reg = <0xb0120000 0x10000>;
298 interrupts = <43 44 45 46 47>;
299 gpio-controller;
300 interrupt-controller;
301
302 lcd_16pins_a: lcd0@0 {
303 lcd {
304 sirf,pins = "lcd_16bitsgrp";
305 sirf,function = "lcd_16bits";
306 };
307 };
308 lcd_18pins_a: lcd0@1 {
309 lcd {
310 sirf,pins = "lcd_18bitsgrp";
311 sirf,function = "lcd_18bits";
312 };
313 };
314 lcd_24pins_a: lcd0@2 {
315 lcd {
316 sirf,pins = "lcd_24bitsgrp";
317 sirf,function = "lcd_24bits";
318 };
319 };
320 lcdrom_pins_a: lcdrom0@0 {
321 lcd {
322 sirf,pins = "lcdromgrp";
323 sirf,function = "lcdrom";
324 };
325 };
326 uart0_pins_a: uart0@0 {
327 uart {
328 sirf,pins = "uart0grp";
329 sirf,function = "uart0";
330 };
331 };
332 uart1_pins_a: uart1@0 {
333 uart {
334 sirf,pins = "uart1grp";
335 sirf,function = "uart1";
336 };
337 };
338 uart2_pins_a: uart2@0 {
339 uart {
340 sirf,pins = "uart2grp";
341 sirf,function = "uart2";
342 };
343 };
344 uart2_noflow_pins_a: uart2@1 {
345 uart {
346 sirf,pins = "uart2_nostreamctrlgrp";
347 sirf,function = "uart2_nostreamctrl";
348 };
349 };
350 spi0_pins_a: spi0@0 {
351 spi {
352 sirf,pins = "spi0grp";
353 sirf,function = "spi0";
354 };
355 };
356 spi1_pins_a: spi1@0 {
357 spi {
358 sirf,pins = "spi1grp";
359 sirf,function = "spi1";
360 };
361 };
362 i2c0_pins_a: i2c0@0 {
363 i2c {
364 sirf,pins = "i2c0grp";
365 sirf,function = "i2c0";
366 };
367 };
368 i2c1_pins_a: i2c1@0 {
369 i2c {
370 sirf,pins = "i2c1grp";
371 sirf,function = "i2c1";
372 };
373 };
374 pwm0_pins_a: pwm0@0 {
375 pwm {
376 sirf,pins = "pwm0grp";
377 sirf,function = "pwm0";
378 };
379 };
380 pwm1_pins_a: pwm1@0 {
381 pwm {
382 sirf,pins = "pwm1grp";
383 sirf,function = "pwm1";
384 };
385 };
386 pwm2_pins_a: pwm2@0 {
387 pwm {
388 sirf,pins = "pwm2grp";
389 sirf,function = "pwm2";
390 };
391 };
392 pwm3_pins_a: pwm3@0 {
393 pwm {
394 sirf,pins = "pwm3grp";
395 sirf,function = "pwm3";
396 };
397 };
398 pwm4_pins_a: pwm4@0 {
399 pwm {
400 sirf,pins = "pwm4grp";
401 sirf,function = "pwm4";
402 };
403 };
404 gps_pins_a: gps@0 {
405 gps {
406 sirf,pins = "gpsgrp";
407 sirf,function = "gps";
408 };
409 };
410 vip_pins_a: vip@0 {
411 vip {
412 sirf,pins = "vipgrp";
413 sirf,function = "vip";
414 };
415 };
416 sdmmc0_pins_a: sdmmc0@0 {
417 sdmmc0 {
418 sirf,pins = "sdmmc0grp";
419 sirf,function = "sdmmc0";
420 };
421 };
422 sdmmc1_pins_a: sdmmc1@0 {
423 sdmmc1 {
424 sirf,pins = "sdmmc1grp";
425 sirf,function = "sdmmc1";
426 };
427 };
428 sdmmc2_pins_a: sdmmc2@0 {
429 sdmmc2 {
430 sirf,pins = "sdmmc2grp";
431 sirf,function = "sdmmc2";
432 };
433 };
434 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
435 sdmmc2_nowp {
436 sirf,pins = "sdmmc2_nowpgrp";
437 sirf,function = "sdmmc2_nowp";
438 };
439 };
440 sdmmc3_pins_a: sdmmc3@0 {
441 sdmmc3 {
442 sirf,pins = "sdmmc3grp";
443 sirf,function = "sdmmc3";
444 };
445 };
446 sdmmc5_pins_a: sdmmc5@0 {
447 sdmmc5 {
448 sirf,pins = "sdmmc5grp";
449 sirf,function = "sdmmc5";
450 };
451 };
452 i2s_pins_a: i2s@0 {
453 i2s {
454 sirf,pins = "i2sgrp";
455 sirf,function = "i2s";
456 };
457 };
458 i2s_no_din_pins_a: i2s_no_din@0 {
459 i2s_no_din {
460 sirf,pins = "i2s_no_dingrp";
461 sirf,function = "i2s_no_din";
462 };
463 };
464 i2s_6chn_pins_a: i2s_6chn@0 {
465 i2s_6chn {
466 sirf,pins = "i2s_6chngrp";
467 sirf,function = "i2s_6chn";
468 };
469 };
470 ac97_pins_a: ac97@0 {
471 ac97 {
472 sirf,pins = "ac97grp";
473 sirf,function = "ac97";
474 };
475 };
476 nand_pins_a: nand@0 {
477 nand {
478 sirf,pins = "nandgrp";
479 sirf,function = "nand";
480 };
481 };
482 usp0_pins_a: usp0@0 {
483 usp0 {
484 sirf,pins = "usp0grp";
485 sirf,function = "usp0";
486 };
487 };
488 usp1_pins_a: usp1@0 {
489 usp1 {
490 sirf,pins = "usp1grp";
491 sirf,function = "usp1";
492 };
493 };
494 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
495 usb0_upli_drvbus {
496 sirf,pins = "usb0_upli_drvbusgrp";
497 sirf,function = "usb0_upli_drvbus";
498 };
499 };
500 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
501 usb1_utmi_drvbus {
502 sirf,pins = "usb1_utmi_drvbusgrp";
503 sirf,function = "usb1_utmi_drvbus";
504 };
505 };
506 warm_rst_pins_a: warm_rst@0 {
507 warm_rst {
508 sirf,pins = "warm_rstgrp";
509 sirf,function = "warm_rst";
510 };
511 };
512 pulse_count_pins_a: pulse_count@0 {
513 pulse_count {
514 sirf,pins = "pulse_countgrp";
515 sirf,function = "pulse_count";
516 };
517 };
518 cko0_rst_pins_a: cko0_rst@0 {
519 cko0_rst {
520 sirf,pins = "cko0_rstgrp";
521 sirf,function = "cko0_rst";
522 };
523 };
524 cko1_rst_pins_a: cko1_rst@0 {
525 cko1_rst {
526 sirf,pins = "cko1_rstgrp";
527 sirf,function = "cko1_rst";
528 };
529 };
530 };
531
532 pwm@b0130000 {
533 compatible = "sirf,prima2-pwm";
534 reg = <0xb0130000 0x10000>;
535 clocks = <&clks 21>;
536 };
537
538 efusesys@b0140000 {
539 compatible = "sirf,prima2-efuse";
540 reg = <0xb0140000 0x10000>;
541 clocks = <&clks 22>;
542 };
543
544 pulsec@b0150000 {
545 compatible = "sirf,prima2-pulsec";
546 reg = <0xb0150000 0x10000>;
547 interrupts = <48>;
548 clocks = <&clks 23>;
549 };
550
551 pci-iobg {
552 compatible = "sirf,prima2-pciiobg", "simple-bus";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges = <0x56000000 0x56000000 0x1b00000>;
556
557 sd0: sdhci@56000000 {
558 cell-index = <0>;
559 compatible = "sirf,prima2-sdhc";
560 reg = <0x56000000 0x100000>;
561 interrupts = <38>;
562 bus-width = <8>;
563 clocks = <&clks 36>;
564 };
565
566 sd1: sdhci@56100000 {
567 cell-index = <1>;
568 compatible = "sirf,prima2-sdhc";
569 reg = <0x56100000 0x100000>;
570 interrupts = <38>;
571 status = "disabled";
572 clocks = <&clks 36>;
573 };
574
575 sd2: sdhci@56200000 {
576 cell-index = <2>;
577 compatible = "sirf,prima2-sdhc";
578 reg = <0x56200000 0x100000>;
579 interrupts = <23>;
580 status = "disabled";
581 clocks = <&clks 37>;
582 };
583
584 sd3: sdhci@56300000 {
585 cell-index = <3>;
586 compatible = "sirf,prima2-sdhc";
587 reg = <0x56300000 0x100000>;
588 interrupts = <23>;
589 status = "disabled";
590 clocks = <&clks 37>;
591 };
592
593 sd5: sdhci@56500000 {
594 cell-index = <5>;
595 compatible = "sirf,prima2-sdhc";
596 reg = <0x56500000 0x100000>;
597 interrupts = <39>;
598 status = "disabled";
599 clocks = <&clks 38>;
600 };
601
602 pci-copy@57900000 {
603 compatible = "sirf,prima2-pcicp";
604 reg = <0x57900000 0x100000>;
605 interrupts = <40>;
606 };
607
608 rom-interface@57a00000 {
609 compatible = "sirf,prima2-romif";
610 reg = <0x57a00000 0x100000>;
611 };
612 };
613 };
614
615 rtc-iobg {
616 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 reg = <0x80030000 0x10000>;
620
621 gpsrtc@1000 {
622 compatible = "sirf,prima2-gpsrtc";
623 reg = <0x1000 0x1000>;
624 interrupts = <55 56 57>;
625 };
626
627 sysrtc@2000 {
628 compatible = "sirf,prima2-sysrtc";
629 reg = <0x2000 0x1000>;
630 interrupts = <52 53 54>;
631 };
632
633 pwrc@3000 {
634 compatible = "sirf,prima2-pwrc";
635 reg = <0x3000 0x1000>;
636 interrupts = <32>;
637 };
638 };
639
640 uus-iobg {
641 compatible = "simple-bus";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0xb8000000 0xb8000000 0x40000>;
645
646 usb0: usb@b00e0000 {
647 compatible = "chipidea,ci13611a-prima2";
648 reg = <0xb8000000 0x10000>;
649 interrupts = <10>;
650 clocks = <&clks 40>;
651 };
652
653 usb1: usb@b00f0000 {
654 compatible = "chipidea,ci13611a-prima2";
655 reg = <0xb8010000 0x10000>;
656 interrupts = <11>;
657 clocks = <&clks 41>;
658 };
659
660 security@b00f0000 {
661 compatible = "sirf,prima2-security";
662 reg = <0xb8030000 0x10000>;
663 interrupts = <42>;
664 clocks = <&clks 7>;
665 };
666 };
667 };
668};
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 3bf0c543216a..e3f2f6a5709b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -3,6 +3,7 @@ CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y 3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_ARCH_MVEBU=y 4CONFIG_ARCH_MVEBU=y
5CONFIG_MACH_ARMADA_370=y 5CONFIG_MACH_ARMADA_370=y
6CONFIG_ARCH_SIRF=y
6CONFIG_MACH_ARMADA_XP=y 7CONFIG_MACH_ARMADA_XP=y
7CONFIG_ARCH_HIGHBANK=y 8CONFIG_ARCH_HIGHBANK=y
8CONFIG_ARCH_SOCFPGA=y 9CONFIG_ARCH_SOCFPGA=y
@@ -40,12 +41,16 @@ CONFIG_KEYBOARD_SPEAR=y
40CONFIG_SERIAL_AMBA_PL011=y 41CONFIG_SERIAL_AMBA_PL011=y
41CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 42CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
42CONFIG_SERIAL_OF_PLATFORM=y 43CONFIG_SERIAL_OF_PLATFORM=y
44CONFIG_SERIAL_SIRFSOC=y
45CONFIG_SERIAL_SIRFSOC_CONSOLE=y
43CONFIG_IPMI_HANDLER=y 46CONFIG_IPMI_HANDLER=y
44CONFIG_IPMI_SI=y 47CONFIG_IPMI_SI=y
45CONFIG_I2C=y 48CONFIG_I2C=y
46CONFIG_I2C_DESIGNWARE_PLATFORM=y 49CONFIG_I2C_DESIGNWARE_PLATFORM=y
50CONFIG_I2C_SIRF=y
47CONFIG_SPI=y 51CONFIG_SPI=y
48CONFIG_SPI_PL022=y 52CONFIG_SPI_PL022=y
53CONFIG_SPI_SIRF=y
49CONFIG_GPIO_PL061=y 54CONFIG_GPIO_PL061=y
50CONFIG_FB=y 55CONFIG_FB=y
51CONFIG_FB_ARMCLCD=y 56CONFIG_FB_ARMCLCD=y
@@ -66,4 +71,5 @@ CONFIG_RTC_CLASS=y
66CONFIG_RTC_DRV_PL031=y 71CONFIG_RTC_DRV_PL031=y
67CONFIG_DMADEVICES=y 72CONFIG_DMADEVICES=y
68CONFIG_PL330_DMA=y 73CONFIG_PL330_DMA=y
74CONFIG_SIRF_DMA=y
69CONFIG_DW_DMAC=y 75CONFIG_DW_DMAC=y
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 0f01f4677bd2..7b2899c2f7fc 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \
34 34
35int twd_local_timer_register(struct twd_local_timer *); 35int twd_local_timer_register(struct twd_local_timer *);
36 36
37#ifdef CONFIG_HAVE_ARM_TWD
38void twd_local_timer_of_register(void);
39#else
40static inline void twd_local_timer_of_register(void)
41{
42}
43#endif
44
45#endif 37#endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/include/debug/sirf.S
index c10510d01a44..dbf250cf18e6 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/include/debug/sirf.S
@@ -1,15 +1,11 @@
1/* 1/*
2 * arch/arm/mach-prima2/include/mach/uart.h 2 * arch/arm/mach-prima2/include/mach/debug-macro.S
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 * 5 *
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
10#define __MACH_PRIMA2_SIRFSOC_UART_H
11
12/* UART-1: used as serial debug port */
13#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) 9#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
14#define SIRFSOC_UART1_PA_BASE 0xb0060000 10#define SIRFSOC_UART1_PA_BASE 0xb0060000
15#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) 11#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
@@ -17,8 +13,8 @@
17#else 13#else
18#define SIRFSOC_UART1_PA_BASE 0 14#define SIRFSOC_UART1_PA_BASE 0
19#endif 15#endif
20#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) 16
21#define SIRFSOC_UART1_SIZE SZ_4K 17#define SIRFSOC_UART1_VA_BASE 0xFEC60000
22 18
23#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 19#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
24#define SIRFSOC_UART_TXFIFO_DATA 0x0118 20#define SIRFSOC_UART_TXFIFO_DATA 0x0118
@@ -26,4 +22,21 @@
26#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) 22#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
27#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) 23#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
28 24
29#endif 25 .macro addruart, rp, rv, tmp
26 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
27 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
28 .endm
29
30 .macro senduart,rd,rx
31 str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
32 .endm
33
34 .macro busyuart,rd,rx
35 .endm
36
37 .macro waituart,rd,rx
381001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
39 tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
40 beq 1001b
41 .endm
42
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 3f2565037480..90525d9d290b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
362} 362}
363 363
364#ifdef CONFIG_OF 364#ifdef CONFIG_OF
365const static struct of_device_id twd_of_match[] __initconst = { 365static void __init twd_local_timer_of_register(struct device_node *np)
366 { .compatible = "arm,cortex-a9-twd-timer", },
367 { .compatible = "arm,cortex-a5-twd-timer", },
368 { .compatible = "arm,arm11mp-twd-timer", },
369 { },
370};
371
372void __init twd_local_timer_of_register(void)
373{ 366{
374 struct device_node *np;
375 int err; 367 int err;
376 368
377 if (!is_smp() || !setup_max_cpus) 369 if (!is_smp() || !setup_max_cpus)
378 return; 370 return;
379 371
380 np = of_find_matching_node(NULL, twd_of_match);
381 if (!np)
382 return;
383
384 twd_ppi = irq_of_parse_and_map(np, 0); 372 twd_ppi = irq_of_parse_and_map(np, 0);
385 if (!twd_ppi) { 373 if (!twd_ppi) {
386 err = -EINVAL; 374 err = -EINVAL;
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
398out: 386out:
399 WARN(err, "twd_local_timer_of_register failed (%d)\n", err); 387 WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
400} 388}
389CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
390CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
391CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
401#endif 392#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index a4f9f50247d4..76c1170b3528 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -32,7 +32,6 @@
32#include <asm/cacheflush.h> 32#include <asm/cacheflush.h>
33#include <asm/cputype.h> 33#include <asm/cputype.h>
34#include <asm/smp_plat.h> 34#include <asm/smp_plat.h>
35#include <asm/smp_twd.h>
36#include <asm/hardware/arm_timer.h> 35#include <asm/hardware/arm_timer.h>
37#include <asm/hardware/timer-sp.h> 36#include <asm/hardware/timer-sp.h>
38#include <asm/hardware/cache-l2x0.h> 37#include <asm/hardware/cache-l2x0.h>
@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void)
119 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 118 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
120 sp804_clockevents_init(timer_base, irq, "timer0"); 119 sp804_clockevents_init(timer_base, irq, "timer0");
121 120
122 twd_local_timer_of_register();
123
124 arch_timer_of_register(); 121 arch_timer_of_register();
125 arch_timer_sched_clock_init(); 122 arch_timer_sched_clock_init();
123
124 clocksource_of_init();
126} 125}
127 126
128static void highbank_power_off(void) 127static void highbank_power_off(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103b27e4..b59ddcb57c78 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clkdev.h> 14#include <linux/clkdev.h>
15#include <linux/clocksource.h>
15#include <linux/cpu.h> 16#include <linux/cpu.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
17#include <linux/export.h> 18#include <linux/export.h>
@@ -28,11 +29,9 @@
28#include <linux/regmap.h> 29#include <linux/regmap.h>
29#include <linux/micrel_phy.h> 30#include <linux/micrel_phy.h>
30#include <linux/mfd/syscon.h> 31#include <linux/mfd/syscon.h>
31#include <asm/smp_twd.h>
32#include <asm/hardware/cache-l2x0.h> 32#include <asm/hardware/cache-l2x0.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <asm/mach/time.h>
36#include <asm/system_misc.h> 35#include <asm/system_misc.h>
37 36
38#include "common.h" 37#include "common.h"
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
292static void __init imx6q_timer_init(void) 291static void __init imx6q_timer_init(void)
293{ 292{
294 mx6q_clocks_init(); 293 mx6q_clocks_init();
295 twd_local_timer_of_register(); 294 clocksource_of_init();
296 imx_print_silicon_rev("i.MX6Q", imx6q_revision()); 295 imx_print_silicon_rev("i.MX6Q", imx6q_revision());
297} 296}
298 297
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2bdd4cf17a8f..4fd80257c73e 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -597,7 +597,7 @@ void __init omap4_local_timer_init(void)
597 int err; 597 int err;
598 598
599 if (of_have_populated_dt()) { 599 if (of_have_populated_dt()) {
600 twd_local_timer_of_register(); 600 clocksource_of_init();
601 return; 601 return;
602 } 602 }
603 603
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 4f7379fe01e2..587c0bd70434 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,6 +1,26 @@
1config ARCH_SIRF
2 bool "CSR SiRF" if ARCH_MULTI_V7
3 select ARCH_REQUIRE_GPIOLIB
4 select GENERIC_CLOCKEVENTS
5 select GENERIC_IRQ_CHIP
6 select MIGHT_HAVE_CACHE_L2X0
7 select NO_IOPORT
8 select PINCTRL
9 select PINCTRL_SIRF
10 help
11 Support for CSR SiRFprimaII/Marco/Polo platforms
12
1if ARCH_SIRF 13if ARCH_SIRF
2 14
3menu "CSR SiRF primaII/Marco/Polo Specific Features" 15menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
16
17config ARCH_ATLAS6
18 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
19 default y
20 select CPU_V7
21 select SIRF_IRQ
22 help
23 Support for CSR SiRFSoC ARM Cortex A9 Platform
4 24
5config ARCH_PRIMA2 25config ARCH_PRIMA2
6 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 26 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index bfe360cbd177..7a6b4a323125 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -4,8 +4,7 @@ obj-y += rtciobrg.o
4obj-$(CONFIG_DEBUG_LL) += lluart.o 4obj-$(CONFIG_DEBUG_LL) += lluart.o
5obj-$(CONFIG_CACHE_L2X0) += l2x0.o 5obj-$(CONFIG_CACHE_L2X0) += l2x0.o
6obj-$(CONFIG_SUSPEND) += pm.o sleep.o 6obj-$(CONFIG_SUSPEND) += pm.o sleep.o
7obj-$(CONFIG_SIRF_IRQ) += irq.o
8obj-$(CONFIG_SMP) += platsmp.o headsmp.o 7obj-$(CONFIG_SMP) += platsmp.o headsmp.o
9obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
10obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o 9
11obj-$(CONFIG_ARCH_MARCO) += timer-marco.o 10CFLAGS_hotplug.o += -march=armv7-a
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 2d57aa479a7b..4f94cd87972a 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -6,6 +6,7 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/clocksource.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/kernel.h> 11#include <linux/kernel.h>
11#include <linux/irqchip.h> 12#include <linux/irqchip.h>
@@ -31,12 +32,38 @@ void __init sirfsoc_init_late(void)
31 sirfsoc_pm_init(); 32 sirfsoc_pm_init();
32} 33}
33 34
35static __init void sirfsoc_init_time(void)
36{
37 /* initialize clocking early, we want to set the OS timer */
38 sirfsoc_of_clk_init();
39 clocksource_of_init();
40}
41
34static __init void sirfsoc_map_io(void) 42static __init void sirfsoc_map_io(void)
35{ 43{
36 sirfsoc_map_lluart(); 44 sirfsoc_map_lluart();
37 sirfsoc_map_scu(); 45 sirfsoc_map_scu();
38} 46}
39 47
48#ifdef CONFIG_ARCH_ATLAS6
49static const char *atlas6_dt_match[] __initdata = {
50 "sirf,atlas6",
51 NULL
52};
53
54DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
55 /* Maintainer: Barry Song <baohua.song@csr.com> */
56 .nr_irqs = 128,
57 .map_io = sirfsoc_map_io,
58 .init_irq = irqchip_init,
59 .init_time = sirfsoc_init_time,
60 .init_machine = sirfsoc_mach_init,
61 .init_late = sirfsoc_init_late,
62 .dt_compat = atlas6_dt_match,
63 .restart = sirfsoc_restart,
64MACHINE_END
65#endif
66
40#ifdef CONFIG_ARCH_PRIMA2 67#ifdef CONFIG_ARCH_PRIMA2
41static const char *prima2_dt_match[] __initdata = { 68static const char *prima2_dt_match[] __initdata = {
42 "sirf,prima2", 69 "sirf,prima2",
@@ -45,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = {
45 72
46DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") 73DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
47 /* Maintainer: Barry Song <baohua.song@csr.com> */ 74 /* Maintainer: Barry Song <baohua.song@csr.com> */
75 .nr_irqs = 128,
48 .map_io = sirfsoc_map_io, 76 .map_io = sirfsoc_map_io,
49 .init_irq = sirfsoc_of_irq_init, 77 .init_irq = irqchip_init,
50 .init_time = sirfsoc_prima2_timer_init, 78 .init_time = sirfsoc_init_time,
51#ifdef CONFIG_MULTI_IRQ_HANDLER
52 .handle_irq = sirfsoc_handle_irq,
53#endif
54 .dma_zone_size = SZ_256M, 79 .dma_zone_size = SZ_256M,
55 .init_machine = sirfsoc_mach_init, 80 .init_machine = sirfsoc_mach_init,
56 .init_late = sirfsoc_init_late, 81 .init_late = sirfsoc_init_late,
@@ -70,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
70 .smp = smp_ops(sirfsoc_smp_ops), 95 .smp = smp_ops(sirfsoc_smp_ops),
71 .map_io = sirfsoc_map_io, 96 .map_io = sirfsoc_map_io,
72 .init_irq = irqchip_init, 97 .init_irq = irqchip_init,
73 .init_time = sirfsoc_marco_timer_init, 98 .init_time = sirfsoc_init_time,
74 .init_machine = sirfsoc_mach_init, 99 .init_machine = sirfsoc_mach_init,
75 .init_late = sirfsoc_init_late, 100 .init_late = sirfsoc_init_late,
76 .dt_compat = marco_dt_match, 101 .dt_compat = marco_dt_match,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index b7c26b62e4a7..81135cd88e54 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -13,8 +13,8 @@
13#include <asm/mach/time.h> 13#include <asm/mach/time.h>
14#include <asm/exception.h> 14#include <asm/exception.h>
15 15
16extern void sirfsoc_prima2_timer_init(void); 16#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL)
17extern void sirfsoc_marco_timer_init(void); 17#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
18 18
19extern struct smp_operations sirfsoc_smp_ops; 19extern struct smp_operations sirfsoc_smp_ops;
20extern void sirfsoc_secondary_startup(void); 20extern void sirfsoc_secondary_startup(void);
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
deleted file mode 100644
index 66932518b1b7..000000000000
--- a/arch/arm/mach-prima2/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/clkdev.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_CLKDEV_H
10#define __MACH_CLKDEV_H
11
12#define __clk_get(clk) ({ 1; })
13#define __clk_put(clk) do { } while (0)
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
deleted file mode 100644
index cd97492bb075..000000000000
--- a/arch/arm/mach-prima2/include/mach/debug-macro.S
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/debug-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10#include <mach/uart.h>
11
12 .macro addruart, rp, rv, tmp
13 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
14 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
15 .endm
16
17 .macro senduart,rd,rx
18 str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
19 .endm
20
21 .macro busyuart,rd,rx
22 .endm
23
24 .macro waituart,rd,rx
251001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
26 tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
27 beq 1001b
28 .endm
29
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
deleted file mode 100644
index 86434e7a5be9..000000000000
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/entry-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10
11#define SIRFSOC_INT_ID 0x38
12
13 .macro get_irqnr_preamble, base, tmp
14 ldr \base, =sirfsoc_intc_base
15 ldr \base, [\base]
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq
20 cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f
21 movges \irqnr, #0
22 .endm
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
deleted file mode 100644
index 105b96964f25..000000000000
--- a/arch/arm/mach-prima2/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/hardware.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_HARDWARE_H__
10#define __MACH_HARDWARE_H__
11
12#include <asm/sizes.h>
13#include <mach/map.h>
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
deleted file mode 100644
index b778a0f248ed..000000000000
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/irqs.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_IRQS_H
10#define __ASM_ARCH_IRQS_H
11
12#define SIRFSOC_INTENAL_IRQ_START 0
13#define SIRFSOC_INTENAL_IRQ_END 127
14#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
15#define NR_IRQS 288
16
17#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
deleted file mode 100644
index 6f243532570c..000000000000
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * memory & I/O static mapping definitions for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_MAP_H__
10#define __MACH_PRIMA2_MAP_H__
11
12#include <linux/const.h>
13
14#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL)
15
16#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
17
18#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
deleted file mode 100644
index d6f98a75e562..000000000000
--- a/arch/arm/mach-prima2/include/mach/timex.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/timex.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_TIMEX_H__
10#define __MACH_TIMEX_H__
11
12#define CLOCK_TICK_RATE 1000000
13
14#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
deleted file mode 100644
index d1513a33709a..000000000000
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/uncompress.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_UNCOMPRESS_H
10#define __ASM_ARCH_UNCOMPRESS_H
11
12#include <linux/io.h>
13#include <mach/hardware.h>
14#include <mach/uart.h>
15
16void arch_decomp_setup(void)
17{
18}
19
20static __inline__ void putc(char c)
21{
22 /*
23 * during kernel decompression, all mappings are flat:
24 * virt_addr == phys_addr
25 */
26 if (!SIRFSOC_UART1_PA_BASE)
27 return;
28
29 while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
30 & SIRFSOC_UART1_TXFIFO_FULL)
31 barrier();
32
33 __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
34}
35
36static inline void flush(void)
37{
38}
39
40#endif
41
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
deleted file mode 100644
index 6c0f3e9c43fb..000000000000
--- a/arch/arm/mach-prima2/irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/irqdomain.h>
15#include <linux/syscore_ops.h>
16#include <asm/mach/irq.h>
17#include <asm/exception.h>
18#include <mach/hardware.h>
19
20#define SIRFSOC_INT_RISC_MASK0 0x0018
21#define SIRFSOC_INT_RISC_MASK1 0x001C
22#define SIRFSOC_INT_RISC_LEVEL0 0x0020
23#define SIRFSOC_INT_RISC_LEVEL1 0x0024
24#define SIRFSOC_INIT_IRQ_ID 0x0038
25
26void __iomem *sirfsoc_intc_base;
27
28static __init void
29sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
30{
31 struct irq_chip_generic *gc;
32 struct irq_chip_type *ct;
33
34 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
35 ct = gc->chip_types;
36
37 ct->chip.irq_mask = irq_gc_mask_clr_bit;
38 ct->chip.irq_unmask = irq_gc_mask_set_bit;
39 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
40
41 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
42}
43
44static __init void sirfsoc_irq_init(void)
45{
46 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
47 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
48 SIRFSOC_INTENAL_IRQ_END + 1 - 32);
49
50 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
51 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
52
53 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
54 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
55}
56
57asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
58{
59 u32 irqstat, irqnr;
60
61 irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
62 irqnr = irqstat & 0xff;
63
64 handle_IRQ(irqnr, regs);
65}
66
67static struct of_device_id intc_ids[] = {
68 { .compatible = "sirf,prima2-intc" },
69 {},
70};
71
72void __init sirfsoc_of_irq_init(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, intc_ids);
77 if (!np)
78 return;
79
80 sirfsoc_intc_base = of_iomap(np, 0);
81 if (!sirfsoc_intc_base)
82 panic("unable to map intc cpu registers\n");
83
84 irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
85 &irq_domain_simple_ops, NULL);
86
87 of_node_put(np);
88
89 sirfsoc_irq_init();
90}
91
92struct sirfsoc_irq_status {
93 u32 mask0;
94 u32 mask1;
95 u32 level0;
96 u32 level1;
97};
98
99static struct sirfsoc_irq_status sirfsoc_irq_st;
100
101static int sirfsoc_irq_suspend(void)
102{
103 sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
104 sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
105 sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
106 sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
107
108 return 0;
109}
110
111static void sirfsoc_irq_resume(void)
112{
113 writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
114 writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
115 writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
116 writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
117}
118
119static struct syscore_ops sirfsoc_irq_syscore_ops = {
120 .suspend = sirfsoc_irq_suspend,
121 .resume = sirfsoc_irq_resume,
122};
123
124static int __init sirfsoc_irq_pm_init(void)
125{
126 register_syscore_ops(&sirfsoc_irq_syscore_ops);
127 return 0;
128}
129device_initcall(sirfsoc_irq_pm_init);
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
index a89f9b3c8cc5..99c0c927ca4a 100644
--- a/arch/arm/mach-prima2/lluart.c
+++ b/arch/arm/mach-prima2/lluart.c
@@ -9,8 +9,18 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <asm/page.h> 10#include <asm/page.h>
11#include <asm/mach/map.h> 11#include <asm/mach/map.h>
12#include <mach/map.h> 12#include "common.h"
13#include <mach/uart.h> 13
14#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
15#define SIRFSOC_UART1_PA_BASE 0xb0060000
16#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
17#define SIRFSOC_UART1_PA_BASE 0xcc060000
18#else
19#define SIRFSOC_UART1_PA_BASE 0
20#endif
21
22#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
23#define SIRFSOC_UART1_SIZE SZ_4K
14 24
15void __init sirfsoc_map_lluart(void) 25void __init sirfsoc_map_lluart(void)
16{ 26{
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 4b788310f6a6..d52e322e616c 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -18,7 +18,6 @@
18#include <asm/smp_scu.h> 18#include <asm/smp_scu.h>
19#include <asm/cacheflush.h> 19#include <asm/cacheflush.h>
20#include <asm/cputype.h> 20#include <asm/cputype.h>
21#include <mach/map.h>
22 21
23#include "common.h" 22#include "common.h"
24 23
diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
deleted file mode 100644
index f4eea2e97eb0..000000000000
--- a/arch/arm/mach-prima2/timer-marco.c
+++ /dev/null
@@ -1,316 +0,0 @@
1/*
2 * System timer for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/clk.h>
16#include <linux/slab.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <asm/sched_clock.h>
21#include <asm/localtimer.h>
22#include <asm/mach/time.h>
23
24#include "common.h"
25
26#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
27#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
28#define SIRFSOC_TIMER_MATCH_0 0x0018
29#define SIRFSOC_TIMER_MATCH_1 0x001c
30#define SIRFSOC_TIMER_COUNTER_0 0x0048
31#define SIRFSOC_TIMER_COUNTER_1 0x004c
32#define SIRFSOC_TIMER_INTR_STATUS 0x0060
33#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
34#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
35#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
36#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
37#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
38#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
39#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
40#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
41
42#define SIRFSOC_TIMER_REG_CNT 6
43
44static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
45 SIRFSOC_TIMER_WATCHDOG_EN,
46 SIRFSOC_TIMER_32COUNTER_0_CTRL,
47 SIRFSOC_TIMER_32COUNTER_1_CTRL,
48 SIRFSOC_TIMER_64COUNTER_CTRL,
49 SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
50 SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
51};
52
53static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
54
55static void __iomem *sirfsoc_timer_base;
56static void __init sirfsoc_of_timer_map(void);
57
58/* disable count and interrupt */
59static inline void sirfsoc_timer_count_disable(int idx)
60{
61 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
62 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
63}
64
65/* enable count and interrupt */
66static inline void sirfsoc_timer_count_enable(int idx)
67{
68 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
69 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
70}
71
72/* timer interrupt handler */
73static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
74{
75 struct clock_event_device *ce = dev_id;
76 int cpu = smp_processor_id();
77
78 /* clear timer interrupt */
79 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
80
81 if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
82 sirfsoc_timer_count_disable(cpu);
83
84 ce->event_handler(ce);
85
86 return IRQ_HANDLED;
87}
88
89/* read 64-bit timer counter */
90static cycle_t sirfsoc_timer_read(struct clocksource *cs)
91{
92 u64 cycles;
93
94 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
95 BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
96
97 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
98 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
99
100 return cycles;
101}
102
103static int sirfsoc_timer_set_next_event(unsigned long delta,
104 struct clock_event_device *ce)
105{
106 int cpu = smp_processor_id();
107
108 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
109 4 * cpu);
110 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
111 4 * cpu);
112
113 /* enable the tick */
114 sirfsoc_timer_count_enable(cpu);
115
116 return 0;
117}
118
119static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
120 struct clock_event_device *ce)
121{
122 switch (mode) {
123 case CLOCK_EVT_MODE_ONESHOT:
124 /* enable in set_next_event */
125 break;
126 default:
127 break;
128 }
129
130 sirfsoc_timer_count_disable(smp_processor_id());
131}
132
133static void sirfsoc_clocksource_suspend(struct clocksource *cs)
134{
135 int i;
136
137 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
138 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
139}
140
141static void sirfsoc_clocksource_resume(struct clocksource *cs)
142{
143 int i;
144
145 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
146 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
147
148 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
149 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
150 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
151 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
152
153 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
154 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
155}
156
157static struct clock_event_device sirfsoc_clockevent = {
158 .name = "sirfsoc_clockevent",
159 .rating = 200,
160 .features = CLOCK_EVT_FEAT_ONESHOT,
161 .set_mode = sirfsoc_timer_set_mode,
162 .set_next_event = sirfsoc_timer_set_next_event,
163};
164
165static struct clocksource sirfsoc_clocksource = {
166 .name = "sirfsoc_clocksource",
167 .rating = 200,
168 .mask = CLOCKSOURCE_MASK(64),
169 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
170 .read = sirfsoc_timer_read,
171 .suspend = sirfsoc_clocksource_suspend,
172 .resume = sirfsoc_clocksource_resume,
173};
174
175static struct irqaction sirfsoc_timer_irq = {
176 .name = "sirfsoc_timer0",
177 .flags = IRQF_TIMER | IRQF_NOBALANCING,
178 .handler = sirfsoc_timer_interrupt,
179 .dev_id = &sirfsoc_clockevent,
180};
181
182#ifdef CONFIG_LOCAL_TIMERS
183
184static struct irqaction sirfsoc_timer1_irq = {
185 .name = "sirfsoc_timer1",
186 .flags = IRQF_TIMER | IRQF_NOBALANCING,
187 .handler = sirfsoc_timer_interrupt,
188};
189
190static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
191{
192 /* Use existing clock_event for cpu 0 */
193 if (!smp_processor_id())
194 return 0;
195
196 ce->irq = sirfsoc_timer1_irq.irq;
197 ce->name = "local_timer";
198 ce->features = sirfsoc_clockevent.features;
199 ce->rating = sirfsoc_clockevent.rating;
200 ce->set_mode = sirfsoc_timer_set_mode;
201 ce->set_next_event = sirfsoc_timer_set_next_event;
202 ce->shift = sirfsoc_clockevent.shift;
203 ce->mult = sirfsoc_clockevent.mult;
204 ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
205 ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
206
207 sirfsoc_timer1_irq.dev_id = ce;
208 BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
209 irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
210
211 clockevents_register_device(ce);
212 return 0;
213}
214
215static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
216{
217 sirfsoc_timer_count_disable(1);
218
219 remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
220}
221
222static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
223 .setup = sirfsoc_local_timer_setup,
224 .stop = sirfsoc_local_timer_stop,
225};
226#endif /* CONFIG_LOCAL_TIMERS */
227
228static void __init sirfsoc_clockevent_init(void)
229{
230 clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
231
232 sirfsoc_clockevent.max_delta_ns =
233 clockevent_delta2ns(-2, &sirfsoc_clockevent);
234 sirfsoc_clockevent.min_delta_ns =
235 clockevent_delta2ns(2, &sirfsoc_clockevent);
236
237 sirfsoc_clockevent.cpumask = cpumask_of(0);
238 clockevents_register_device(&sirfsoc_clockevent);
239#ifdef CONFIG_LOCAL_TIMERS
240 local_timer_register(&sirfsoc_local_timer_ops);
241#endif
242}
243
244/* initialize the kernel jiffy timer source */
245void __init sirfsoc_marco_timer_init(void)
246{
247 unsigned long rate;
248 u32 timer_div;
249 struct clk *clk;
250
251 /* initialize clocking early, we want to set the OS timer */
252 sirfsoc_of_clk_init();
253
254 /* timer's input clock is io clock */
255 clk = clk_get_sys("io", NULL);
256
257 BUG_ON(IS_ERR(clk));
258 rate = clk_get_rate(clk);
259
260 BUG_ON(rate < CLOCK_TICK_RATE);
261 BUG_ON(rate % CLOCK_TICK_RATE);
262
263 sirfsoc_of_timer_map();
264
265 /* Initialize the timer dividers */
266 timer_div = rate / CLOCK_TICK_RATE - 1;
267 writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
268 writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
269 writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
270
271 /* Initialize timer counters to 0 */
272 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
273 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
274 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
275 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
276 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
277 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
278
279 /* Clear all interrupts */
280 writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
281
282 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
283
284 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
285
286 sirfsoc_clockevent_init();
287}
288
289static struct of_device_id timer_ids[] = {
290 { .compatible = "sirf,marco-tick" },
291 {},
292};
293
294static void __init sirfsoc_of_timer_map(void)
295{
296 struct device_node *np;
297
298 np = of_find_matching_node(NULL, timer_ids);
299 if (!np)
300 return;
301 sirfsoc_timer_base = of_iomap(np, 0);
302 if (!sirfsoc_timer_base)
303 panic("unable to map timer cpu registers\n");
304
305 sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
306 if (!sirfsoc_timer_irq.irq)
307 panic("No irq passed for timer0 via DT\n");
308
309#ifdef CONFIG_LOCAL_TIMERS
310 sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
311 if (!sirfsoc_timer1_irq.irq)
312 panic("No irq passed for timer1 via DT\n");
313#endif
314
315 of_node_put(np);
316}
diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c
deleted file mode 100644
index 6da584f8a949..000000000000
--- a/arch/arm/mach-prima2/timer-prima2.c
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * System timer for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <mach/map.h>
21#include <asm/sched_clock.h>
22#include <asm/mach/time.h>
23
24#include "common.h"
25
26#define SIRFSOC_TIMER_COUNTER_LO 0x0000
27#define SIRFSOC_TIMER_COUNTER_HI 0x0004
28#define SIRFSOC_TIMER_MATCH_0 0x0008
29#define SIRFSOC_TIMER_MATCH_1 0x000C
30#define SIRFSOC_TIMER_MATCH_2 0x0010
31#define SIRFSOC_TIMER_MATCH_3 0x0014
32#define SIRFSOC_TIMER_MATCH_4 0x0018
33#define SIRFSOC_TIMER_MATCH_5 0x001C
34#define SIRFSOC_TIMER_STATUS 0x0020
35#define SIRFSOC_TIMER_INT_EN 0x0024
36#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
37#define SIRFSOC_TIMER_DIV 0x002C
38#define SIRFSOC_TIMER_LATCH 0x0030
39#define SIRFSOC_TIMER_LATCHED_LO 0x0034
40#define SIRFSOC_TIMER_LATCHED_HI 0x0038
41
42#define SIRFSOC_TIMER_WDT_INDEX 5
43
44#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
45
46#define SIRFSOC_TIMER_REG_CNT 11
47
48static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
49 SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
50 SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
51 SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
52 SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
53};
54
55static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
56
57static void __iomem *sirfsoc_timer_base;
58static void __init sirfsoc_of_timer_map(void);
59
60/* timer0 interrupt handler */
61static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
62{
63 struct clock_event_device *ce = dev_id;
64
65 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
66
67 /* clear timer0 interrupt */
68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
69
70 ce->event_handler(ce);
71
72 return IRQ_HANDLED;
73}
74
75/* read 64-bit timer counter */
76static cycle_t sirfsoc_timer_read(struct clocksource *cs)
77{
78 u64 cycles;
79
80 /* latch the 64-bit timer counter */
81 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
82 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
83 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
84
85 return cycles;
86}
87
88static int sirfsoc_timer_set_next_event(unsigned long delta,
89 struct clock_event_device *ce)
90{
91 unsigned long now, next;
92
93 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
94 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
95 next = now + delta;
96 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
97 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
98 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
99
100 return next - now > delta ? -ETIME : 0;
101}
102
103static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
104 struct clock_event_device *ce)
105{
106 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
107 switch (mode) {
108 case CLOCK_EVT_MODE_PERIODIC:
109 WARN_ON(1);
110 break;
111 case CLOCK_EVT_MODE_ONESHOT:
112 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
113 break;
114 case CLOCK_EVT_MODE_SHUTDOWN:
115 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
116 break;
117 case CLOCK_EVT_MODE_UNUSED:
118 case CLOCK_EVT_MODE_RESUME:
119 break;
120 }
121}
122
123static void sirfsoc_clocksource_suspend(struct clocksource *cs)
124{
125 int i;
126
127 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
128
129 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
130 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
131}
132
133static void sirfsoc_clocksource_resume(struct clocksource *cs)
134{
135 int i;
136
137 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
138 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
139
140 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
142}
143
144static struct clock_event_device sirfsoc_clockevent = {
145 .name = "sirfsoc_clockevent",
146 .rating = 200,
147 .features = CLOCK_EVT_FEAT_ONESHOT,
148 .set_mode = sirfsoc_timer_set_mode,
149 .set_next_event = sirfsoc_timer_set_next_event,
150};
151
152static struct clocksource sirfsoc_clocksource = {
153 .name = "sirfsoc_clocksource",
154 .rating = 200,
155 .mask = CLOCKSOURCE_MASK(64),
156 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
157 .read = sirfsoc_timer_read,
158 .suspend = sirfsoc_clocksource_suspend,
159 .resume = sirfsoc_clocksource_resume,
160};
161
162static struct irqaction sirfsoc_timer_irq = {
163 .name = "sirfsoc_timer0",
164 .flags = IRQF_TIMER,
165 .irq = 0,
166 .handler = sirfsoc_timer_interrupt,
167 .dev_id = &sirfsoc_clockevent,
168};
169
170/* Overwrite weak default sched_clock with more precise one */
171static u32 notrace sirfsoc_read_sched_clock(void)
172{
173 return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff);
174}
175
176static void __init sirfsoc_clockevent_init(void)
177{
178 sirfsoc_clockevent.cpumask = cpumask_of(0);
179 clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
180 2, -2);
181}
182
183/* initialize the kernel jiffy timer source */
184void __init sirfsoc_prima2_timer_init(void)
185{
186 unsigned long rate;
187 struct clk *clk;
188
189 /* initialize clocking early, we want to set the OS timer */
190 sirfsoc_of_clk_init();
191
192 /* timer's input clock is io clock */
193 clk = clk_get_sys("io", NULL);
194
195 BUG_ON(IS_ERR(clk));
196
197 rate = clk_get_rate(clk);
198
199 BUG_ON(rate < CLOCK_TICK_RATE);
200 BUG_ON(rate % CLOCK_TICK_RATE);
201
202 sirfsoc_of_timer_map();
203
204 writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
205 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
206 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
207 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
208
209 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
210
211 setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE);
212
213 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
214
215 sirfsoc_clockevent_init();
216}
217
218static struct of_device_id timer_ids[] = {
219 { .compatible = "sirf,prima2-tick" },
220 {},
221};
222
223static void __init sirfsoc_of_timer_map(void)
224{
225 struct device_node *np;
226 const unsigned int *intspec;
227
228 np = of_find_matching_node(NULL, timer_ids);
229 if (!np)
230 return;
231 sirfsoc_timer_base = of_iomap(np, 0);
232 if (!sirfsoc_timer_base)
233 panic("unable to map timer cpu registers\n");
234
235 /* Get the interrupts property */
236 intspec = of_get_property(np, "interrupts", NULL);
237 BUG_ON(!intspec);
238 sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
239
240 of_node_put(np);
241}
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 1b97e8623472..6dd208997176 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -15,12 +15,12 @@
15 15
16#include <linux/amba/pl022.h> 16#include <linux/amba/pl022.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/clocksource.h>
18#include <linux/dw_dmac.h> 19#include <linux/dw_dmac.h>
19#include <linux/err.h> 20#include <linux/err.h>
20#include <linux/of.h> 21#include <linux/of.h>
21#include <asm/hardware/cache-l2x0.h> 22#include <asm/hardware/cache-l2x0.h>
22#include <asm/mach/map.h> 23#include <asm/mach/map.h>
23#include <asm/smp_twd.h>
24#include "generic.h" 24#include "generic.h"
25#include <mach/spear.h> 25#include <mach/spear.h>
26 26
@@ -180,5 +180,5 @@ void __init spear13xx_timer_init(void)
180 clk_put(pclk); 180 clk_put(pclk);
181 181
182 spear_setup_of_timer(); 182 spear_setup_of_timer();
183 twd_local_timer_of_register(); 183 clocksource_of_init();
184} 184}
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index a6af0b8732ba..d07bbe7f04a6 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -7,6 +7,7 @@
7#include <linux/io.h> 7#include <linux/io.h>
8#include <linux/errno.h> 8#include <linux/errno.h>
9#include <linux/clksrc-dbx500-prcmu.h> 9#include <linux/clksrc-dbx500-prcmu.h>
10#include <linux/clocksource.h>
10#include <linux/of.h> 11#include <linux/of.h>
11#include <linux/of_address.h> 12#include <linux/of_address.h>
12#include <linux/platform_data/clocksource-nomadik-mtu.h> 13#include <linux/platform_data/clocksource-nomadik-mtu.h>
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void)
32 twd_local_timer = &u8500_twd_local_timer; 33 twd_local_timer = &u8500_twd_local_timer;
33 34
34 if (of_have_populated_dt()) 35 if (of_have_populated_dt())
35 twd_local_timer_of_register(); 36 clocksource_of_init();
36 else { 37 else {
37 err = twd_local_timer_register(twd_local_timer); 38 err = twd_local_timer_register(twd_local_timer);
38 if (err) 39 if (err)
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 915683cb67d6..d0ad78998cb6 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,6 +5,7 @@
5#include <linux/amba/bus.h> 5#include <linux/amba/bus.h>
6#include <linux/amba/mmci.h> 6#include <linux/amba/mmci.h>
7#include <linux/io.h> 7#include <linux/io.h>
8#include <linux/clocksource.h>
8#include <linux/smp.h> 9#include <linux/smp.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/irqchip.h> 11#include <linux/irqchip.h>
@@ -25,7 +26,6 @@
25#include <asm/arch_timer.h> 26#include <asm/arch_timer.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
27#include <asm/sizes.h> 28#include <asm/sizes.h>
28#include <asm/smp_twd.h>
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31#include <asm/mach/time.h> 31#include <asm/mach/time.h>
@@ -435,6 +435,7 @@ static void __init v2m_dt_timer_init(void)
435 435
436 vexpress_clk_of_init(); 436 vexpress_clk_of_init();
437 437
438 clocksource_of_init();
438 do { 439 do {
439 node = of_find_compatible_node(node, NULL, "arm,sp804"); 440 node = of_find_compatible_node(node, NULL, "arm,sp804");
440 } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); 441 } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
@@ -445,8 +446,7 @@ static void __init v2m_dt_timer_init(void)
445 irq_of_parse_and_map(node, 0)); 446 irq_of_parse_and_map(node, 0));
446 } 447 }
447 448
448 if (arch_timer_of_register() != 0) 449 arch_timer_of_register();
449 twd_local_timer_of_register();
450 450
451 if (arch_timer_sched_clock_init() != 0) 451 if (arch_timer_sched_clock_init() != 0)
452 versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 452 versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 08:29:34 -0500