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-rw-r--r--arch/xtensa/mm/mmu.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 5bb8e3c61d85..36ec171698b8 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -13,6 +13,8 @@
13#include <asm/tlbflush.h> 13#include <asm/tlbflush.h>
14#include <asm/mmu_context.h> 14#include <asm/mmu_context.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm/initialize_mmu.h>
17#include <asm/io.h>
16 18
17void __init paging_init(void) 19void __init paging_init(void)
18{ 20{
@@ -37,6 +39,20 @@ void init_mmu(void)
37 set_itlbcfg_register(0); 39 set_itlbcfg_register(0);
38 set_dtlbcfg_register(0); 40 set_dtlbcfg_register(0);
39#endif 41#endif
42#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
43 /*
44 * Update the IO area mapping in case xtensa_kio_paddr has changed
45 */
46 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
47 XCHAL_KIO_CACHED_VADDR + 6);
48 write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
49 XCHAL_KIO_CACHED_VADDR + 6);
50 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
51 XCHAL_KIO_BYPASS_VADDR + 6);
52 write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
53 XCHAL_KIO_BYPASS_VADDR + 6);
54#endif
55
40 local_flush_tlb_all(); 56 local_flush_tlb_all();
41 57
42 /* Set rasid register to a known value. */ 58 /* Set rasid register to a known value. */