4 files changed, 66 insertions, 10 deletions

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index fa5f71e021d5..9c91683ab5e6 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -188,6 +188,9 @@ extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
                                     const char __user *ubuf,
                                     size_t usize, loff_t *off));
 
+/* Disable CMCI/polling for MCA bank claimed by firmware */
+extern void mce_disable_bank(int bank);
+
 /*
  * Exception handler
  */
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index 5b7d4fa5d3b7..09edd0b65fef 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -25,15 +25,18 @@ int mce_severity(struct mce *a, int tolerant, char **msg);
 struct dentry *mce_get_debugfs_dir(void);
 
 extern struct mce_bank *mce_banks;
+extern mce_banks_t mce_banks_ce_disabled;
 
 #ifdef CONFIG_X86_MCE_INTEL
 unsigned long mce_intel_adjust_timer(unsigned long interval);
 void mce_intel_cmci_poll(void);
 void mce_intel_hcpu_update(unsigned long cpu);
+void cmci_disable_bank(int bank);
 #else
 # define mce_intel_adjust_timer mce_adjust_timer_default
 static inline void mce_intel_cmci_poll(void) { }
 static inline void mce_intel_hcpu_update(unsigned long cpu) { }
+static inline void cmci_disable_bank(int bank) { }
 #endif
 
 void mce_timer_kick(unsigned long interval);
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9239504b41cb..5bf32c70a9c0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -94,6 +94,15 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
         [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
 };
 
+/*
+ * MCA banks controlled through firmware first for corrected errors.
+ * This is a global list of banks for which we won't enable CMCI and we
+ * won't poll. Firmware controls these banks and is responsible for
+ * reporting corrected errors through GHES. Uncorrected/recoverable
+ * errors are still notified through a machine check.
+ */
+mce_banks_t mce_banks_ce_disabled;
+
 static DEFINE_PER_CPU(struct work_struct, mce_work);
 
 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
@@ -1932,6 +1941,25 @@ static struct miscdevice mce_chrdev_device = {
         &mce_chrdev_ops,
 };
 
+static void __mce_disable_bank(void *arg)
+{
+        int bank = *((int *)arg);
+        __clear_bit(bank, __get_cpu_var(mce_poll_banks));
+        cmci_disable_bank(bank);
+}
+
+void mce_disable_bank(int bank)
+{
+        if (bank >= mca_cfg.banks) {
+                pr_warn(FW_BUG
+                        "Ignoring request to disable invalid MCA bank %d.\n",
+                        bank);
+                return;
+        }
+        set_bit(bank, mce_banks_ce_disabled);
+        on_each_cpu(__mce_disable_bank, &bank, 1);
+}
+
 /*
  * mce=off Disables machine check
  * mce=no_cmci Disables CMCI
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index ae1697c2afe3..488eae3ec3e2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -191,6 +191,10 @@ static void cmci_discover(int banks)
                 if (test_bit(i, owned))
                         continue;
 
+                /* Skip banks in firmware first mode */
+                if (test_bit(i, mce_banks_ce_disabled))
+                        continue;
+
                 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
 
                 /* Already owned by someone else? */
@@ -259,6 +263,19 @@ void cmci_recheck(void)
         local_irq_restore(flags);
 }
 
+/* Caller must hold the lock on cmci_discover_lock */
+static void __cmci_disable_bank(int bank)
+{
+        u64 val;
+
+        if (!test_bit(bank, __get_cpu_var(mce_banks_owned)))
+                return;
+        rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
+        val &= ~MCI_CTL2_CMCI_EN;
+        wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
+        __clear_bit(bank, __get_cpu_var(mce_banks_owned));
+}
+
 /*
  * Disable CMCI on this CPU for all banks it owns when it goes down.
  * This allows other CPUs to claim the banks on rediscovery.
@@ -268,20 +285,12 @@ void cmci_clear(void)
         unsigned long flags;
         int i;
         int banks;
-        u64 val;
 
         if (!cmci_supported(&banks))
                 return;
         raw_spin_lock_irqsave(&cmci_discover_lock, flags);
-        for (i = 0; i < banks; i++) {
-                if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
-                        continue;
-                /* Disable CMCI */
-                rdmsrl(MSR_IA32_MCx_CTL2(i), val);
-                val &= ~MCI_CTL2_CMCI_EN;
-                wrmsrl(MSR_IA32_MCx_CTL2(i), val);
-                __clear_bit(i, __get_cpu_var(mce_banks_owned));
-        }
+        for (i = 0; i < banks; i++)
+                __cmci_disable_bank(i);
         raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
@@ -315,6 +324,19 @@ void cmci_reenable(void)
                 cmci_discover(banks);
 }
 
+void cmci_disable_bank(int bank)
+{
+        int banks;
+        unsigned long flags;
+
+        if (!cmci_supported(&banks))
+                return;
+
+        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        __cmci_disable_bank(bank);
+        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+}
+
 static void intel_init_cmci(void)
 {
         int banks;