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-rw-r--r--arch/x86/oprofile/nmi_int.c100
-rw-r--r--arch/x86/oprofile/op_counter.h3
-rw-r--r--arch/x86/oprofile/op_model_amd.c76
-rw-r--r--arch/x86/oprofile/op_model_p4.c4
-rw-r--r--arch/x86/oprofile/op_model_ppro.c2
-rw-r--r--arch/x86/oprofile/op_x86_model.h3
6 files changed, 40 insertions, 148 deletions
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 114df508b407..57f6c9088081 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -24,8 +24,6 @@
24#include "op_counter.h" 24#include "op_counter.h"
25#include "op_x86_model.h" 25#include "op_x86_model.h"
26 26
27DEFINE_PER_CPU(int, switch_index);
28
29static struct op_x86_model_spec const *model; 27static struct op_x86_model_spec const *model;
30static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); 28static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
31static DEFINE_PER_CPU(unsigned long, saved_lvtpc); 29static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
@@ -34,8 +32,6 @@ static int nmi_start(void);
34static void nmi_stop(void); 32static void nmi_stop(void);
35static void nmi_cpu_start(void *dummy); 33static void nmi_cpu_start(void *dummy);
36static void nmi_cpu_stop(void *dummy); 34static void nmi_cpu_stop(void *dummy);
37static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs);
38static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs);
39 35
40/* 0 == registered but off, 1 == registered and on */ 36/* 0 == registered but off, 1 == registered and on */
41static int nmi_enabled = 0; 37static int nmi_enabled = 0;
@@ -111,47 +107,6 @@ static void exit_sysfs(void)
111#define exit_sysfs() do { } while (0) 107#define exit_sysfs() do { } while (0)
112#endif /* CONFIG_PM */ 108#endif /* CONFIG_PM */
113 109
114static void nmi_cpu_switch(void *dummy)
115{
116 int cpu = smp_processor_id();
117 int si = per_cpu(switch_index, cpu);
118 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
119
120 nmi_cpu_stop(NULL);
121 nmi_cpu_save_mpx_registers(msrs);
122
123 /* move to next set */
124 si += model->num_hardware_counters;
125 if ((si > model->num_counters) || (counter_config[si].count == 0))
126 per_cpu(switch_index, smp_processor_id()) = 0;
127 else
128 per_cpu(switch_index, smp_processor_id()) = si;
129
130 nmi_cpu_restore_mpx_registers(msrs);
131 model->setup_ctrs(msrs);
132 nmi_cpu_start(NULL);
133}
134
135/*
136 * Quick check to see if multiplexing is necessary.
137 * The check should be sufficient since counters are used
138 * in ordre.
139 */
140static int nmi_multiplex_on(void)
141{
142 return counter_config[model->num_hardware_counters].count ? 0 : -EINVAL;
143}
144
145static int nmi_switch_event(void)
146{
147 if (nmi_multiplex_on() < 0)
148 return -EINVAL;
149
150 on_each_cpu(nmi_cpu_switch, NULL, 1);
151
152 return 0;
153}
154
155static int profile_exceptions_notify(struct notifier_block *self, 110static int profile_exceptions_notify(struct notifier_block *self,
156 unsigned long val, void *data) 111 unsigned long val, void *data)
157{ 112{
@@ -215,10 +170,11 @@ static void free_msrs(void)
215 170
216static int allocate_msrs(void) 171static int allocate_msrs(void)
217{ 172{
218 int i, success = 1; 173 int success = 1;
219 size_t controls_size = sizeof(struct op_msr) * model->num_controls; 174 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
220 size_t counters_size = sizeof(struct op_msr) * model->num_counters; 175 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
221 176
177 int i;
222 for_each_possible_cpu(i) { 178 for_each_possible_cpu(i) {
223 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, 179 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
224 GFP_KERNEL); 180 GFP_KERNEL);
@@ -226,8 +182,8 @@ static int allocate_msrs(void)
226 success = 0; 182 success = 0;
227 break; 183 break;
228 } 184 }
229 per_cpu(cpu_msrs, i).controls = 185 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
230 kmalloc(controls_size, GFP_KERNEL); 186 GFP_KERNEL);
231 if (!per_cpu(cpu_msrs, i).controls) { 187 if (!per_cpu(cpu_msrs, i).controls) {
232 success = 0; 188 success = 0;
233 break; 189 break;
@@ -271,8 +227,7 @@ static int nmi_setup(void)
271 return err; 227 return err;
272 } 228 }
273 229
274 /* 230 /* We need to serialize save and setup for HT because the subset
275 * We need to serialize save and setup for HT because the subset
276 * of msrs are distinct for save and setup operations 231 * of msrs are distinct for save and setup operations
277 */ 232 */
278 233
@@ -288,6 +243,7 @@ static int nmi_setup(void)
288 per_cpu(cpu_msrs, 0).controls, 243 per_cpu(cpu_msrs, 0).controls,
289 sizeof(struct op_msr) * model->num_controls); 244 sizeof(struct op_msr) * model->num_controls);
290 } 245 }
246
291 } 247 }
292 on_each_cpu(nmi_save_registers, NULL, 1); 248 on_each_cpu(nmi_save_registers, NULL, 1);
293 on_each_cpu(nmi_cpu_setup, NULL, 1); 249 on_each_cpu(nmi_cpu_setup, NULL, 1);
@@ -295,41 +251,7 @@ static int nmi_setup(void)
295 return 0; 251 return 0;
296} 252}
297 253
298static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) 254static void nmi_restore_registers(struct op_msrs *msrs)
299{
300 unsigned int si = __get_cpu_var(switch_index);
301 unsigned int const nr_ctrs = model->num_hardware_counters;
302 struct op_msr *counters = &msrs->counters[si];
303 unsigned int i;
304
305 for (i = 0; i < nr_ctrs; ++i) {
306 int offset = i + si;
307 if (counters[offset].addr) {
308 rdmsr(counters[offset].addr,
309 counters[offset].multiplex.low,
310 counters[offset].multiplex.high);
311 }
312 }
313}
314
315static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
316{
317 unsigned int si = __get_cpu_var(switch_index);
318 unsigned int const nr_ctrs = model->num_hardware_counters;
319 struct op_msr *counters = &msrs->counters[si];
320 unsigned int i;
321
322 for (i = 0; i < nr_ctrs; ++i) {
323 int offset = i + si;
324 if (counters[offset].addr) {
325 wrmsr(counters[offset].addr,
326 counters[offset].multiplex.low,
327 counters[offset].multiplex.high);
328 }
329 }
330}
331
332static void nmi_cpu_restore_registers(struct op_msrs *msrs)
333{ 255{
334 unsigned int const nr_ctrs = model->num_counters; 256 unsigned int const nr_ctrs = model->num_counters;
335 unsigned int const nr_ctrls = model->num_controls; 257 unsigned int const nr_ctrls = model->num_controls;
@@ -369,8 +291,7 @@ static void nmi_cpu_shutdown(void *dummy)
369 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 291 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
370 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); 292 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
371 apic_write(APIC_LVTERR, v); 293 apic_write(APIC_LVTERR, v);
372 nmi_cpu_restore_registers(msrs); 294 nmi_restore_registers(msrs);
373 __get_cpu_var(switch_index) = 0;
374} 295}
375 296
376static void nmi_shutdown(void) 297static void nmi_shutdown(void)
@@ -435,7 +356,6 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root)
435 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); 356 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
436 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); 357 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
437 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); 358 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
438 counter_config[i].save_count_low = 0;
439 } 359 }
440 360
441 return 0; 361 return 0;
@@ -580,14 +500,12 @@ int __init op_nmi_init(struct oprofile_operations *ops)
580 register_cpu_notifier(&oprofile_cpu_nb); 500 register_cpu_notifier(&oprofile_cpu_nb);
581#endif 501#endif
582 /* default values, can be overwritten by model */ 502 /* default values, can be overwritten by model */
583 __raw_get_cpu_var(switch_index) = 0;
584 ops->create_files = nmi_create_files; 503 ops->create_files = nmi_create_files;
585 ops->setup = nmi_setup; 504 ops->setup = nmi_setup;
586 ops->shutdown = nmi_shutdown; 505 ops->shutdown = nmi_shutdown;
587 ops->start = nmi_start; 506 ops->start = nmi_start;
588 ops->stop = nmi_stop; 507 ops->stop = nmi_stop;
589 ops->cpu_type = cpu_type; 508 ops->cpu_type = cpu_type;
590 ops->switch_events = nmi_switch_event;
591 509
592 if (model->init) 510 if (model->init)
593 ret = model->init(ops); 511 ret = model->init(ops);
@@ -607,7 +525,7 @@ void op_nmi_exit(void)
607#ifdef CONFIG_SMP 525#ifdef CONFIG_SMP
608 unregister_cpu_notifier(&oprofile_cpu_nb); 526 unregister_cpu_notifier(&oprofile_cpu_nb);
609#endif 527#endif
528 }
610 if (model->exit) 529 if (model->exit)
611 model->exit(); 530 model->exit();
612 }
613} 531}
diff --git a/arch/x86/oprofile/op_counter.h b/arch/x86/oprofile/op_counter.h
index 786d6e01cf7f..2880b15c4675 100644
--- a/arch/x86/oprofile/op_counter.h
+++ b/arch/x86/oprofile/op_counter.h
@@ -10,14 +10,13 @@
10#ifndef OP_COUNTER_H 10#ifndef OP_COUNTER_H
11#define OP_COUNTER_H 11#define OP_COUNTER_H
12 12
13#define OP_MAX_COUNTER 32 13#define OP_MAX_COUNTER 8
14 14
15/* Per-perfctr configuration as set via 15/* Per-perfctr configuration as set via
16 * oprofilefs. 16 * oprofilefs.
17 */ 17 */
18struct op_counter_config { 18struct op_counter_config {
19 unsigned long count; 19 unsigned long count;
20 unsigned long save_count_low;
21 unsigned long enabled; 20 unsigned long enabled;
22 unsigned long event; 21 unsigned long event;
23 unsigned long kernel; 22 unsigned long kernel;
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index bbf2b68bcc5d..d9faf607b3a6 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -15,7 +15,6 @@
15#include <linux/oprofile.h> 15#include <linux/oprofile.h>
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/pci.h> 17#include <linux/pci.h>
18#include <linux/percpu.h>
19 18
20#include <asm/ptrace.h> 19#include <asm/ptrace.h>
21#include <asm/msr.h> 20#include <asm/msr.h>
@@ -24,10 +23,8 @@
24#include "op_x86_model.h" 23#include "op_x86_model.h"
25#include "op_counter.h" 24#include "op_counter.h"
26 25
27#define NUM_COUNTERS 32 26#define NUM_COUNTERS 4
28#define NUM_HARDWARE_COUNTERS 4 27#define NUM_CONTROLS 4
29#define NUM_CONTROLS 32
30#define NUM_HARDWARE_CONTROLS 4
31 28
32#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) 29#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
33#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) 30#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
@@ -51,7 +48,6 @@
51#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) 48#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
52 49
53static unsigned long reset_value[NUM_COUNTERS]; 50static unsigned long reset_value[NUM_COUNTERS];
54DECLARE_PER_CPU(int, switch_index);
55 51
56#ifdef CONFIG_OPROFILE_IBS 52#ifdef CONFIG_OPROFILE_IBS
57 53
@@ -134,17 +130,15 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
134 int i; 130 int i;
135 131
136 for (i = 0; i < NUM_COUNTERS; i++) { 132 for (i = 0; i < NUM_COUNTERS; i++) {
137 int hw_counter = i % NUM_HARDWARE_COUNTERS; 133 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
138 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + hw_counter)) 134 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
139 msrs->counters[i].addr = MSR_K7_PERFCTR0 + hw_counter;
140 else 135 else
141 msrs->counters[i].addr = 0; 136 msrs->counters[i].addr = 0;
142 } 137 }
143 138
144 for (i = 0; i < NUM_CONTROLS; i++) { 139 for (i = 0; i < NUM_CONTROLS; i++) {
145 int hw_control = i % NUM_HARDWARE_CONTROLS; 140 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
146 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + hw_control)) 141 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
147 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + hw_control;
148 else 142 else
149 msrs->controls[i].addr = 0; 143 msrs->controls[i].addr = 0;
150 } 144 }
@@ -156,16 +150,8 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
156 unsigned int low, high; 150 unsigned int low, high;
157 int i; 151 int i;
158 152
159 for (i = 0; i < NUM_HARDWARE_CONTROLS; ++i) {
160 int offset = i + __get_cpu_var(switch_index);
161 if (counter_config[offset].enabled)
162 reset_value[offset] = counter_config[offset].count;
163 else
164 reset_value[offset] = 0;
165 }
166
167 /* clear all counters */ 153 /* clear all counters */
168 for (i = 0 ; i < NUM_HARDWARE_CONTROLS; ++i) { 154 for (i = 0 ; i < NUM_CONTROLS; ++i) {
169 if (unlikely(!CTRL_IS_RESERVED(msrs, i))) 155 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
170 continue; 156 continue;
171 CTRL_READ(low, high, msrs, i); 157 CTRL_READ(low, high, msrs, i);
@@ -175,31 +161,34 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
175 } 161 }
176 162
177 /* avoid a false detection of ctr overflows in NMI handler */ 163 /* avoid a false detection of ctr overflows in NMI handler */
178 for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) { 164 for (i = 0; i < NUM_COUNTERS; ++i) {
179 if (unlikely(!CTR_IS_RESERVED(msrs, i))) 165 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
180 continue; 166 continue;
181 CTR_WRITE(1, msrs, i); 167 CTR_WRITE(1, msrs, i);
182 } 168 }
183 169
184 /* enable active counters */ 170 /* enable active counters */
185 for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) { 171 for (i = 0; i < NUM_COUNTERS; ++i) {
186 int offset = i + __get_cpu_var(switch_index); 172 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
187 if ((counter_config[offset].enabled) && (CTR_IS_RESERVED(msrs, i))) { 173 reset_value[i] = counter_config[i].count;
188 CTR_WRITE(counter_config[offset].count, msrs, i); 174
175 CTR_WRITE(counter_config[i].count, msrs, i);
189 176
190 CTRL_READ(low, high, msrs, i); 177 CTRL_READ(low, high, msrs, i);
191 CTRL_CLEAR_LO(low); 178 CTRL_CLEAR_LO(low);
192 CTRL_CLEAR_HI(high); 179 CTRL_CLEAR_HI(high);
193 CTRL_SET_ENABLE(low); 180 CTRL_SET_ENABLE(low);
194 CTRL_SET_USR(low, counter_config[offset].user); 181 CTRL_SET_USR(low, counter_config[i].user);
195 CTRL_SET_KERN(low, counter_config[offset].kernel); 182 CTRL_SET_KERN(low, counter_config[i].kernel);
196 CTRL_SET_UM(low, counter_config[offset].unit_mask); 183 CTRL_SET_UM(low, counter_config[i].unit_mask);
197 CTRL_SET_EVENT_LOW(low, counter_config[offset].event); 184 CTRL_SET_EVENT_LOW(low, counter_config[i].event);
198 CTRL_SET_EVENT_HIGH(high, counter_config[offset].event); 185 CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
199 CTRL_SET_HOST_ONLY(high, 0); 186 CTRL_SET_HOST_ONLY(high, 0);
200 CTRL_SET_GUEST_ONLY(high, 0); 187 CTRL_SET_GUEST_ONLY(high, 0);
201 188
202 CTRL_WRITE(low, high, msrs, i); 189 CTRL_WRITE(low, high, msrs, i);
190 } else {
191 reset_value[i] = 0;
203 } 192 }
204 } 193 }
205} 194}
@@ -287,14 +276,13 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
287 unsigned int low, high; 276 unsigned int low, high;
288 int i; 277 int i;
289 278
290 for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { 279 for (i = 0 ; i < NUM_COUNTERS; ++i) {
291 int offset = i + __get_cpu_var(switch_index); 280 if (!reset_value[i])
292 if (!reset_value[offset])
293 continue; 281 continue;
294 CTR_READ(low, high, msrs, i); 282 CTR_READ(low, high, msrs, i);
295 if (CTR_OVERFLOWED(low)) { 283 if (CTR_OVERFLOWED(low)) {
296 oprofile_add_sample(regs, offset); 284 oprofile_add_sample(regs, i);
297 CTR_WRITE(reset_value[offset], msrs, i); 285 CTR_WRITE(reset_value[i], msrs, i);
298 } 286 }
299 } 287 }
300 288
@@ -310,10 +298,8 @@ static void op_amd_start(struct op_msrs const * const msrs)
310{ 298{
311 unsigned int low, high; 299 unsigned int low, high;
312 int i; 300 int i;
313 301 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
314 for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { 302 if (reset_value[i]) {
315 int offset = i + __get_cpu_var(switch_index);
316 if (reset_value[offset]) {
317 CTRL_READ(low, high, msrs, i); 303 CTRL_READ(low, high, msrs, i);
318 CTRL_SET_ACTIVE(low); 304 CTRL_SET_ACTIVE(low);
319 CTRL_WRITE(low, high, msrs, i); 305 CTRL_WRITE(low, high, msrs, i);
@@ -343,8 +329,8 @@ static void op_amd_stop(struct op_msrs const * const msrs)
343 329
344 /* Subtle: stop on all counters to avoid race with 330 /* Subtle: stop on all counters to avoid race with
345 * setting our pm callback */ 331 * setting our pm callback */
346 for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { 332 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
347 if (!reset_value[i + per_cpu(switch_index, smp_processor_id())]) 333 if (!reset_value[i])
348 continue; 334 continue;
349 CTRL_READ(low, high, msrs, i); 335 CTRL_READ(low, high, msrs, i);
350 CTRL_SET_INACTIVE(low); 336 CTRL_SET_INACTIVE(low);
@@ -370,11 +356,11 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
370{ 356{
371 int i; 357 int i;
372 358
373 for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { 359 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
374 if (CTR_IS_RESERVED(msrs, i)) 360 if (CTR_IS_RESERVED(msrs, i))
375 release_perfctr_nmi(MSR_K7_PERFCTR0 + i); 361 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
376 } 362 }
377 for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { 363 for (i = 0 ; i < NUM_CONTROLS ; ++i) {
378 if (CTRL_IS_RESERVED(msrs, i)) 364 if (CTRL_IS_RESERVED(msrs, i))
379 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); 365 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
380 } 366 }
@@ -548,8 +534,6 @@ struct op_x86_model_spec const op_amd_spec = {
548 .exit = op_amd_exit, 534 .exit = op_amd_exit,
549 .num_counters = NUM_COUNTERS, 535 .num_counters = NUM_COUNTERS,
550 .num_controls = NUM_CONTROLS, 536 .num_controls = NUM_CONTROLS,
551 .num_hardware_counters = NUM_HARDWARE_COUNTERS,
552 .num_hardware_controls = NUM_HARDWARE_CONTROLS,
553 .fill_in_addresses = &op_amd_fill_in_addresses, 537 .fill_in_addresses = &op_amd_fill_in_addresses,
554 .setup_ctrs = &op_amd_setup_ctrs, 538 .setup_ctrs = &op_amd_setup_ctrs,
555 .check_ctrs = &op_amd_check_ctrs, 539 .check_ctrs = &op_amd_check_ctrs,
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index cacba61ffbac..43ac5af338d8 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -700,8 +700,6 @@ static void p4_shutdown(struct op_msrs const * const msrs)
700struct op_x86_model_spec const op_p4_ht2_spec = { 700struct op_x86_model_spec const op_p4_ht2_spec = {
701 .num_counters = NUM_COUNTERS_HT2, 701 .num_counters = NUM_COUNTERS_HT2,
702 .num_controls = NUM_CONTROLS_HT2, 702 .num_controls = NUM_CONTROLS_HT2,
703 .num_hardware_counters = NUM_COUNTERS_HT2,
704 .num_hardware_controls = NUM_CONTROLS_HT2,
705 .fill_in_addresses = &p4_fill_in_addresses, 703 .fill_in_addresses = &p4_fill_in_addresses,
706 .setup_ctrs = &p4_setup_ctrs, 704 .setup_ctrs = &p4_setup_ctrs,
707 .check_ctrs = &p4_check_ctrs, 705 .check_ctrs = &p4_check_ctrs,
@@ -714,8 +712,6 @@ struct op_x86_model_spec const op_p4_ht2_spec = {
714struct op_x86_model_spec const op_p4_spec = { 712struct op_x86_model_spec const op_p4_spec = {
715 .num_counters = NUM_COUNTERS_NON_HT, 713 .num_counters = NUM_COUNTERS_NON_HT,
716 .num_controls = NUM_CONTROLS_NON_HT, 714 .num_controls = NUM_CONTROLS_NON_HT,
717 .num_hardware_counters = NUM_COUNTERS_NON_HT,
718 .num_hardware_controls = NUM_CONTROLS_NON_HT,
719 .fill_in_addresses = &p4_fill_in_addresses, 715 .fill_in_addresses = &p4_fill_in_addresses,
720 .setup_ctrs = &p4_setup_ctrs, 716 .setup_ctrs = &p4_setup_ctrs,
721 .check_ctrs = &p4_check_ctrs, 717 .check_ctrs = &p4_check_ctrs,
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index e5811aa480eb..eff431f6c57b 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -183,8 +183,6 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
183struct op_x86_model_spec const op_ppro_spec = { 183struct op_x86_model_spec const op_ppro_spec = {
184 .num_counters = NUM_COUNTERS, 184 .num_counters = NUM_COUNTERS,
185 .num_controls = NUM_CONTROLS, 185 .num_controls = NUM_CONTROLS,
186 .num_hardware_counters = NUM_COUNTERS,
187 .num_hardware_controls = NUM_CONTROLS,
188 .fill_in_addresses = &ppro_fill_in_addresses, 186 .fill_in_addresses = &ppro_fill_in_addresses,
189 .setup_ctrs = &ppro_setup_ctrs, 187 .setup_ctrs = &ppro_setup_ctrs,
190 .check_ctrs = &ppro_check_ctrs, 188 .check_ctrs = &ppro_check_ctrs,
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index e07ba1076371..05a0261ba0c3 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -19,7 +19,6 @@ struct op_saved_msr {
19struct op_msr { 19struct op_msr {
20 unsigned long addr; 20 unsigned long addr;
21 struct op_saved_msr saved; 21 struct op_saved_msr saved;
22 struct op_saved_msr multiplex;
23}; 22};
24 23
25struct op_msrs { 24struct op_msrs {
@@ -35,8 +34,6 @@ struct pt_regs;
35struct op_x86_model_spec { 34struct op_x86_model_spec {
36 int (*init)(struct oprofile_operations *ops); 35 int (*init)(struct oprofile_operations *ops);
37 void (*exit)(void); 36 void (*exit)(void);
38 unsigned int const num_hardware_counters;
39 unsigned int const num_hardware_controls;
40 unsigned int const num_counters; 37 unsigned int const num_counters;
41 unsigned int const num_controls; 38 unsigned int const num_controls;
42 void (*fill_in_addresses)(struct op_msrs * const msrs); 39 void (*fill_in_addresses)(struct op_msrs * const msrs);