1 files changed, 34 insertions, 30 deletions

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index f90e290f689f..1bbedc4b0f88 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -35,6 +35,8 @@
 #include <asm/apb_timer.h>
 #include <asm/reboot.h>
 
+#include "intel_mid_weak_decls.h"
+
 /*
  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
  * cmdline option x86_intel_mid_timer can be used to override the configuration
@@ -58,12 +60,16 @@
 
 enum intel_mid_timer_options intel_mid_timer_options;
 
+/* intel_mid_ops to store sub arch ops */
+struct intel_mid_ops *intel_mid_ops;
+/* getter function for sub arch ops*/
+static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
 enum intel_mid_cpu_type __intel_mid_cpu_chip;
 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 
 static void intel_mid_power_off(void)
 {
-}
+};
 
 static void intel_mid_reboot(void)
 {
@@ -72,32 +78,6 @@ static void intel_mid_reboot(void)
 
 static unsigned long __init intel_mid_calibrate_tsc(void)
 {
-        unsigned long fast_calibrate;
-        u32 lo, hi, ratio, fsb;
-
-        rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
-        pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
-        ratio = (hi >> 8) & 0x1f;
-        pr_debug("ratio is %d\n", ratio);
-        if (!ratio) {
-                pr_err("read a zero ratio, should be incorrect!\n");
-                pr_err("force tsc ratio to 16 ...\n");
-                ratio = 16;
-        }
-        rdmsr(MSR_FSB_FREQ, lo, hi);
-        if ((lo & 0x7) == 0x7)
-                fsb = PENWELL_FSB_FREQ_83SKU;
-        else
-                fsb = PENWELL_FSB_FREQ_100SKU;
-        fast_calibrate = ratio * fsb;
-        pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
-        lapic_timer_frequency = fsb * 1000 / HZ;
-        /* mark tsc clocksource as reliable */
-        set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
-
-        if (fast_calibrate)
-                return fast_calibrate;
-
         return 0;
 }
 
@@ -125,13 +105,37 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-        if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
-                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
-        else {
+        if (boot_cpu_data.x86 != 6) {
                 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
                         boot_cpu_data.x86, boot_cpu_data.x86_model);
                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
+                goto out;
         }
+
+        switch (boot_cpu_data.x86_model) {
+        case 0x35:
+                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
+                break;
+        case 0x3C:
+        case 0x4A:
+                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
+                break;
+        case 0x27:
+        default:
+                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
+                break;
+        }
+
+        if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
+                intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
+        else {
+                intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
+                pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
+        }
+
+out:
+        if (intel_mid_ops->arch_setup)
+                intel_mid_ops->arch_setup();
 }
 
 /* MID systems don't have i8042 controller */