diff options
Diffstat (limited to 'arch/x86/platform/ce4100')
-rw-r--r-- | arch/x86/platform/ce4100/Makefile | 1 | ||||
-rw-r--r-- | arch/x86/platform/ce4100/ce4100.c | 146 | ||||
-rw-r--r-- | arch/x86/platform/ce4100/falconfalls.dts | 430 |
3 files changed, 577 insertions, 0 deletions
diff --git a/arch/x86/platform/ce4100/Makefile b/arch/x86/platform/ce4100/Makefile new file mode 100644 index 000000000000..91fc92971d94 --- /dev/null +++ b/arch/x86/platform/ce4100/Makefile | |||
@@ -0,0 +1 @@ | |||
obj-$(CONFIG_X86_INTEL_CE) += ce4100.o | |||
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c new file mode 100644 index 000000000000..28071bb31db7 --- /dev/null +++ b/arch/x86/platform/ce4100/ce4100.c | |||
@@ -0,0 +1,146 @@ | |||
1 | /* | ||
2 | * Intel CE4100 platform specific setup code | ||
3 | * | ||
4 | * (C) Copyright 2010 Intel Corporation | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; version 2 | ||
9 | * of the License. | ||
10 | */ | ||
11 | #include <linux/init.h> | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/irq.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/serial_reg.h> | ||
16 | #include <linux/serial_8250.h> | ||
17 | |||
18 | #include <asm/ce4100.h> | ||
19 | #include <asm/prom.h> | ||
20 | #include <asm/setup.h> | ||
21 | #include <asm/i8259.h> | ||
22 | #include <asm/io.h> | ||
23 | #include <asm/io_apic.h> | ||
24 | |||
25 | static int ce4100_i8042_detect(void) | ||
26 | { | ||
27 | return 0; | ||
28 | } | ||
29 | |||
30 | #ifdef CONFIG_SERIAL_8250 | ||
31 | |||
32 | static unsigned int mem_serial_in(struct uart_port *p, int offset) | ||
33 | { | ||
34 | offset = offset << p->regshift; | ||
35 | return readl(p->membase + offset); | ||
36 | } | ||
37 | |||
38 | /* | ||
39 | * The UART Tx interrupts are not set under some conditions and therefore serial | ||
40 | * transmission hangs. This is a silicon issue and has not been root caused. The | ||
41 | * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT | ||
42 | * bit of LSR register in interrupt handler to see whether at least one of these | ||
43 | * two bits is set, if so then process the transmit request. If this workaround | ||
44 | * is not applied, then the serial transmission may hang. This workaround is for | ||
45 | * errata number 9 in Errata - B step. | ||
46 | */ | ||
47 | |||
48 | static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset) | ||
49 | { | ||
50 | unsigned int ret, ier, lsr; | ||
51 | |||
52 | if (offset == UART_IIR) { | ||
53 | offset = offset << p->regshift; | ||
54 | ret = readl(p->membase + offset); | ||
55 | if (ret & UART_IIR_NO_INT) { | ||
56 | /* see if the TX interrupt should have really set */ | ||
57 | ier = mem_serial_in(p, UART_IER); | ||
58 | /* see if the UART's XMIT interrupt is enabled */ | ||
59 | if (ier & UART_IER_THRI) { | ||
60 | lsr = mem_serial_in(p, UART_LSR); | ||
61 | /* now check to see if the UART should be | ||
62 | generating an interrupt (but isn't) */ | ||
63 | if (lsr & (UART_LSR_THRE | UART_LSR_TEMT)) | ||
64 | ret &= ~UART_IIR_NO_INT; | ||
65 | } | ||
66 | } | ||
67 | } else | ||
68 | ret = mem_serial_in(p, offset); | ||
69 | return ret; | ||
70 | } | ||
71 | |||
72 | static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value) | ||
73 | { | ||
74 | offset = offset << p->regshift; | ||
75 | writel(value, p->membase + offset); | ||
76 | } | ||
77 | |||
78 | static void ce4100_serial_fixup(int port, struct uart_port *up, | ||
79 | unsigned short *capabilites) | ||
80 | { | ||
81 | #ifdef CONFIG_EARLY_PRINTK | ||
82 | /* | ||
83 | * Over ride the legacy port configuration that comes from | ||
84 | * asm/serial.h. Using the ioport driver then switching to the | ||
85 | * PCI memmaped driver hangs the IOAPIC | ||
86 | */ | ||
87 | if (up->iotype != UPIO_MEM32) { | ||
88 | up->uartclk = 14745600; | ||
89 | up->mapbase = 0xdffe0200; | ||
90 | set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, | ||
91 | up->mapbase & PAGE_MASK); | ||
92 | up->membase = | ||
93 | (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); | ||
94 | up->membase += up->mapbase & ~PAGE_MASK; | ||
95 | up->iotype = UPIO_MEM32; | ||
96 | up->regshift = 2; | ||
97 | } | ||
98 | #endif | ||
99 | up->iobase = 0; | ||
100 | up->serial_in = ce4100_mem_serial_in; | ||
101 | up->serial_out = ce4100_mem_serial_out; | ||
102 | |||
103 | *capabilites |= (1 << 12); | ||
104 | } | ||
105 | |||
106 | static __init void sdv_serial_fixup(void) | ||
107 | { | ||
108 | serial8250_set_isa_configurator(ce4100_serial_fixup); | ||
109 | } | ||
110 | |||
111 | #else | ||
112 | static inline void sdv_serial_fixup(void); | ||
113 | #endif | ||
114 | |||
115 | static void __init sdv_arch_setup(void) | ||
116 | { | ||
117 | sdv_serial_fixup(); | ||
118 | } | ||
119 | |||
120 | #ifdef CONFIG_X86_IO_APIC | ||
121 | static void __cpuinit sdv_pci_init(void) | ||
122 | { | ||
123 | x86_of_pci_init(); | ||
124 | /* We can't set this earlier, because we need to calibrate the timer */ | ||
125 | legacy_pic = &null_legacy_pic; | ||
126 | } | ||
127 | #endif | ||
128 | |||
129 | /* | ||
130 | * CE4100 specific x86_init function overrides and early setup | ||
131 | * calls. | ||
132 | */ | ||
133 | void __init x86_ce4100_early_setup(void) | ||
134 | { | ||
135 | x86_init.oem.arch_setup = sdv_arch_setup; | ||
136 | x86_platform.i8042_detect = ce4100_i8042_detect; | ||
137 | x86_init.resources.probe_roms = x86_init_noop; | ||
138 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; | ||
139 | x86_init.mpparse.find_smp_config = x86_init_noop; | ||
140 | x86_init.pci.init = ce4100_pci_init; | ||
141 | |||
142 | #ifdef CONFIG_X86_IO_APIC | ||
143 | x86_init.pci.init_irq = sdv_pci_init; | ||
144 | x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck; | ||
145 | #endif | ||
146 | } | ||
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts new file mode 100644 index 000000000000..e70be38ce039 --- /dev/null +++ b/arch/x86/platform/ce4100/falconfalls.dts | |||
@@ -0,0 +1,430 @@ | |||
1 | /* | ||
2 | * CE4100 on Falcon Falls | ||
3 | * | ||
4 | * (c) Copyright 2010 Intel Corporation | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; version 2 of the License. | ||
9 | */ | ||
10 | /dts-v1/; | ||
11 | / { | ||
12 | model = "intel,falconfalls"; | ||
13 | compatible = "intel,falconfalls"; | ||
14 | #address-cells = <1>; | ||
15 | #size-cells = <1>; | ||
16 | |||
17 | cpus { | ||
18 | #address-cells = <1>; | ||
19 | #size-cells = <0>; | ||
20 | |||
21 | cpu@0 { | ||
22 | device_type = "cpu"; | ||
23 | compatible = "intel,ce4100"; | ||
24 | reg = <0>; | ||
25 | lapic = <&lapic0>; | ||
26 | }; | ||
27 | }; | ||
28 | |||
29 | soc@0 { | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <1>; | ||
32 | compatible = "intel,ce4100-cp"; | ||
33 | ranges; | ||
34 | |||
35 | ioapic1: interrupt-controller@fec00000 { | ||
36 | #interrupt-cells = <2>; | ||
37 | compatible = "intel,ce4100-ioapic"; | ||
38 | interrupt-controller; | ||
39 | reg = <0xfec00000 0x1000>; | ||
40 | }; | ||
41 | |||
42 | timer@fed00000 { | ||
43 | compatible = "intel,ce4100-hpet"; | ||
44 | reg = <0xfed00000 0x200>; | ||
45 | }; | ||
46 | |||
47 | lapic0: interrupt-controller@fee00000 { | ||
48 | compatible = "intel,ce4100-lapic"; | ||
49 | reg = <0xfee00000 0x1000>; | ||
50 | }; | ||
51 | |||
52 | pci@3fc { | ||
53 | #address-cells = <3>; | ||
54 | #size-cells = <2>; | ||
55 | compatible = "intel,ce4100-pci", "pci"; | ||
56 | device_type = "pci"; | ||
57 | bus-range = <0 0>; | ||
58 | ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000 | ||
59 | 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000 | ||
60 | 0x0000000 0 0x0 0x0 0 0x100>; | ||
61 | |||
62 | /* Secondary IO-APIC */ | ||
63 | ioapic2: interrupt-controller@0,1 { | ||
64 | #interrupt-cells = <2>; | ||
65 | compatible = "intel,ce4100-ioapic"; | ||
66 | interrupt-controller; | ||
67 | reg = <0x100 0x0 0x0 0x0 0x0>; | ||
68 | assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>; | ||
69 | }; | ||
70 | |||
71 | pci@1,0 { | ||
72 | #address-cells = <3>; | ||
73 | #size-cells = <2>; | ||
74 | compatible = "intel,ce4100-pci", "pci"; | ||
75 | device_type = "pci"; | ||
76 | bus-range = <1 1>; | ||
77 | reg = <0x0800 0x0 0x0 0x0 0x0>; | ||
78 | ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>; | ||
79 | |||
80 | interrupt-parent = <&ioapic2>; | ||
81 | |||
82 | display@2,0 { | ||
83 | compatible = "pci8086,2e5b.2", | ||
84 | "pci8086,2e5b", | ||
85 | "pciclass038000", | ||
86 | "pciclass0380"; | ||
87 | |||
88 | reg = <0x11000 0x0 0x0 0x0 0x0>; | ||
89 | interrupts = <0 1>; | ||
90 | }; | ||
91 | |||
92 | multimedia@3,0 { | ||
93 | compatible = "pci8086,2e5c.2", | ||
94 | "pci8086,2e5c", | ||
95 | "pciclass048000", | ||
96 | "pciclass0480"; | ||
97 | |||
98 | reg = <0x11800 0x0 0x0 0x0 0x0>; | ||
99 | interrupts = <2 1>; | ||
100 | }; | ||
101 | |||
102 | multimedia@4,0 { | ||
103 | compatible = "pci8086,2e5d.2", | ||
104 | "pci8086,2e5d", | ||
105 | "pciclass048000", | ||
106 | "pciclass0480"; | ||
107 | |||
108 | reg = <0x12000 0x0 0x0 0x0 0x0>; | ||
109 | interrupts = <4 1>; | ||
110 | }; | ||
111 | |||
112 | multimedia@4,1 { | ||
113 | compatible = "pci8086,2e5e.2", | ||
114 | "pci8086,2e5e", | ||
115 | "pciclass048000", | ||
116 | "pciclass0480"; | ||
117 | |||
118 | reg = <0x12100 0x0 0x0 0x0 0x0>; | ||
119 | interrupts = <5 1>; | ||
120 | }; | ||
121 | |||
122 | sound@6,0 { | ||
123 | compatible = "pci8086,2e5f.2", | ||
124 | "pci8086,2e5f", | ||
125 | "pciclass040100", | ||
126 | "pciclass0401"; | ||
127 | |||
128 | reg = <0x13000 0x0 0x0 0x0 0x0>; | ||
129 | interrupts = <6 1>; | ||
130 | }; | ||
131 | |||
132 | sound@6,1 { | ||
133 | compatible = "pci8086,2e5f.2", | ||
134 | "pci8086,2e5f", | ||
135 | "pciclass040100", | ||
136 | "pciclass0401"; | ||
137 | |||
138 | reg = <0x13100 0x0 0x0 0x0 0x0>; | ||
139 | interrupts = <7 1>; | ||
140 | }; | ||
141 | |||
142 | sound@6,2 { | ||
143 | compatible = "pci8086,2e60.2", | ||
144 | "pci8086,2e60", | ||
145 | "pciclass040100", | ||
146 | "pciclass0401"; | ||
147 | |||
148 | reg = <0x13200 0x0 0x0 0x0 0x0>; | ||
149 | interrupts = <8 1>; | ||
150 | }; | ||
151 | |||
152 | display@8,0 { | ||
153 | compatible = "pci8086,2e61.2", | ||
154 | "pci8086,2e61", | ||
155 | "pciclass038000", | ||
156 | "pciclass0380"; | ||
157 | |||
158 | reg = <0x14000 0x0 0x0 0x0 0x0>; | ||
159 | interrupts = <9 1>; | ||
160 | }; | ||
161 | |||
162 | display@8,1 { | ||
163 | compatible = "pci8086,2e62.2", | ||
164 | "pci8086,2e62", | ||
165 | "pciclass038000", | ||
166 | "pciclass0380"; | ||
167 | |||
168 | reg = <0x14100 0x0 0x0 0x0 0x0>; | ||
169 | interrupts = <10 1>; | ||
170 | }; | ||
171 | |||
172 | multimedia@8,2 { | ||
173 | compatible = "pci8086,2e63.2", | ||
174 | "pci8086,2e63", | ||
175 | "pciclass048000", | ||
176 | "pciclass0480"; | ||
177 | |||
178 | reg = <0x14200 0x0 0x0 0x0 0x0>; | ||
179 | interrupts = <11 1>; | ||
180 | }; | ||
181 | |||
182 | entertainment-encryption@9,0 { | ||
183 | compatible = "pci8086,2e64.2", | ||
184 | "pci8086,2e64", | ||
185 | "pciclass101000", | ||
186 | "pciclass1010"; | ||
187 | |||
188 | reg = <0x14800 0x0 0x0 0x0 0x0>; | ||
189 | interrupts = <12 1>; | ||
190 | }; | ||
191 | |||
192 | localbus@a,0 { | ||
193 | compatible = "pci8086,2e65.2", | ||
194 | "pci8086,2e65", | ||
195 | "pciclassff0000", | ||
196 | "pciclassff00"; | ||
197 | |||
198 | reg = <0x15000 0x0 0x0 0x0 0x0>; | ||
199 | }; | ||
200 | |||
201 | serial@b,0 { | ||
202 | compatible = "pci8086,2e66.2", | ||
203 | "pci8086,2e66", | ||
204 | "pciclass070003", | ||
205 | "pciclass0700"; | ||
206 | |||
207 | reg = <0x15800 0x0 0x0 0x0 0x0>; | ||
208 | interrupts = <14 1>; | ||
209 | }; | ||
210 | |||
211 | gpio@b,1 { | ||
212 | compatible = "pci8086,2e67.2", | ||
213 | "pci8086,2e67", | ||
214 | "pciclassff0000", | ||
215 | "pciclassff00"; | ||
216 | |||
217 | #gpio-cells = <2>; | ||
218 | reg = <0x15900 0x0 0x0 0x0 0x0>; | ||
219 | interrupts = <15 1>; | ||
220 | gpio-controller; | ||
221 | }; | ||
222 | |||
223 | i2c-controller@b,2 { | ||
224 | #address-cells = <2>; | ||
225 | #size-cells = <1>; | ||
226 | compatible = "pci8086,2e68.2", | ||
227 | "pci8086,2e68", | ||
228 | "pciclass,ff0000", | ||
229 | "pciclass,ff00"; | ||
230 | |||
231 | reg = <0x15a00 0x0 0x0 0x0 0x0>; | ||
232 | interrupts = <16 1>; | ||
233 | ranges = <0 0 0x02000000 0 0xdffe0500 0x100 | ||
234 | 1 0 0x02000000 0 0xdffe0600 0x100 | ||
235 | 2 0 0x02000000 0 0xdffe0700 0x100>; | ||
236 | |||
237 | i2c@0 { | ||
238 | #address-cells = <1>; | ||
239 | #size-cells = <0>; | ||
240 | compatible = "intel,ce4100-i2c-controller"; | ||
241 | reg = <0 0 0x100>; | ||
242 | }; | ||
243 | |||
244 | i2c@1 { | ||
245 | #address-cells = <1>; | ||
246 | #size-cells = <0>; | ||
247 | compatible = "intel,ce4100-i2c-controller"; | ||
248 | reg = <1 0 0x100>; | ||
249 | |||
250 | gpio@26 { | ||
251 | #gpio-cells = <2>; | ||
252 | compatible = "ti,pcf8575"; | ||
253 | reg = <0x26>; | ||
254 | gpio-controller; | ||
255 | }; | ||
256 | }; | ||
257 | |||
258 | i2c@2 { | ||
259 | #address-cells = <1>; | ||
260 | #size-cells = <0>; | ||
261 | compatible = "intel,ce4100-i2c-controller"; | ||
262 | reg = <2 0 0x100>; | ||
263 | |||
264 | gpio@26 { | ||
265 | #gpio-cells = <2>; | ||
266 | compatible = "ti,pcf8575"; | ||
267 | reg = <0x26>; | ||
268 | gpio-controller; | ||
269 | }; | ||
270 | }; | ||
271 | }; | ||
272 | |||
273 | smard-card@b,3 { | ||
274 | compatible = "pci8086,2e69.2", | ||
275 | "pci8086,2e69", | ||
276 | "pciclass070500", | ||
277 | "pciclass0705"; | ||
278 | |||
279 | reg = <0x15b00 0x0 0x0 0x0 0x0>; | ||
280 | interrupts = <15 1>; | ||
281 | }; | ||
282 | |||
283 | spi-controller@b,4 { | ||
284 | #address-cells = <1>; | ||
285 | #size-cells = <0>; | ||
286 | compatible = | ||
287 | "pci8086,2e6a.2", | ||
288 | "pci8086,2e6a", | ||
289 | "pciclass,ff0000", | ||
290 | "pciclass,ff00"; | ||
291 | |||
292 | reg = <0x15c00 0x0 0x0 0x0 0x0>; | ||
293 | interrupts = <15 1>; | ||
294 | |||
295 | dac@0 { | ||
296 | compatible = "ti,pcm1755"; | ||
297 | reg = <0>; | ||
298 | spi-max-frequency = <115200>; | ||
299 | }; | ||
300 | |||
301 | dac@1 { | ||
302 | compatible = "ti,pcm1609a"; | ||
303 | reg = <1>; | ||
304 | spi-max-frequency = <115200>; | ||
305 | }; | ||
306 | |||
307 | eeprom@2 { | ||
308 | compatible = "atmel,at93c46"; | ||
309 | reg = <2>; | ||
310 | spi-max-frequency = <115200>; | ||
311 | }; | ||
312 | }; | ||
313 | |||
314 | multimedia@b,7 { | ||
315 | compatible = "pci8086,2e6d.2", | ||
316 | "pci8086,2e6d", | ||
317 | "pciclassff0000", | ||
318 | "pciclassff00"; | ||
319 | |||
320 | reg = <0x15f00 0x0 0x0 0x0 0x0>; | ||
321 | }; | ||
322 | |||
323 | ethernet@c,0 { | ||
324 | compatible = "pci8086,2e6e.2", | ||
325 | "pci8086,2e6e", | ||
326 | "pciclass020000", | ||
327 | "pciclass0200"; | ||
328 | |||
329 | reg = <0x16000 0x0 0x0 0x0 0x0>; | ||
330 | interrupts = <21 1>; | ||
331 | }; | ||
332 | |||
333 | clock@c,1 { | ||
334 | compatible = "pci8086,2e6f.2", | ||
335 | "pci8086,2e6f", | ||
336 | "pciclassff0000", | ||
337 | "pciclassff00"; | ||
338 | |||
339 | reg = <0x16100 0x0 0x0 0x0 0x0>; | ||
340 | interrupts = <3 1>; | ||
341 | }; | ||
342 | |||
343 | usb@d,0 { | ||
344 | compatible = "pci8086,2e70.2", | ||
345 | "pci8086,2e70", | ||
346 | "pciclass0c0320", | ||
347 | "pciclass0c03"; | ||
348 | |||
349 | reg = <0x16800 0x0 0x0 0x0 0x0>; | ||
350 | interrupts = <22 1>; | ||
351 | }; | ||
352 | |||
353 | usb@d,1 { | ||
354 | compatible = "pci8086,2e70.2", | ||
355 | "pci8086,2e70", | ||
356 | "pciclass0c0320", | ||
357 | "pciclass0c03"; | ||
358 | |||
359 | reg = <0x16900 0x0 0x0 0x0 0x0>; | ||
360 | interrupts = <22 1>; | ||
361 | }; | ||
362 | |||
363 | sata@e,0 { | ||
364 | compatible = "pci8086,2e71.0", | ||
365 | "pci8086,2e71", | ||
366 | "pciclass010601", | ||
367 | "pciclass0106"; | ||
368 | |||
369 | reg = <0x17000 0x0 0x0 0x0 0x0>; | ||
370 | interrupts = <23 1>; | ||
371 | }; | ||
372 | |||
373 | flash@f,0 { | ||
374 | compatible = "pci8086,701.1", | ||
375 | "pci8086,701", | ||
376 | "pciclass050100", | ||
377 | "pciclass0501"; | ||
378 | |||
379 | reg = <0x17800 0x0 0x0 0x0 0x0>; | ||
380 | interrupts = <13 1>; | ||
381 | }; | ||
382 | |||
383 | entertainment-encryption@10,0 { | ||
384 | compatible = "pci8086,702.1", | ||
385 | "pci8086,702", | ||
386 | "pciclass101000", | ||
387 | "pciclass1010"; | ||
388 | |||
389 | reg = <0x18000 0x0 0x0 0x0 0x0>; | ||
390 | }; | ||
391 | |||
392 | co-processor@11,0 { | ||
393 | compatible = "pci8086,703.1", | ||
394 | "pci8086,703", | ||
395 | "pciclass0b4000", | ||
396 | "pciclass0b40"; | ||
397 | |||
398 | reg = <0x18800 0x0 0x0 0x0 0x0>; | ||
399 | interrupts = <1 1>; | ||
400 | }; | ||
401 | |||
402 | multimedia@12,0 { | ||
403 | compatible = "pci8086,704.0", | ||
404 | "pci8086,704", | ||
405 | "pciclass048000", | ||
406 | "pciclass0480"; | ||
407 | |||
408 | reg = <0x19000 0x0 0x0 0x0 0x0>; | ||
409 | }; | ||
410 | }; | ||
411 | |||
412 | isa@1f,0 { | ||
413 | #address-cells = <2>; | ||
414 | #size-cells = <1>; | ||
415 | compatible = "isa"; | ||
416 | reg = <0xf800 0x0 0x0 0x0 0x0>; | ||
417 | ranges = <1 0 0 0 0 0x100>; | ||
418 | |||
419 | rtc@70 { | ||
420 | compatible = "intel,ce4100-rtc", "motorola,mc146818"; | ||
421 | interrupts = <8 3>; | ||
422 | interrupt-parent = <&ioapic1>; | ||
423 | ctrl-reg = <2>; | ||
424 | freq-reg = <0x26>; | ||
425 | reg = <1 0x70 2>; | ||
426 | }; | ||
427 | }; | ||
428 | }; | ||
429 | }; | ||
430 | }; | ||