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-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/mmconf-fam10h_64.c215
-rw-r--r--arch/x86/kernel/setup_64.c216
3 files changed, 226 insertions, 207 deletions
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 90e092d0af0c..815b650977b4 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -99,4 +99,6 @@ ifeq ($(CONFIG_X86_64),y)
99 obj-$(CONFIG_GART_IOMMU) += pci-gart_64.o aperture_64.o 99 obj-$(CONFIG_GART_IOMMU) += pci-gart_64.o aperture_64.o
100 obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o 100 obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o
101 obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o 101 obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o
102
103 obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
102endif 104endif
diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c
new file mode 100644
index 000000000000..37897920ec65
--- /dev/null
+++ b/arch/x86/kernel/mmconf-fam10h_64.c
@@ -0,0 +1,215 @@
1/*
2 * AMD Family 10h mmconfig enablement
3 */
4
5#include <linux/types.h>
6#include <linux/mm.h>
7#include <linux/string.h>
8#include <linux/pci.h>
9#include <asm/pci-direct.h>
10#include <linux/sort.h>
11#include <asm/io.h>
12#include <asm/msr.h>
13#include <asm/acpi.h>
14
15struct pci_hostbridge_probe {
16 u32 bus;
17 u32 slot;
18 u32 vendor;
19 u32 device;
20};
21
22static u64 __cpuinitdata fam10h_pci_mmconf_base;
23static int __cpuinitdata fam10h_pci_mmconf_base_status;
24
25static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
26 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
27 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
28};
29
30struct range {
31 u64 start;
32 u64 end;
33};
34
35static int __cpuinit cmp_range(const void *x1, const void *x2)
36{
37 const struct range *r1 = x1;
38 const struct range *r2 = x2;
39 int start1, start2;
40
41 start1 = r1->start >> 32;
42 start2 = r2->start >> 32;
43
44 return start1 - start2;
45}
46
47/*[47:0] */
48/* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
49#define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
50#define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
51static void __cpuinit get_fam10h_pci_mmconf_base(void)
52{
53 int i;
54 unsigned bus;
55 unsigned slot;
56 int found;
57
58 u64 val;
59 u32 address;
60 u64 tom2;
61 u64 base = FAM10H_PCI_MMCONF_BASE;
62
63 int hi_mmio_num;
64 struct range range[8];
65
66 /* only try to get setting from BSP */
67 /* -1 or 1 */
68 if (fam10h_pci_mmconf_base_status)
69 return;
70
71 if (!early_pci_allowed())
72 goto fail;
73
74 found = 0;
75 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
76 u32 id;
77 u16 device;
78 u16 vendor;
79
80 bus = pci_probes[i].bus;
81 slot = pci_probes[i].slot;
82 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
83
84 vendor = id & 0xffff;
85 device = (id>>16) & 0xffff;
86 if (pci_probes[i].vendor == vendor &&
87 pci_probes[i].device == device) {
88 found = 1;
89 break;
90 }
91 }
92
93 if (!found)
94 goto fail;
95
96 /* SYS_CFG */
97 address = MSR_K8_SYSCFG;
98 rdmsrl(address, val);
99
100 /* TOP_MEM2 is not enabled? */
101 if (!(val & (1<<21))) {
102 tom2 = 0;
103 } else {
104 /* TOP_MEM2 */
105 address = MSR_K8_TOP_MEM2;
106 rdmsrl(address, val);
107 tom2 = val & (0xffffULL<<32);
108 }
109
110 if (base <= tom2)
111 base = tom2 + (1ULL<<32);
112
113 /*
114 * need to check if the range is in the high mmio range that is
115 * above 4G
116 */
117 hi_mmio_num = 0;
118 for (i = 0; i < 8; i++) {
119 u32 reg;
120 u64 start;
121 u64 end;
122 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
123 if (!(reg & 3))
124 continue;
125
126 start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
127 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
128 end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
129
130 if (!end)
131 continue;
132
133 range[hi_mmio_num].start = start;
134 range[hi_mmio_num].end = end;
135 hi_mmio_num++;
136 }
137
138 if (!hi_mmio_num)
139 goto out;
140
141 /* sort the range */
142 sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
143
144 if (range[hi_mmio_num - 1].end < base)
145 goto out;
146 if (range[0].start > base)
147 goto out;
148
149 /* need to find one window */
150 base = range[0].start - (1ULL << 32);
151 if ((base > tom2) && BASE_VALID(base))
152 goto out;
153 base = range[hi_mmio_num - 1].end + (1ULL << 32);
154 if ((base > tom2) && BASE_VALID(base))
155 goto out;
156 /* need to find window between ranges */
157 if (hi_mmio_num > 1)
158 for (i = 0; i < hi_mmio_num - 1; i++) {
159 if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
160 base = range[i].end + (1ULL << 32);
161 if ((base > tom2) && BASE_VALID(base))
162 goto out;
163 }
164 }
165
166fail:
167 fam10h_pci_mmconf_base_status = -1;
168 return;
169out:
170 fam10h_pci_mmconf_base = base;
171 fam10h_pci_mmconf_base_status = 1;
172}
173
174void __cpuinit fam10h_check_enable_mmcfg(void)
175{
176 u64 val;
177 u32 address;
178
179 address = MSR_FAM10H_MMIO_CONF_BASE;
180 rdmsrl(address, val);
181
182 /* try to make sure that AP's setting is identical to BSP setting */
183 if (val & FAM10H_MMIO_CONF_ENABLE) {
184 unsigned busnbits;
185 busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
186 FAM10H_MMIO_CONF_BUSRANGE_MASK;
187
188 /* only trust the one handle 256 buses, if acpi=off */
189 if (!acpi_pci_disabled || busnbits >= 8) {
190 u64 base;
191 base = val & (0xffffULL << 32);
192 if (fam10h_pci_mmconf_base_status <= 0) {
193 fam10h_pci_mmconf_base = base;
194 fam10h_pci_mmconf_base_status = 1;
195 return;
196 } else if (fam10h_pci_mmconf_base == base)
197 return;
198 }
199 }
200
201 /*
202 * if it is not enabled, try to enable it and assume only one segment
203 * with 256 buses
204 */
205 get_fam10h_pci_mmconf_base();
206 if (fam10h_pci_mmconf_base_status <= 0)
207 return;
208
209 printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
210 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
211 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
212 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
213 FAM10H_MMIO_CONF_ENABLE;
214 wrmsrl(address, val);
215}
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 5e269a5dde2e..d8a9ee752fb3 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -579,212 +579,6 @@ static int __cpuinit nearby_node(int apicid)
579} 579}
580#endif 580#endif
581 581
582#ifdef CONFIG_PCI_MMCONFIG
583struct pci_hostbridge_probe {
584 u32 bus;
585 u32 slot;
586 u32 vendor;
587 u32 device;
588};
589
590static u64 __cpuinitdata fam10h_pci_mmconf_base;
591static int __cpuinitdata fam10h_pci_mmconf_base_status;
592
593static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
594 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
595 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
596};
597
598struct range {
599 u64 start;
600 u64 end;
601};
602
603static int __cpuinit cmp_range(const void *x1, const void *x2)
604{
605 const struct range *r1 = x1;
606 const struct range *r2 = x2;
607 int start1, start2;
608
609 start1 = r1->start >> 32;
610 start2 = r2->start >> 32;
611
612 return start1 - start2;
613}
614
615/*[47:0] */
616/* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
617#define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
618#define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
619static void __cpuinit get_fam10h_pci_mmconf_base(void)
620{
621 int i;
622 unsigned bus;
623 unsigned slot;
624 int found;
625
626 u64 val;
627 u32 address;
628 u64 tom2;
629 u64 base = FAM10H_PCI_MMCONF_BASE;
630
631 int hi_mmio_num;
632 struct range range[8];
633
634 /* only try to get setting from BSP */
635 /* -1 or 1 */
636 if (fam10h_pci_mmconf_base_status)
637 return;
638
639 if (!early_pci_allowed())
640 goto fail;
641
642 found = 0;
643 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
644 u32 id;
645 u16 device;
646 u16 vendor;
647
648 bus = pci_probes[i].bus;
649 slot = pci_probes[i].slot;
650 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
651
652 vendor = id & 0xffff;
653 device = (id>>16) & 0xffff;
654 if (pci_probes[i].vendor == vendor &&
655 pci_probes[i].device == device) {
656 found = 1;
657 break;
658 }
659 }
660
661 if (!found)
662 goto fail;
663
664 /* SYS_CFG */
665 address = MSR_K8_SYSCFG;
666 rdmsrl(address, val);
667
668 /* TOP_MEM2 is not enabled? */
669 if (!(val & (1<<21))) {
670 tom2 = 0;
671 } else {
672 /* TOP_MEM2 */
673 address = MSR_K8_TOP_MEM2;
674 rdmsrl(address, val);
675 tom2 = val & (0xffffULL<<32);
676 }
677
678 if (base <= tom2)
679 base = tom2 + (1ULL<<32);
680
681 /*
682 * need to check if the range is in the high mmio range that is
683 * above 4G
684 */
685 hi_mmio_num = 0;
686 for (i = 0; i < 8; i++) {
687 u32 reg;
688 u64 start;
689 u64 end;
690 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
691 if (!(reg & 3))
692 continue;
693
694 start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
695 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
696 end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
697
698 if (!end)
699 continue;
700
701 range[hi_mmio_num].start = start;
702 range[hi_mmio_num].end = end;
703 hi_mmio_num++;
704 }
705
706 if (!hi_mmio_num)
707 goto out;
708
709 /* sort the range */
710 sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
711
712 if (range[hi_mmio_num - 1].end < base)
713 goto out;
714 if (range[0].start > base)
715 goto out;
716
717 /* need to find one window */
718 base = range[0].start - (1ULL << 32);
719 if ((base > tom2) && BASE_VALID(base))
720 goto out;
721 base = range[hi_mmio_num - 1].end + (1ULL << 32);
722 if ((base > tom2) && BASE_VALID(base))
723 goto out;
724 /* need to find window between ranges */
725 if (hi_mmio_num > 1)
726 for (i = 0; i < hi_mmio_num - 1; i++) {
727 if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
728 base = range[i].end + (1ULL << 32);
729 if ((base > tom2) && BASE_VALID(base))
730 goto out;
731 }
732 }
733
734fail:
735 fam10h_pci_mmconf_base_status = -1;
736 return;
737out:
738 fam10h_pci_mmconf_base = base;
739 fam10h_pci_mmconf_base_status = 1;
740}
741#endif
742
743static void __cpuinit fam10h_check_enable_mmcfg(struct cpuinfo_x86 *c)
744{
745#ifdef CONFIG_PCI_MMCONFIG
746 u64 val;
747 u32 address;
748
749 address = MSR_FAM10H_MMIO_CONF_BASE;
750 rdmsrl(address, val);
751
752 /* try to make sure that AP's setting is identical to BSP setting */
753 if (val & FAM10H_MMIO_CONF_ENABLE) {
754 unsigned busnbits;
755 busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
756 FAM10H_MMIO_CONF_BUSRANGE_MASK;
757
758 /* only trust the one handle 256 buses, if acpi=off */
759 if (!acpi_pci_disabled || busnbits >= 8) {
760 u64 base;
761 base = val & (0xffffULL << 32);
762 if (fam10h_pci_mmconf_base_status <= 0) {
763 fam10h_pci_mmconf_base = base;
764 fam10h_pci_mmconf_base_status = 1;
765 return;
766 } else if (fam10h_pci_mmconf_base == base)
767 return;
768 }
769 }
770
771 /*
772 * if it is not enabled, try to enable it and assume only one segment
773 * with 256 buses
774 */
775 get_fam10h_pci_mmconf_base();
776 if (fam10h_pci_mmconf_base_status <= 0)
777 return;
778
779 printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
780 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
781 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
782 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
783 FAM10H_MMIO_CONF_ENABLE;
784 wrmsrl(address, val);
785#endif
786}
787
788/* 582/*
789 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 583 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
790 * Assumes number of cores is a power of two. 584 * Assumes number of cores is a power of two.
@@ -903,6 +697,14 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
903 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 697 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
904} 698}
905 699
700#ifdef CONFIG_PCI_MMCONFIG
701extern void __cpuinit fam10h_check_enable_mmcfg(void);
702#else
703void __cpuinit fam10h_check_enable_mmcfg(void)
704{
705}
706#endif
707
906static void __cpuinit init_amd(struct cpuinfo_x86 *c) 708static void __cpuinit init_amd(struct cpuinfo_x86 *c)
907{ 709{
908 unsigned level; 710 unsigned level;
@@ -969,7 +771,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
969 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 771 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
970 772
971 if (c->x86 == 0x10) 773 if (c->x86 == 0x10)
972 fam10h_check_enable_mmcfg(c); 774 fam10h_check_enable_mmcfg();
973 775
974 if (amd_apic_timer_broken()) 776 if (amd_apic_timer_broken())
975 disable_apic_timer = 1; 777 disable_apic_timer = 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 05:04:46 -0500