diff options
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/acpi/sleep.c | 4 | ||||
-rw-r--r-- | arch/x86/kernel/apic.c | 2 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/cpufreq/Kconfig | 11 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 15 | ||||
-rw-r--r-- | arch/x86/kernel/entry_64.S | 1 | ||||
-rw-r--r-- | arch/x86/kernel/io_apic.c | 5 | ||||
-rw-r--r-- | arch/x86/kernel/irqinit_32.c | 12 |
7 files changed, 22 insertions, 28 deletions
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 707c1f6f95fa..a60c1f3bcb87 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c | |||
@@ -156,11 +156,11 @@ static int __init acpi_sleep_setup(char *str) | |||
156 | #ifdef CONFIG_HIBERNATION | 156 | #ifdef CONFIG_HIBERNATION |
157 | if (strncmp(str, "s4_nohwsig", 10) == 0) | 157 | if (strncmp(str, "s4_nohwsig", 10) == 0) |
158 | acpi_no_s4_hw_signature(); | 158 | acpi_no_s4_hw_signature(); |
159 | if (strncmp(str, "s4_nonvs", 8) == 0) | ||
160 | acpi_s4_no_nvs(); | ||
159 | #endif | 161 | #endif |
160 | if (strncmp(str, "old_ordering", 12) == 0) | 162 | if (strncmp(str, "old_ordering", 12) == 0) |
161 | acpi_old_suspend_ordering(); | 163 | acpi_old_suspend_ordering(); |
162 | if (strncmp(str, "s4_nonvs", 8) == 0) | ||
163 | acpi_s4_no_nvs(); | ||
164 | str = strchr(str, ','); | 164 | str = strchr(str, ','); |
165 | if (str != NULL) | 165 | if (str != NULL) |
166 | str += strspn(str, ", \t"); | 166 | str += strspn(str, ", \t"); |
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index 4b6df2469fe3..115449f869ee 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c | |||
@@ -1436,7 +1436,7 @@ static int __init detect_init_APIC(void) | |||
1436 | switch (boot_cpu_data.x86_vendor) { | 1436 | switch (boot_cpu_data.x86_vendor) { |
1437 | case X86_VENDOR_AMD: | 1437 | case X86_VENDOR_AMD: |
1438 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | 1438 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
1439 | (boot_cpu_data.x86 == 15)) | 1439 | (boot_cpu_data.x86 >= 15)) |
1440 | break; | 1440 | break; |
1441 | goto no_apic; | 1441 | goto no_apic; |
1442 | case X86_VENDOR_INTEL: | 1442 | case X86_VENDOR_INTEL: |
diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig index efae3b22a0ff..65792c2cc462 100644 --- a/arch/x86/kernel/cpu/cpufreq/Kconfig +++ b/arch/x86/kernel/cpu/cpufreq/Kconfig | |||
@@ -245,17 +245,6 @@ config X86_E_POWERSAVER | |||
245 | 245 | ||
246 | comment "shared options" | 246 | comment "shared options" |
247 | 247 | ||
248 | config X86_ACPI_CPUFREQ_PROC_INTF | ||
249 | bool "/proc/acpi/processor/../performance interface (deprecated)" | ||
250 | depends on PROC_FS | ||
251 | depends on X86_ACPI_CPUFREQ || X86_POWERNOW_K7_ACPI || X86_POWERNOW_K8_ACPI | ||
252 | help | ||
253 | This enables the deprecated /proc/acpi/processor/../performance | ||
254 | interface. While it is helpful for debugging, the generic, | ||
255 | cross-architecture cpufreq interfaces should be used. | ||
256 | |||
257 | If in doubt, say N. | ||
258 | |||
259 | config X86_SPEEDSTEP_LIB | 248 | config X86_SPEEDSTEP_LIB |
260 | tristate | 249 | tristate |
261 | default (X86_SPEEDSTEP_ICH || X86_SPEEDSTEP_SMI || X86_P4_CLOCKMOD) | 250 | default (X86_SPEEDSTEP_ICH || X86_SPEEDSTEP_SMI || X86_P4_CLOCKMOD) |
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 48533d77be78..da299eb85fc0 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
@@ -36,8 +36,11 @@ static struct _cache_table cache_table[] __cpuinitdata = | |||
36 | { | 36 | { |
37 | { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */ | 37 | { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */ |
38 | { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */ | 38 | { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */ |
39 | { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */ | ||
39 | { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */ | 40 | { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */ |
40 | { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */ | 41 | { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */ |
42 | { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */ | ||
43 | { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */ | ||
41 | { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ | 44 | { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
42 | { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */ | 45 | { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
43 | { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */ | 46 | { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
@@ -85,6 +88,18 @@ static struct _cache_table cache_table[] __cpuinitdata = | |||
85 | { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */ | 88 | { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */ |
86 | { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */ | 89 | { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */ |
87 | { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */ | 90 | { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */ |
91 | { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */ | ||
92 | { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */ | ||
93 | { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */ | ||
94 | { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */ | ||
95 | { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */ | ||
96 | { 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */ | ||
97 | { 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */ | ||
98 | { 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */ | ||
99 | { 0xde, LVL_3, 8192 }, /* 12-way set assoc, 64 byte line size */ | ||
100 | { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */ | ||
101 | { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */ | ||
102 | { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */ | ||
88 | { 0x00, 0, 0} | 103 | { 0x00, 0, 0} |
89 | }; | 104 | }; |
90 | 105 | ||
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index e28c7a987793..a1346217e43c 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S | |||
@@ -346,6 +346,7 @@ ENTRY(save_args) | |||
346 | popq_cfi %rax /* move return address... */ | 346 | popq_cfi %rax /* move return address... */ |
347 | mov %gs:pda_irqstackptr,%rsp | 347 | mov %gs:pda_irqstackptr,%rsp |
348 | EMPTY_FRAME 0 | 348 | EMPTY_FRAME 0 |
349 | pushq_cfi %rbp /* backlink for unwinder */ | ||
349 | pushq_cfi %rax /* ... to the new stack */ | 350 | pushq_cfi %rax /* ... to the new stack */ |
350 | /* | 351 | /* |
351 | * We entered an interrupt context - irqs are off: | 352 | * We entered an interrupt context - irqs are off: |
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c index 1c4a1302536c..9b0c480c383b 100644 --- a/arch/x86/kernel/io_apic.c +++ b/arch/x86/kernel/io_apic.c | |||
@@ -2528,14 +2528,15 @@ static void irq_complete_move(struct irq_desc **descp) | |||
2528 | 2528 | ||
2529 | vector = ~get_irq_regs()->orig_ax; | 2529 | vector = ~get_irq_regs()->orig_ax; |
2530 | me = smp_processor_id(); | 2530 | me = smp_processor_id(); |
2531 | |||
2532 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) { | ||
2531 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | 2533 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2532 | *descp = desc = move_irq_desc(desc, me); | 2534 | *descp = desc = move_irq_desc(desc, me); |
2533 | /* get the new one */ | 2535 | /* get the new one */ |
2534 | cfg = desc->chip_data; | 2536 | cfg = desc->chip_data; |
2535 | #endif | 2537 | #endif |
2536 | |||
2537 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) | ||
2538 | send_cleanup_vector(cfg); | 2538 | send_cleanup_vector(cfg); |
2539 | } | ||
2539 | } | 2540 | } |
2540 | #else | 2541 | #else |
2541 | static inline void irq_complete_move(struct irq_desc **descp) {} | 2542 | static inline void irq_complete_move(struct irq_desc **descp) {} |
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c index 1507ad4e674d..10a09c2f1828 100644 --- a/arch/x86/kernel/irqinit_32.c +++ b/arch/x86/kernel/irqinit_32.c | |||
@@ -78,15 +78,6 @@ void __init init_ISA_irqs(void) | |||
78 | } | 78 | } |
79 | } | 79 | } |
80 | 80 | ||
81 | /* | ||
82 | * IRQ2 is cascade interrupt to second interrupt controller | ||
83 | */ | ||
84 | static struct irqaction irq2 = { | ||
85 | .handler = no_action, | ||
86 | .mask = CPU_MASK_NONE, | ||
87 | .name = "cascade", | ||
88 | }; | ||
89 | |||
90 | DEFINE_PER_CPU(vector_irq_t, vector_irq) = { | 81 | DEFINE_PER_CPU(vector_irq_t, vector_irq) = { |
91 | [0 ... IRQ0_VECTOR - 1] = -1, | 82 | [0 ... IRQ0_VECTOR - 1] = -1, |
92 | [IRQ0_VECTOR] = 0, | 83 | [IRQ0_VECTOR] = 0, |
@@ -178,9 +169,6 @@ void __init native_init_IRQ(void) | |||
178 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | 169 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
179 | #endif | 170 | #endif |
180 | 171 | ||
181 | if (!acpi_ioapic) | ||
182 | setup_irq(2, &irq2); | ||
183 | |||
184 | /* setup after call gates are initialised (usually add in | 172 | /* setup after call gates are initialised (usually add in |
185 | * the architecture specific gates) | 173 | * the architecture specific gates) |
186 | */ | 174 | */ |