8 files changed, 72 insertions, 47 deletions

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index b88645191fe5..895604f2e916 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1521,6 +1521,8 @@ static int __init init_hw_perf_events(void)
 
         pr_cont("%s PMU driver.\n", x86_pmu.name);
 
+        x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
+
         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
                 quirk->func();
 
@@ -1534,7 +1536,6 @@ static int __init init_hw_perf_events(void)
                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
                                    0, x86_pmu.num_counters, 0, 0);
 
-        x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
 
         if (x86_pmu.event_attrs)
@@ -1820,9 +1821,12 @@ static ssize_t set_attr_rdpmc(struct device *cdev,
         if (ret)
                 return ret;
 
+        if (x86_pmu.attr_rdpmc_broken)
+                return -ENOTSUPP;
+
         if (!!val != !!x86_pmu.attr_rdpmc) {
                 x86_pmu.attr_rdpmc = !!val;
-                smp_call_function(change_rdpmc, (void *)val, 1);
+                on_each_cpu(change_rdpmc, (void *)val, 1);
         }
 
         return count;
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index c1a861829d81..4972c244d0bc 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -409,6 +409,7 @@ struct x86_pmu {
         /*
          * sysfs attrs
          */
+        int             attr_rdpmc_broken;
         int             attr_rdpmc;
         struct attribute **format_attrs;
         struct attribute **event_attrs;
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 0fa4f242f050..aa333d966886 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1361,10 +1361,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         intel_pmu_disable_all();
         handled = intel_pmu_drain_bts_buffer();
         status = intel_pmu_get_status();
-        if (!status) {
-                intel_pmu_enable_all(0);
-                return handled;
-        }
+        if (!status)
+                goto done;
 
         loops = 0;
 again:
@@ -2310,10 +2308,7 @@ __init int intel_pmu_init(void)
         if (version > 1)
                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
 
-        /*
-         * v2 and above have a perf capabilities MSR
-         */
-        if (version > 1) {
+        if (boot_cpu_has(X86_FEATURE_PDCM)) {
                 u64 capabilities;
 
                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 29c248799ced..c88f7f4b03ee 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -501,8 +501,11 @@ static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
         SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
                                   SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
@@ -1178,10 +1181,15 @@ static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
         SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
                                   SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
         SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
-        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
         SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index b1e2fe115323..7c1a0c07b607 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -231,31 +231,49 @@ static __initconst const struct x86_pmu p6_pmu = {
 
 };
 
+static __init void p6_pmu_rdpmc_quirk(void)
+{
+        if (boot_cpu_data.x86_mask < 9) {
+                /*
+                 * PPro erratum 26; fixed in stepping 9 and above.
+                 */
+                pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
+                x86_pmu.attr_rdpmc_broken = 1;
+                x86_pmu.attr_rdpmc = 0;
+        }
+}
+
 __init int p6_pmu_init(void)
 {
+        x86_pmu = p6_pmu;
+
         switch (boot_cpu_data.x86_model) {
-        case 1:
-        case 3:  /* Pentium Pro */
-        case 5:
-        case 6:  /* Pentium II */
-        case 7:
-        case 8:
-        case 11: /* Pentium III */
-        case 9:
-        case 13:
-                /* Pentium M */
+        case  1: /* Pentium Pro */
+                x86_add_quirk(p6_pmu_rdpmc_quirk);
+                break;
+
+        case  3: /* Pentium II - Klamath */
+        case  5: /* Pentium II - Deschutes */
+        case  6: /* Pentium II - Mendocino */
                 break;
+
+        case  7: /* Pentium III - Katmai */
+        case  8: /* Pentium III - Coppermine */
+        case 10: /* Pentium III Xeon */
+        case 11: /* Pentium III - Tualatin */
+                break;
+
+        case  9: /* Pentium M - Banias */
+        case 13: /* Pentium M - Dothan */
+                break;
+
         default:
-                pr_cont("unsupported p6 CPU model %d ",
-                        boot_cpu_data.x86_model);
+                pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
                 return -ENODEV;
         }
 
-        x86_pmu = p6_pmu;
-
         memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
                 sizeof(hw_cache_event_ids));
 
-
         return 0;
 }
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 872079a67e4d..f7d0672481fd 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -100,8 +100,10 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
         flag |= __GFP_ZERO;
 again:
         page = NULL;
-        if (!(flag & GFP_ATOMIC))
+        /* CMA can be used only in the context which permits sleeping */
+        if (flag & __GFP_WAIT)
                 page = dma_alloc_from_contiguous(dev, count, get_order(size));
+        /* fallback */
         if (!page)
                 page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
         if (!page)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index acb3b606613e..cfbe99f88830 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -653,13 +653,10 @@ unsigned long native_calibrate_tsc(void)
 
         /* Calibrate TSC using MSR for Intel Atom SoCs */
         local_irq_save(flags);
-        i = try_msr_calibrate_tsc(&fast_calibrate);
+        fast_calibrate = try_msr_calibrate_tsc();
         local_irq_restore(flags);
-        if (i >= 0) {
-                if (i == 0)
-                        pr_warn("Fast TSC calibration using MSR failed\n");
+        if (fast_calibrate)
                 return fast_calibrate;
-        }
 
         local_irq_save(flags);
         fast_calibrate = quick_pit_calibrate();
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 8b5434f4389f..92ae6acac8a7 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -53,7 +53,7 @@ static struct freq_desc freq_desc_tables[] = {
         /* TNG */
         { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
         /* VLV2 */
-        { 6, 0x37, 1, { 0, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+        { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
         /* ANN */
         { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
 };
@@ -77,21 +77,18 @@ static int match_cpu(u8 family, u8 model)
 
 /*
  * Do MSR calibration only for known/supported CPUs.
- * Return values:
- * -1: CPU is unknown/unsupported for MSR based calibration
- *  0: CPU is known/supported, but calibration failed
- *  1: CPU is known/supported, and calibration succeeded
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
  */
-int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
+unsigned long try_msr_calibrate_tsc(void)
 {
-        int cpu_index;
         u32 lo, hi, ratio, freq_id, freq;
+        unsigned long res;
+        int cpu_index;
 
         cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
         if (cpu_index < 0)
-                return -1;
-
-        *fast_calibrate = 0;
+                return 0;
 
         if (freq_desc_tables[cpu_index].msr_plat) {
                 rdmsr(MSR_PLATFORM_INFO, lo, hi);
@@ -103,7 +100,7 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
         pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
 
         if (!ratio)
-                return 0;
+                goto fail;
 
         /* Get FSB FREQ ID */
         rdmsr(MSR_FSB_FREQ, lo, hi);
@@ -112,16 +109,19 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
         pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
                                 freq_id, freq);
         if (!freq)
-                return 0;
+                goto fail;
 
         /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
-        *fast_calibrate = freq * ratio;
-        pr_info("TSC runs at %lu KHz\n", *fast_calibrate);
+        res = freq * ratio;
+        pr_info("TSC runs at %lu KHz\n", res);
 
 #ifdef CONFIG_X86_LOCAL_APIC
         lapic_timer_frequency = (freq * 1000) / HZ;
         pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
 #endif
+        return res;
 
-        return 1;
+fail:
+        pr_warn("Fast TSC calibration using MSR failed\n");
+        return 0;
 }