1 files changed, 309 insertions, 246 deletions

diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 30d94d1d5f5f..77fb87bf6e5a 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -30,6 +30,7 @@
 #include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/pci.h>
+#include <linux/efi.h>
 #include <linux/acpi.h>
 #include <linux/kallsyms.h>
 #include <linux/edd.h>
@@ -39,10 +40,13 @@
 #include <linux/dmi.h>
 #include <linux/dma-mapping.h>
 #include <linux/ctype.h>
+#include <linux/uaccess.h>
+#include <linux/init_ohci1394_dma.h>
 
 #include <asm/mtrr.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
+#include <asm/vsyscall.h>
 #include <asm/io.h>
 #include <asm/smp.h>
 #include <asm/msr.h>
@@ -50,6 +54,7 @@
 #include <video/edid.h>
 #include <asm/e820.h>
 #include <asm/dma.h>
+#include <asm/gart.h>
 #include <asm/mpspec.h>
 #include <asm/mmu_context.h>
 #include <asm/proto.h>
@@ -59,6 +64,15 @@
 #include <asm/sections.h>
 #include <asm/dmi.h>
 #include <asm/cacheflush.h>
+#include <asm/mce.h>
+#include <asm/ds.h>
+#include <asm/topology.h>
+
+#ifdef CONFIG_PARAVIRT
+#include <asm/paravirt.h>
+#else
+#define ARCH_SETUP
+#endif
 
 /*
  * Machine setup..
@@ -67,6 +81,8 @@
 struct cpuinfo_x86 boot_cpu_data __read_mostly;
 EXPORT_SYMBOL(boot_cpu_data);
 
+__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
+
 unsigned long mmu_cr4_features;
 
 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
@@ -76,7 +92,7 @@ unsigned long saved_video_mode;
 
 int force_mwait __cpuinitdata;
 
-/* 
+/*
  * Early DMI memory
  */
 int dmi_alloc_index;
@@ -122,25 +138,27 @@ struct resource standard_io_resources[] = {
 
 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 
-struct resource data_resource = {
+static struct resource data_resource = {
         .name = "Kernel data",
         .start = 0,
         .end = 0,
         .flags = IORESOURCE_RAM,
 };
-struct resource code_resource = {
+static struct resource code_resource = {
         .name = "Kernel code",
         .start = 0,
         .end = 0,
         .flags = IORESOURCE_RAM,
 };
-struct resource bss_resource = {
+static struct resource bss_resource = {
         .name = "Kernel bss",
         .start = 0,
         .end = 0,
         .flags = IORESOURCE_RAM,
 };
 
+static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
+
 #ifdef CONFIG_PROC_VMCORE
 /* elfcorehdr= specifies the location of elf core header
  * stored by the crashed kernel. This option will be passed
@@ -166,12 +184,12 @@ contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
         if (bootmap == -1L)
-                panic("Cannot find bootmem map of size %ld\n",bootmap_size);
+                panic("Cannot find bootmem map of size %ld\n", bootmap_size);
         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
         e820_register_active_regions(0, start_pfn, end_pfn);
         free_bootmem_with_active_regions(0, end_pfn);
         reserve_bootmem(bootmap, bootmap_size);
-} 
+}
 #endif
 
 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
@@ -205,7 +223,8 @@ static void __init reserve_crashkernel(void)
         unsigned long long crash_size, crash_base;
         int ret;
 
-        free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
+        free_mem =
+                ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
 
         ret = parse_crashkernel(boot_command_line, free_mem,
                         &crash_size, &crash_base);
@@ -229,33 +248,21 @@ static inline void __init reserve_crashkernel(void)
 {}
 #endif
 
-#define EBDA_ADDR_POINTER 0x40E
-
-unsigned __initdata ebda_addr;
-unsigned __initdata ebda_size;
-
-static void discover_ebda(void)
+/* Overridden in paravirt.c if CONFIG_PARAVIRT */
+void __attribute__((weak)) __init memory_setup(void)
 {
-        /*
-         * there is a real-mode segmented pointer pointing to the 
-         * 4K EBDA area at 0x40E
-         */
-        ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
-        ebda_addr <<= 4;
-
-        ebda_size = *(unsigned short *)__va(ebda_addr);
-
-        /* Round EBDA up to pages */
-        if (ebda_size == 0)
-                ebda_size = 1;
-        ebda_size <<= 10;
-        ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
-        if (ebda_size > 64*1024)
-                ebda_size = 64*1024;
+       machine_specific_memory_setup();
 }
 
+/*
+ * setup_arch - architecture-specific boot-time initializations
+ *
+ * Note: On x86_64, fixmaps are ready for use even before this is called.
+ */
 void __init setup_arch(char **cmdline_p)
 {
+        unsigned i;
+
         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 
         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
@@ -269,7 +276,15 @@ void __init setup_arch(char **cmdline_p)
         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 #endif
-        setup_memory_region();
+#ifdef CONFIG_EFI
+        if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
+                     "EL64", 4))
+                efi_enabled = 1;
+#endif
+
+        ARCH_SETUP
+
+        memory_setup();
         copy_edd();
 
         if (!boot_params.hdr.root_flags)
@@ -293,27 +308,47 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
+        if (init_ohci1394_dma_early)
+                init_ohci1394_dma_on_all_controllers();
+#endif
+
         finish_e820_parsing();
 
+        early_gart_iommu_check();
+
         e820_register_active_regions(0, 0, -1UL);
         /*
          * partially used pages are not usable - thus
          * we are rounding upwards:
          */
         end_pfn = e820_end_of_ram();
+        /* update e820 for memory not covered by WB MTRRs */
+        mtrr_bp_init();
+        if (mtrr_trim_uncached_memory(end_pfn)) {
+                e820_register_active_regions(0, 0, -1UL);
+                end_pfn = e820_end_of_ram();
+        }
+
         num_physpages = end_pfn;
 
         check_efer();
 
-        discover_ebda();
-
         init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
+        if (efi_enabled)
+                efi_init();
 
         dmi_scan_machine();
 
+        io_delay_init();
+
 #ifdef CONFIG_SMP
-        /* setup to use the static apicid table during kernel startup */
-        x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
+        /* setup to use the early static init tables during kernel startup */
+        x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
+        x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
+#ifdef CONFIG_NUMA
+        x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
+#endif
 #endif
 
 #ifdef CONFIG_ACPI
@@ -340,48 +375,26 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
 #ifdef CONFIG_NUMA
-        numa_initmem_init(0, end_pfn); 
+        numa_initmem_init(0, end_pfn);
 #else
         contig_initmem_init(0, end_pfn);
 #endif
 
-        /* Reserve direct mapping */
-        reserve_bootmem_generic(table_start << PAGE_SHIFT, 
-                                (table_end - table_start) << PAGE_SHIFT);
-
-        /* reserve kernel */
-        reserve_bootmem_generic(__pa_symbol(&_text),
-                                __pa_symbol(&_end) - __pa_symbol(&_text));
+        early_res_to_bootmem();
 
+#ifdef CONFIG_ACPI_SLEEP
         /*
-         * reserve physical page 0 - it's a special BIOS page on many boxes,
-         * enabling clean reboots, SMP operation, laptop functions.
+         * Reserve low memory region for sleep support.
          */
-        reserve_bootmem_generic(0, PAGE_SIZE);
-
-        /* reserve ebda region */
-        if (ebda_addr)
-                reserve_bootmem_generic(ebda_addr, ebda_size);
-#ifdef CONFIG_NUMA
-        /* reserve nodemap region */
-        if (nodemap_addr)
-                reserve_bootmem_generic(nodemap_addr, nodemap_size);
+       acpi_reserve_bootmem();
 #endif
 
-#ifdef CONFIG_SMP
-        /* Reserve SMP trampoline */
-        reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
-#endif
+        if (efi_enabled)
+                efi_reserve_bootmem();
 
-#ifdef CONFIG_ACPI_SLEEP
        /*
-        * Reserve low memory region for sleep support.
-        */
-       acpi_reserve_bootmem();
-#endif
-        /*
-         * Find and reserve possible boot-time SMP configuration:
-         */
+        * Find and reserve possible boot-time SMP configuration:
+        */
         find_smp_config();
 #ifdef CONFIG_BLK_DEV_INITRD
         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
@@ -395,6 +408,8 @@ void __init setup_arch(char **cmdline_p)
                         initrd_start = ramdisk_image + PAGE_OFFSET;
                         initrd_end = initrd_start+ramdisk_size;
                 } else {
+                        /* Assumes everything on node 0 */
+                        free_bootmem(ramdisk_image, ramdisk_size);
                         printk(KERN_ERR "initrd extends beyond end of memory "
                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
                                ramdisk_end, end_of_mem);
@@ -404,17 +419,10 @@ void __init setup_arch(char **cmdline_p)
 #endif
         reserve_crashkernel();
         paging_init();
+        map_vsyscall();
 
-#ifdef CONFIG_PCI
         early_quirks();
-#endif
 
-        /*
-         * set this early, so we dont allocate cpu0
-         * if MADT list doesnt list BSP first
-         * mpparse.c/MP_processor_info() allocates logical cpu numbers.
-         */
-        cpu_set(0, cpu_present_map);
 #ifdef CONFIG_ACPI
         /*
          * Read APIC and some other early information from ACPI tables.
@@ -430,25 +438,24 @@ void __init setup_arch(char **cmdline_p)
         if (smp_found_config)
                 get_smp_config();
         init_apic_mappings();
+        ioapic_init_mappings();
 
         /*
          * We trust e820 completely. No explicit ROM probing in memory.
-         */
-        e820_reserve_resources(); 
+         */
+        e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
         e820_mark_nosave_regions();
 
-        {
-        unsigned i;
         /* request I/O space for devices used on all i[345]86 PCs */
         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
                 request_resource(&ioport_resource, &standard_io_resources[i]);
-        }
 
         e820_setup_gap();
 
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
-        conswitchp = &vga_con;
+        if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
+                conswitchp = &vga_con;
 #elif defined(CONFIG_DUMMY_CONSOLE)
         conswitchp = &dummy_con;
 #endif
@@ -479,9 +486,10 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 
         if (n >= 0x80000005) {
                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
-                printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
-                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
-                c->x86_cache_size=(ecx>>24)+(edx>>24);
+                printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
+                       "D cache %dK (%d bytes/line)\n",
+                       edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
+                c->x86_cache_size = (ecx>>24) + (edx>>24);
                 /* On K8 L1 TLB is inclusive, so don't count it */
                 c->x86_tlbsize = 0;
         }
@@ -495,11 +503,8 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
                 c->x86_cache_size, ecx & 0xFF);
         }
-
-        if (n >= 0x80000007)
-                cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power); 
         if (n >= 0x80000008) {
-                cpuid(0x80000008, &eax, &dummy, &dummy, &dummy); 
+                cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
                 c->x86_virt_bits = (eax >> 8) & 0xff;
                 c->x86_phys_bits = eax & 0xff;
         }
@@ -508,14 +513,15 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 #ifdef CONFIG_NUMA
 static int nearby_node(int apicid)
 {
-        int i;
+        int i, node;
+
         for (i = apicid - 1; i >= 0; i--) {
-                int node = apicid_to_node[i];
+                node = apicid_to_node[i];
                 if (node != NUMA_NO_NODE && node_online(node))
                         return node;
         }
         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
-                int node = apicid_to_node[i];
+                node = apicid_to_node[i];
                 if (node != NUMA_NO_NODE && node_online(node))
                         return node;
         }
@@ -527,7 +533,7 @@ static int nearby_node(int apicid)
  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  * Assumes number of cores is a power of two.
  */
-static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
+static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
         unsigned bits;
@@ -536,7 +542,54 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
         int node = 0;
         unsigned apicid = hard_smp_processor_id();
 #endif
-        unsigned ecx = cpuid_ecx(0x80000008);
+        bits = c->x86_coreid_bits;
+
+        /* Low order bits define the core id (index of core in socket) */
+        c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
+        /* Convert the APIC ID into the socket ID */
+        c->phys_proc_id = phys_pkg_id(bits);
+
+#ifdef CONFIG_NUMA
+        node = c->phys_proc_id;
+        if (apicid_to_node[apicid] != NUMA_NO_NODE)
+                node = apicid_to_node[apicid];
+        if (!node_online(node)) {
+                /* Two possibilities here:
+                   - The CPU is missing memory and no node was created.
+                   In that case try picking one from a nearby CPU
+                   - The APIC IDs differ from the HyperTransport node IDs
+                   which the K8 northbridge parsing fills in.
+                   Assume they are all increased by a constant offset,
+                   but in the same order as the HT nodeids.
+                   If that doesn't result in a usable node fall back to the
+                   path for the previous case.  */
+
+                int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
+
+                if (ht_nodeid >= 0 &&
+                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
+                        node = apicid_to_node[ht_nodeid];
+                /* Pick a nearby node */
+                if (!node_online(node))
+                        node = nearby_node(apicid);
+        }
+        numa_set_node(cpu, node);
+
+        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+#endif
+#endif
+}
+
+static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_SMP
+        unsigned bits, ecx;
+
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level < 0x80000008)
+                return;
+
+        ecx = cpuid_ecx(0x80000008);
 
         c->x86_max_cores = (ecx & 0xff) + 1;
 
@@ -549,37 +602,8 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
                         bits++;
         }
 
-        /* Low order bits define the core id (index of core in socket) */
-        c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
-        /* Convert the APIC ID into the socket ID */
-        c->phys_proc_id = phys_pkg_id(bits);
-
-#ifdef CONFIG_NUMA
-        node = c->phys_proc_id;
-        if (apicid_to_node[apicid] != NUMA_NO_NODE)
-                node = apicid_to_node[apicid];
-        if (!node_online(node)) {
-                /* Two possibilities here:
-                   - The CPU is missing memory and no node was created.
-                   In that case try picking one from a nearby CPU
-                   - The APIC IDs differ from the HyperTransport node IDs
-                   which the K8 northbridge parsing fills in.
-                   Assume they are all increased by a constant offset,
-                   but in the same order as the HT nodeids.
-                   If that doesn't result in a usable node fall back to the
-                   path for the previous case.  */
-                int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
-                if (ht_nodeid >= 0 &&
-                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
-                        node = apicid_to_node[ht_nodeid];
-                /* Pick a nearby node */
-                if (!node_online(node))
-                        node = nearby_node(apicid);
-        }
-        numa_set_node(cpu, node);
+        c->x86_coreid_bits = bits;
 
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
 #endif
 }
 
@@ -595,8 +619,8 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 static __cpuinit int amd_apic_timer_broken(void)
 {
-        u32 lo, hi;
-        u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
+        u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
+
         switch (eax & CPUID_XFAM) {
         case CPUID_XFAM_K8:
                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
@@ -614,6 +638,15 @@ static __cpuinit int amd_apic_timer_broken(void)
         return 0;
 }
 
+static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+{
+        early_init_amd_mc(c);
+
+        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
+        if (c->x86_power & (1<<8))
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+}
+
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
         unsigned level;
@@ -624,7 +657,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         /*
          * Disable TLB flush filter by setting HWCR.FFDIS on K8
          * bit 6 of msr C001_0015
-         *
+         *
          * Errata 63 for SH-B3 steppings
          * Errata 122 for all steppings (F+ have it disabled by default)
          */
@@ -637,35 +670,32 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 
         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
-        clear_bit(0*32+31, &c->x86_capability);
-        
+        clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
+
         /* On C+ stepping K8 rep microcode works well for copy/memset */
         level = cpuid_eax(1);
-        if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
-                set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
+        if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
+                             level >= 0x0f58))
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
         if (c->x86 == 0x10 || c->x86 == 0x11)
-                set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 
         /* Enable workaround for FXSAVE leak */
         if (c->x86 >= 6)
-                set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 
         level = get_model_name(c);
         if (!level) {
-                switch (c->x86) { 
+                switch (c->x86) {
                 case 15:
                         /* Should distinguish Models here, but this is only
                            a fallback anyways. */
                         strcpy(c->x86_model_id, "Hammer");
-                        break; 
-                } 
-        } 
+                        break;
+                }
+        }
         display_cacheinfo(c);
 
-        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
-        if (c->x86_power & (1<<8))
-                set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
-
         /* Multi core CPU? */
         if (c->extended_cpuid_level >= 0x80000008)
                 amd_detect_cmp(c);
@@ -677,41 +707,38 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 num_cache_leaves = 3;
 
         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
-                set_bit(X86_FEATURE_K8, &c->x86_capability);
-
-        /* RDTSC can be speculated around */
-        clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_K8);
 
-        /* Family 10 doesn't support C states in MWAIT so don't use it */
-        if (c->x86 == 0x10 && !force_mwait)
-                clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
+        /* MFENCE stops RDTSC speculation */
+        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 
         if (amd_apic_timer_broken())
                 disable_apic_timer = 1;
 }
 
-static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
+void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
-        u32     eax, ebx, ecx, edx;
-        int     index_msb, core_bits;
+        u32 eax, ebx, ecx, edx;
+        int index_msb, core_bits;
 
         cpuid(1, &eax, &ebx, &ecx, &edx);
 
 
         if (!cpu_has(c, X86_FEATURE_HT))
                 return;
-        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
+        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
                 goto out;
 
         smp_num_siblings = (ebx & 0xff0000) >> 16;
 
         if (smp_num_siblings == 1) {
                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
-        } else if (smp_num_siblings > 1 ) {
+        } else if (smp_num_siblings > 1) {
 
                 if (smp_num_siblings > NR_CPUS) {
-                        printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
+                        printk(KERN_WARNING "CPU: Unsupported number of "
+                               "siblings %d", smp_num_siblings);
                         smp_num_siblings = 1;
                         return;
                 }
@@ -721,7 +748,7 @@ static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 
                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 
-                index_msb = get_count_order(smp_num_siblings) ;
+                index_msb = get_count_order(smp_num_siblings);
 
                 core_bits = get_count_order(c->x86_max_cores);
 
@@ -730,8 +757,10 @@ static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
         }
 out:
         if ((c->x86_max_cores * smp_num_siblings) > 1) {
-                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
-                printk(KERN_INFO  "CPU: Processor Core ID: %d\n", c->cpu_core_id);
+                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
+                       c->phys_proc_id);
+                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
+                       c->cpu_core_id);
         }
 
 #endif
@@ -773,28 +802,39 @@ static void srat_detect_node(void)
 #endif
 }
 
+static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
+{
+        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
+            (c->x86 == 0x6 && c->x86_model >= 0x0e))
+                set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+}
+
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
         /* Cache sizes */
         unsigned n;
 
         init_intel_cacheinfo(c);
-        if (c->cpuid_level > 9 ) {
+        if (c->cpuid_level > 9) {
                 unsigned eax = cpuid_eax(10);
                 /* Check for version and the number of counters */
                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
-                        set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
         }
 
         if (cpu_has_ds) {
                 unsigned int l1, l2;
                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
                 if (!(l1 & (1<<11)))
-                        set_bit(X86_FEATURE_BTS, c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_BTS);
                 if (!(l1 & (1<<12)))
-                        set_bit(X86_FEATURE_PEBS, c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_PEBS);
         }
 
+
+        if (cpu_has_bts)
+                ds_init_intel(c);
+
         n = c->extended_cpuid_level;
         if (n >= 0x80000008) {
                 unsigned eax = cpuid_eax(0x80000008);
@@ -811,14 +851,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                 c->x86_cache_alignment = c->x86_clflush_size * 2;
         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
             (c->x86 == 0x6 && c->x86_model >= 0x0e))
-                set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
         if (c->x86 == 6)
-                set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
-        if (c->x86 == 15)
-                set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
-        else
-                clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
-        c->x86_max_cores = intel_num_cpu_cores(c);
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+        c->x86_max_cores = intel_num_cpu_cores(c);
 
         srat_detect_node();
 }
@@ -835,18 +872,12 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
                 c->x86_vendor = X86_VENDOR_UNKNOWN;
 }
 
-struct cpu_model_info {
-        int vendor;
-        int family;
-        char *model_names[16];
-};
-
 /* Do some early cpuid on the boot CPU to get some parameter that are
    needed before check_bugs. Everything advanced is in identify_cpu
    below. */
-void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
+static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 {
-        u32 tfms;
+        u32 tfms, xlvl;
 
         c->loops_per_jiffy = loops_per_jiffy;
         c->x86_cache_size = -1;
@@ -857,6 +888,7 @@ void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
         c->x86_clflush_size = 64;
         c->x86_cache_alignment = c->x86_clflush_size;
         c->x86_max_cores = 1;
+        c->x86_coreid_bits = 0;
         c->extended_cpuid_level = 0;
         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 
@@ -865,7 +897,7 @@ void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
               (unsigned int *)&c->x86_vendor_id[0],
               (unsigned int *)&c->x86_vendor_id[8],
               (unsigned int *)&c->x86_vendor_id[4]);
-                
+
         get_cpu_vendor(c);
 
         /* Initialize the standard set of capabilities */
@@ -883,7 +915,7 @@ void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
                         c->x86 += (tfms >> 20) & 0xff;
                 if (c->x86 >= 0x6)
                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
-                if (c->x86_capability[0] & (1<<19)) 
+                if (c->x86_capability[0] & (1<<19))
                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
         } else {
                 /* Have CPUID level 0 only - unheard of */
@@ -893,18 +925,6 @@ void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
         c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
 #endif
-}
-
-/*
- * This does the hard work of actually picking apart the CPU stuff...
- */
-void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
-{
-        int i;
-        u32 xlvl;
-
-        early_identify_cpu(c);
-
         /* AMD-defined flags: level 0x80000001 */
         xlvl = cpuid_eax(0x80000000);
         c->extended_cpuid_level = xlvl;
@@ -925,6 +945,30 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                         c->x86_capability[2] = cpuid_edx(0x80860001);
         }
 
+        c->extended_cpuid_level = cpuid_eax(0x80000000);
+        if (c->extended_cpuid_level >= 0x80000007)
+                c->x86_power = cpuid_edx(0x80000007);
+
+        switch (c->x86_vendor) {
+        case X86_VENDOR_AMD:
+                early_init_amd(c);
+                break;
+        case X86_VENDOR_INTEL:
+                early_init_intel(c);
+                break;
+        }
+
+}
+
+/*
+ * This does the hard work of actually picking apart the CPU stuff...
+ */
+void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
+{
+        int i;
+
+        early_identify_cpu(c);
+
         init_scattered_cpuid_features(c);
 
         c->apicid = phys_pkg_id(0);
@@ -954,8 +998,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                 break;
         }
 
-        select_idle_routine(c);
-        detect_ht(c); 
+        detect_ht(c);
 
         /*
          * On SMP, boot_cpu_data holds the common feature set between
@@ -965,32 +1008,56 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
          */
         if (c != &boot_cpu_data) {
                 /* AND the already accumulated flags with these */
-                for (i = 0 ; i < NCAPINTS ; i++)
+                for (i = 0; i < NCAPINTS; i++)
                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
         }
 
+        /* Clear all flags overriden by options */
+        for (i = 0; i < NCAPINTS; i++)
+                c->x86_capability[i] ^= cleared_cpu_caps[i];
+
 #ifdef CONFIG_X86_MCE
         mcheck_init(c);
 #endif
+        select_idle_routine(c);
+
         if (c != &boot_cpu_data)
                 mtrr_ap_init();
 #ifdef CONFIG_NUMA
         numa_add_cpu(smp_processor_id());
 #endif
+
+}
+
+static __init int setup_noclflush(char *arg)
+{
+        setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
+        return 1;
 }
- 
+__setup("noclflush", setup_noclflush);
 
 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 {
         if (c->x86_model_id[0])
-                printk("%s", c->x86_model_id);
+                printk(KERN_INFO "%s", c->x86_model_id);
 
-        if (c->x86_mask || c->cpuid_level >= 0) 
-                printk(" stepping %02x\n", c->x86_mask);
+        if (c->x86_mask || c->cpuid_level >= 0)
+                printk(KERN_CONT " stepping %02x\n", c->x86_mask);
         else
-                printk("\n");
+                printk(KERN_CONT "\n");
 }
 
+static __init int setup_disablecpuid(char *arg)
+{
+        int bit;
+        if (get_option(&arg, &bit) && bit < NCAPINTS*32)
+                setup_clear_cpu_cap(bit);
+        else
+                return 0;
+        return 1;
+}
+__setup("clearcpuid=", setup_disablecpuid);
+
 /*
  *      Get CPU information for use by the procfs.
  */
@@ -998,9 +1065,9 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 static int show_cpuinfo(struct seq_file *m, void *v)
 {
         struct cpuinfo_x86 *c = v;
-        int cpu = 0;
+        int cpu = 0, i;
 
-        /* 
+        /*
          * These flag bits must match the definitions in <asm/cpufeature.h>.
          * NULL means this bit is undefined or reserved; either way it doesn't
          * have meaning as far as Linux is concerned.  Note that it's important
@@ -1010,10 +1077,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
          */
         static const char *const x86_cap_flags[] = {
                 /* Intel-defined */
-                "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
-                "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
-                "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
-                "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
+                "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
+                "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
+                "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
+                "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
 
                 /* AMD-defined */
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -1080,34 +1147,35 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         cpu = c->cpu_index;
 #endif
 
-        seq_printf(m,"processor\t: %u\n"
-                     "vendor_id\t: %s\n"
-                     "cpu family\t: %d\n"
-                     "model\t\t: %d\n"
-                     "model name\t: %s\n",
-                     (unsigned)cpu,
-                     c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
-                     c->x86,
-                     (int)c->x86_model,
-                     c->x86_model_id[0] ? c->x86_model_id : "unknown");
-        
+        seq_printf(m, "processor\t: %u\n"
+                   "vendor_id\t: %s\n"
+                   "cpu family\t: %d\n"
+                   "model\t\t: %d\n"
+                   "model name\t: %s\n",
+                   (unsigned)cpu,
+                   c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
+                   c->x86,
+                   (int)c->x86_model,
+                   c->x86_model_id[0] ? c->x86_model_id : "unknown");
+
         if (c->x86_mask || c->cpuid_level >= 0)
                 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
         else
                 seq_printf(m, "stepping\t: unknown\n");
-        
-        if (cpu_has(c,X86_FEATURE_TSC)) {
+
+        if (cpu_has(c, X86_FEATURE_TSC)) {
                 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
+
                 if (!freq)
                         freq = cpu_khz;
                 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
-                             freq / 1000, (freq % 1000));
+                           freq / 1000, (freq % 1000));
         }
 
         /* Cache size */
-        if (c->x86_cache_size >= 0) 
+        if (c->x86_cache_size >= 0)
                 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
-        
+
 #ifdef CONFIG_SMP
         if (smp_num_siblings * c->x86_max_cores > 1) {
                 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
@@ -1116,48 +1184,43 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
                 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
         }
-#endif  
+#endif
 
         seq_printf(m,
-                "fpu\t\t: yes\n"
-                "fpu_exception\t: yes\n"
-                "cpuid level\t: %d\n"
-                "wp\t\t: yes\n"
-                "flags\t\t:",
+                   "fpu\t\t: yes\n"
+                   "fpu_exception\t: yes\n"
+                   "cpuid level\t: %d\n"
+                   "wp\t\t: yes\n"
+                   "flags\t\t:",
                    c->cpuid_level);
 
-        { 
-                int i; 
-                for ( i = 0 ; i < 32*NCAPINTS ; i++ )
-                        if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
-                                seq_printf(m, " %s", x86_cap_flags[i]);
-        }
-                
+        for (i = 0; i < 32*NCAPINTS; i++)
+                if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
+                        seq_printf(m, " %s", x86_cap_flags[i]);
+
         seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
                    c->loops_per_jiffy/(500000/HZ),
                    (c->loops_per_jiffy/(5000/HZ)) % 100);
 
-        if (c->x86_tlbsize > 0) 
+        if (c->x86_tlbsize > 0)
                 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
         seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
         seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
 
-        seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", 
+        seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
                    c->x86_phys_bits, c->x86_virt_bits);
 
         seq_printf(m, "power management:");
-        {
-                unsigned i;
-                for (i = 0; i < 32; i++) 
-                        if (c->x86_power & (1 << i)) {
-                                if (i < ARRAY_SIZE(x86_power_flags) &&
-                                        x86_power_flags[i])
-                                        seq_printf(m, "%s%s",
-                                                x86_power_flags[i][0]?" ":"",
-                                                x86_power_flags[i]);
-                                else
-                                        seq_printf(m, " [%d]", i);
-                        }
+        for (i = 0; i < 32; i++) {
+                if (c->x86_power & (1 << i)) {
+                        if (i < ARRAY_SIZE(x86_power_flags) &&
+                            x86_power_flags[i])
+                                seq_printf(m, "%s%s",
+                                           x86_power_flags[i][0]?" ":"",
+                                           x86_power_flags[i]);
+                        else
+                                seq_printf(m, " [%d]", i);
+                }
         }
 
         seq_printf(m, "\n\n");
@@ -1184,8 +1247,8 @@ static void c_stop(struct seq_file *m, void *v)
 {
 }
 
-struct seq_operations cpuinfo_op = {
-        .start =c_start,
+const struct seq_operations cpuinfo_op = {
+        .start = c_start,
         .next = c_next,
         .stop = c_stop,
         .show = show_cpuinfo,