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-rw-r--r--arch/x86/kernel/io_apic_32.c727
1 files changed, 396 insertions, 331 deletions
diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
index 4dc8600d9d20..72ba06314c7b 100644
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic_32.c
@@ -25,6 +25,7 @@
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/sched.h> 27#include <linux/sched.h>
28#include <linux/bootmem.h>
28#include <linux/mc146818rtc.h> 29#include <linux/mc146818rtc.h>
29#include <linux/compiler.h> 30#include <linux/compiler.h>
30#include <linux/acpi.h> 31#include <linux/acpi.h>
@@ -45,6 +46,7 @@
45#include <asm/nmi.h> 46#include <asm/nmi.h>
46#include <asm/msidef.h> 47#include <asm/msidef.h>
47#include <asm/hypertransport.h> 48#include <asm/hypertransport.h>
49#include <asm/setup.h>
48 50
49#include <mach_apic.h> 51#include <mach_apic.h>
50#include <mach_apicdef.h> 52#include <mach_apicdef.h>
@@ -58,7 +60,7 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58static DEFINE_SPINLOCK(ioapic_lock); 60static DEFINE_SPINLOCK(ioapic_lock);
59static DEFINE_SPINLOCK(vector_lock); 61static DEFINE_SPINLOCK(vector_lock);
60 62
61int timer_over_8254 __initdata = 1; 63int timer_through_8259 __initdata;
62 64
63/* 65/*
64 * Is the SiS APIC rmw bug present ? 66 * Is the SiS APIC rmw bug present ?
@@ -72,15 +74,21 @@ int sis_apic_bug = -1;
72int nr_ioapic_registers[MAX_IO_APICS]; 74int nr_ioapic_registers[MAX_IO_APICS];
73 75
74/* I/O APIC entries */ 76/* I/O APIC entries */
75struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 77struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
76int nr_ioapics; 78int nr_ioapics;
77 79
78/* MP IRQ source entries */ 80/* MP IRQ source entries */
79struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; 81struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
80 82
81/* # of MP IRQ source entries */ 83/* # of MP IRQ source entries */
82int mp_irq_entries; 84int mp_irq_entries;
83 85
86#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
87int mp_bus_id_to_type[MAX_MP_BUSSES];
88#endif
89
90DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
91
84static int disable_timer_pin_1 __initdata; 92static int disable_timer_pin_1 __initdata;
85 93
86/* 94/*
@@ -110,7 +118,7 @@ struct io_apic {
110static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) 118static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
111{ 119{
112 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) 120 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
113 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); 121 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
114} 122}
115 123
116static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) 124static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
@@ -239,7 +247,7 @@ static void __init replace_pin_at_irq(unsigned int irq,
239 } 247 }
240} 248}
241 249
242static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) 250static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
243{ 251{
244 struct irq_pin_list *entry = irq_2_pin + irq; 252 struct irq_pin_list *entry = irq_2_pin + irq;
245 unsigned int pin, reg; 253 unsigned int pin, reg;
@@ -259,30 +267,32 @@ static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsign
259} 267}
260 268
261/* mask = 1 */ 269/* mask = 1 */
262static void __mask_IO_APIC_irq (unsigned int irq) 270static void __mask_IO_APIC_irq(unsigned int irq)
263{ 271{
264 __modify_IO_APIC_irq(irq, 0x00010000, 0); 272 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
265} 273}
266 274
267/* mask = 0 */ 275/* mask = 0 */
268static void __unmask_IO_APIC_irq (unsigned int irq) 276static void __unmask_IO_APIC_irq(unsigned int irq)
269{ 277{
270 __modify_IO_APIC_irq(irq, 0, 0x00010000); 278 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
271} 279}
272 280
273/* mask = 1, trigger = 0 */ 281/* mask = 1, trigger = 0 */
274static void __mask_and_edge_IO_APIC_irq (unsigned int irq) 282static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
275{ 283{
276 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); 284 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
285 IO_APIC_REDIR_LEVEL_TRIGGER);
277} 286}
278 287
279/* mask = 0, trigger = 1 */ 288/* mask = 0, trigger = 1 */
280static void __unmask_and_level_IO_APIC_irq (unsigned int irq) 289static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
281{ 290{
282 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); 291 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
292 IO_APIC_REDIR_MASKED);
283} 293}
284 294
285static void mask_IO_APIC_irq (unsigned int irq) 295static void mask_IO_APIC_irq(unsigned int irq)
286{ 296{
287 unsigned long flags; 297 unsigned long flags;
288 298
@@ -291,7 +301,7 @@ static void mask_IO_APIC_irq (unsigned int irq)
291 spin_unlock_irqrestore(&ioapic_lock, flags); 301 spin_unlock_irqrestore(&ioapic_lock, flags);
292} 302}
293 303
294static void unmask_IO_APIC_irq (unsigned int irq) 304static void unmask_IO_APIC_irq(unsigned int irq)
295{ 305{
296 unsigned long flags; 306 unsigned long flags;
297 307
@@ -303,7 +313,7 @@ static void unmask_IO_APIC_irq (unsigned int irq)
303static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) 313static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
304{ 314{
305 struct IO_APIC_route_entry entry; 315 struct IO_APIC_route_entry entry;
306 316
307 /* Check delivery_mode to be sure we're not clearing an SMI pin */ 317 /* Check delivery_mode to be sure we're not clearing an SMI pin */
308 entry = ioapic_read_entry(apic, pin); 318 entry = ioapic_read_entry(apic, pin);
309 if (entry.delivery_mode == dest_SMI) 319 if (entry.delivery_mode == dest_SMI)
@@ -315,7 +325,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
315 ioapic_mask_entry(apic, pin); 325 ioapic_mask_entry(apic, pin);
316} 326}
317 327
318static void clear_IO_APIC (void) 328static void clear_IO_APIC(void)
319{ 329{
320 int apic, pin; 330 int apic, pin;
321 331
@@ -332,7 +342,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
332 struct irq_pin_list *entry = irq_2_pin + irq; 342 struct irq_pin_list *entry = irq_2_pin + irq;
333 unsigned int apicid_value; 343 unsigned int apicid_value;
334 cpumask_t tmp; 344 cpumask_t tmp;
335 345
336 cpus_and(tmp, cpumask, cpu_online_map); 346 cpus_and(tmp, cpumask, cpu_online_map);
337 if (cpus_empty(tmp)) 347 if (cpus_empty(tmp))
338 tmp = TARGET_CPUS; 348 tmp = TARGET_CPUS;
@@ -361,7 +371,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
361# include <linux/kernel_stat.h> /* kstat */ 371# include <linux/kernel_stat.h> /* kstat */
362# include <linux/slab.h> /* kmalloc() */ 372# include <linux/slab.h> /* kmalloc() */
363# include <linux/timer.h> 373# include <linux/timer.h>
364 374
365#define IRQBALANCE_CHECK_ARCH -999 375#define IRQBALANCE_CHECK_ARCH -999
366#define MAX_BALANCED_IRQ_INTERVAL (5*HZ) 376#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
367#define MIN_BALANCED_IRQ_INTERVAL (HZ/2) 377#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
@@ -373,14 +383,14 @@ static int physical_balance __read_mostly;
373static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; 383static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
374 384
375static struct irq_cpu_info { 385static struct irq_cpu_info {
376 unsigned long * last_irq; 386 unsigned long *last_irq;
377 unsigned long * irq_delta; 387 unsigned long *irq_delta;
378 unsigned long irq; 388 unsigned long irq;
379} irq_cpu_data[NR_CPUS]; 389} irq_cpu_data[NR_CPUS];
380 390
381#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) 391#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
382#define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) 392#define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
383#define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) 393#define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
384 394
385#define IDLE_ENOUGH(cpu,now) \ 395#define IDLE_ENOUGH(cpu,now) \
386 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) 396 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
@@ -419,8 +429,8 @@ inside:
419 if (cpu == -1) 429 if (cpu == -1)
420 cpu = NR_CPUS-1; 430 cpu = NR_CPUS-1;
421 } 431 }
422 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || 432 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
423 (search_idle && !IDLE_ENOUGH(cpu,now))); 433 (search_idle && !IDLE_ENOUGH(cpu, now)));
424 434
425 return cpu; 435 return cpu;
426} 436}
@@ -430,15 +440,14 @@ static inline void balance_irq(int cpu, int irq)
430 unsigned long now = jiffies; 440 unsigned long now = jiffies;
431 cpumask_t allowed_mask; 441 cpumask_t allowed_mask;
432 unsigned int new_cpu; 442 unsigned int new_cpu;
433 443
434 if (irqbalance_disabled) 444 if (irqbalance_disabled)
435 return; 445 return;
436 446
437 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); 447 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
438 new_cpu = move(cpu, allowed_mask, now, 1); 448 new_cpu = move(cpu, allowed_mask, now, 1);
439 if (cpu != new_cpu) { 449 if (cpu != new_cpu)
440 set_pending_irq(irq, cpumask_of_cpu(new_cpu)); 450 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
441 }
442} 451}
443 452
444static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) 453static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
@@ -450,14 +459,14 @@ static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
450 if (!irq_desc[j].action) 459 if (!irq_desc[j].action)
451 continue; 460 continue;
452 /* Is it a significant load ? */ 461 /* Is it a significant load ? */
453 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < 462 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
454 useful_load_threshold) 463 useful_load_threshold)
455 continue; 464 continue;
456 balance_irq(i, j); 465 balance_irq(i, j);
457 } 466 }
458 } 467 }
459 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, 468 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
460 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); 469 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
461 return; 470 return;
462} 471}
463 472
@@ -486,22 +495,22 @@ static void do_irq_balance(void)
486 /* Is this an active IRQ or balancing disabled ? */ 495 /* Is this an active IRQ or balancing disabled ? */
487 if (!irq_desc[j].action || irq_balancing_disabled(j)) 496 if (!irq_desc[j].action || irq_balancing_disabled(j))
488 continue; 497 continue;
489 if ( package_index == i ) 498 if (package_index == i)
490 IRQ_DELTA(package_index,j) = 0; 499 IRQ_DELTA(package_index, j) = 0;
491 /* Determine the total count per processor per IRQ */ 500 /* Determine the total count per processor per IRQ */
492 value_now = (unsigned long) kstat_cpu(i).irqs[j]; 501 value_now = (unsigned long) kstat_cpu(i).irqs[j];
493 502
494 /* Determine the activity per processor per IRQ */ 503 /* Determine the activity per processor per IRQ */
495 delta = value_now - LAST_CPU_IRQ(i,j); 504 delta = value_now - LAST_CPU_IRQ(i, j);
496 505
497 /* Update last_cpu_irq[][] for the next time */ 506 /* Update last_cpu_irq[][] for the next time */
498 LAST_CPU_IRQ(i,j) = value_now; 507 LAST_CPU_IRQ(i, j) = value_now;
499 508
500 /* Ignore IRQs whose rate is less than the clock */ 509 /* Ignore IRQs whose rate is less than the clock */
501 if (delta < useful_load_threshold) 510 if (delta < useful_load_threshold)
502 continue; 511 continue;
503 /* update the load for the processor or package total */ 512 /* update the load for the processor or package total */
504 IRQ_DELTA(package_index,j) += delta; 513 IRQ_DELTA(package_index, j) += delta;
505 514
506 /* Keep track of the higher numbered sibling as well */ 515 /* Keep track of the higher numbered sibling as well */
507 if (i != package_index) 516 if (i != package_index)
@@ -527,7 +536,8 @@ static void do_irq_balance(void)
527 max_cpu_irq = ULONG_MAX; 536 max_cpu_irq = ULONG_MAX;
528 537
529tryanothercpu: 538tryanothercpu:
530 /* Look for heaviest loaded processor. 539 /*
540 * Look for heaviest loaded processor.
531 * We may come back to get the next heaviest loaded processor. 541 * We may come back to get the next heaviest loaded processor.
532 * Skip processors with trivial loads. 542 * Skip processors with trivial loads.
533 */ 543 */
@@ -536,7 +546,7 @@ tryanothercpu:
536 for_each_online_cpu(i) { 546 for_each_online_cpu(i) {
537 if (i != CPU_TO_PACKAGEINDEX(i)) 547 if (i != CPU_TO_PACKAGEINDEX(i))
538 continue; 548 continue;
539 if (max_cpu_irq <= CPU_IRQ(i)) 549 if (max_cpu_irq <= CPU_IRQ(i))
540 continue; 550 continue;
541 if (tmp_cpu_irq < CPU_IRQ(i)) { 551 if (tmp_cpu_irq < CPU_IRQ(i)) {
542 tmp_cpu_irq = CPU_IRQ(i); 552 tmp_cpu_irq = CPU_IRQ(i);
@@ -545,8 +555,9 @@ tryanothercpu:
545 } 555 }
546 556
547 if (tmp_loaded == -1) { 557 if (tmp_loaded == -1) {
548 /* In the case of small number of heavy interrupt sources, 558 /*
549 * loading some of the cpus too much. We use Ingo's original 559 * In the case of small number of heavy interrupt sources,
560 * loading some of the cpus too much. We use Ingo's original
550 * approach to rotate them around. 561 * approach to rotate them around.
551 */ 562 */
552 if (!first_attempt && imbalance >= useful_load_threshold) { 563 if (!first_attempt && imbalance >= useful_load_threshold) {
@@ -555,13 +566,14 @@ tryanothercpu:
555 } 566 }
556 goto not_worth_the_effort; 567 goto not_worth_the_effort;
557 } 568 }
558 569
559 first_attempt = 0; /* heaviest search */ 570 first_attempt = 0; /* heaviest search */
560 max_cpu_irq = tmp_cpu_irq; /* load */ 571 max_cpu_irq = tmp_cpu_irq; /* load */
561 max_loaded = tmp_loaded; /* processor */ 572 max_loaded = tmp_loaded; /* processor */
562 imbalance = (max_cpu_irq - min_cpu_irq) / 2; 573 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
563 574
564 /* if imbalance is less than approx 10% of max load, then 575 /*
576 * if imbalance is less than approx 10% of max load, then
565 * observe diminishing returns action. - quit 577 * observe diminishing returns action. - quit
566 */ 578 */
567 if (imbalance < (max_cpu_irq >> 3)) 579 if (imbalance < (max_cpu_irq >> 3))
@@ -577,26 +589,25 @@ tryanotherirq:
577 /* Is this an active IRQ? */ 589 /* Is this an active IRQ? */
578 if (!irq_desc[j].action) 590 if (!irq_desc[j].action)
579 continue; 591 continue;
580 if (imbalance <= IRQ_DELTA(max_loaded,j)) 592 if (imbalance <= IRQ_DELTA(max_loaded, j))
581 continue; 593 continue;
582 /* Try to find the IRQ that is closest to the imbalance 594 /* Try to find the IRQ that is closest to the imbalance
583 * without going over. 595 * without going over.
584 */ 596 */
585 if (move_this_load < IRQ_DELTA(max_loaded,j)) { 597 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
586 move_this_load = IRQ_DELTA(max_loaded,j); 598 move_this_load = IRQ_DELTA(max_loaded, j);
587 selected_irq = j; 599 selected_irq = j;
588 } 600 }
589 } 601 }
590 if (selected_irq == -1) { 602 if (selected_irq == -1)
591 goto tryanothercpu; 603 goto tryanothercpu;
592 }
593 604
594 imbalance = move_this_load; 605 imbalance = move_this_load;
595 606
596 /* For physical_balance case, we accumulated both load 607 /* For physical_balance case, we accumulated both load
597 * values in the one of the siblings cpu_irq[], 608 * values in the one of the siblings cpu_irq[],
598 * to use the same code for physical and logical processors 609 * to use the same code for physical and logical processors
599 * as much as possible. 610 * as much as possible.
600 * 611 *
601 * NOTE: the cpu_irq[] array holds the sum of the load for 612 * NOTE: the cpu_irq[] array holds the sum of the load for
602 * sibling A and sibling B in the slot for the lowest numbered 613 * sibling A and sibling B in the slot for the lowest numbered
@@ -625,11 +636,11 @@ tryanotherirq:
625 /* mark for change destination */ 636 /* mark for change destination */
626 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); 637 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
627 638
628 /* Since we made a change, come back sooner to 639 /* Since we made a change, come back sooner to
629 * check for more variation. 640 * check for more variation.
630 */ 641 */
631 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, 642 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
632 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); 643 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
633 return; 644 return;
634 } 645 }
635 goto tryanotherirq; 646 goto tryanotherirq;
@@ -640,7 +651,7 @@ not_worth_the_effort:
640 * upward 651 * upward
641 */ 652 */
642 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, 653 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
643 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); 654 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
644 return; 655 return;
645} 656}
646 657
@@ -679,13 +690,13 @@ static int __init balanced_irq_init(void)
679 cpumask_t tmp; 690 cpumask_t tmp;
680 691
681 cpus_shift_right(tmp, cpu_online_map, 2); 692 cpus_shift_right(tmp, cpu_online_map, 2);
682 c = &boot_cpu_data; 693 c = &boot_cpu_data;
683 /* When not overwritten by the command line ask subarchitecture. */ 694 /* When not overwritten by the command line ask subarchitecture. */
684 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) 695 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
685 irqbalance_disabled = NO_BALANCE_IRQ; 696 irqbalance_disabled = NO_BALANCE_IRQ;
686 if (irqbalance_disabled) 697 if (irqbalance_disabled)
687 return 0; 698 return 0;
688 699
689 /* disable irqbalance completely if there is only one processor online */ 700 /* disable irqbalance completely if there is only one processor online */
690 if (num_online_cpus() < 2) { 701 if (num_online_cpus() < 2) {
691 irqbalance_disabled = 1; 702 irqbalance_disabled = 1;
@@ -699,16 +710,14 @@ static int __init balanced_irq_init(void)
699 physical_balance = 1; 710 physical_balance = 1;
700 711
701 for_each_online_cpu(i) { 712 for_each_online_cpu(i) {
702 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); 713 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
703 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); 714 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
704 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { 715 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
705 printk(KERN_ERR "balanced_irq_init: out of memory"); 716 printk(KERN_ERR "balanced_irq_init: out of memory");
706 goto failed; 717 goto failed;
707 } 718 }
708 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
709 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
710 } 719 }
711 720
712 printk(KERN_INFO "Starting balanced_irq\n"); 721 printk(KERN_INFO "Starting balanced_irq\n");
713 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) 722 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
714 return 0; 723 return 0;
@@ -748,7 +757,7 @@ void send_IPI_self(int vector)
748 /* 757 /*
749 * Send the IPI. The write to APIC_ICR fires this off. 758 * Send the IPI. The write to APIC_ICR fires this off.
750 */ 759 */
751 apic_write_around(APIC_ICR, cfg); 760 apic_write(APIC_ICR, cfg);
752} 761}
753#endif /* !CONFIG_SMP */ 762#endif /* !CONFIG_SMP */
754 763
@@ -801,10 +810,10 @@ static int find_irq_entry(int apic, int pin, int type)
801 int i; 810 int i;
802 811
803 for (i = 0; i < mp_irq_entries; i++) 812 for (i = 0; i < mp_irq_entries; i++)
804 if (mp_irqs[i].mpc_irqtype == type && 813 if (mp_irqs[i].mp_irqtype == type &&
805 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || 814 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
806 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && 815 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
807 mp_irqs[i].mpc_dstirq == pin) 816 mp_irqs[i].mp_dstirq == pin)
808 return i; 817 return i;
809 818
810 return -1; 819 return -1;
@@ -818,13 +827,13 @@ static int __init find_isa_irq_pin(int irq, int type)
818 int i; 827 int i;
819 828
820 for (i = 0; i < mp_irq_entries; i++) { 829 for (i = 0; i < mp_irq_entries; i++) {
821 int lbus = mp_irqs[i].mpc_srcbus; 830 int lbus = mp_irqs[i].mp_srcbus;
822 831
823 if (test_bit(lbus, mp_bus_not_pci) && 832 if (test_bit(lbus, mp_bus_not_pci) &&
824 (mp_irqs[i].mpc_irqtype == type) && 833 (mp_irqs[i].mp_irqtype == type) &&
825 (mp_irqs[i].mpc_srcbusirq == irq)) 834 (mp_irqs[i].mp_srcbusirq == irq))
826 835
827 return mp_irqs[i].mpc_dstirq; 836 return mp_irqs[i].mp_dstirq;
828 } 837 }
829 return -1; 838 return -1;
830} 839}
@@ -834,17 +843,17 @@ static int __init find_isa_irq_apic(int irq, int type)
834 int i; 843 int i;
835 844
836 for (i = 0; i < mp_irq_entries; i++) { 845 for (i = 0; i < mp_irq_entries; i++) {
837 int lbus = mp_irqs[i].mpc_srcbus; 846 int lbus = mp_irqs[i].mp_srcbus;
838 847
839 if (test_bit(lbus, mp_bus_not_pci) && 848 if (test_bit(lbus, mp_bus_not_pci) &&
840 (mp_irqs[i].mpc_irqtype == type) && 849 (mp_irqs[i].mp_irqtype == type) &&
841 (mp_irqs[i].mpc_srcbusirq == irq)) 850 (mp_irqs[i].mp_srcbusirq == irq))
842 break; 851 break;
843 } 852 }
844 if (i < mp_irq_entries) { 853 if (i < mp_irq_entries) {
845 int apic; 854 int apic;
846 for(apic = 0; apic < nr_ioapics; apic++) { 855 for (apic = 0; apic < nr_ioapics; apic++) {
847 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) 856 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
848 return apic; 857 return apic;
849 } 858 }
850 } 859 }
@@ -864,28 +873,28 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
864 873
865 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " 874 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
866 "slot:%d, pin:%d.\n", bus, slot, pin); 875 "slot:%d, pin:%d.\n", bus, slot, pin);
867 if (mp_bus_id_to_pci_bus[bus] == -1) { 876 if (test_bit(bus, mp_bus_not_pci)) {
868 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 877 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
869 return -1; 878 return -1;
870 } 879 }
871 for (i = 0; i < mp_irq_entries; i++) { 880 for (i = 0; i < mp_irq_entries; i++) {
872 int lbus = mp_irqs[i].mpc_srcbus; 881 int lbus = mp_irqs[i].mp_srcbus;
873 882
874 for (apic = 0; apic < nr_ioapics; apic++) 883 for (apic = 0; apic < nr_ioapics; apic++)
875 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || 884 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
876 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) 885 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
877 break; 886 break;
878 887
879 if (!test_bit(lbus, mp_bus_not_pci) && 888 if (!test_bit(lbus, mp_bus_not_pci) &&
880 !mp_irqs[i].mpc_irqtype && 889 !mp_irqs[i].mp_irqtype &&
881 (bus == lbus) && 890 (bus == lbus) &&
882 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { 891 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
883 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); 892 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
884 893
885 if (!(apic || IO_APIC_IRQ(irq))) 894 if (!(apic || IO_APIC_IRQ(irq)))
886 continue; 895 continue;
887 896
888 if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) 897 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
889 return irq; 898 return irq;
890 /* 899 /*
891 * Use the first all-but-pin matching entry as a 900 * Use the first all-but-pin matching entry as a
@@ -900,7 +909,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
900EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 909EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
901 910
902/* 911/*
903 * This function currently is only a helper for the i386 smp boot process where 912 * This function currently is only a helper for the i386 smp boot process where
904 * we need to reprogram the ioredtbls to cater for the cpus which have come online 913 * we need to reprogram the ioredtbls to cater for the cpus which have come online
905 * so mask in all cases should simply be TARGET_CPUS 914 * so mask in all cases should simply be TARGET_CPUS
906 */ 915 */
@@ -952,7 +961,7 @@ static int EISA_ELCR(unsigned int irq)
952 * EISA conforming in the MP table, that means its trigger type must 961 * EISA conforming in the MP table, that means its trigger type must
953 * be read in from the ELCR */ 962 * be read in from the ELCR */
954 963
955#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) 964#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
956#define default_EISA_polarity(idx) default_ISA_polarity(idx) 965#define default_EISA_polarity(idx) default_ISA_polarity(idx)
957 966
958/* PCI interrupts are always polarity one level triggered, 967/* PCI interrupts are always polarity one level triggered,
@@ -969,118 +978,115 @@ static int EISA_ELCR(unsigned int irq)
969 978
970static int MPBIOS_polarity(int idx) 979static int MPBIOS_polarity(int idx)
971{ 980{
972 int bus = mp_irqs[idx].mpc_srcbus; 981 int bus = mp_irqs[idx].mp_srcbus;
973 int polarity; 982 int polarity;
974 983
975 /* 984 /*
976 * Determine IRQ line polarity (high active or low active): 985 * Determine IRQ line polarity (high active or low active):
977 */ 986 */
978 switch (mp_irqs[idx].mpc_irqflag & 3) 987 switch (mp_irqs[idx].mp_irqflag & 3) {
988 case 0: /* conforms, ie. bus-type dependent polarity */
979 { 989 {
980 case 0: /* conforms, ie. bus-type dependent polarity */ 990 polarity = test_bit(bus, mp_bus_not_pci)?
981 { 991 default_ISA_polarity(idx):
982 polarity = test_bit(bus, mp_bus_not_pci)? 992 default_PCI_polarity(idx);
983 default_ISA_polarity(idx): 993 break;
984 default_PCI_polarity(idx); 994 }
985 break; 995 case 1: /* high active */
986 } 996 {
987 case 1: /* high active */ 997 polarity = 0;
988 { 998 break;
989 polarity = 0; 999 }
990 break; 1000 case 2: /* reserved */
991 } 1001 {
992 case 2: /* reserved */ 1002 printk(KERN_WARNING "broken BIOS!!\n");
993 { 1003 polarity = 1;
994 printk(KERN_WARNING "broken BIOS!!\n"); 1004 break;
995 polarity = 1; 1005 }
996 break; 1006 case 3: /* low active */
997 } 1007 {
998 case 3: /* low active */ 1008 polarity = 1;
999 { 1009 break;
1000 polarity = 1; 1010 }
1001 break; 1011 default: /* invalid */
1002 } 1012 {
1003 default: /* invalid */ 1013 printk(KERN_WARNING "broken BIOS!!\n");
1004 { 1014 polarity = 1;
1005 printk(KERN_WARNING "broken BIOS!!\n"); 1015 break;
1006 polarity = 1; 1016 }
1007 break;
1008 }
1009 } 1017 }
1010 return polarity; 1018 return polarity;
1011} 1019}
1012 1020
1013static int MPBIOS_trigger(int idx) 1021static int MPBIOS_trigger(int idx)
1014{ 1022{
1015 int bus = mp_irqs[idx].mpc_srcbus; 1023 int bus = mp_irqs[idx].mp_srcbus;
1016 int trigger; 1024 int trigger;
1017 1025
1018 /* 1026 /*
1019 * Determine IRQ trigger mode (edge or level sensitive): 1027 * Determine IRQ trigger mode (edge or level sensitive):
1020 */ 1028 */
1021 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) 1029 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1030 case 0: /* conforms, ie. bus-type dependent */
1022 { 1031 {
1023 case 0: /* conforms, ie. bus-type dependent */ 1032 trigger = test_bit(bus, mp_bus_not_pci)?
1024 { 1033 default_ISA_trigger(idx):
1025 trigger = test_bit(bus, mp_bus_not_pci)? 1034 default_PCI_trigger(idx);
1026 default_ISA_trigger(idx):
1027 default_PCI_trigger(idx);
1028#if defined(CONFIG_EISA) || defined(CONFIG_MCA) 1035#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1029 switch (mp_bus_id_to_type[bus]) 1036 switch (mp_bus_id_to_type[bus]) {
1030 { 1037 case MP_BUS_ISA: /* ISA pin */
1031 case MP_BUS_ISA: /* ISA pin */ 1038 {
1032 { 1039 /* set before the switch */
1033 /* set before the switch */
1034 break;
1035 }
1036 case MP_BUS_EISA: /* EISA pin */
1037 {
1038 trigger = default_EISA_trigger(idx);
1039 break;
1040 }
1041 case MP_BUS_PCI: /* PCI pin */
1042 {
1043 /* set before the switch */
1044 break;
1045 }
1046 case MP_BUS_MCA: /* MCA pin */
1047 {
1048 trigger = default_MCA_trigger(idx);
1049 break;
1050 }
1051 default:
1052 {
1053 printk(KERN_WARNING "broken BIOS!!\n");
1054 trigger = 1;
1055 break;
1056 }
1057 }
1058#endif
1059 break; 1040 break;
1060 } 1041 }
1061 case 1: /* edge */ 1042 case MP_BUS_EISA: /* EISA pin */
1062 { 1043 {
1063 trigger = 0; 1044 trigger = default_EISA_trigger(idx);
1064 break; 1045 break;
1065 } 1046 }
1066 case 2: /* reserved */ 1047 case MP_BUS_PCI: /* PCI pin */
1067 { 1048 {
1068 printk(KERN_WARNING "broken BIOS!!\n"); 1049 /* set before the switch */
1069 trigger = 1;
1070 break; 1050 break;
1071 } 1051 }
1072 case 3: /* level */ 1052 case MP_BUS_MCA: /* MCA pin */
1073 { 1053 {
1074 trigger = 1; 1054 trigger = default_MCA_trigger(idx);
1075 break; 1055 break;
1076 } 1056 }
1077 default: /* invalid */ 1057 default:
1078 { 1058 {
1079 printk(KERN_WARNING "broken BIOS!!\n"); 1059 printk(KERN_WARNING "broken BIOS!!\n");
1080 trigger = 0; 1060 trigger = 1;
1081 break; 1061 break;
1082 } 1062 }
1083 } 1063 }
1064#endif
1065 break;
1066 }
1067 case 1: /* edge */
1068 {
1069 trigger = 0;
1070 break;
1071 }
1072 case 2: /* reserved */
1073 {
1074 printk(KERN_WARNING "broken BIOS!!\n");
1075 trigger = 1;
1076 break;
1077 }
1078 case 3: /* level */
1079 {
1080 trigger = 1;
1081 break;
1082 }
1083 default: /* invalid */
1084 {
1085 printk(KERN_WARNING "broken BIOS!!\n");
1086 trigger = 0;
1087 break;
1088 }
1089 }
1084 return trigger; 1090 return trigger;
1085} 1091}
1086 1092
@@ -1097,16 +1103,16 @@ static inline int irq_trigger(int idx)
1097static int pin_2_irq(int idx, int apic, int pin) 1103static int pin_2_irq(int idx, int apic, int pin)
1098{ 1104{
1099 int irq, i; 1105 int irq, i;
1100 int bus = mp_irqs[idx].mpc_srcbus; 1106 int bus = mp_irqs[idx].mp_srcbus;
1101 1107
1102 /* 1108 /*
1103 * Debugging check, we are in big trouble if this message pops up! 1109 * Debugging check, we are in big trouble if this message pops up!
1104 */ 1110 */
1105 if (mp_irqs[idx].mpc_dstirq != pin) 1111 if (mp_irqs[idx].mp_dstirq != pin)
1106 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); 1112 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1107 1113
1108 if (test_bit(bus, mp_bus_not_pci)) 1114 if (test_bit(bus, mp_bus_not_pci))
1109 irq = mp_irqs[idx].mpc_srcbusirq; 1115 irq = mp_irqs[idx].mp_srcbusirq;
1110 else { 1116 else {
1111 /* 1117 /*
1112 * PCI IRQs are mapped in order 1118 * PCI IRQs are mapped in order
@@ -1148,8 +1154,8 @@ static inline int IO_APIC_irq_trigger(int irq)
1148 1154
1149 for (apic = 0; apic < nr_ioapics; apic++) { 1155 for (apic = 0; apic < nr_ioapics; apic++) {
1150 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 1156 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1151 idx = find_irq_entry(apic,pin,mp_INT); 1157 idx = find_irq_entry(apic, pin, mp_INT);
1152 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) 1158 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1153 return irq_trigger(idx); 1159 return irq_trigger(idx);
1154 } 1160 }
1155 } 1161 }
@@ -1164,7 +1170,7 @@ static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }
1164 1170
1165static int __assign_irq_vector(int irq) 1171static int __assign_irq_vector(int irq)
1166{ 1172{
1167 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; 1173 static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1168 int vector, offset; 1174 int vector, offset;
1169 1175
1170 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); 1176 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
@@ -1176,7 +1182,7 @@ static int __assign_irq_vector(int irq)
1176 offset = current_offset; 1182 offset = current_offset;
1177next: 1183next:
1178 vector += 8; 1184 vector += 8;
1179 if (vector >= FIRST_SYSTEM_VECTOR) { 1185 if (vector >= first_system_vector) {
1180 offset = (offset + 1) % 8; 1186 offset = (offset + 1) % 8;
1181 vector = FIRST_DEVICE_VECTOR + offset; 1187 vector = FIRST_DEVICE_VECTOR + offset;
1182 } 1188 }
@@ -1203,6 +1209,11 @@ static int assign_irq_vector(int irq)
1203 1209
1204 return vector; 1210 return vector;
1205} 1211}
1212
1213void setup_vector_irq(int cpu)
1214{
1215}
1216
1206static struct irq_chip ioapic_chip; 1217static struct irq_chip ioapic_chip;
1207 1218
1208#define IOAPIC_AUTO -1 1219#define IOAPIC_AUTO -1
@@ -1237,25 +1248,25 @@ static void __init setup_IO_APIC_irqs(void)
1237 /* 1248 /*
1238 * add it to the IO-APIC irq-routing table: 1249 * add it to the IO-APIC irq-routing table:
1239 */ 1250 */
1240 memset(&entry,0,sizeof(entry)); 1251 memset(&entry, 0, sizeof(entry));
1241 1252
1242 entry.delivery_mode = INT_DELIVERY_MODE; 1253 entry.delivery_mode = INT_DELIVERY_MODE;
1243 entry.dest_mode = INT_DEST_MODE; 1254 entry.dest_mode = INT_DEST_MODE;
1244 entry.mask = 0; /* enable IRQ */ 1255 entry.mask = 0; /* enable IRQ */
1245 entry.dest.logical.logical_dest = 1256 entry.dest.logical.logical_dest =
1246 cpu_mask_to_apicid(TARGET_CPUS); 1257 cpu_mask_to_apicid(TARGET_CPUS);
1247 1258
1248 idx = find_irq_entry(apic,pin,mp_INT); 1259 idx = find_irq_entry(apic, pin, mp_INT);
1249 if (idx == -1) { 1260 if (idx == -1) {
1250 if (first_notcon) { 1261 if (first_notcon) {
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG 1262 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 " IO-APIC (apicid-pin) %d-%d", 1263 " IO-APIC (apicid-pin) %d-%d",
1253 mp_ioapics[apic].mpc_apicid, 1264 mp_ioapics[apic].mp_apicid,
1254 pin); 1265 pin);
1255 first_notcon = 0; 1266 first_notcon = 0;
1256 } else 1267 } else
1257 apic_printk(APIC_VERBOSE, ", %d-%d", 1268 apic_printk(APIC_VERBOSE, ", %d-%d",
1258 mp_ioapics[apic].mpc_apicid, pin); 1269 mp_ioapics[apic].mp_apicid, pin);
1259 continue; 1270 continue;
1260 } 1271 }
1261 1272
@@ -1289,7 +1300,7 @@ static void __init setup_IO_APIC_irqs(void)
1289 vector = assign_irq_vector(irq); 1300 vector = assign_irq_vector(irq);
1290 entry.vector = vector; 1301 entry.vector = vector;
1291 ioapic_register_intr(irq, vector, IOAPIC_AUTO); 1302 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1292 1303
1293 if (!apic && (irq < 16)) 1304 if (!apic && (irq < 16))
1294 disable_8259A_irq(irq); 1305 disable_8259A_irq(irq);
1295 } 1306 }
@@ -1302,25 +1313,21 @@ static void __init setup_IO_APIC_irqs(void)
1302} 1313}
1303 1314
1304/* 1315/*
1305 * Set up the 8259A-master output pin: 1316 * Set up the timer pin, possibly with the 8259A-master behind.
1306 */ 1317 */
1307static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) 1318static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1319 int vector)
1308{ 1320{
1309 struct IO_APIC_route_entry entry; 1321 struct IO_APIC_route_entry entry;
1310 1322
1311 memset(&entry,0,sizeof(entry)); 1323 memset(&entry, 0, sizeof(entry));
1312
1313 disable_8259A_irq(0);
1314
1315 /* mask LVT0 */
1316 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1317 1324
1318 /* 1325 /*
1319 * We use logical delivery to get the timer IRQ 1326 * We use logical delivery to get the timer IRQ
1320 * to the first CPU. 1327 * to the first CPU.
1321 */ 1328 */
1322 entry.dest_mode = INT_DEST_MODE; 1329 entry.dest_mode = INT_DEST_MODE;
1323 entry.mask = 0; /* unmask IRQ now */ 1330 entry.mask = 1; /* mask IRQ now */
1324 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); 1331 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1325 entry.delivery_mode = INT_DELIVERY_MODE; 1332 entry.delivery_mode = INT_DELIVERY_MODE;
1326 entry.polarity = 0; 1333 entry.polarity = 0;
@@ -1329,17 +1336,14 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
1329 1336
1330 /* 1337 /*
1331 * The timer IRQ doesn't have to know that behind the 1338 * The timer IRQ doesn't have to know that behind the
1332 * scene we have a 8259A-master in AEOI mode ... 1339 * scene we may have a 8259A-master in AEOI mode ...
1333 */ 1340 */
1334 irq_desc[0].chip = &ioapic_chip; 1341 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1335 set_irq_handler(0, handle_edge_irq);
1336 1342
1337 /* 1343 /*
1338 * Add it to the IO-APIC irq-routing table: 1344 * Add it to the IO-APIC irq-routing table:
1339 */ 1345 */
1340 ioapic_write_entry(apic, pin, entry); 1346 ioapic_write_entry(apic, pin, entry);
1341
1342 enable_8259A_irq(0);
1343} 1347}
1344 1348
1345void __init print_IO_APIC(void) 1349void __init print_IO_APIC(void)
@@ -1354,10 +1358,10 @@ void __init print_IO_APIC(void)
1354 if (apic_verbosity == APIC_QUIET) 1358 if (apic_verbosity == APIC_QUIET)
1355 return; 1359 return;
1356 1360
1357 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 1361 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1358 for (i = 0; i < nr_ioapics; i++) 1362 for (i = 0; i < nr_ioapics; i++)
1359 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 1363 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1360 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); 1364 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1361 1365
1362 /* 1366 /*
1363 * We are a bit conservative about what we expect. We have to 1367 * We are a bit conservative about what we expect. We have to
@@ -1376,7 +1380,7 @@ void __init print_IO_APIC(void)
1376 reg_03.raw = io_apic_read(apic, 3); 1380 reg_03.raw = io_apic_read(apic, 3);
1377 spin_unlock_irqrestore(&ioapic_lock, flags); 1381 spin_unlock_irqrestore(&ioapic_lock, flags);
1378 1382
1379 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); 1383 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1380 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); 1384 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1381 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); 1385 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1382 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1386 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
@@ -1459,7 +1463,7 @@ void __init print_IO_APIC(void)
1459 1463
1460#if 0 1464#if 0
1461 1465
1462static void print_APIC_bitfield (int base) 1466static void print_APIC_bitfield(int base)
1463{ 1467{
1464 unsigned int v; 1468 unsigned int v;
1465 int i, j; 1469 int i, j;
@@ -1480,7 +1484,7 @@ static void print_APIC_bitfield (int base)
1480 } 1484 }
1481} 1485}
1482 1486
1483void /*__init*/ print_local_APIC(void * dummy) 1487void /*__init*/ print_local_APIC(void *dummy)
1484{ 1488{
1485 unsigned int v, ver, maxlvt; 1489 unsigned int v, ver, maxlvt;
1486 1490
@@ -1489,8 +1493,9 @@ void /*__init*/ print_local_APIC(void * dummy)
1489 1493
1490 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 1494 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1491 smp_processor_id(), hard_smp_processor_id()); 1495 smp_processor_id(), hard_smp_processor_id());
1496 v = apic_read(APIC_ID);
1492 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, 1497 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1493 GET_APIC_ID(read_apic_id())); 1498 GET_APIC_ID(v));
1494 v = apic_read(APIC_LVR); 1499 v = apic_read(APIC_LVR);
1495 printk(KERN_INFO "... APIC VERSION: %08x\n", v); 1500 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1496 ver = GET_APIC_VERSION(v); 1501 ver = GET_APIC_VERSION(v);
@@ -1563,9 +1568,9 @@ void /*__init*/ print_local_APIC(void * dummy)
1563 printk("\n"); 1568 printk("\n");
1564} 1569}
1565 1570
1566void print_all_local_APICs (void) 1571void print_all_local_APICs(void)
1567{ 1572{
1568 on_each_cpu(print_local_APIC, NULL, 1, 1); 1573 on_each_cpu(print_local_APIC, NULL, 1);
1569} 1574}
1570 1575
1571void /*__init*/ print_PIC(void) 1576void /*__init*/ print_PIC(void)
@@ -1586,11 +1591,11 @@ void /*__init*/ print_PIC(void)
1586 v = inb(0xa0) << 8 | inb(0x20); 1591 v = inb(0xa0) << 8 | inb(0x20);
1587 printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 1592 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1588 1593
1589 outb(0x0b,0xa0); 1594 outb(0x0b, 0xa0);
1590 outb(0x0b,0x20); 1595 outb(0x0b, 0x20);
1591 v = inb(0xa0) << 8 | inb(0x20); 1596 v = inb(0xa0) << 8 | inb(0x20);
1592 outb(0x0a,0xa0); 1597 outb(0x0a, 0xa0);
1593 outb(0x0a,0x20); 1598 outb(0x0a, 0x20);
1594 1599
1595 spin_unlock_irqrestore(&i8259A_lock, flags); 1600 spin_unlock_irqrestore(&i8259A_lock, flags);
1596 1601
@@ -1626,7 +1631,7 @@ static void __init enable_IO_APIC(void)
1626 spin_unlock_irqrestore(&ioapic_lock, flags); 1631 spin_unlock_irqrestore(&ioapic_lock, flags);
1627 nr_ioapic_registers[apic] = reg_01.bits.entries+1; 1632 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1628 } 1633 }
1629 for(apic = 0; apic < nr_ioapics; apic++) { 1634 for (apic = 0; apic < nr_ioapics; apic++) {
1630 int pin; 1635 int pin;
1631 /* See if any of the pins is in ExtINT mode */ 1636 /* See if any of the pins is in ExtINT mode */
1632 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 1637 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
@@ -1698,8 +1703,7 @@ void disable_IO_APIC(void)
1698 entry.dest_mode = 0; /* Physical */ 1703 entry.dest_mode = 0; /* Physical */
1699 entry.delivery_mode = dest_ExtINT; /* ExtInt */ 1704 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1700 entry.vector = 0; 1705 entry.vector = 0;
1701 entry.dest.physical.physical_dest = 1706 entry.dest.physical.physical_dest = read_apic_id();
1702 GET_APIC_ID(read_apic_id());
1703 1707
1704 /* 1708 /*
1705 * Add it to the IO-APIC irq-routing table: 1709 * Add it to the IO-APIC irq-routing table:
@@ -1716,7 +1720,6 @@ void disable_IO_APIC(void)
1716 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 1720 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1717 */ 1721 */
1718 1722
1719#ifndef CONFIG_X86_NUMAQ
1720static void __init setup_ioapic_ids_from_mpc(void) 1723static void __init setup_ioapic_ids_from_mpc(void)
1721{ 1724{
1722 union IO_APIC_reg_00 reg_00; 1725 union IO_APIC_reg_00 reg_00;
@@ -1726,6 +1729,9 @@ static void __init setup_ioapic_ids_from_mpc(void)
1726 unsigned char old_id; 1729 unsigned char old_id;
1727 unsigned long flags; 1730 unsigned long flags;
1728 1731
1732 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1733 return;
1734
1729 /* 1735 /*
1730 * Don't check I/O APIC IDs for xAPIC systems. They have 1736 * Don't check I/O APIC IDs for xAPIC systems. They have
1731 * no meaning without the serial APIC bus. 1737 * no meaning without the serial APIC bus.
@@ -1748,15 +1754,15 @@ static void __init setup_ioapic_ids_from_mpc(void)
1748 spin_lock_irqsave(&ioapic_lock, flags); 1754 spin_lock_irqsave(&ioapic_lock, flags);
1749 reg_00.raw = io_apic_read(apic, 0); 1755 reg_00.raw = io_apic_read(apic, 0);
1750 spin_unlock_irqrestore(&ioapic_lock, flags); 1756 spin_unlock_irqrestore(&ioapic_lock, flags);
1751
1752 old_id = mp_ioapics[apic].mpc_apicid;
1753 1757
1754 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { 1758 old_id = mp_ioapics[apic].mp_apicid;
1759
1760 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1755 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 1761 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1756 apic, mp_ioapics[apic].mpc_apicid); 1762 apic, mp_ioapics[apic].mp_apicid);
1757 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 1763 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1758 reg_00.bits.ID); 1764 reg_00.bits.ID);
1759 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; 1765 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1760 } 1766 }
1761 1767
1762 /* 1768 /*
@@ -1765,9 +1771,9 @@ static void __init setup_ioapic_ids_from_mpc(void)
1765 * 'stuck on smp_invalidate_needed IPI wait' messages. 1771 * 'stuck on smp_invalidate_needed IPI wait' messages.
1766 */ 1772 */
1767 if (check_apicid_used(phys_id_present_map, 1773 if (check_apicid_used(phys_id_present_map,
1768 mp_ioapics[apic].mpc_apicid)) { 1774 mp_ioapics[apic].mp_apicid)) {
1769 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 1775 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1770 apic, mp_ioapics[apic].mpc_apicid); 1776 apic, mp_ioapics[apic].mp_apicid);
1771 for (i = 0; i < get_physical_broadcast(); i++) 1777 for (i = 0; i < get_physical_broadcast(); i++)
1772 if (!physid_isset(i, phys_id_present_map)) 1778 if (!physid_isset(i, phys_id_present_map))
1773 break; 1779 break;
@@ -1776,13 +1782,13 @@ static void __init setup_ioapic_ids_from_mpc(void)
1776 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 1782 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1777 i); 1783 i);
1778 physid_set(i, phys_id_present_map); 1784 physid_set(i, phys_id_present_map);
1779 mp_ioapics[apic].mpc_apicid = i; 1785 mp_ioapics[apic].mp_apicid = i;
1780 } else { 1786 } else {
1781 physid_mask_t tmp; 1787 physid_mask_t tmp;
1782 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); 1788 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1783 apic_printk(APIC_VERBOSE, "Setting %d in the " 1789 apic_printk(APIC_VERBOSE, "Setting %d in the "
1784 "phys_id_present_map\n", 1790 "phys_id_present_map\n",
1785 mp_ioapics[apic].mpc_apicid); 1791 mp_ioapics[apic].mp_apicid);
1786 physids_or(phys_id_present_map, phys_id_present_map, tmp); 1792 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1787 } 1793 }
1788 1794
@@ -1791,21 +1797,21 @@ static void __init setup_ioapic_ids_from_mpc(void)
1791 * We need to adjust the IRQ routing table 1797 * We need to adjust the IRQ routing table
1792 * if the ID changed. 1798 * if the ID changed.
1793 */ 1799 */
1794 if (old_id != mp_ioapics[apic].mpc_apicid) 1800 if (old_id != mp_ioapics[apic].mp_apicid)
1795 for (i = 0; i < mp_irq_entries; i++) 1801 for (i = 0; i < mp_irq_entries; i++)
1796 if (mp_irqs[i].mpc_dstapic == old_id) 1802 if (mp_irqs[i].mp_dstapic == old_id)
1797 mp_irqs[i].mpc_dstapic 1803 mp_irqs[i].mp_dstapic
1798 = mp_ioapics[apic].mpc_apicid; 1804 = mp_ioapics[apic].mp_apicid;
1799 1805
1800 /* 1806 /*
1801 * Read the right value from the MPC table and 1807 * Read the right value from the MPC table and
1802 * write it into the ID register. 1808 * write it into the ID register.
1803 */ 1809 */
1804 apic_printk(APIC_VERBOSE, KERN_INFO 1810 apic_printk(APIC_VERBOSE, KERN_INFO
1805 "...changing IO-APIC physical APIC ID to %d ...", 1811 "...changing IO-APIC physical APIC ID to %d ...",
1806 mp_ioapics[apic].mpc_apicid); 1812 mp_ioapics[apic].mp_apicid);
1807 1813
1808 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; 1814 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1809 spin_lock_irqsave(&ioapic_lock, flags); 1815 spin_lock_irqsave(&ioapic_lock, flags);
1810 io_apic_write(apic, 0, reg_00.raw); 1816 io_apic_write(apic, 0, reg_00.raw);
1811 spin_unlock_irqrestore(&ioapic_lock, flags); 1817 spin_unlock_irqrestore(&ioapic_lock, flags);
@@ -1816,15 +1822,12 @@ static void __init setup_ioapic_ids_from_mpc(void)
1816 spin_lock_irqsave(&ioapic_lock, flags); 1822 spin_lock_irqsave(&ioapic_lock, flags);
1817 reg_00.raw = io_apic_read(apic, 0); 1823 reg_00.raw = io_apic_read(apic, 0);
1818 spin_unlock_irqrestore(&ioapic_lock, flags); 1824 spin_unlock_irqrestore(&ioapic_lock, flags);
1819 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) 1825 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1820 printk("could not set ID!\n"); 1826 printk("could not set ID!\n");
1821 else 1827 else
1822 apic_printk(APIC_VERBOSE, " ok.\n"); 1828 apic_printk(APIC_VERBOSE, " ok.\n");
1823 } 1829 }
1824} 1830}
1825#else
1826static void __init setup_ioapic_ids_from_mpc(void) { }
1827#endif
1828 1831
1829int no_timer_check __initdata; 1832int no_timer_check __initdata;
1830 1833
@@ -2015,45 +2018,53 @@ static inline void init_IO_APIC_traps(void)
2015 * The local APIC irq-chip implementation: 2018 * The local APIC irq-chip implementation:
2016 */ 2019 */
2017 2020
2018static void ack_apic(unsigned int irq) 2021static void ack_lapic_irq(unsigned int irq)
2019{ 2022{
2020 ack_APIC_irq(); 2023 ack_APIC_irq();
2021} 2024}
2022 2025
2023static void mask_lapic_irq (unsigned int irq) 2026static void mask_lapic_irq(unsigned int irq)
2024{ 2027{
2025 unsigned long v; 2028 unsigned long v;
2026 2029
2027 v = apic_read(APIC_LVT0); 2030 v = apic_read(APIC_LVT0);
2028 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); 2031 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2029} 2032}
2030 2033
2031static void unmask_lapic_irq (unsigned int irq) 2034static void unmask_lapic_irq(unsigned int irq)
2032{ 2035{
2033 unsigned long v; 2036 unsigned long v;
2034 2037
2035 v = apic_read(APIC_LVT0); 2038 v = apic_read(APIC_LVT0);
2036 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); 2039 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2037} 2040}
2038 2041
2039static struct irq_chip lapic_chip __read_mostly = { 2042static struct irq_chip lapic_chip __read_mostly = {
2040 .name = "local-APIC-edge", 2043 .name = "local-APIC",
2041 .mask = mask_lapic_irq, 2044 .mask = mask_lapic_irq,
2042 .unmask = unmask_lapic_irq, 2045 .unmask = unmask_lapic_irq,
2043 .eoi = ack_apic, 2046 .ack = ack_lapic_irq,
2044}; 2047};
2045 2048
2049static void lapic_register_intr(int irq, int vector)
2050{
2051 irq_desc[irq].status &= ~IRQ_LEVEL;
2052 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2053 "edge");
2054 set_intr_gate(vector, interrupt[irq]);
2055}
2056
2046static void __init setup_nmi(void) 2057static void __init setup_nmi(void)
2047{ 2058{
2048 /* 2059 /*
2049 * Dirty trick to enable the NMI watchdog ... 2060 * Dirty trick to enable the NMI watchdog ...
2050 * We put the 8259A master into AEOI mode and 2061 * We put the 8259A master into AEOI mode and
2051 * unmask on all local APICs LVT0 as NMI. 2062 * unmask on all local APICs LVT0 as NMI.
2052 * 2063 *
2053 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') 2064 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2054 * is from Maciej W. Rozycki - so we do not have to EOI from 2065 * is from Maciej W. Rozycki - so we do not have to EOI from
2055 * the NMI handler or the timer interrupt. 2066 * the NMI handler or the timer interrupt.
2056 */ 2067 */
2057 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); 2068 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2058 2069
2059 enable_NMI_through_LVT0(); 2070 enable_NMI_through_LVT0();
@@ -2129,11 +2140,16 @@ static inline void __init unlock_ExtINT_logic(void)
2129static inline void __init check_timer(void) 2140static inline void __init check_timer(void)
2130{ 2141{
2131 int apic1, pin1, apic2, pin2; 2142 int apic1, pin1, apic2, pin2;
2143 int no_pin1 = 0;
2132 int vector; 2144 int vector;
2145 unsigned int ver;
2133 unsigned long flags; 2146 unsigned long flags;
2134 2147
2135 local_irq_save(flags); 2148 local_irq_save(flags);
2136 2149
2150 ver = apic_read(APIC_LVR);
2151 ver = GET_APIC_VERSION(ver);
2152
2137 /* 2153 /*
2138 * get/set the timer IRQ vector: 2154 * get/set the timer IRQ vector:
2139 */ 2155 */
@@ -2142,34 +2158,54 @@ static inline void __init check_timer(void)
2142 set_intr_gate(vector, interrupt[0]); 2158 set_intr_gate(vector, interrupt[0]);
2143 2159
2144 /* 2160 /*
2145 * Subtle, code in do_timer_interrupt() expects an AEOI 2161 * As IRQ0 is to be enabled in the 8259A, the virtual
2146 * mode for the 8259A whenever interrupts are routed 2162 * wire has to be disabled in the local APIC. Also
2147 * through I/O APICs. Also IRQ0 has to be enabled in 2163 * timer interrupts need to be acknowledged manually in
2148 * the 8259A which implies the virtual wire has to be 2164 * the 8259A for the i82489DX when using the NMI
2149 * disabled in the local APIC. 2165 * watchdog as that APIC treats NMIs as level-triggered.
2166 * The AEOI mode will finish them in the 8259A
2167 * automatically.
2150 */ 2168 */
2151 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 2169 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2152 init_8259A(1); 2170 init_8259A(1);
2153 timer_ack = 1; 2171 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2154 if (timer_over_8254 > 0)
2155 enable_8259A_irq(0);
2156 2172
2157 pin1 = find_isa_irq_pin(0, mp_INT); 2173 pin1 = find_isa_irq_pin(0, mp_INT);
2158 apic1 = find_isa_irq_apic(0, mp_INT); 2174 apic1 = find_isa_irq_apic(0, mp_INT);
2159 pin2 = ioapic_i8259.pin; 2175 pin2 = ioapic_i8259.pin;
2160 apic2 = ioapic_i8259.apic; 2176 apic2 = ioapic_i8259.apic;
2161 2177
2162 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", 2178 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2163 vector, apic1, pin1, apic2, pin2); 2179 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2180 vector, apic1, pin1, apic2, pin2);
2181
2182 /*
2183 * Some BIOS writers are clueless and report the ExtINTA
2184 * I/O APIC input from the cascaded 8259A as the timer
2185 * interrupt input. So just in case, if only one pin
2186 * was found above, try it both directly and through the
2187 * 8259A.
2188 */
2189 if (pin1 == -1) {
2190 pin1 = pin2;
2191 apic1 = apic2;
2192 no_pin1 = 1;
2193 } else if (pin2 == -1) {
2194 pin2 = pin1;
2195 apic2 = apic1;
2196 }
2164 2197
2165 if (pin1 != -1) { 2198 if (pin1 != -1) {
2166 /* 2199 /*
2167 * Ok, does IRQ0 through the IOAPIC work? 2200 * Ok, does IRQ0 through the IOAPIC work?
2168 */ 2201 */
2202 if (no_pin1) {
2203 add_pin_to_irq(0, apic1, pin1);
2204 setup_timer_IRQ0_pin(apic1, pin1, vector);
2205 }
2169 unmask_IO_APIC_irq(0); 2206 unmask_IO_APIC_irq(0);
2170 if (timer_irq_works()) { 2207 if (timer_irq_works()) {
2171 if (nmi_watchdog == NMI_IO_APIC) { 2208 if (nmi_watchdog == NMI_IO_APIC) {
2172 disable_8259A_irq(0);
2173 setup_nmi(); 2209 setup_nmi();
2174 enable_8259A_irq(0); 2210 enable_8259A_irq(0);
2175 } 2211 }
@@ -2178,81 +2214,97 @@ static inline void __init check_timer(void)
2178 goto out; 2214 goto out;
2179 } 2215 }
2180 clear_IO_APIC_pin(apic1, pin1); 2216 clear_IO_APIC_pin(apic1, pin1);
2181 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " 2217 if (!no_pin1)
2182 "IO-APIC\n"); 2218 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2183 } 2219 "8254 timer not connected to IO-APIC\n");
2184 2220
2185 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); 2221 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2186 if (pin2 != -1) { 2222 "(IRQ0) through the 8259A ...\n");
2187 printk("\n..... (found pin %d) ...", pin2); 2223 apic_printk(APIC_QUIET, KERN_INFO
2224 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2188 /* 2225 /*
2189 * legacy devices should be connected to IO APIC #0 2226 * legacy devices should be connected to IO APIC #0
2190 */ 2227 */
2191 setup_ExtINT_IRQ0_pin(apic2, pin2, vector); 2228 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2229 setup_timer_IRQ0_pin(apic2, pin2, vector);
2230 unmask_IO_APIC_irq(0);
2231 enable_8259A_irq(0);
2192 if (timer_irq_works()) { 2232 if (timer_irq_works()) {
2193 printk("works.\n"); 2233 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2194 if (pin1 != -1) 2234 timer_through_8259 = 1;
2195 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2196 else
2197 add_pin_to_irq(0, apic2, pin2);
2198 if (nmi_watchdog == NMI_IO_APIC) { 2235 if (nmi_watchdog == NMI_IO_APIC) {
2236 disable_8259A_irq(0);
2199 setup_nmi(); 2237 setup_nmi();
2238 enable_8259A_irq(0);
2200 } 2239 }
2201 goto out; 2240 goto out;
2202 } 2241 }
2203 /* 2242 /*
2204 * Cleanup, just in case ... 2243 * Cleanup, just in case ...
2205 */ 2244 */
2245 disable_8259A_irq(0);
2206 clear_IO_APIC_pin(apic2, pin2); 2246 clear_IO_APIC_pin(apic2, pin2);
2247 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2207 } 2248 }
2208 printk(" failed.\n");
2209 2249
2210 if (nmi_watchdog == NMI_IO_APIC) { 2250 if (nmi_watchdog == NMI_IO_APIC) {
2211 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); 2251 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2212 nmi_watchdog = 0; 2252 "through the IO-APIC - disabling NMI Watchdog!\n");
2253 nmi_watchdog = NMI_NONE;
2213 } 2254 }
2255 timer_ack = 0;
2214 2256
2215 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); 2257 apic_printk(APIC_QUIET, KERN_INFO
2258 "...trying to set up timer as Virtual Wire IRQ...\n");
2216 2259
2217 disable_8259A_irq(0); 2260 lapic_register_intr(0, vector);
2218 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, 2261 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2219 "fasteoi");
2220 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2221 enable_8259A_irq(0); 2262 enable_8259A_irq(0);
2222 2263
2223 if (timer_irq_works()) { 2264 if (timer_irq_works()) {
2224 printk(" works.\n"); 2265 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2225 goto out; 2266 goto out;
2226 } 2267 }
2227 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); 2268 disable_8259A_irq(0);
2228 printk(" failed.\n"); 2269 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2270 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2229 2271
2230 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); 2272 apic_printk(APIC_QUIET, KERN_INFO
2273 "...trying to set up timer as ExtINT IRQ...\n");
2231 2274
2232 timer_ack = 0;
2233 init_8259A(0); 2275 init_8259A(0);
2234 make_8259A_irq(0); 2276 make_8259A_irq(0);
2235 apic_write_around(APIC_LVT0, APIC_DM_EXTINT); 2277 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2236 2278
2237 unlock_ExtINT_logic(); 2279 unlock_ExtINT_logic();
2238 2280
2239 if (timer_irq_works()) { 2281 if (timer_irq_works()) {
2240 printk(" works.\n"); 2282 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2241 goto out; 2283 goto out;
2242 } 2284 }
2243 printk(" failed :(.\n"); 2285 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2244 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " 2286 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2245 "report. Then try booting with the 'noapic' option"); 2287 "report. Then try booting with the 'noapic' option.\n");
2246out: 2288out:
2247 local_irq_restore(flags); 2289 local_irq_restore(flags);
2248} 2290}
2249 2291
2250/* 2292/*
2251 * 2293 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2252 * IRQ's that are handled by the PIC in the MPS IOAPIC case. 2294 * to devices. However there may be an I/O APIC pin available for
2253 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. 2295 * this interrupt regardless. The pin may be left unconnected, but
2254 * Linux doesn't really care, as it's not actually used 2296 * typically it will be reused as an ExtINT cascade interrupt for
2255 * for any interrupt handling anyway. 2297 * the master 8259A. In the MPS case such a pin will normally be
2298 * reported as an ExtINT interrupt in the MP table. With ACPI
2299 * there is no provision for ExtINT interrupts, and in the absence
2300 * of an override it would be treated as an ordinary ISA I/O APIC
2301 * interrupt, that is edge-triggered and unmasked by default. We
2302 * used to do this, but it caused problems on some systems because
2303 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2304 * the same ExtINT cascade interrupt to drive the local APIC of the
2305 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2306 * the I/O APIC in all cases now. No actual device should request
2307 * it anyway. --macro
2256 */ 2308 */
2257#define PIC_IRQS (1 << PIC_CASCADE_IR) 2309#define PIC_IRQS (1 << PIC_CASCADE_IR)
2258 2310
@@ -2261,15 +2313,12 @@ void __init setup_IO_APIC(void)
2261 int i; 2313 int i;
2262 2314
2263 /* Reserve all the system vectors. */ 2315 /* Reserve all the system vectors. */
2264 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++) 2316 for (i = first_system_vector; i < NR_VECTORS; i++)
2265 set_bit(i, used_vectors); 2317 set_bit(i, used_vectors);
2266 2318
2267 enable_IO_APIC(); 2319 enable_IO_APIC();
2268 2320
2269 if (acpi_ioapic) 2321 io_apic_irqs = ~PIC_IRQS;
2270 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2271 else
2272 io_apic_irqs = ~PIC_IRQS;
2273 2322
2274 printk("ENABLING IO-APIC IRQs\n"); 2323 printk("ENABLING IO-APIC IRQs\n");
2275 2324
@@ -2286,28 +2335,14 @@ void __init setup_IO_APIC(void)
2286 print_IO_APIC(); 2335 print_IO_APIC();
2287} 2336}
2288 2337
2289static int __init setup_disable_8254_timer(char *s)
2290{
2291 timer_over_8254 = -1;
2292 return 1;
2293}
2294static int __init setup_enable_8254_timer(char *s)
2295{
2296 timer_over_8254 = 2;
2297 return 1;
2298}
2299
2300__setup("disable_8254_timer", setup_disable_8254_timer);
2301__setup("enable_8254_timer", setup_enable_8254_timer);
2302
2303/* 2338/*
2304 * Called after all the initialization is done. If we didnt find any 2339 * Called after all the initialization is done. If we didnt find any
2305 * APIC bugs then we can allow the modify fast path 2340 * APIC bugs then we can allow the modify fast path
2306 */ 2341 */
2307 2342
2308static int __init io_apic_bug_finalize(void) 2343static int __init io_apic_bug_finalize(void)
2309{ 2344{
2310 if(sis_apic_bug == -1) 2345 if (sis_apic_bug == -1)
2311 sis_apic_bug = 0; 2346 sis_apic_bug = 0;
2312 return 0; 2347 return 0;
2313} 2348}
@@ -2318,17 +2353,17 @@ struct sysfs_ioapic_data {
2318 struct sys_device dev; 2353 struct sys_device dev;
2319 struct IO_APIC_route_entry entry[0]; 2354 struct IO_APIC_route_entry entry[0];
2320}; 2355};
2321static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; 2356static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2322 2357
2323static int ioapic_suspend(struct sys_device *dev, pm_message_t state) 2358static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2324{ 2359{
2325 struct IO_APIC_route_entry *entry; 2360 struct IO_APIC_route_entry *entry;
2326 struct sysfs_ioapic_data *data; 2361 struct sysfs_ioapic_data *data;
2327 int i; 2362 int i;
2328 2363
2329 data = container_of(dev, struct sysfs_ioapic_data, dev); 2364 data = container_of(dev, struct sysfs_ioapic_data, dev);
2330 entry = data->entry; 2365 entry = data->entry;
2331 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) 2366 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2332 entry[i] = ioapic_read_entry(dev->id, i); 2367 entry[i] = ioapic_read_entry(dev->id, i);
2333 2368
2334 return 0; 2369 return 0;
@@ -2341,18 +2376,18 @@ static int ioapic_resume(struct sys_device *dev)
2341 unsigned long flags; 2376 unsigned long flags;
2342 union IO_APIC_reg_00 reg_00; 2377 union IO_APIC_reg_00 reg_00;
2343 int i; 2378 int i;
2344 2379
2345 data = container_of(dev, struct sysfs_ioapic_data, dev); 2380 data = container_of(dev, struct sysfs_ioapic_data, dev);
2346 entry = data->entry; 2381 entry = data->entry;
2347 2382
2348 spin_lock_irqsave(&ioapic_lock, flags); 2383 spin_lock_irqsave(&ioapic_lock, flags);
2349 reg_00.raw = io_apic_read(dev->id, 0); 2384 reg_00.raw = io_apic_read(dev->id, 0);
2350 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { 2385 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2351 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; 2386 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2352 io_apic_write(dev->id, 0, reg_00.raw); 2387 io_apic_write(dev->id, 0, reg_00.raw);
2353 } 2388 }
2354 spin_unlock_irqrestore(&ioapic_lock, flags); 2389 spin_unlock_irqrestore(&ioapic_lock, flags);
2355 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) 2390 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2356 ioapic_write_entry(dev->id, i, entry[i]); 2391 ioapic_write_entry(dev->id, i, entry[i]);
2357 2392
2358 return 0; 2393 return 0;
@@ -2366,24 +2401,23 @@ static struct sysdev_class ioapic_sysdev_class = {
2366 2401
2367static int __init ioapic_init_sysfs(void) 2402static int __init ioapic_init_sysfs(void)
2368{ 2403{
2369 struct sys_device * dev; 2404 struct sys_device *dev;
2370 int i, size, error = 0; 2405 int i, size, error = 0;
2371 2406
2372 error = sysdev_class_register(&ioapic_sysdev_class); 2407 error = sysdev_class_register(&ioapic_sysdev_class);
2373 if (error) 2408 if (error)
2374 return error; 2409 return error;
2375 2410
2376 for (i = 0; i < nr_ioapics; i++ ) { 2411 for (i = 0; i < nr_ioapics; i++) {
2377 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 2412 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2378 * sizeof(struct IO_APIC_route_entry); 2413 * sizeof(struct IO_APIC_route_entry);
2379 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); 2414 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2380 if (!mp_ioapic_data[i]) { 2415 if (!mp_ioapic_data[i]) {
2381 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); 2416 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2382 continue; 2417 continue;
2383 } 2418 }
2384 memset(mp_ioapic_data[i], 0, size);
2385 dev = &mp_ioapic_data[i]->dev; 2419 dev = &mp_ioapic_data[i]->dev;
2386 dev->id = i; 2420 dev->id = i;
2387 dev->cls = &ioapic_sysdev_class; 2421 dev->cls = &ioapic_sysdev_class;
2388 error = sysdev_register(dev); 2422 error = sysdev_register(dev);
2389 if (error) { 2423 if (error) {
@@ -2458,7 +2492,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
2458 msg->address_lo = 2492 msg->address_lo =
2459 MSI_ADDR_BASE_LO | 2493 MSI_ADDR_BASE_LO |
2460 ((INT_DEST_MODE == 0) ? 2494 ((INT_DEST_MODE == 0) ?
2461 MSI_ADDR_DEST_MODE_PHYSICAL: 2495MSI_ADDR_DEST_MODE_PHYSICAL:
2462 MSI_ADDR_DEST_MODE_LOGICAL) | 2496 MSI_ADDR_DEST_MODE_LOGICAL) |
2463 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 2497 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2464 MSI_ADDR_REDIRECTION_CPU: 2498 MSI_ADDR_REDIRECTION_CPU:
@@ -2469,7 +2503,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
2469 MSI_DATA_TRIGGER_EDGE | 2503 MSI_DATA_TRIGGER_EDGE |
2470 MSI_DATA_LEVEL_ASSERT | 2504 MSI_DATA_LEVEL_ASSERT |
2471 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 2505 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2472 MSI_DATA_DELIVERY_FIXED: 2506MSI_DATA_DELIVERY_FIXED:
2473 MSI_DATA_DELIVERY_LOWPRI) | 2507 MSI_DATA_DELIVERY_LOWPRI) |
2474 MSI_DATA_VECTOR(vector); 2508 MSI_DATA_VECTOR(vector);
2475 } 2509 }
@@ -2640,12 +2674,12 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2640#endif /* CONFIG_HT_IRQ */ 2674#endif /* CONFIG_HT_IRQ */
2641 2675
2642/* -------------------------------------------------------------------------- 2676/* --------------------------------------------------------------------------
2643 ACPI-based IOAPIC Configuration 2677 ACPI-based IOAPIC Configuration
2644 -------------------------------------------------------------------------- */ 2678 -------------------------------------------------------------------------- */
2645 2679
2646#ifdef CONFIG_ACPI 2680#ifdef CONFIG_ACPI
2647 2681
2648int __init io_apic_get_unique_id (int ioapic, int apic_id) 2682int __init io_apic_get_unique_id(int ioapic, int apic_id)
2649{ 2683{
2650 union IO_APIC_reg_00 reg_00; 2684 union IO_APIC_reg_00 reg_00;
2651 static physid_mask_t apic_id_map = PHYSID_MASK_NONE; 2685 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
@@ -2654,10 +2688,10 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
2654 int i = 0; 2688 int i = 0;
2655 2689
2656 /* 2690 /*
2657 * The P4 platform supports up to 256 APIC IDs on two separate APIC 2691 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2658 * buses (one for LAPICs, one for IOAPICs), where predecessors only 2692 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2659 * supports up to 16 on one shared APIC bus. 2693 * supports up to 16 on one shared APIC bus.
2660 * 2694 *
2661 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full 2695 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2662 * advantage of new APIC bus architecture. 2696 * advantage of new APIC bus architecture.
2663 */ 2697 */
@@ -2676,7 +2710,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
2676 } 2710 }
2677 2711
2678 /* 2712 /*
2679 * Every APIC in a system must have a unique ID or we get lots of nice 2713 * Every APIC in a system must have a unique ID or we get lots of nice
2680 * 'stuck on smp_invalidate_needed IPI wait' messages. 2714 * 'stuck on smp_invalidate_needed IPI wait' messages.
2681 */ 2715 */
2682 if (check_apicid_used(apic_id_map, apic_id)) { 2716 if (check_apicid_used(apic_id_map, apic_id)) {
@@ -2693,7 +2727,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
2693 "trying %d\n", ioapic, apic_id, i); 2727 "trying %d\n", ioapic, apic_id, i);
2694 2728
2695 apic_id = i; 2729 apic_id = i;
2696 } 2730 }
2697 2731
2698 tmp = apicid_to_cpu_present(apic_id); 2732 tmp = apicid_to_cpu_present(apic_id);
2699 physids_or(apic_id_map, apic_id_map, tmp); 2733 physids_or(apic_id_map, apic_id_map, tmp);
@@ -2720,7 +2754,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
2720} 2754}
2721 2755
2722 2756
2723int __init io_apic_get_version (int ioapic) 2757int __init io_apic_get_version(int ioapic)
2724{ 2758{
2725 union IO_APIC_reg_01 reg_01; 2759 union IO_APIC_reg_01 reg_01;
2726 unsigned long flags; 2760 unsigned long flags;
@@ -2733,7 +2767,7 @@ int __init io_apic_get_version (int ioapic)
2733} 2767}
2734 2768
2735 2769
2736int __init io_apic_get_redir_entries (int ioapic) 2770int __init io_apic_get_redir_entries(int ioapic)
2737{ 2771{
2738 union IO_APIC_reg_01 reg_01; 2772 union IO_APIC_reg_01 reg_01;
2739 unsigned long flags; 2773 unsigned long flags;
@@ -2746,7 +2780,7 @@ int __init io_apic_get_redir_entries (int ioapic)
2746} 2780}
2747 2781
2748 2782
2749int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) 2783int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2750{ 2784{
2751 struct IO_APIC_route_entry entry; 2785 struct IO_APIC_route_entry entry;
2752 2786
@@ -2762,7 +2796,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
2762 * corresponding device driver registers for this IRQ. 2796 * corresponding device driver registers for this IRQ.
2763 */ 2797 */
2764 2798
2765 memset(&entry,0,sizeof(entry)); 2799 memset(&entry, 0, sizeof(entry));
2766 2800
2767 entry.delivery_mode = INT_DELIVERY_MODE; 2801 entry.delivery_mode = INT_DELIVERY_MODE;
2768 entry.dest_mode = INT_DEST_MODE; 2802 entry.dest_mode = INT_DEST_MODE;
@@ -2781,7 +2815,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
2781 2815
2782 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " 2816 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2783 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, 2817 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2784 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, 2818 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2785 edge_level, active_high_low); 2819 edge_level, active_high_low);
2786 2820
2787 ioapic_register_intr(irq, entry.vector, edge_level); 2821 ioapic_register_intr(irq, entry.vector, edge_level);
@@ -2802,8 +2836,8 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2802 return -1; 2836 return -1;
2803 2837
2804 for (i = 0; i < mp_irq_entries; i++) 2838 for (i = 0; i < mp_irq_entries; i++)
2805 if (mp_irqs[i].mpc_irqtype == mp_INT && 2839 if (mp_irqs[i].mp_irqtype == mp_INT &&
2806 mp_irqs[i].mpc_srcbusirq == bus_irq) 2840 mp_irqs[i].mp_srcbusirq == bus_irq)
2807 break; 2841 break;
2808 if (i >= mp_irq_entries) 2842 if (i >= mp_irq_entries)
2809 return -1; 2843 return -1;
@@ -2836,3 +2870,34 @@ static int __init parse_noapic(char *arg)
2836 return 0; 2870 return 0;
2837} 2871}
2838early_param("noapic", parse_noapic); 2872early_param("noapic", parse_noapic);
2873
2874void __init ioapic_init_mappings(void)
2875{
2876 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2877 int i;
2878
2879 for (i = 0; i < nr_ioapics; i++) {
2880 if (smp_found_config) {
2881 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2882 if (!ioapic_phys) {
2883 printk(KERN_ERR
2884 "WARNING: bogus zero IO-APIC "
2885 "address found in MPTABLE, "
2886 "disabling IO/APIC support!\n");
2887 smp_found_config = 0;
2888 skip_ioapic_setup = 1;
2889 goto fake_ioapic_page;
2890 }
2891 } else {
2892fake_ioapic_page:
2893 ioapic_phys = (unsigned long)
2894 alloc_bootmem_pages(PAGE_SIZE);
2895 ioapic_phys = __pa(ioapic_phys);
2896 }
2897 set_fixmap_nocache(idx, ioapic_phys);
2898 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2899 __fix_to_virt(idx), ioapic_phys);
2900 idx++;
2901 }
2902}
2903
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 01:18:32 -0500