3 files changed, 160 insertions, 7 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index ed44c8a65858..6a05c1d327a9 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -28,6 +28,18 @@ extern int mce_ser;
 
 extern struct mce_bank *mce_banks;
 
+#ifdef CONFIG_X86_MCE_INTEL
+unsigned long mce_intel_adjust_timer(unsigned long interval);
+void mce_intel_cmci_poll(void);
+void mce_intel_hcpu_update(unsigned long cpu);
+#else
+# define mce_intel_adjust_timer mce_adjust_timer_default
+static inline void mce_intel_cmci_poll(void) { }
+static inline void mce_intel_hcpu_update(unsigned long cpu) { }
+#endif
+
+void mce_timer_kick(unsigned long interval);
+
 #ifdef CONFIG_ACPI_APEI
 int apei_write_mce(struct mce *m);
 ssize_t apei_read_mce(struct mce *m, u64 *record_id);
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index b4dde1527edd..8c1beea6cabf 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1260,6 +1260,14 @@ static unsigned long check_interval = 5 * 60; /* 5 minutes */
 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
 static DEFINE_PER_CPU(struct timer_list, mce_timer);
 
+static unsigned long mce_adjust_timer_default(unsigned long interval)
+{
+        return interval;
+}
+
+static unsigned long (*mce_adjust_timer)(unsigned long interval) =
+        mce_adjust_timer_default;
+
 static void mce_timer_fn(unsigned long data)
 {
         struct timer_list *t = &__get_cpu_var(mce_timer);
@@ -1270,6 +1278,7 @@ static void mce_timer_fn(unsigned long data)
         if (mce_available(__this_cpu_ptr(&cpu_info))) {
                 machine_check_poll(MCP_TIMESTAMP,
                                 &__get_cpu_var(mce_poll_banks));
+                mce_intel_cmci_poll();
         }
 
         /*
@@ -1277,14 +1286,38 @@ static void mce_timer_fn(unsigned long data)
          * polling interval, otherwise increase the polling interval.
          */
         iv = __this_cpu_read(mce_next_interval);
-        if (mce_notify_irq())
+        if (mce_notify_irq()) {
                 iv = max(iv / 2, (unsigned long) HZ/100);
-        else
+        } else {
                 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
+                iv = mce_adjust_timer(iv);
+        }
         __this_cpu_write(mce_next_interval, iv);
+        /* Might have become 0 after CMCI storm subsided */
+        if (iv) {
+                t->expires = jiffies + iv;
+                add_timer_on(t, smp_processor_id());
+        }
+}
 
-        t->expires = jiffies + iv;
-        add_timer_on(t, smp_processor_id());
+/*
+ * Ensure that the timer is firing in @interval from now.
+ */
+void mce_timer_kick(unsigned long interval)
+{
+        struct timer_list *t = &__get_cpu_var(mce_timer);
+        unsigned long when = jiffies + interval;
+        unsigned long iv = __this_cpu_read(mce_next_interval);
+
+        if (timer_pending(t)) {
+                if (time_before(when, t->expires))
+                        mod_timer_pinned(t, when);
+        } else {
+                t->expires = round_jiffies(when);
+                add_timer_on(t, smp_processor_id());
+        }
+        if (interval < iv)
+                __this_cpu_write(mce_next_interval, interval);
 }
 
 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
@@ -1548,6 +1581,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
         switch (c->x86_vendor) {
         case X86_VENDOR_INTEL:
                 mce_intel_feature_init(c);
+                mce_adjust_timer = mce_intel_adjust_timer;
                 break;
         case X86_VENDOR_AMD:
                 mce_amd_feature_init(c);
@@ -1559,7 +1593,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 
 static void mce_start_timer(unsigned int cpu, struct timer_list *t)
 {
-        unsigned long iv = check_interval * HZ;
+        unsigned long iv = mce_adjust_timer(check_interval * HZ);
 
         __this_cpu_write(mce_next_interval, iv);
 
@@ -2272,10 +2306,11 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
                 if (threshold_cpu_callback)
                         threshold_cpu_callback(action, cpu);
                 mce_device_remove(cpu);
+                mce_intel_hcpu_update(cpu);
                 break;
         case CPU_DOWN_PREPARE:
-                del_timer_sync(t);
                 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
+                del_timer_sync(t);
                 break;
         case CPU_DOWN_FAILED:
                 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 59648e48a145..098386fed48e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -15,6 +15,8 @@
 #include <asm/msr.h>
 #include <asm/mce.h>
 
+#include "mce-internal.h"
+
 /*
  * Support for Intel Correct Machine Check Interrupts. This allows
  * the CPU to raise an interrupt when a corrected machine check happened.
@@ -30,7 +32,22 @@ static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  */
 static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
 
-#define CMCI_THRESHOLD 1
+#define CMCI_THRESHOLD          1
+#define CMCI_POLL_INTERVAL      (30 * HZ)
+#define CMCI_STORM_INTERVAL     (1 * HZ)
+#define CMCI_STORM_THRESHOLD    15
+
+static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
+static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt);
+static DEFINE_PER_CPU(unsigned int, cmci_storm_state);
+
+enum {
+        CMCI_STORM_NONE,
+        CMCI_STORM_ACTIVE,
+        CMCI_STORM_SUBSIDED,
+};
+
+static atomic_t cmci_storm_on_cpus;
 
 static int cmci_supported(int *banks)
 {
@@ -53,6 +70,93 @@ static int cmci_supported(int *banks)
         return !!(cap & MCG_CMCI_P);
 }
 
+void mce_intel_cmci_poll(void)
+{
+        if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
+                return;
+        machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
+}
+
+void mce_intel_hcpu_update(unsigned long cpu)
+{
+        if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE)
+                atomic_dec(&cmci_storm_on_cpus);
+
+        per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
+}
+
+unsigned long mce_intel_adjust_timer(unsigned long interval)
+{
+        int r;
+
+        if (interval < CMCI_POLL_INTERVAL)
+                return interval;
+
+        switch (__this_cpu_read(cmci_storm_state)) {
+        case CMCI_STORM_ACTIVE:
+                /*
+                 * We switch back to interrupt mode once the poll timer has
+                 * silenced itself. That means no events recorded and the
+                 * timer interval is back to our poll interval.
+                 */
+                __this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
+                r = atomic_sub_return(1, &cmci_storm_on_cpus);
+                if (r == 0)
+                        pr_notice("CMCI storm subsided: switching to interrupt mode\n");
+                /* FALLTHROUGH */
+
+        case CMCI_STORM_SUBSIDED:
+                /*
+                 * We wait for all cpus to go back to SUBSIDED
+                 * state. When that happens we switch back to
+                 * interrupt mode.
+                 */
+                if (!atomic_read(&cmci_storm_on_cpus)) {
+                        __this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
+                        cmci_reenable();
+                        cmci_recheck();
+                }
+                return CMCI_POLL_INTERVAL;
+        default:
+                /*
+                 * We have shiny weather. Let the poll do whatever it
+                 * thinks.
+                 */
+                return interval;
+        }
+}
+
+static bool cmci_storm_detect(void)
+{
+        unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
+        unsigned long ts = __this_cpu_read(cmci_time_stamp);
+        unsigned long now = jiffies;
+        int r;
+
+        if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE)
+                return true;
+
+        if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) {
+                cnt++;
+        } else {
+                cnt = 1;
+                __this_cpu_write(cmci_time_stamp, now);
+        }
+        __this_cpu_write(cmci_storm_cnt, cnt);
+
+        if (cnt <= CMCI_STORM_THRESHOLD)
+                return false;
+
+        cmci_clear();
+        __this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
+        r = atomic_add_return(1, &cmci_storm_on_cpus);
+        mce_timer_kick(CMCI_POLL_INTERVAL);
+
+        if (r == 1)
+                pr_notice("CMCI storm detected: switching to poll mode\n");
+        return true;
+}
+
 /*
  * The interrupt handler. This is called on every event.
  * Just call the poller directly to log any events.
@@ -61,6 +165,8 @@ static int cmci_supported(int *banks)
  */
 static void intel_threshold_interrupt(void)
 {
+        if (cmci_storm_detect())
+                return;
         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
         mce_notify_irq();
 }