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-rw-r--r--arch/x86/kernel/cpu/Makefile32
-rw-r--r--arch/x86/kernel/cpu/addon_cpuid_features.c88
-rw-r--r--arch/x86/kernel/cpu/amd.c12
-rw-r--r--arch/x86/kernel/cpu/amd_64.c4
-rw-r--r--arch/x86/kernel/cpu/centaur.c14
-rw-r--r--arch/x86/kernel/cpu/centaur_64.c3
-rw-r--r--arch/x86/kernel/cpu/cmpxchg.c72
-rw-r--r--arch/x86/kernel/cpu/common.c626
-rw-r--r--arch/x86/kernel/cpu/common_64.c388
-rw-r--r--arch/x86/kernel/cpu/cpu.h18
-rw-r--r--arch/x86/kernel/cpu/cyrix.c54
-rw-r--r--arch/x86/kernel/cpu/feature_names.c83
-rw-r--r--arch/x86/kernel/cpu/intel.c85
-rw-r--r--arch/x86/kernel/cpu/intel_64.c8
-rw-r--r--arch/x86/kernel/cpu/intel_cacheinfo.c169
-rw-r--r--arch/x86/kernel/cpu/mkcapflags.pl32
-rw-r--r--arch/x86/kernel/cpu/mtrr/main.c2
-rw-r--r--arch/x86/kernel/cpu/powerflags.c20
-rw-r--r--arch/x86/kernel/cpu/transmeta.c3
-rw-r--r--arch/x86/kernel/cpu/umc.c3
20 files changed, 1091 insertions, 625 deletions
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index ee76eaad3001..403e689df0b8 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -3,22 +3,32 @@
3# 3#
4 4
5obj-y := intel_cacheinfo.o addon_cpuid_features.o 5obj-y := intel_cacheinfo.o addon_cpuid_features.o
6obj-y += proc.o feature_names.o 6obj-y += proc.o capflags.o powerflags.o
7 7
8obj-$(CONFIG_X86_32) += common.o bugs.o 8obj-$(CONFIG_X86_32) += common.o bugs.o cmpxchg.o
9obj-$(CONFIG_X86_64) += common_64.o bugs_64.o 9obj-$(CONFIG_X86_64) += common_64.o bugs_64.o
10obj-$(CONFIG_X86_32) += amd.o 10
11obj-$(CONFIG_X86_64) += amd_64.o 11obj-$(CONFIG_CPU_SUP_INTEL_32) += intel.o
12obj-$(CONFIG_X86_32) += cyrix.o 12obj-$(CONFIG_CPU_SUP_INTEL_64) += intel_64.o
13obj-$(CONFIG_X86_32) += centaur.o 13obj-$(CONFIG_CPU_SUP_AMD_32) += amd.o
14obj-$(CONFIG_X86_64) += centaur_64.o 14obj-$(CONFIG_CPU_SUP_AMD_64) += amd_64.o
15obj-$(CONFIG_X86_32) += transmeta.o 15obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
16obj-$(CONFIG_X86_32) += intel.o 16obj-$(CONFIG_CPU_SUP_CENTAUR_32) += centaur.o
17obj-$(CONFIG_X86_64) += intel_64.o 17obj-$(CONFIG_CPU_SUP_CENTAUR_64) += centaur_64.o
18obj-$(CONFIG_X86_32) += umc.o 18obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
19obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
19 20
20obj-$(CONFIG_X86_MCE) += mcheck/ 21obj-$(CONFIG_X86_MCE) += mcheck/
21obj-$(CONFIG_MTRR) += mtrr/ 22obj-$(CONFIG_MTRR) += mtrr/
22obj-$(CONFIG_CPU_FREQ) += cpufreq/ 23obj-$(CONFIG_CPU_FREQ) += cpufreq/
23 24
24obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o 25obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
26
27quiet_cmd_mkcapflags = MKCAP $@
28 cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
29
30cpufeature = $(src)/../../../../include/asm-x86/cpufeature.h
31
32targets += capflags.c
33$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.pl FORCE
34 $(call if_changed,mkcapflags)
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index a6ef672adbba..0d9c993aa93e 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -7,6 +7,8 @@
7#include <asm/pat.h> 7#include <asm/pat.h>
8#include <asm/processor.h> 8#include <asm/processor.h>
9 9
10#include <mach_apic.h>
11
10struct cpuid_bit { 12struct cpuid_bit {
11 u16 feature; 13 u16 feature;
12 u8 reg; 14 u8 reg;
@@ -48,6 +50,92 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
48 } 50 }
49} 51}
50 52
53/* leaf 0xb SMT level */
54#define SMT_LEVEL 0
55
56/* leaf 0xb sub-leaf types */
57#define INVALID_TYPE 0
58#define SMT_TYPE 1
59#define CORE_TYPE 2
60
61#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
62#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
63#define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
64
65/*
66 * Check for extended topology enumeration cpuid leaf 0xb and if it
67 * exists, use it for populating initial_apicid and cpu topology
68 * detection.
69 */
70void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
71{
72#ifdef CONFIG_SMP
73 unsigned int eax, ebx, ecx, edx, sub_index;
74 unsigned int ht_mask_width, core_plus_mask_width;
75 unsigned int core_select_mask, core_level_siblings;
76
77 if (c->cpuid_level < 0xb)
78 return;
79
80 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
81
82 /*
83 * check if the cpuid leaf 0xb is actually implemented.
84 */
85 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
86 return;
87
88 set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
89
90 /*
91 * initial apic id, which also represents 32-bit extended x2apic id.
92 */
93 c->initial_apicid = edx;
94
95 /*
96 * Populate HT related information from sub-leaf level 0.
97 */
98 core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
99 core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
100
101 sub_index = 1;
102 do {
103 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
104
105 /*
106 * Check for the Core type in the implemented sub leaves.
107 */
108 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
109 core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
110 core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
111 break;
112 }
113
114 sub_index++;
115 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
116
117 core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
118
119#ifdef CONFIG_X86_32
120 c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
121 & core_select_mask;
122 c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
123#else
124 c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
125 c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
126#endif
127 c->x86_max_cores = (core_level_siblings / smp_num_siblings);
128
129
130 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
131 c->phys_proc_id);
132 if (c->x86_max_cores > 1)
133 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
134 c->cpu_core_id);
135 return;
136#endif
137}
138
51#ifdef CONFIG_X86_PAT 139#ifdef CONFIG_X86_PAT
52void __cpuinit validate_pat_support(struct cpuinfo_x86 *c) 140void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
53{ 141{
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index cae9cabc3031..d64ea6097ca7 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -31,6 +31,11 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
31 if (c->x86_power & (1<<8)) 31 if (c->x86_power & (1<<8))
32 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 32 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
33 } 33 }
34
35 /* Set MTRR capability flag if appropriate */
36 if (c->x86_model == 13 || c->x86_model == 9 ||
37 (c->x86_model == 8 && c->x86_mask >= 8))
38 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
34} 39}
35 40
36static void __cpuinit init_amd(struct cpuinfo_x86 *c) 41static void __cpuinit init_amd(struct cpuinfo_x86 *c)
@@ -166,10 +171,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
166 mbytes); 171 mbytes);
167 } 172 }
168 173
169 /* Set MTRR capability flag if appropriate */
170 if (c->x86_model == 13 || c->x86_model == 9 ||
171 (c->x86_model == 8 && c->x86_mask >= 8))
172 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
173 break; 174 break;
174 } 175 }
175 176
@@ -297,6 +298,7 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
297 .c_early_init = early_init_amd, 298 .c_early_init = early_init_amd,
298 .c_init = init_amd, 299 .c_init = init_amd,
299 .c_size_cache = amd_size_cache, 300 .c_size_cache = amd_size_cache,
301 .c_x86_vendor = X86_VENDOR_AMD,
300}; 302};
301 303
302cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev); 304cpu_dev_register(amd_cpu_dev);
diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
index d1692b2a41ff..d1c721c0c49f 100644
--- a/arch/x86/kernel/cpu/amd_64.c
+++ b/arch/x86/kernel/cpu/amd_64.c
@@ -218,7 +218,7 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
218 .c_ident = { "AuthenticAMD" }, 218 .c_ident = { "AuthenticAMD" },
219 .c_early_init = early_init_amd, 219 .c_early_init = early_init_amd,
220 .c_init = init_amd, 220 .c_init = init_amd,
221 .c_x86_vendor = X86_VENDOR_AMD,
221}; 222};
222 223
223cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev); 224cpu_dev_register(amd_cpu_dev);
224
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index e0f45edd6a55..e5f6d89521bf 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -314,6 +314,16 @@ enum {
314 EAMD3D = 1<<20, 314 EAMD3D = 1<<20,
315}; 315};
316 316
317static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
318{
319 switch (c->x86) {
320 case 5:
321 /* Emulate MTRRs using Centaur's MCR. */
322 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
323 break;
324 }
325}
326
317static void __cpuinit init_centaur(struct cpuinfo_x86 *c) 327static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
318{ 328{
319 329
@@ -462,8 +472,10 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
462static struct cpu_dev centaur_cpu_dev __cpuinitdata = { 472static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
463 .c_vendor = "Centaur", 473 .c_vendor = "Centaur",
464 .c_ident = { "CentaurHauls" }, 474 .c_ident = { "CentaurHauls" },
475 .c_early_init = early_init_centaur,
465 .c_init = init_centaur, 476 .c_init = init_centaur,
466 .c_size_cache = centaur_size_cache, 477 .c_size_cache = centaur_size_cache,
478 .c_x86_vendor = X86_VENDOR_CENTAUR,
467}; 479};
468 480
469cpu_vendor_dev_register(X86_VENDOR_CENTAUR, &centaur_cpu_dev); 481cpu_dev_register(centaur_cpu_dev);
diff --git a/arch/x86/kernel/cpu/centaur_64.c b/arch/x86/kernel/cpu/centaur_64.c
index 1d181c40e2e1..49cfc6d2f2fb 100644
--- a/arch/x86/kernel/cpu/centaur_64.c
+++ b/arch/x86/kernel/cpu/centaur_64.c
@@ -29,7 +29,8 @@ static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
29 .c_ident = { "CentaurHauls" }, 29 .c_ident = { "CentaurHauls" },
30 .c_early_init = early_init_centaur, 30 .c_early_init = early_init_centaur,
31 .c_init = init_centaur, 31 .c_init = init_centaur,
32 .c_x86_vendor = X86_VENDOR_CENTAUR,
32}; 33};
33 34
34cpu_vendor_dev_register(X86_VENDOR_CENTAUR, &centaur_cpu_dev); 35cpu_dev_register(centaur_cpu_dev);
35 36
diff --git a/arch/x86/kernel/cpu/cmpxchg.c b/arch/x86/kernel/cpu/cmpxchg.c
new file mode 100644
index 000000000000..2056ccf572cc
--- /dev/null
+++ b/arch/x86/kernel/cpu/cmpxchg.c
@@ -0,0 +1,72 @@
1/*
2 * cmpxchg*() fallbacks for CPU not supporting these instructions
3 */
4
5#include <linux/kernel.h>
6#include <linux/smp.h>
7#include <linux/module.h>
8
9#ifndef CONFIG_X86_CMPXCHG
10unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
11{
12 u8 prev;
13 unsigned long flags;
14
15 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
16 local_irq_save(flags);
17 prev = *(u8 *)ptr;
18 if (prev == old)
19 *(u8 *)ptr = new;
20 local_irq_restore(flags);
21 return prev;
22}
23EXPORT_SYMBOL(cmpxchg_386_u8);
24
25unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
26{
27 u16 prev;
28 unsigned long flags;
29
30 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
31 local_irq_save(flags);
32 prev = *(u16 *)ptr;
33 if (prev == old)
34 *(u16 *)ptr = new;
35 local_irq_restore(flags);
36 return prev;
37}
38EXPORT_SYMBOL(cmpxchg_386_u16);
39
40unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
41{
42 u32 prev;
43 unsigned long flags;
44
45 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
46 local_irq_save(flags);
47 prev = *(u32 *)ptr;
48 if (prev == old)
49 *(u32 *)ptr = new;
50 local_irq_restore(flags);
51 return prev;
52}
53EXPORT_SYMBOL(cmpxchg_386_u32);
54#endif
55
56#ifndef CONFIG_X86_CMPXCHG64
57unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
58{
59 u64 prev;
60 unsigned long flags;
61
62 /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
63 local_irq_save(flags);
64 prev = *(u64 *)ptr;
65 if (prev == old)
66 *(u64 *)ptr = new;
67 local_irq_restore(flags);
68 return prev;
69}
70EXPORT_SYMBOL(cmpxchg_486_u64);
71#endif
72
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 80ab20d4fa39..7d5a07f0fd24 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -13,6 +13,7 @@
13#include <asm/mtrr.h> 13#include <asm/mtrr.h>
14#include <asm/mce.h> 14#include <asm/mce.h>
15#include <asm/pat.h> 15#include <asm/pat.h>
16#include <asm/asm.h>
16#ifdef CONFIG_X86_LOCAL_APIC 17#ifdef CONFIG_X86_LOCAL_APIC
17#include <asm/mpspec.h> 18#include <asm/mpspec.h>
18#include <asm/apic.h> 19#include <asm/apic.h>
@@ -21,7 +22,9 @@
21 22
22#include "cpu.h" 23#include "cpu.h"
23 24
24DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { 25static struct cpu_dev *this_cpu __cpuinitdata;
26
27DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 28 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 29 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 30 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
@@ -57,12 +60,124 @@ DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
57} }; 60} };
58EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 61EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
59 62
60__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
61
62static int cachesize_override __cpuinitdata = -1; 63static int cachesize_override __cpuinitdata = -1;
63static int disable_x86_serial_nr __cpuinitdata = 1; 64static int disable_x86_serial_nr __cpuinitdata = 1;
64 65
65struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 66static int __init cachesize_setup(char *str)
67{
68 get_option(&str, &cachesize_override);
69 return 1;
70}
71__setup("cachesize=", cachesize_setup);
72
73/*
74 * Naming convention should be: <Name> [(<Codename>)]
75 * This table only is used unless init_<vendor>() below doesn't set it;
76 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
77 *
78 */
79
80/* Look up CPU names by table lookup. */
81static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
82{
83 struct cpu_model_info *info;
84
85 if (c->x86_model >= 16)
86 return NULL; /* Range check */
87
88 if (!this_cpu)
89 return NULL;
90
91 info = this_cpu->c_models;
92
93 while (info && info->family) {
94 if (info->family == c->x86)
95 return info->model_names[c->x86_model];
96 info++;
97 }
98 return NULL; /* Not found */
99}
100
101static int __init x86_fxsr_setup(char *s)
102{
103 setup_clear_cpu_cap(X86_FEATURE_FXSR);
104 setup_clear_cpu_cap(X86_FEATURE_XMM);
105 return 1;
106}
107__setup("nofxsr", x86_fxsr_setup);
108
109static int __init x86_sep_setup(char *s)
110{
111 setup_clear_cpu_cap(X86_FEATURE_SEP);
112 return 1;
113}
114__setup("nosep", x86_sep_setup);
115
116/* Standard macro to see if a specific flag is changeable */
117static inline int flag_is_changeable_p(u32 flag)
118{
119 u32 f1, f2;
120
121 asm("pushfl\n\t"
122 "pushfl\n\t"
123 "popl %0\n\t"
124 "movl %0,%1\n\t"
125 "xorl %2,%0\n\t"
126 "pushl %0\n\t"
127 "popfl\n\t"
128 "pushfl\n\t"
129 "popl %0\n\t"
130 "popfl\n\t"
131 : "=&r" (f1), "=&r" (f2)
132 : "ir" (flag));
133
134 return ((f1^f2) & flag) != 0;
135}
136
137/* Probe for the CPUID instruction */
138static int __cpuinit have_cpuid_p(void)
139{
140 return flag_is_changeable_p(X86_EFLAGS_ID);
141}
142
143static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
144{
145 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
146 /* Disable processor serial number */
147 unsigned long lo, hi;
148 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
149 lo |= 0x200000;
150 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
151 printk(KERN_NOTICE "CPU serial number disabled.\n");
152 clear_cpu_cap(c, X86_FEATURE_PN);
153
154 /* Disabling the serial number may affect the cpuid level */
155 c->cpuid_level = cpuid_eax(0);
156 }
157}
158
159static int __init x86_serial_nr_setup(char *s)
160{
161 disable_x86_serial_nr = 0;
162 return 1;
163}
164__setup("serialnumber", x86_serial_nr_setup);
165
166__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
167
168/* Current gdt points %fs at the "master" per-cpu area: after this,
169 * it's on the real one. */
170void switch_to_new_gdt(void)
171{
172 struct desc_ptr gdt_descr;
173
174 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
175 gdt_descr.size = GDT_SIZE - 1;
176 load_gdt(&gdt_descr);
177 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
178}
179
180static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
66 181
67static void __cpuinit default_init(struct cpuinfo_x86 *c) 182static void __cpuinit default_init(struct cpuinfo_x86 *c)
68{ 183{
@@ -80,22 +195,15 @@ static void __cpuinit default_init(struct cpuinfo_x86 *c)
80static struct cpu_dev __cpuinitdata default_cpu = { 195static struct cpu_dev __cpuinitdata default_cpu = {
81 .c_init = default_init, 196 .c_init = default_init,
82 .c_vendor = "Unknown", 197 .c_vendor = "Unknown",
198 .c_x86_vendor = X86_VENDOR_UNKNOWN,
83}; 199};
84static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
85
86static int __init cachesize_setup(char *str)
87{
88 get_option(&str, &cachesize_override);
89 return 1;
90}
91__setup("cachesize=", cachesize_setup);
92 200
93int __cpuinit get_model_name(struct cpuinfo_x86 *c) 201int __cpuinit get_model_name(struct cpuinfo_x86 *c)
94{ 202{
95 unsigned int *v; 203 unsigned int *v;
96 char *p, *q; 204 char *p, *q;
97 205
98 if (cpuid_eax(0x80000000) < 0x80000004) 206 if (c->extended_cpuid_level < 0x80000004)
99 return 0; 207 return 0;
100 208
101 v = (unsigned int *) c->x86_model_id; 209 v = (unsigned int *) c->x86_model_id;
@@ -119,24 +227,23 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
119 return 1; 227 return 1;
120} 228}
121 229
122
123void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 230void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
124{ 231{
125 unsigned int n, dummy, ecx, edx, l2size; 232 unsigned int n, dummy, ebx, ecx, edx, l2size;
126 233
127 n = cpuid_eax(0x80000000); 234 n = c->extended_cpuid_level;
128 235
129 if (n >= 0x80000005) { 236 if (n >= 0x80000005) {
130 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); 237 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
131 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 238 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
132 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 239 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
133 c->x86_cache_size = (ecx>>24)+(edx>>24); 240 c->x86_cache_size = (ecx>>24) + (edx>>24);
134 } 241 }
135 242
136 if (n < 0x80000006) /* Some chips just has a large L1. */ 243 if (n < 0x80000006) /* Some chips just has a large L1. */
137 return; 244 return;
138 245
139 ecx = cpuid_ecx(0x80000006); 246 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
140 l2size = ecx >> 16; 247 l2size = ecx >> 16;
141 248
142 /* do processor-specific cache resizing */ 249 /* do processor-specific cache resizing */
@@ -153,112 +260,90 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
153 c->x86_cache_size = l2size; 260 c->x86_cache_size = l2size;
154 261
155 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 262 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
156 l2size, ecx & 0xFF); 263 l2size, ecx & 0xFF);
157} 264}
158 265
159/* 266#ifdef CONFIG_X86_HT
160 * Naming convention should be: <Name> [(<Codename>)] 267void __cpuinit detect_ht(struct cpuinfo_x86 *c)
161 * This table only is used unless init_<vendor>() below doesn't set it;
162 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
163 *
164 */
165
166/* Look up CPU names by table lookup. */
167static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
168{ 268{
169 struct cpu_model_info *info; 269 u32 eax, ebx, ecx, edx;
270 int index_msb, core_bits;
170 271
171 if (c->x86_model >= 16) 272 if (!cpu_has(c, X86_FEATURE_HT))
172 return NULL; /* Range check */ 273 return;
173 274
174 if (!this_cpu) 275 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
175 return NULL; 276 goto out;
176 277
177 info = this_cpu->c_models; 278 cpuid(1, &eax, &ebx, &ecx, &edx);
178 279
179 while (info && info->family) { 280 smp_num_siblings = (ebx & 0xff0000) >> 16;
180 if (info->family == c->x86) 281
181 return info->model_names[c->x86_model]; 282 if (smp_num_siblings == 1) {
182 info++; 283 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
284 } else if (smp_num_siblings > 1) {
285
286 if (smp_num_siblings > NR_CPUS) {
287 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
288 smp_num_siblings);
289 smp_num_siblings = 1;
290 return;
291 }
292
293 index_msb = get_count_order(smp_num_siblings);
294 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
295
296
297 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
298
299 index_msb = get_count_order(smp_num_siblings);
300
301 core_bits = get_count_order(c->x86_max_cores);
302
303 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
304 ((1 << core_bits) - 1);
183 } 305 }
184 return NULL; /* Not found */
185}
186 306
307out:
308 if ((c->x86_max_cores * smp_num_siblings) > 1) {
309 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
310 c->phys_proc_id);
311 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
312 c->cpu_core_id);
313 }
314}
315#endif
187 316
188static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) 317static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
189{ 318{
190 char *v = c->x86_vendor_id; 319 char *v = c->x86_vendor_id;
191 int i; 320 int i;
192 static int printed; 321 static int printed;
193 322
194 for (i = 0; i < X86_VENDOR_NUM; i++) { 323 for (i = 0; i < X86_VENDOR_NUM; i++) {
195 if (cpu_devs[i]) { 324 if (!cpu_devs[i])
196 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 325 break;
197 (cpu_devs[i]->c_ident[1] && 326
198 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 327 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
199 c->x86_vendor = i; 328 (cpu_devs[i]->c_ident[1] &&
200 if (!early) 329 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
201 this_cpu = cpu_devs[i]; 330 this_cpu = cpu_devs[i];
202 return; 331 c->x86_vendor = this_cpu->c_x86_vendor;
203 } 332 return;
204 } 333 }
205 } 334 }
335
206 if (!printed) { 336 if (!printed) {
207 printed++; 337 printed++;
208 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); 338 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
209 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 339 printk(KERN_ERR "CPU: Your system may be unstable.\n");
210 } 340 }
341
211 c->x86_vendor = X86_VENDOR_UNKNOWN; 342 c->x86_vendor = X86_VENDOR_UNKNOWN;
212 this_cpu = &default_cpu; 343 this_cpu = &default_cpu;
213} 344}
214 345
215 346void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
216static int __init x86_fxsr_setup(char *s)
217{
218 setup_clear_cpu_cap(X86_FEATURE_FXSR);
219 setup_clear_cpu_cap(X86_FEATURE_XMM);
220 return 1;
221}
222__setup("nofxsr", x86_fxsr_setup);
223
224
225static int __init x86_sep_setup(char *s)
226{
227 setup_clear_cpu_cap(X86_FEATURE_SEP);
228 return 1;
229}
230__setup("nosep", x86_sep_setup);
231
232
233/* Standard macro to see if a specific flag is changeable */
234static inline int flag_is_changeable_p(u32 flag)
235{
236 u32 f1, f2;
237
238 asm("pushfl\n\t"
239 "pushfl\n\t"
240 "popl %0\n\t"
241 "movl %0,%1\n\t"
242 "xorl %2,%0\n\t"
243 "pushl %0\n\t"
244 "popfl\n\t"
245 "pushfl\n\t"
246 "popl %0\n\t"
247 "popfl\n\t"
248 : "=&r" (f1), "=&r" (f2)
249 : "ir" (flag));
250
251 return ((f1^f2) & flag) != 0;
252}
253
254
255/* Probe for the CPUID instruction */
256static int __cpuinit have_cpuid_p(void)
257{
258 return flag_is_changeable_p(X86_EFLAGS_ID);
259}
260
261void __init cpu_detect(struct cpuinfo_x86 *c)
262{ 347{
263 /* Get vendor name */ 348 /* Get vendor name */
264 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 349 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
@@ -267,50 +352,47 @@ void __init cpu_detect(struct cpuinfo_x86 *c)
267 (unsigned int *)&c->x86_vendor_id[4]); 352 (unsigned int *)&c->x86_vendor_id[4]);
268 353
269 c->x86 = 4; 354 c->x86 = 4;
355 /* Intel-defined flags: level 0x00000001 */
270 if (c->cpuid_level >= 0x00000001) { 356 if (c->cpuid_level >= 0x00000001) {
271 u32 junk, tfms, cap0, misc; 357 u32 junk, tfms, cap0, misc;
272 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 358 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
273 c->x86 = (tfms >> 8) & 15; 359 c->x86 = (tfms >> 8) & 0xf;
274 c->x86_model = (tfms >> 4) & 15; 360 c->x86_model = (tfms >> 4) & 0xf;
361 c->x86_mask = tfms & 0xf;
275 if (c->x86 == 0xf) 362 if (c->x86 == 0xf)
276 c->x86 += (tfms >> 20) & 0xff; 363 c->x86 += (tfms >> 20) & 0xff;
277 if (c->x86 >= 0x6) 364 if (c->x86 >= 0x6)
278 c->x86_model += ((tfms >> 16) & 0xF) << 4; 365 c->x86_model += ((tfms >> 16) & 0xf) << 4;
279 c->x86_mask = tfms & 15;
280 if (cap0 & (1<<19)) { 366 if (cap0 & (1<<19)) {
281 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
282 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 367 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
368 c->x86_cache_alignment = c->x86_clflush_size;
283 } 369 }
284 } 370 }
285} 371}
286static void __cpuinit early_get_cap(struct cpuinfo_x86 *c) 372
373static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
287{ 374{
288 u32 tfms, xlvl; 375 u32 tfms, xlvl;
289 unsigned int ebx; 376 u32 ebx;
290 377
291 memset(&c->x86_capability, 0, sizeof c->x86_capability); 378 /* Intel-defined flags: level 0x00000001 */
292 if (have_cpuid_p()) { 379 if (c->cpuid_level >= 0x00000001) {
293 /* Intel-defined flags: level 0x00000001 */ 380 u32 capability, excap;
294 if (c->cpuid_level >= 0x00000001) { 381 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
295 u32 capability, excap; 382 c->x86_capability[0] = capability;
296 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 383 c->x86_capability[4] = excap;
297 c->x86_capability[0] = capability; 384 }
298 c->x86_capability[4] = excap;
299 }
300 385
301 /* AMD-defined flags: level 0x80000001 */ 386 /* AMD-defined flags: level 0x80000001 */
302 xlvl = cpuid_eax(0x80000000); 387 xlvl = cpuid_eax(0x80000000);
303 if ((xlvl & 0xffff0000) == 0x80000000) { 388 c->extended_cpuid_level = xlvl;
304 if (xlvl >= 0x80000001) { 389 if ((xlvl & 0xffff0000) == 0x80000000) {
305 c->x86_capability[1] = cpuid_edx(0x80000001); 390 if (xlvl >= 0x80000001) {
306 c->x86_capability[6] = cpuid_ecx(0x80000001); 391 c->x86_capability[1] = cpuid_edx(0x80000001);
307 } 392 c->x86_capability[6] = cpuid_ecx(0x80000001);
308 } 393 }
309
310 } 394 }
311
312} 395}
313
314/* 396/*
315 * Do minimum CPU detection early. 397 * Do minimum CPU detection early.
316 * Fields really needed: vendor, cpuid_level, family, model, mask, 398 * Fields really needed: vendor, cpuid_level, family, model, mask,
@@ -320,109 +402,114 @@ static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
320 * WARNING: this function is only called on the BP. Don't add code here 402 * WARNING: this function is only called on the BP. Don't add code here
321 * that is supposed to run on all CPUs. 403 * that is supposed to run on all CPUs.
322 */ 404 */
323static void __init early_cpu_detect(void) 405static void __init early_identify_cpu(struct cpuinfo_x86 *c)
324{ 406{
325 struct cpuinfo_x86 *c = &boot_cpu_data;
326
327 c->x86_cache_alignment = 32;
328 c->x86_clflush_size = 32; 407 c->x86_clflush_size = 32;
408 c->x86_cache_alignment = c->x86_clflush_size;
329 409
330 if (!have_cpuid_p()) 410 if (!have_cpuid_p())
331 return; 411 return;
332 412
413 memset(&c->x86_capability, 0, sizeof c->x86_capability);
414
415 c->extended_cpuid_level = 0;
416
333 cpu_detect(c); 417 cpu_detect(c);
334 418
335 get_cpu_vendor(c, 1); 419 get_cpu_vendor(c);
420
421 get_cpu_cap(c);
336 422
337 if (c->x86_vendor != X86_VENDOR_UNKNOWN && 423 if (this_cpu->c_early_init)
338 cpu_devs[c->x86_vendor]->c_early_init) 424 this_cpu->c_early_init(c);
339 cpu_devs[c->x86_vendor]->c_early_init(c);
340 425
341 early_get_cap(c); 426 validate_pat_support(c);
342} 427}
343 428
344static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 429void __init early_cpu_init(void)
345{ 430{
346 u32 tfms, xlvl; 431 struct cpu_dev **cdev;
347 unsigned int ebx; 432 int count = 0;
348 433
349 if (have_cpuid_p()) { 434 printk("KERNEL supported cpus:\n");
350 /* Get vendor name */ 435 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
351 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 436 struct cpu_dev *cpudev = *cdev;
352 (unsigned int *)&c->x86_vendor_id[0], 437 unsigned int j;
353 (unsigned int *)&c->x86_vendor_id[8], 438
354 (unsigned int *)&c->x86_vendor_id[4]); 439 if (count >= X86_VENDOR_NUM)
355 440 break;
356 get_cpu_vendor(c, 0); 441 cpu_devs[count] = cpudev;
357 /* Initialize the standard set of capabilities */ 442 count++;
358 /* Note that the vendor-specific code below might override */ 443
359 /* Intel-defined flags: level 0x00000001 */ 444 for (j = 0; j < 2; j++) {
360 if (c->cpuid_level >= 0x00000001) { 445 if (!cpudev->c_ident[j])
361 u32 capability, excap; 446 continue;
362 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 447 printk(" %s %s\n", cpudev->c_vendor,
363 c->x86_capability[0] = capability; 448 cpudev->c_ident[j]);
364 c->x86_capability[4] = excap;
365 c->x86 = (tfms >> 8) & 15;
366 c->x86_model = (tfms >> 4) & 15;
367 if (c->x86 == 0xf)
368 c->x86 += (tfms >> 20) & 0xff;
369 if (c->x86 >= 0x6)
370 c->x86_model += ((tfms >> 16) & 0xF) << 4;
371 c->x86_mask = tfms & 15;
372 c->initial_apicid = (ebx >> 24) & 0xFF;
373#ifdef CONFIG_X86_HT
374 c->apicid = phys_pkg_id(c->initial_apicid, 0);
375 c->phys_proc_id = c->initial_apicid;
376#else
377 c->apicid = c->initial_apicid;
378#endif
379 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
380 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
381 } else {
382 /* Have CPUID level 0 only - unheard of */
383 c->x86 = 4;
384 }
385
386 /* AMD-defined flags: level 0x80000001 */
387 xlvl = cpuid_eax(0x80000000);
388 if ((xlvl & 0xffff0000) == 0x80000000) {
389 if (xlvl >= 0x80000001) {
390 c->x86_capability[1] = cpuid_edx(0x80000001);
391 c->x86_capability[6] = cpuid_ecx(0x80000001);
392 }
393 if (xlvl >= 0x80000004)
394 get_model_name(c); /* Default name */
395 } 449 }
396
397 init_scattered_cpuid_features(c);
398 } 450 }
399 451
452 early_identify_cpu(&boot_cpu_data);
400} 453}
401 454
402static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 455/*
456 * The NOPL instruction is supposed to exist on all CPUs with
457 * family >= 6, unfortunately, that's not true in practice because
458 * of early VIA chips and (more importantly) broken virtualizers that
459 * are not easy to detect. Hence, probe for it based on first
460 * principles.
461 */
462static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
403{ 463{
404 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { 464 const u32 nopl_signature = 0x888c53b1; /* Random number */
405 /* Disable processor serial number */ 465 u32 has_nopl = nopl_signature;
406 unsigned long lo, hi; 466
407 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 467 clear_cpu_cap(c, X86_FEATURE_NOPL);
408 lo |= 0x200000; 468 if (c->x86 >= 6) {
409 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 469 asm volatile("\n"
410 printk(KERN_NOTICE "CPU serial number disabled.\n"); 470 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
411 clear_cpu_cap(c, X86_FEATURE_PN); 471 "2:\n"
412 472 " .section .fixup,\"ax\"\n"
413 /* Disabling the serial number may affect the cpuid level */ 473 "3: xor %0,%0\n"
414 c->cpuid_level = cpuid_eax(0); 474 " jmp 2b\n"
475 " .previous\n"
476 _ASM_EXTABLE(1b,3b)
477 : "+a" (has_nopl));
478
479 if (has_nopl == nopl_signature)
480 set_cpu_cap(c, X86_FEATURE_NOPL);
415 } 481 }
416} 482}
417 483
418static int __init x86_serial_nr_setup(char *s) 484static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
419{ 485{
420 disable_x86_serial_nr = 0; 486 if (!have_cpuid_p())
421 return 1; 487 return;
422}
423__setup("serialnumber", x86_serial_nr_setup);
424 488
489 c->extended_cpuid_level = 0;
425 490
491 cpu_detect(c);
492
493 get_cpu_vendor(c);
494
495 get_cpu_cap(c);
496
497 if (c->cpuid_level >= 0x00000001) {
498 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
499#ifdef CONFIG_X86_HT
500 c->apicid = phys_pkg_id(c->initial_apicid, 0);
501 c->phys_proc_id = c->initial_apicid;
502#else
503 c->apicid = c->initial_apicid;
504#endif
505 }
506
507 if (c->extended_cpuid_level >= 0x80000004)
508 get_model_name(c); /* Default name */
509
510 init_scattered_cpuid_features(c);
511 detect_nopl(c);
512}
426 513
427/* 514/*
428 * This does the hard work of actually picking apart the CPU stuff... 515 * This does the hard work of actually picking apart the CPU stuff...
@@ -499,7 +586,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
499 */ 586 */
500 if (c != &boot_cpu_data) { 587 if (c != &boot_cpu_data) {
501 /* AND the already accumulated flags with these */ 588 /* AND the already accumulated flags with these */
502 for (i = 0 ; i < NCAPINTS ; i++) 589 for (i = 0; i < NCAPINTS; i++)
503 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 590 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
504 } 591 }
505 592
@@ -528,51 +615,48 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
528 mtrr_ap_init(); 615 mtrr_ap_init();
529} 616}
530 617
531#ifdef CONFIG_X86_HT 618struct msr_range {
532void __cpuinit detect_ht(struct cpuinfo_x86 *c) 619 unsigned min;
533{ 620 unsigned max;
534 u32 eax, ebx, ecx, edx; 621};
535 int index_msb, core_bits;
536
537 cpuid(1, &eax, &ebx, &ecx, &edx);
538
539 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
540 return;
541
542 smp_num_siblings = (ebx & 0xff0000) >> 16;
543 622
544 if (smp_num_siblings == 1) { 623static struct msr_range msr_range_array[] __cpuinitdata = {
545 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 624 { 0x00000000, 0x00000418},
546 } else if (smp_num_siblings > 1) { 625 { 0xc0000000, 0xc000040b},
626 { 0xc0010000, 0xc0010142},
627 { 0xc0011000, 0xc001103b},
628};
547 629
548 if (smp_num_siblings > NR_CPUS) { 630static void __cpuinit print_cpu_msr(void)
549 printk(KERN_WARNING "CPU: Unsupported number of the " 631{
550 "siblings %d", smp_num_siblings); 632 unsigned index;
551 smp_num_siblings = 1; 633 u64 val;
552 return; 634 int i;
635 unsigned index_min, index_max;
636
637 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
638 index_min = msr_range_array[i].min;
639 index_max = msr_range_array[i].max;
640 for (index = index_min; index < index_max; index++) {
641 if (rdmsrl_amd_safe(index, &val))
642 continue;
643 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
553 } 644 }
645 }
646}
554 647
555 index_msb = get_count_order(smp_num_siblings); 648static int show_msr __cpuinitdata;
556 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); 649static __init int setup_show_msr(char *arg)
557 650{
558 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 651 int num;
559 c->phys_proc_id);
560
561 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
562
563 index_msb = get_count_order(smp_num_siblings) ;
564
565 core_bits = get_count_order(c->x86_max_cores);
566 652
567 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & 653 get_option(&arg, &num);
568 ((1 << core_bits) - 1);
569 654
570 if (c->x86_max_cores > 1) 655 if (num > 0)
571 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 656 show_msr = num;
572 c->cpu_core_id); 657 return 1;
573 }
574} 658}
575#endif 659__setup("show_msr=", setup_show_msr);
576 660
577static __init int setup_noclflush(char *arg) 661static __init int setup_noclflush(char *arg)
578{ 662{
@@ -591,17 +675,25 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
591 vendor = c->x86_vendor_id; 675 vendor = c->x86_vendor_id;
592 676
593 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) 677 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
594 printk("%s ", vendor); 678 printk(KERN_CONT "%s ", vendor);
595 679
596 if (!c->x86_model_id[0]) 680 if (c->x86_model_id[0])
597 printk("%d86", c->x86); 681 printk(KERN_CONT "%s", c->x86_model_id);
598 else 682 else
599 printk("%s", c->x86_model_id); 683 printk(KERN_CONT "%d86", c->x86);
600 684
601 if (c->x86_mask || c->cpuid_level >= 0) 685 if (c->x86_mask || c->cpuid_level >= 0)
602 printk(" stepping %02x\n", c->x86_mask); 686 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
603 else 687 else
604 printk("\n"); 688 printk(KERN_CONT "\n");
689
690#ifdef CONFIG_SMP
691 if (c->cpu_index < show_msr)
692 print_cpu_msr();
693#else
694 if (show_msr)
695 print_cpu_msr();
696#endif
605} 697}
606 698
607static __init int setup_disablecpuid(char *arg) 699static __init int setup_disablecpuid(char *arg)
@@ -617,19 +709,6 @@ __setup("clearcpuid=", setup_disablecpuid);
617 709
618cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; 710cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
619 711
620void __init early_cpu_init(void)
621{
622 struct cpu_vendor_dev *cvdev;
623
624 for (cvdev = __x86cpuvendor_start ;
625 cvdev < __x86cpuvendor_end ;
626 cvdev++)
627 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
628
629 early_cpu_detect();
630 validate_pat_support(&boot_cpu_data);
631}
632
633/* Make sure %fs is initialized properly in idle threads */ 712/* Make sure %fs is initialized properly in idle threads */
634struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 713struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
635{ 714{
@@ -638,18 +717,6 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
638 return regs; 717 return regs;
639} 718}
640 719
641/* Current gdt points %fs at the "master" per-cpu area: after this,
642 * it's on the real one. */
643void switch_to_new_gdt(void)
644{
645 struct desc_ptr gdt_descr;
646
647 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
648 gdt_descr.size = GDT_SIZE - 1;
649 load_gdt(&gdt_descr);
650 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
651}
652
653/* 720/*
654 * cpu_init() initializes state that is per-CPU. Some data is already 721 * cpu_init() initializes state that is per-CPU. Some data is already
655 * initialized (naturally) in the bootstrap process, such as the GDT 722 * initialized (naturally) in the bootstrap process, such as the GDT
@@ -709,9 +776,20 @@ void __cpuinit cpu_init(void)
709 /* 776 /*
710 * Force FPU initialization: 777 * Force FPU initialization:
711 */ 778 */
712 current_thread_info()->status = 0; 779 if (cpu_has_xsave)
780 current_thread_info()->status = TS_XSAVE;
781 else
782 current_thread_info()->status = 0;
713 clear_used_math(); 783 clear_used_math();
714 mxcsr_feature_mask_init(); 784 mxcsr_feature_mask_init();
785
786 /*
787 * Boot processor to setup the FP and extended state context info.
788 */
789 if (!smp_processor_id())
790 init_thread_xstate();
791
792 xsave_init();
715} 793}
716 794
717#ifdef CONFIG_HOTPLUG_CPU 795#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
index dd6e3f15017e..bcb48ce05d23 100644
--- a/arch/x86/kernel/cpu/common_64.c
+++ b/arch/x86/kernel/cpu/common_64.c
@@ -18,6 +18,7 @@
18#include <asm/mtrr.h> 18#include <asm/mtrr.h>
19#include <asm/mce.h> 19#include <asm/mce.h>
20#include <asm/pat.h> 20#include <asm/pat.h>
21#include <asm/asm.h>
21#include <asm/numa.h> 22#include <asm/numa.h>
22#ifdef CONFIG_X86_LOCAL_APIC 23#ifdef CONFIG_X86_LOCAL_APIC
23#include <asm/mpspec.h> 24#include <asm/mpspec.h>
@@ -36,6 +37,8 @@
36 37
37#include "cpu.h" 38#include "cpu.h"
38 39
40static struct cpu_dev *this_cpu __cpuinitdata;
41
39/* We need valid kernel segments for data and code in long mode too 42/* We need valid kernel segments for data and code in long mode too
40 * IRET will check the segment types kkeil 2000/10/28 43 * IRET will check the segment types kkeil 2000/10/28
41 * Also sysret mandates a special GDT layout 44 * Also sysret mandates a special GDT layout
@@ -65,7 +68,7 @@ void switch_to_new_gdt(void)
65 load_gdt(&gdt_descr); 68 load_gdt(&gdt_descr);
66} 69}
67 70
68struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 71static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
69 72
70static void __cpuinit default_init(struct cpuinfo_x86 *c) 73static void __cpuinit default_init(struct cpuinfo_x86 *c)
71{ 74{
@@ -75,12 +78,13 @@ static void __cpuinit default_init(struct cpuinfo_x86 *c)
75static struct cpu_dev __cpuinitdata default_cpu = { 78static struct cpu_dev __cpuinitdata default_cpu = {
76 .c_init = default_init, 79 .c_init = default_init,
77 .c_vendor = "Unknown", 80 .c_vendor = "Unknown",
81 .c_x86_vendor = X86_VENDOR_UNKNOWN,
78}; 82};
79static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
80 83
81int __cpuinit get_model_name(struct cpuinfo_x86 *c) 84int __cpuinit get_model_name(struct cpuinfo_x86 *c)
82{ 85{
83 unsigned int *v; 86 unsigned int *v;
87 char *p, *q;
84 88
85 if (c->extended_cpuid_level < 0x80000004) 89 if (c->extended_cpuid_level < 0x80000004)
86 return 0; 90 return 0;
@@ -90,35 +94,49 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
90 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 94 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
91 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 95 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
92 c->x86_model_id[48] = 0; 96 c->x86_model_id[48] = 0;
97
98 /* Intel chips right-justify this string for some dumb reason;
99 undo that brain damage */
100 p = q = &c->x86_model_id[0];
101 while (*p == ' ')
102 p++;
103 if (p != q) {
104 while (*p)
105 *q++ = *p++;
106 while (q <= &c->x86_model_id[48])
107 *q++ = '\0'; /* Zero-pad the rest */
108 }
109
93 return 1; 110 return 1;
94} 111}
95 112
96 113
97void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 114void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
98{ 115{
99 unsigned int n, dummy, ebx, ecx, edx; 116 unsigned int n, dummy, ebx, ecx, edx, l2size;
100 117
101 n = c->extended_cpuid_level; 118 n = c->extended_cpuid_level;
102 119
103 if (n >= 0x80000005) { 120 if (n >= 0x80000005) {
104 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 121 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
105 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " 122 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
106 "D cache %dK (%d bytes/line)\n", 123 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
107 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
108 c->x86_cache_size = (ecx>>24) + (edx>>24); 124 c->x86_cache_size = (ecx>>24) + (edx>>24);
109 /* On K8 L1 TLB is inclusive, so don't count it */ 125 /* On K8 L1 TLB is inclusive, so don't count it */
110 c->x86_tlbsize = 0; 126 c->x86_tlbsize = 0;
111 } 127 }
112 128
113 if (n >= 0x80000006) { 129 if (n < 0x80000006) /* Some chips just has a large L1. */
114 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 130 return;
115 ecx = cpuid_ecx(0x80000006);
116 c->x86_cache_size = ecx >> 16;
117 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
118 131
119 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 132 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
120 c->x86_cache_size, ecx & 0xFF); 133 l2size = ecx >> 16;
121 } 134 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
135
136 c->x86_cache_size = l2size;
137
138 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
139 l2size, ecx & 0xFF);
122} 140}
123 141
124void __cpuinit detect_ht(struct cpuinfo_x86 *c) 142void __cpuinit detect_ht(struct cpuinfo_x86 *c)
@@ -127,14 +145,16 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
127 u32 eax, ebx, ecx, edx; 145 u32 eax, ebx, ecx, edx;
128 int index_msb, core_bits; 146 int index_msb, core_bits;
129 147
130 cpuid(1, &eax, &ebx, &ecx, &edx);
131
132
133 if (!cpu_has(c, X86_FEATURE_HT)) 148 if (!cpu_has(c, X86_FEATURE_HT))
134 return; 149 return;
135 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 150 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
136 goto out; 151 goto out;
137 152
153 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
154 return;
155
156 cpuid(1, &eax, &ebx, &ecx, &edx);
157
138 smp_num_siblings = (ebx & 0xff0000) >> 16; 158 smp_num_siblings = (ebx & 0xff0000) >> 16;
139 159
140 if (smp_num_siblings == 1) { 160 if (smp_num_siblings == 1) {
@@ -142,8 +162,8 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
142 } else if (smp_num_siblings > 1) { 162 } else if (smp_num_siblings > 1) {
143 163
144 if (smp_num_siblings > NR_CPUS) { 164 if (smp_num_siblings > NR_CPUS) {
145 printk(KERN_WARNING "CPU: Unsupported number of " 165 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
146 "siblings %d", smp_num_siblings); 166 smp_num_siblings);
147 smp_num_siblings = 1; 167 smp_num_siblings = 1;
148 return; 168 return;
149 } 169 }
@@ -160,6 +180,7 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
160 c->cpu_core_id = phys_pkg_id(index_msb) & 180 c->cpu_core_id = phys_pkg_id(index_msb) &
161 ((1 << core_bits) - 1); 181 ((1 << core_bits) - 1);
162 } 182 }
183
163out: 184out:
164 if ((c->x86_max_cores * smp_num_siblings) > 1) { 185 if ((c->x86_max_cores * smp_num_siblings) > 1) {
165 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 186 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
@@ -167,7 +188,6 @@ out:
167 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 188 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
168 c->cpu_core_id); 189 c->cpu_core_id);
169 } 190 }
170
171#endif 191#endif
172} 192}
173 193
@@ -178,111 +198,70 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
178 static int printed; 198 static int printed;
179 199
180 for (i = 0; i < X86_VENDOR_NUM; i++) { 200 for (i = 0; i < X86_VENDOR_NUM; i++) {
181 if (cpu_devs[i]) { 201 if (!cpu_devs[i])
182 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 202 break;
183 (cpu_devs[i]->c_ident[1] && 203
184 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 204 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
185 c->x86_vendor = i; 205 (cpu_devs[i]->c_ident[1] &&
186 this_cpu = cpu_devs[i]; 206 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
187 return; 207 this_cpu = cpu_devs[i];
188 } 208 c->x86_vendor = this_cpu->c_x86_vendor;
209 return;
189 } 210 }
190 } 211 }
212
191 if (!printed) { 213 if (!printed) {
192 printed++; 214 printed++;
193 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); 215 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
194 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 216 printk(KERN_ERR "CPU: Your system may be unstable.\n");
195 } 217 }
196 c->x86_vendor = X86_VENDOR_UNKNOWN;
197}
198
199static void __init early_cpu_support_print(void)
200{
201 int i,j;
202 struct cpu_dev *cpu_devx;
203
204 printk("KERNEL supported cpus:\n");
205 for (i = 0; i < X86_VENDOR_NUM; i++) {
206 cpu_devx = cpu_devs[i];
207 if (!cpu_devx)
208 continue;
209 for (j = 0; j < 2; j++) {
210 if (!cpu_devx->c_ident[j])
211 continue;
212 printk(" %s %s\n", cpu_devx->c_vendor,
213 cpu_devx->c_ident[j]);
214 }
215 }
216}
217
218static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
219
220void __init early_cpu_init(void)
221{
222 struct cpu_vendor_dev *cvdev;
223 218
224 for (cvdev = __x86cpuvendor_start ; 219 c->x86_vendor = X86_VENDOR_UNKNOWN;
225 cvdev < __x86cpuvendor_end ; 220 this_cpu = &default_cpu;
226 cvdev++)
227 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
228 early_cpu_support_print();
229 early_identify_cpu(&boot_cpu_data);
230} 221}
231 222
232/* Do some early cpuid on the boot CPU to get some parameter that are 223void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
233 needed before check_bugs. Everything advanced is in identify_cpu
234 below. */
235static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
236{ 224{
237 u32 tfms, xlvl;
238
239 c->loops_per_jiffy = loops_per_jiffy;
240 c->x86_cache_size = -1;
241 c->x86_vendor = X86_VENDOR_UNKNOWN;
242 c->x86_model = c->x86_mask = 0; /* So far unknown... */
243 c->x86_vendor_id[0] = '\0'; /* Unset */
244 c->x86_model_id[0] = '\0'; /* Unset */
245 c->x86_clflush_size = 64;
246 c->x86_cache_alignment = c->x86_clflush_size;
247 c->x86_max_cores = 1;
248 c->x86_coreid_bits = 0;
249 c->extended_cpuid_level = 0;
250 memset(&c->x86_capability, 0, sizeof c->x86_capability);
251
252 /* Get vendor name */ 225 /* Get vendor name */
253 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 226 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
254 (unsigned int *)&c->x86_vendor_id[0], 227 (unsigned int *)&c->x86_vendor_id[0],
255 (unsigned int *)&c->x86_vendor_id[8], 228 (unsigned int *)&c->x86_vendor_id[8],
256 (unsigned int *)&c->x86_vendor_id[4]); 229 (unsigned int *)&c->x86_vendor_id[4]);
257 230
258 get_cpu_vendor(c); 231 c->x86 = 4;
259
260 /* Initialize the standard set of capabilities */
261 /* Note that the vendor-specific code below might override */
262
263 /* Intel-defined flags: level 0x00000001 */ 232 /* Intel-defined flags: level 0x00000001 */
264 if (c->cpuid_level >= 0x00000001) { 233 if (c->cpuid_level >= 0x00000001) {
265 __u32 misc; 234 u32 junk, tfms, cap0, misc;
266 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], 235 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
267 &c->x86_capability[0]);
268 c->x86 = (tfms >> 8) & 0xf; 236 c->x86 = (tfms >> 8) & 0xf;
269 c->x86_model = (tfms >> 4) & 0xf; 237 c->x86_model = (tfms >> 4) & 0xf;
270 c->x86_mask = tfms & 0xf; 238 c->x86_mask = tfms & 0xf;
271 if (c->x86 == 0xf) 239 if (c->x86 == 0xf)
272 c->x86 += (tfms >> 20) & 0xff; 240 c->x86 += (tfms >> 20) & 0xff;
273 if (c->x86 >= 0x6) 241 if (c->x86 >= 0x6)
274 c->x86_model += ((tfms >> 16) & 0xF) << 4; 242 c->x86_model += ((tfms >> 16) & 0xf) << 4;
275 if (test_cpu_cap(c, X86_FEATURE_CLFLSH)) 243 if (cap0 & (1<<19)) {
276 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 244 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
277 } else { 245 c->x86_cache_alignment = c->x86_clflush_size;
278 /* Have CPUID level 0 only - unheard of */ 246 }
279 c->x86 = 4; 247 }
248}
249
250
251static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
252{
253 u32 tfms, xlvl;
254 u32 ebx;
255
256 /* Intel-defined flags: level 0x00000001 */
257 if (c->cpuid_level >= 0x00000001) {
258 u32 capability, excap;
259
260 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
261 c->x86_capability[0] = capability;
262 c->x86_capability[4] = excap;
280 } 263 }
281 264
282 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
283#ifdef CONFIG_SMP
284 c->phys_proc_id = c->initial_apicid;
285#endif
286 /* AMD-defined flags: level 0x80000001 */ 265 /* AMD-defined flags: level 0x80000001 */
287 xlvl = cpuid_eax(0x80000000); 266 xlvl = cpuid_eax(0x80000000);
288 c->extended_cpuid_level = xlvl; 267 c->extended_cpuid_level = xlvl;
@@ -291,8 +270,6 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
291 c->x86_capability[1] = cpuid_edx(0x80000001); 270 c->x86_capability[1] = cpuid_edx(0x80000001);
292 c->x86_capability[6] = cpuid_ecx(0x80000001); 271 c->x86_capability[6] = cpuid_ecx(0x80000001);
293 } 272 }
294 if (xlvl >= 0x80000004)
295 get_model_name(c); /* Default name */
296 } 273 }
297 274
298 /* Transmeta-defined flags: level 0x80860001 */ 275 /* Transmeta-defined flags: level 0x80860001 */
@@ -312,14 +289,114 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
312 c->x86_virt_bits = (eax >> 8) & 0xff; 289 c->x86_virt_bits = (eax >> 8) & 0xff;
313 c->x86_phys_bits = eax & 0xff; 290 c->x86_phys_bits = eax & 0xff;
314 } 291 }
292}
293
294/* Do some early cpuid on the boot CPU to get some parameter that are
295 needed before check_bugs. Everything advanced is in identify_cpu
296 below. */
297static void __init early_identify_cpu(struct cpuinfo_x86 *c)
298{
299
300 c->x86_clflush_size = 64;
301 c->x86_cache_alignment = c->x86_clflush_size;
302
303 memset(&c->x86_capability, 0, sizeof c->x86_capability);
304
305 c->extended_cpuid_level = 0;
315 306
316 if (c->x86_vendor != X86_VENDOR_UNKNOWN && 307 cpu_detect(c);
317 cpu_devs[c->x86_vendor]->c_early_init) 308
318 cpu_devs[c->x86_vendor]->c_early_init(c); 309 get_cpu_vendor(c);
310
311 get_cpu_cap(c);
312
313 if (this_cpu->c_early_init)
314 this_cpu->c_early_init(c);
319 315
320 validate_pat_support(c); 316 validate_pat_support(c);
321} 317}
322 318
319void __init early_cpu_init(void)
320{
321 struct cpu_dev **cdev;
322 int count = 0;
323
324 printk("KERNEL supported cpus:\n");
325 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
326 struct cpu_dev *cpudev = *cdev;
327 unsigned int j;
328
329 if (count >= X86_VENDOR_NUM)
330 break;
331 cpu_devs[count] = cpudev;
332 count++;
333
334 for (j = 0; j < 2; j++) {
335 if (!cpudev->c_ident[j])
336 continue;
337 printk(" %s %s\n", cpudev->c_vendor,
338 cpudev->c_ident[j]);
339 }
340 }
341
342 early_identify_cpu(&boot_cpu_data);
343}
344
345/*
346 * The NOPL instruction is supposed to exist on all CPUs with
347 * family >= 6, unfortunately, that's not true in practice because
348 * of early VIA chips and (more importantly) broken virtualizers that
349 * are not easy to detect. Hence, probe for it based on first
350 * principles.
351 *
352 * Note: no 64-bit chip is known to lack these, but put the code here
353 * for consistency with 32 bits, and to make it utterly trivial to
354 * diagnose the problem should it ever surface.
355 */
356static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
357{
358 const u32 nopl_signature = 0x888c53b1; /* Random number */
359 u32 has_nopl = nopl_signature;
360
361 clear_cpu_cap(c, X86_FEATURE_NOPL);
362 if (c->x86 >= 6) {
363 asm volatile("\n"
364 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
365 "2:\n"
366 " .section .fixup,\"ax\"\n"
367 "3: xor %0,%0\n"
368 " jmp 2b\n"
369 " .previous\n"
370 _ASM_EXTABLE(1b,3b)
371 : "+a" (has_nopl));
372
373 if (has_nopl == nopl_signature)
374 set_cpu_cap(c, X86_FEATURE_NOPL);
375 }
376}
377
378static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
379{
380 c->extended_cpuid_level = 0;
381
382 cpu_detect(c);
383
384 get_cpu_vendor(c);
385
386 get_cpu_cap(c);
387
388 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
389#ifdef CONFIG_SMP
390 c->phys_proc_id = c->initial_apicid;
391#endif
392
393 if (c->extended_cpuid_level >= 0x80000004)
394 get_model_name(c); /* Default name */
395
396 init_scattered_cpuid_features(c);
397 detect_nopl(c);
398}
399
323/* 400/*
324 * This does the hard work of actually picking apart the CPU stuff... 401 * This does the hard work of actually picking apart the CPU stuff...
325 */ 402 */
@@ -327,9 +404,19 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
327{ 404{
328 int i; 405 int i;
329 406
330 early_identify_cpu(c); 407 c->loops_per_jiffy = loops_per_jiffy;
408 c->x86_cache_size = -1;
409 c->x86_vendor = X86_VENDOR_UNKNOWN;
410 c->x86_model = c->x86_mask = 0; /* So far unknown... */
411 c->x86_vendor_id[0] = '\0'; /* Unset */
412 c->x86_model_id[0] = '\0'; /* Unset */
413 c->x86_max_cores = 1;
414 c->x86_coreid_bits = 0;
415 c->x86_clflush_size = 64;
416 c->x86_cache_alignment = c->x86_clflush_size;
417 memset(&c->x86_capability, 0, sizeof c->x86_capability);
331 418
332 init_scattered_cpuid_features(c); 419 generic_identify(c);
333 420
334 c->apicid = phys_pkg_id(0); 421 c->apicid = phys_pkg_id(0);
335 422
@@ -375,7 +462,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
375 462
376} 463}
377 464
378void __cpuinit identify_boot_cpu(void) 465void __init identify_boot_cpu(void)
379{ 466{
380 identify_cpu(&boot_cpu_data); 467 identify_cpu(&boot_cpu_data);
381} 468}
@@ -387,6 +474,49 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
387 mtrr_ap_init(); 474 mtrr_ap_init();
388} 475}
389 476
477struct msr_range {
478 unsigned min;
479 unsigned max;
480};
481
482static struct msr_range msr_range_array[] __cpuinitdata = {
483 { 0x00000000, 0x00000418},
484 { 0xc0000000, 0xc000040b},
485 { 0xc0010000, 0xc0010142},
486 { 0xc0011000, 0xc001103b},
487};
488
489static void __cpuinit print_cpu_msr(void)
490{
491 unsigned index;
492 u64 val;
493 int i;
494 unsigned index_min, index_max;
495
496 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
497 index_min = msr_range_array[i].min;
498 index_max = msr_range_array[i].max;
499 for (index = index_min; index < index_max; index++) {
500 if (rdmsrl_amd_safe(index, &val))
501 continue;
502 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
503 }
504 }
505}
506
507static int show_msr __cpuinitdata;
508static __init int setup_show_msr(char *arg)
509{
510 int num;
511
512 get_option(&arg, &num);
513
514 if (num > 0)
515 show_msr = num;
516 return 1;
517}
518__setup("show_msr=", setup_show_msr);
519
390static __init int setup_noclflush(char *arg) 520static __init int setup_noclflush(char *arg)
391{ 521{
392 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 522 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
@@ -403,6 +533,14 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
403 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 533 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
404 else 534 else
405 printk(KERN_CONT "\n"); 535 printk(KERN_CONT "\n");
536
537#ifdef CONFIG_SMP
538 if (c->cpu_index < show_msr)
539 print_cpu_msr();
540#else
541 if (show_msr)
542 print_cpu_msr();
543#endif
406} 544}
407 545
408static __init int setup_disablecpuid(char *arg) 546static __init int setup_disablecpuid(char *arg)
@@ -493,17 +631,20 @@ void pda_init(int cpu)
493 /* others are initialized in smpboot.c */ 631 /* others are initialized in smpboot.c */
494 pda->pcurrent = &init_task; 632 pda->pcurrent = &init_task;
495 pda->irqstackptr = boot_cpu_stack; 633 pda->irqstackptr = boot_cpu_stack;
634 pda->irqstackptr += IRQSTACKSIZE - 64;
496 } else { 635 } else {
497 pda->irqstackptr = (char *) 636 if (!pda->irqstackptr) {
498 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); 637 pda->irqstackptr = (char *)
499 if (!pda->irqstackptr) 638 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
500 panic("cannot allocate irqstack for cpu %d", cpu); 639 if (!pda->irqstackptr)
640 panic("cannot allocate irqstack for cpu %d",
641 cpu);
642 pda->irqstackptr += IRQSTACKSIZE - 64;
643 }
501 644
502 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) 645 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
503 pda->nodenumber = cpu_to_node(cpu); 646 pda->nodenumber = cpu_to_node(cpu);
504 } 647 }
505
506 pda->irqstackptr += IRQSTACKSIZE-64;
507} 648}
508 649
509char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + 650char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
@@ -597,23 +738,28 @@ void __cpuinit cpu_init(void)
597 barrier(); 738 barrier();
598 739
599 check_efer(); 740 check_efer();
741 if (cpu != 0 && x2apic)
742 enable_x2apic();
600 743
601 /* 744 /*
602 * set up and load the per-CPU TSS 745 * set up and load the per-CPU TSS
603 */ 746 */
604 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 747 if (!orig_ist->ist[0]) {
605 static const unsigned int order[N_EXCEPTION_STACKS] = { 748 static const unsigned int order[N_EXCEPTION_STACKS] = {
606 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, 749 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
607 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER 750 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
608 }; 751 };
609 if (cpu) { 752 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
610 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); 753 if (cpu) {
611 if (!estacks) 754 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
612 panic("Cannot allocate exception stack %ld %d\n", 755 if (!estacks)
613 v, cpu); 756 panic("Cannot allocate exception "
757 "stack %ld %d\n", v, cpu);
758 }
759 estacks += PAGE_SIZE << order[v];
760 orig_ist->ist[v] = t->x86_tss.ist[v] =
761 (unsigned long)estacks;
614 } 762 }
615 estacks += PAGE_SIZE << order[v];
616 orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
617 } 763 }
618 764
619 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 765 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 4d894e8565fe..3cc9d92afd8f 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -21,21 +21,15 @@ struct cpu_dev {
21 void (*c_init)(struct cpuinfo_x86 * c); 21 void (*c_init)(struct cpuinfo_x86 * c);
22 void (*c_identify)(struct cpuinfo_x86 * c); 22 void (*c_identify)(struct cpuinfo_x86 * c);
23 unsigned int (*c_size_cache)(struct cpuinfo_x86 * c, unsigned int size); 23 unsigned int (*c_size_cache)(struct cpuinfo_x86 * c, unsigned int size);
24 int c_x86_vendor;
24}; 25};
25 26
26extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM]; 27#define cpu_dev_register(cpu_devX) \
28 static struct cpu_dev *__cpu_dev_##cpu_devX __used \
29 __attribute__((__section__(".x86_cpu_dev.init"))) = \
30 &cpu_devX;
27 31
28struct cpu_vendor_dev { 32extern struct cpu_dev *__x86_cpu_dev_start[], *__x86_cpu_dev_end[];
29 int vendor;
30 struct cpu_dev *cpu_dev;
31};
32
33#define cpu_vendor_dev_register(cpu_vendor_id, cpu_dev) \
34 static struct cpu_vendor_dev __cpu_vendor_dev_##cpu_vendor_id __used \
35 __attribute__((__section__(".x86cpuvendor.init"))) = \
36 { cpu_vendor_id, cpu_dev }
37
38extern struct cpu_vendor_dev __x86cpuvendor_start[], __x86cpuvendor_end[];
39 33
40extern int get_model_name(struct cpuinfo_x86 *c); 34extern int get_model_name(struct cpuinfo_x86 *c);
41extern void display_cacheinfo(struct cpuinfo_x86 *c); 35extern void display_cacheinfo(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index e710a21bb6e8..3f8c7283d816 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -15,13 +15,11 @@
15/* 15/*
16 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU 16 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
17 */ 17 */
18static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 18static void __cpuinit __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
19{ 19{
20 unsigned char ccr2, ccr3; 20 unsigned char ccr2, ccr3;
21 unsigned long flags;
22 21
23 /* we test for DEVID by checking whether CCR3 is writable */ 22 /* we test for DEVID by checking whether CCR3 is writable */
24 local_irq_save(flags);
25 ccr3 = getCx86(CX86_CCR3); 23 ccr3 = getCx86(CX86_CCR3);
26 setCx86(CX86_CCR3, ccr3 ^ 0x80); 24 setCx86(CX86_CCR3, ccr3 ^ 0x80);
27 getCx86(0xc0); /* dummy to change bus */ 25 getCx86(0xc0); /* dummy to change bus */
@@ -44,9 +42,16 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
44 *dir0 = getCx86(CX86_DIR0); 42 *dir0 = getCx86(CX86_DIR0);
45 *dir1 = getCx86(CX86_DIR1); 43 *dir1 = getCx86(CX86_DIR1);
46 } 44 }
47 local_irq_restore(flags);
48} 45}
49 46
47static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
48{
49 unsigned long flags;
50
51 local_irq_save(flags);
52 __do_cyrix_devid(dir0, dir1);
53 local_irq_restore(flags);
54}
50/* 55/*
51 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in 56 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
52 * order to identify the Cyrix CPU model after we're out of setup.c 57 * order to identify the Cyrix CPU model after we're out of setup.c
@@ -116,7 +121,7 @@ static void __cpuinit set_cx86_reorder(void)
116 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 121 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
117 122
118 /* Load/Store Serialize to mem access disable (=reorder it) */ 123 /* Load/Store Serialize to mem access disable (=reorder it) */
119 setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80); 124 setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
120 /* set load/store serialize from 1GB to 4GB */ 125 /* set load/store serialize from 1GB to 4GB */
121 ccr3 |= 0xe0; 126 ccr3 |= 0xe0;
122 setCx86(CX86_CCR3, ccr3); 127 setCx86(CX86_CCR3, ccr3);
@@ -127,11 +132,11 @@ static void __cpuinit set_cx86_memwb(void)
127 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n"); 132 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
128 133
129 /* CCR2 bit 2: unlock NW bit */ 134 /* CCR2 bit 2: unlock NW bit */
130 setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04); 135 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
131 /* set 'Not Write-through' */ 136 /* set 'Not Write-through' */
132 write_cr0(read_cr0() | X86_CR0_NW); 137 write_cr0(read_cr0() | X86_CR0_NW);
133 /* CCR2 bit 2: lock NW bit and set WT1 */ 138 /* CCR2 bit 2: lock NW bit and set WT1 */
134 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); 139 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
135} 140}
136 141
137/* 142/*
@@ -145,14 +150,14 @@ static void __cpuinit geode_configure(void)
145 local_irq_save(flags); 150 local_irq_save(flags);
146 151
147 /* Suspend on halt power saving and enable #SUSP pin */ 152 /* Suspend on halt power saving and enable #SUSP pin */
148 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); 153 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);
149 154
150 ccr3 = getCx86(CX86_CCR3); 155 ccr3 = getCx86(CX86_CCR3);
151 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 156 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
152 157
153 158
154 /* FPU fast, DTE cache, Mem bypass */ 159 /* FPU fast, DTE cache, Mem bypass */
155 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); 160 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
156 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 161 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
157 162
158 set_cx86_memwb(); 163 set_cx86_memwb();
@@ -161,6 +166,24 @@ static void __cpuinit geode_configure(void)
161 local_irq_restore(flags); 166 local_irq_restore(flags);
162} 167}
163 168
169static void __cpuinit early_init_cyrix(struct cpuinfo_x86 *c)
170{
171 unsigned char dir0, dir0_msn, dir1 = 0;
172
173 __do_cyrix_devid(&dir0, &dir1);
174 dir0_msn = dir0 >> 4; /* identifies CPU "family" */
175
176 switch (dir0_msn) {
177 case 3: /* 6x86/6x86L */
178 /* Emulate MTRRs using Cyrix's ARRs. */
179 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
180 break;
181 case 5: /* 6x86MX/M II */
182 /* Emulate MTRRs using Cyrix's ARRs. */
183 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
184 break;
185 }
186}
164 187
165static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) 188static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
166{ 189{
@@ -268,7 +291,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
268 /* GXm supports extended cpuid levels 'ala' AMD */ 291 /* GXm supports extended cpuid levels 'ala' AMD */
269 if (c->cpuid_level == 2) { 292 if (c->cpuid_level == 2) {
270 /* Enable cxMMX extensions (GX1 Datasheet 54) */ 293 /* Enable cxMMX extensions (GX1 Datasheet 54) */
271 setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); 294 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);
272 295
273 /* 296 /*
274 * GXm : 0x30 ... 0x5f GXm datasheet 51 297 * GXm : 0x30 ... 0x5f GXm datasheet 51
@@ -291,7 +314,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
291 if (dir1 > 7) { 314 if (dir1 > 7) {
292 dir0_msn++; /* M II */ 315 dir0_msn++; /* M II */
293 /* Enable MMX extensions (App note 108) */ 316 /* Enable MMX extensions (App note 108) */
294 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); 317 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
295 } else { 318 } else {
296 c->coma_bug = 1; /* 6x86MX, it has the bug. */ 319 c->coma_bug = 1; /* 6x86MX, it has the bug. */
297 } 320 }
@@ -406,7 +429,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
406 local_irq_save(flags); 429 local_irq_save(flags);
407 ccr3 = getCx86(CX86_CCR3); 430 ccr3 = getCx86(CX86_CCR3);
408 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 431 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
409 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); /* enable cpuid */ 432 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80); /* enable cpuid */
410 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 433 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
411 local_irq_restore(flags); 434 local_irq_restore(flags);
412 } 435 }
@@ -416,16 +439,19 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
416static struct cpu_dev cyrix_cpu_dev __cpuinitdata = { 439static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
417 .c_vendor = "Cyrix", 440 .c_vendor = "Cyrix",
418 .c_ident = { "CyrixInstead" }, 441 .c_ident = { "CyrixInstead" },
442 .c_early_init = early_init_cyrix,
419 .c_init = init_cyrix, 443 .c_init = init_cyrix,
420 .c_identify = cyrix_identify, 444 .c_identify = cyrix_identify,
445 .c_x86_vendor = X86_VENDOR_CYRIX,
421}; 446};
422 447
423cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev); 448cpu_dev_register(cyrix_cpu_dev);
424 449
425static struct cpu_dev nsc_cpu_dev __cpuinitdata = { 450static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
426 .c_vendor = "NSC", 451 .c_vendor = "NSC",
427 .c_ident = { "Geode by NSC" }, 452 .c_ident = { "Geode by NSC" },
428 .c_init = init_nsc, 453 .c_init = init_nsc,
454 .c_x86_vendor = X86_VENDOR_NSC,
429}; 455};
430 456
431cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev); 457cpu_dev_register(nsc_cpu_dev);
diff --git a/arch/x86/kernel/cpu/feature_names.c b/arch/x86/kernel/cpu/feature_names.c
deleted file mode 100644
index e43ad4ad4cba..000000000000
--- a/arch/x86/kernel/cpu/feature_names.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * Strings for the various x86 capability flags.
3 *
4 * This file must not contain any executable code.
5 */
6
7#include <asm/cpufeature.h>
8
9/*
10 * These flag bits must match the definitions in <asm/cpufeature.h>.
11 * NULL means this bit is undefined or reserved; either way it doesn't
12 * have meaning as far as Linux is concerned. Note that it's important
13 * to realize there is a difference between this table and CPUID -- if
14 * applications want to get the raw CPUID data, they should access
15 * /dev/cpu/<cpu_nr>/cpuid instead.
16 */
17const char * const x86_cap_flags[NCAPINTS*32] = {
18 /* Intel-defined */
19 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
20 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
21 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
22 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
23
24 /* AMD-defined */
25 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
26 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
27 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
28 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
29 "3dnowext", "3dnow",
30
31 /* Transmeta-defined */
32 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
33 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
34 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
35 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
36
37 /* Other (Linux-defined) */
38 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
39 NULL, NULL, NULL, NULL,
40 "constant_tsc", "up", NULL, "arch_perfmon",
41 "pebs", "bts", NULL, NULL,
42 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
43 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
44
45 /* Intel-defined (#2) */
46 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
47 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
48 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
49 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
50
51 /* VIA/Cyrix/Centaur-defined */
52 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
53 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
54 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
55 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
56
57 /* AMD-defined (#2) */
58 "lahf_lm", "cmp_legacy", "svm", "extapic",
59 "cr8_legacy", "abm", "sse4a", "misalignsse",
60 "3dnowprefetch", "osvw", "ibs", "sse5",
61 "skinit", "wdt", NULL, NULL,
62 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
63 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
64
65 /* Auxiliary (Linux-defined) */
66 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
67 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
68 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
69 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
70};
71
72const char *const x86_power_flags[32] = {
73 "ts", /* temperature sensor */
74 "fid", /* frequency id control */
75 "vid", /* voltage id control */
76 "ttp", /* thermal trip */
77 "tm",
78 "stc",
79 "100mhzsteps",
80 "hwpstate",
81 "", /* tsc invariant mapped to constant_tsc */
82 /* nothing */
83};
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b75f2569b8f8..959417b8cd64 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -23,13 +23,6 @@
23#include <mach_apic.h> 23#include <mach_apic.h>
24#endif 24#endif
25 25
26#ifdef CONFIG_X86_INTEL_USERCOPY
27/*
28 * Alignment at which movsl is preferred for bulk memory copies.
29 */
30struct movsl_mask movsl_mask __read_mostly;
31#endif
32
33static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 26static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
34{ 27{
35 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 28 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
@@ -183,9 +176,16 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
183 if (p) 176 if (p)
184 strcpy(c->x86_model_id, p); 177 strcpy(c->x86_model_id, p);
185 178
186 c->x86_max_cores = num_cpu_cores(c); 179 detect_extended_topology(c);
187 180
188 detect_ht(c); 181 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
182 /*
183 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
184 * detection.
185 */
186 c->x86_max_cores = num_cpu_cores(c);
187 detect_ht(c);
188 }
189 189
190 /* Work around errata */ 190 /* Work around errata */
191 Intel_errata_workarounds(c); 191 Intel_errata_workarounds(c);
@@ -310,73 +310,10 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
310 .c_early_init = early_init_intel, 310 .c_early_init = early_init_intel,
311 .c_init = init_intel, 311 .c_init = init_intel,
312 .c_size_cache = intel_size_cache, 312 .c_size_cache = intel_size_cache,
313 .c_x86_vendor = X86_VENDOR_INTEL,
313}; 314};
314 315
315cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev); 316cpu_dev_register(intel_cpu_dev);
316
317#ifndef CONFIG_X86_CMPXCHG
318unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
319{
320 u8 prev;
321 unsigned long flags;
322
323 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
324 local_irq_save(flags);
325 prev = *(u8 *)ptr;
326 if (prev == old)
327 *(u8 *)ptr = new;
328 local_irq_restore(flags);
329 return prev;
330}
331EXPORT_SYMBOL(cmpxchg_386_u8);
332
333unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
334{
335 u16 prev;
336 unsigned long flags;
337
338 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
339 local_irq_save(flags);
340 prev = *(u16 *)ptr;
341 if (prev == old)
342 *(u16 *)ptr = new;
343 local_irq_restore(flags);
344 return prev;
345}
346EXPORT_SYMBOL(cmpxchg_386_u16);
347
348unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
349{
350 u32 prev;
351 unsigned long flags;
352
353 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
354 local_irq_save(flags);
355 prev = *(u32 *)ptr;
356 if (prev == old)
357 *(u32 *)ptr = new;
358 local_irq_restore(flags);
359 return prev;
360}
361EXPORT_SYMBOL(cmpxchg_386_u32);
362#endif
363
364#ifndef CONFIG_X86_CMPXCHG64
365unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
366{
367 u64 prev;
368 unsigned long flags;
369
370 /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
371 local_irq_save(flags);
372 prev = *(u64 *)ptr;
373 if (prev == old)
374 *(u64 *)ptr = new;
375 local_irq_restore(flags);
376 return prev;
377}
378EXPORT_SYMBOL(cmpxchg_486_u64);
379#endif
380 317
381/* arch_initcall(intel_cpu_init); */ 318/* arch_initcall(intel_cpu_init); */
382 319
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c
index 1019c58d39f0..0c0a58dfe099 100644
--- a/arch/x86/kernel/cpu/intel_64.c
+++ b/arch/x86/kernel/cpu/intel_64.c
@@ -80,7 +80,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
80 if (c->x86 == 6) 80 if (c->x86 == 6)
81 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 81 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
82 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 82 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
83 c->x86_max_cores = intel_num_cpu_cores(c); 83
84 detect_extended_topology(c);
85 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY))
86 c->x86_max_cores = intel_num_cpu_cores(c);
84 87
85 srat_detect_node(); 88 srat_detect_node();
86} 89}
@@ -90,6 +93,7 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
90 .c_ident = { "GenuineIntel" }, 93 .c_ident = { "GenuineIntel" },
91 .c_early_init = early_init_intel, 94 .c_early_init = early_init_intel,
92 .c_init = init_intel, 95 .c_init = init_intel,
96 .c_x86_vendor = X86_VENDOR_INTEL,
93}; 97};
94cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
95 98
99cpu_dev_register(intel_cpu_dev);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6b0a10b002f1..3f46afbb1cf1 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Routines to indentify caches on Intel CPU. 2 * Routines to indentify caches on Intel CPU.
3 * 3 *
4 * Changes: 4 * Changes:
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4) 5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure. 6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD. 7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
8 */ 8 */
@@ -13,6 +13,7 @@
13#include <linux/compiler.h> 13#include <linux/compiler.h>
14#include <linux/cpu.h> 14#include <linux/cpu.h>
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/pci.h>
16 17
17#include <asm/processor.h> 18#include <asm/processor.h>
18#include <asm/smp.h> 19#include <asm/smp.h>
@@ -130,9 +131,18 @@ struct _cpuid4_info {
130 union _cpuid4_leaf_ebx ebx; 131 union _cpuid4_leaf_ebx ebx;
131 union _cpuid4_leaf_ecx ecx; 132 union _cpuid4_leaf_ecx ecx;
132 unsigned long size; 133 unsigned long size;
134 unsigned long can_disable;
133 cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */ 135 cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */
134}; 136};
135 137
138#ifdef CONFIG_PCI
139static struct pci_device_id k8_nb_id[] = {
140 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
141 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
142 {}
143};
144#endif
145
136unsigned short num_cache_leaves; 146unsigned short num_cache_leaves;
137 147
138/* AMD doesn't have CPUID4. Emulate it here to report the same 148/* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -182,9 +192,10 @@ static unsigned short assocs[] __cpuinitdata = {
182static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 }; 192static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 };
183static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 }; 193static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 };
184 194
185static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, 195static void __cpuinit
186 union _cpuid4_leaf_ebx *ebx, 196amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
187 union _cpuid4_leaf_ecx *ecx) 197 union _cpuid4_leaf_ebx *ebx,
198 union _cpuid4_leaf_ecx *ecx)
188{ 199{
189 unsigned dummy; 200 unsigned dummy;
190 unsigned line_size, lines_per_tag, assoc, size_in_kb; 201 unsigned line_size, lines_per_tag, assoc, size_in_kb;
@@ -251,27 +262,40 @@ static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
251 (ebx->split.ways_of_associativity + 1) - 1; 262 (ebx->split.ways_of_associativity + 1) - 1;
252} 263}
253 264
254static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf) 265static void __cpuinit
266amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
267{
268 if (index < 3)
269 return;
270 this_leaf->can_disable = 1;
271}
272
273static int
274__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
255{ 275{
256 union _cpuid4_leaf_eax eax; 276 union _cpuid4_leaf_eax eax;
257 union _cpuid4_leaf_ebx ebx; 277 union _cpuid4_leaf_ebx ebx;
258 union _cpuid4_leaf_ecx ecx; 278 union _cpuid4_leaf_ecx ecx;
259 unsigned edx; 279 unsigned edx;
260 280
261 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 281 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
262 amd_cpuid4(index, &eax, &ebx, &ecx); 282 amd_cpuid4(index, &eax, &ebx, &ecx);
263 else 283 if (boot_cpu_data.x86 >= 0x10)
264 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); 284 amd_check_l3_disable(index, this_leaf);
285 } else {
286 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
287 }
288
265 if (eax.split.type == CACHE_TYPE_NULL) 289 if (eax.split.type == CACHE_TYPE_NULL)
266 return -EIO; /* better error ? */ 290 return -EIO; /* better error ? */
267 291
268 this_leaf->eax = eax; 292 this_leaf->eax = eax;
269 this_leaf->ebx = ebx; 293 this_leaf->ebx = ebx;
270 this_leaf->ecx = ecx; 294 this_leaf->ecx = ecx;
271 this_leaf->size = (ecx.split.number_of_sets + 1) * 295 this_leaf->size = (ecx.split.number_of_sets + 1) *
272 (ebx.split.coherency_line_size + 1) * 296 (ebx.split.coherency_line_size + 1) *
273 (ebx.split.physical_line_partition + 1) * 297 (ebx.split.physical_line_partition + 1) *
274 (ebx.split.ways_of_associativity + 1); 298 (ebx.split.ways_of_associativity + 1);
275 return 0; 299 return 0;
276} 300}
277 301
@@ -453,7 +477,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
453 477
454/* pointer to _cpuid4_info array (for each cache leaf) */ 478/* pointer to _cpuid4_info array (for each cache leaf) */
455static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info); 479static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
456#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y])) 480#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
457 481
458#ifdef CONFIG_SMP 482#ifdef CONFIG_SMP
459static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) 483static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@@ -490,7 +514,7 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
490 514
491 this_leaf = CPUID4_INFO_IDX(cpu, index); 515 this_leaf = CPUID4_INFO_IDX(cpu, index);
492 for_each_cpu_mask_nr(sibling, this_leaf->shared_cpu_map) { 516 for_each_cpu_mask_nr(sibling, this_leaf->shared_cpu_map) {
493 sibling_leaf = CPUID4_INFO_IDX(sibling, index); 517 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
494 cpu_clear(cpu, sibling_leaf->shared_cpu_map); 518 cpu_clear(cpu, sibling_leaf->shared_cpu_map);
495 } 519 }
496} 520}
@@ -572,7 +596,7 @@ struct _index_kobject {
572 596
573/* pointer to array of kobjects for cpuX/cache/indexY */ 597/* pointer to array of kobjects for cpuX/cache/indexY */
574static DEFINE_PER_CPU(struct _index_kobject *, index_kobject); 598static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
575#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y])) 599#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
576 600
577#define show_one_plus(file_name, object, val) \ 601#define show_one_plus(file_name, object, val) \
578static ssize_t show_##file_name \ 602static ssize_t show_##file_name \
@@ -637,6 +661,99 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
637 } 661 }
638} 662}
639 663
664#define to_object(k) container_of(k, struct _index_kobject, kobj)
665#define to_attr(a) container_of(a, struct _cache_attr, attr)
666
667#ifdef CONFIG_PCI
668static struct pci_dev *get_k8_northbridge(int node)
669{
670 struct pci_dev *dev = NULL;
671 int i;
672
673 for (i = 0; i <= node; i++) {
674 do {
675 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
676 if (!dev)
677 break;
678 } while (!pci_match_id(&k8_nb_id[0], dev));
679 if (!dev)
680 break;
681 }
682 return dev;
683}
684#else
685static struct pci_dev *get_k8_northbridge(int node)
686{
687 return NULL;
688}
689#endif
690
691static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
692{
693 int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
694 struct pci_dev *dev = NULL;
695 ssize_t ret = 0;
696 int i;
697
698 if (!this_leaf->can_disable)
699 return sprintf(buf, "Feature not enabled\n");
700
701 dev = get_k8_northbridge(node);
702 if (!dev) {
703 printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
704 return -EINVAL;
705 }
706
707 for (i = 0; i < 2; i++) {
708 unsigned int reg;
709
710 pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
711
712 ret += sprintf(buf, "%sEntry: %d\n", buf, i);
713 ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
714 buf,
715 reg & 0x80000000 ? "Disabled" : "Allowed",
716 reg & 0x40000000 ? "Disabled" : "Allowed");
717 ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
718 buf, (reg & 0x30000) >> 16, reg & 0xfff);
719 }
720 return ret;
721}
722
723static ssize_t
724store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
725 size_t count)
726{
727 int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
728 struct pci_dev *dev = NULL;
729 unsigned int ret, index, val;
730
731 if (!this_leaf->can_disable)
732 return 0;
733
734 if (strlen(buf) > 15)
735 return -EINVAL;
736
737 ret = sscanf(buf, "%x %x", &index, &val);
738 if (ret != 2)
739 return -EINVAL;
740 if (index > 1)
741 return -EINVAL;
742
743 val |= 0xc0000000;
744 dev = get_k8_northbridge(node);
745 if (!dev) {
746 printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
747 return -EINVAL;
748 }
749
750 pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
751 wbinvd();
752 pci_write_config_dword(dev, 0x1BC + index * 4, val);
753
754 return 1;
755}
756
640struct _cache_attr { 757struct _cache_attr {
641 struct attribute attr; 758 struct attribute attr;
642 ssize_t (*show)(struct _cpuid4_info *, char *); 759 ssize_t (*show)(struct _cpuid4_info *, char *);
@@ -657,6 +774,8 @@ define_one_ro(size);
657define_one_ro(shared_cpu_map); 774define_one_ro(shared_cpu_map);
658define_one_ro(shared_cpu_list); 775define_one_ro(shared_cpu_list);
659 776
777static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
778
660static struct attribute * default_attrs[] = { 779static struct attribute * default_attrs[] = {
661 &type.attr, 780 &type.attr,
662 &level.attr, 781 &level.attr,
@@ -667,12 +786,10 @@ static struct attribute * default_attrs[] = {
667 &size.attr, 786 &size.attr,
668 &shared_cpu_map.attr, 787 &shared_cpu_map.attr,
669 &shared_cpu_list.attr, 788 &shared_cpu_list.attr,
789 &cache_disable.attr,
670 NULL 790 NULL
671}; 791};
672 792
673#define to_object(k) container_of(k, struct _index_kobject, kobj)
674#define to_attr(a) container_of(a, struct _cache_attr, attr)
675
676static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf) 793static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
677{ 794{
678 struct _cache_attr *fattr = to_attr(attr); 795 struct _cache_attr *fattr = to_attr(attr);
@@ -682,14 +799,22 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
682 ret = fattr->show ? 799 ret = fattr->show ?
683 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), 800 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
684 buf) : 801 buf) :
685 0; 802 0;
686 return ret; 803 return ret;
687} 804}
688 805
689static ssize_t store(struct kobject * kobj, struct attribute * attr, 806static ssize_t store(struct kobject * kobj, struct attribute * attr,
690 const char * buf, size_t count) 807 const char * buf, size_t count)
691{ 808{
692 return 0; 809 struct _cache_attr *fattr = to_attr(attr);
810 struct _index_kobject *this_leaf = to_object(kobj);
811 ssize_t ret;
812
813 ret = fattr->store ?
814 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
815 buf, count) :
816 0;
817 return ret;
693} 818}
694 819
695static struct sysfs_ops sysfs_ops = { 820static struct sysfs_ops sysfs_ops = {
diff --git a/arch/x86/kernel/cpu/mkcapflags.pl b/arch/x86/kernel/cpu/mkcapflags.pl
new file mode 100644
index 000000000000..dfea390e1608
--- /dev/null
+++ b/arch/x86/kernel/cpu/mkcapflags.pl
@@ -0,0 +1,32 @@
1#!/usr/bin/perl
2#
3# Generate the x86_cap_flags[] array from include/asm-x86/cpufeature.h
4#
5
6($in, $out) = @ARGV;
7
8open(IN, "< $in\0") or die "$0: cannot open: $in: $!\n";
9open(OUT, "> $out\0") or die "$0: cannot create: $out: $!\n";
10
11print OUT "#include <asm/cpufeature.h>\n\n";
12print OUT "const char * const x86_cap_flags[NCAPINTS*32] = {\n";
13
14while (defined($line = <IN>)) {
15 if ($line =~ /^\s*\#\s*define\s+(X86_FEATURE_(\S+))\s+(.*)$/) {
16 $macro = $1;
17 $feature = $2;
18 $tail = $3;
19 if ($tail =~ /\/\*\s*\"([^"]*)\".*\*\//) {
20 $feature = $1;
21 }
22
23 if ($feature ne '') {
24 printf OUT "\t%-32s = \"%s\",\n",
25 "[$macro]", "\L$feature";
26 }
27 }
28}
29print OUT "};\n";
30
31close(IN);
32close(OUT);
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index b117d7f8a564..58ac5d3d4361 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -729,7 +729,7 @@ struct var_mtrr_range_state {
729 mtrr_type type; 729 mtrr_type type;
730}; 730};
731 731
732struct var_mtrr_range_state __initdata range_state[RANGE_NUM]; 732static struct var_mtrr_range_state __initdata range_state[RANGE_NUM];
733static int __initdata debug_print; 733static int __initdata debug_print;
734 734
735static int __init 735static int __init
diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerflags.c
new file mode 100644
index 000000000000..5abbea297e0c
--- /dev/null
+++ b/arch/x86/kernel/cpu/powerflags.c
@@ -0,0 +1,20 @@
1/*
2 * Strings for the various x86 power flags
3 *
4 * This file must not contain any executable code.
5 */
6
7#include <asm/cpufeature.h>
8
9const char *const x86_power_flags[32] = {
10 "ts", /* temperature sensor */
11 "fid", /* frequency id control */
12 "vid", /* voltage id control */
13 "ttp", /* thermal trip */
14 "tm",
15 "stc",
16 "100mhzsteps",
17 "hwpstate",
18 "", /* tsc invariant mapped to constant_tsc */
19 /* nothing */
20};
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index b911a2c61b8f..7c46e6ecedca 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -102,6 +102,7 @@ static struct cpu_dev transmeta_cpu_dev __cpuinitdata = {
102 .c_ident = { "GenuineTMx86", "TransmetaCPU" }, 102 .c_ident = { "GenuineTMx86", "TransmetaCPU" },
103 .c_init = init_transmeta, 103 .c_init = init_transmeta,
104 .c_identify = transmeta_identify, 104 .c_identify = transmeta_identify,
105 .c_x86_vendor = X86_VENDOR_TRANSMETA,
105}; 106};
106 107
107cpu_vendor_dev_register(X86_VENDOR_TRANSMETA, &transmeta_cpu_dev); 108cpu_dev_register(transmeta_cpu_dev);
diff --git a/arch/x86/kernel/cpu/umc.c b/arch/x86/kernel/cpu/umc.c
index b1fc90989d75..e777f79e0960 100644
--- a/arch/x86/kernel/cpu/umc.c
+++ b/arch/x86/kernel/cpu/umc.c
@@ -19,7 +19,8 @@ static struct cpu_dev umc_cpu_dev __cpuinitdata = {
19 } 19 }
20 }, 20 },
21 }, 21 },
22 .c_x86_vendor = X86_VENDOR_UMC,
22}; 23};
23 24
24cpu_vendor_dev_register(X86_VENDOR_UMC, &umc_cpu_dev); 25cpu_dev_register(umc_cpu_dev);
25 26
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 00:25:45 -0400