1 files changed, 124 insertions, 53 deletions

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 95962a93f99a..33eae2062cf5 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -148,13 +148,19 @@ union _cpuid4_leaf_ecx {
         u32 full;
 };
 
+struct amd_l3_cache {
+        struct   pci_dev *dev;
+        bool     can_disable;
+        unsigned indices;
+        u8       subcaches[4];
+};
+
 struct _cpuid4_info {
         union _cpuid4_leaf_eax eax;
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
-        bool can_disable;
-        unsigned int l3_indices;
+        struct amd_l3_cache *l3;
         DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
 };
 
@@ -164,8 +170,7 @@ struct _cpuid4_info_regs {
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
-        bool can_disable;
-        unsigned int l3_indices;
+        struct amd_l3_cache *l3;
 };
 
 unsigned short                  num_cache_leaves;
@@ -302,91 +307,163 @@ struct _cache_attr {
 };
 
 #ifdef CONFIG_CPU_SUP_AMD
-static unsigned int __cpuinit amd_calc_l3_indices(void)
+
+/*
+ * L3 cache descriptors
+ */
+static struct amd_l3_cache **__cpuinitdata l3_caches;
+
+static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
 {
-        /*
-         * We're called over smp_call_function_single() and therefore
-         * are on the correct cpu.
-         */
-        int cpu = smp_processor_id();
-        int node = cpu_to_node(cpu);
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
         unsigned int sc0, sc1, sc2, sc3;
         u32 val = 0;
 
-        pci_read_config_dword(dev, 0x1C4, &val);
+        pci_read_config_dword(l3->dev, 0x1C4, &val);
 
         /* calculate subcache sizes */
-        sc0 = !(val & BIT(0));
-        sc1 = !(val & BIT(4));
-        sc2 = !(val & BIT(8))  + !(val & BIT(9));
-        sc3 = !(val & BIT(12)) + !(val & BIT(13));
+        l3->subcaches[0] = sc0 = !(val & BIT(0));
+        l3->subcaches[1] = sc1 = !(val & BIT(4));
+        l3->subcaches[2] = sc2 = !(val & BIT(8))  + !(val & BIT(9));
+        l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
+
+        l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
+}
+
+static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
+{
+        struct amd_l3_cache *l3;
+        struct pci_dev *dev = node_to_k8_nb_misc(node);
 
-        return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
+        l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
+        if (!l3) {
+                printk(KERN_WARNING "Error allocating L3 struct\n");
+                return NULL;
+        }
+
+        l3->dev = dev;
+
+        amd_calc_l3_indices(l3);
+
+        return l3;
 }
 
 static void __cpuinit
 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
-        if (index < 3)
+        int node;
+
+        if (boot_cpu_data.x86 != 0x10)
                 return;
 
-        if (boot_cpu_data.x86 == 0x11)
+        if (index < 3)
                 return;
 
         /* see errata #382 and #388 */
-        if ((boot_cpu_data.x86 == 0x10) &&
-            ((boot_cpu_data.x86_model < 0x8) ||
-             (boot_cpu_data.x86_mask  < 0x1)))
+        if (boot_cpu_data.x86_model < 0x8)
                 return;
 
+        if ((boot_cpu_data.x86_model == 0x8 ||
+             boot_cpu_data.x86_model == 0x9)
+                &&
+             boot_cpu_data.x86_mask < 0x1)
+                        return;
+
         /* not in virtualized environments */
         if (num_k8_northbridges == 0)
                 return;
 
-        this_leaf->can_disable = true;
-        this_leaf->l3_indices  = amd_calc_l3_indices();
+        /*
+         * Strictly speaking, the amount in @size below is leaked since it is
+         * never freed but this is done only on shutdown so it doesn't matter.
+         */
+        if (!l3_caches) {
+                int size = num_k8_northbridges * sizeof(struct amd_l3_cache *);
+
+                l3_caches = kzalloc(size, GFP_ATOMIC);
+                if (!l3_caches)
+                        return;
+        }
+
+        node = amd_get_nb_id(smp_processor_id());
+
+        if (!l3_caches[node]) {
+                l3_caches[node] = amd_init_l3_cache(node);
+                l3_caches[node]->can_disable = true;
+        }
+
+        WARN_ON(!l3_caches[node]);
+
+        this_leaf->l3 = l3_caches[node];
 }
 
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
-                                  unsigned int index)
+                                  unsigned int slot)
 {
-        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-        int node = amd_get_nb_id(cpu);
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
+        struct pci_dev *dev = this_leaf->l3->dev;
         unsigned int reg = 0;
 
-        if (!this_leaf->can_disable)
+        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
                 return -EINVAL;
 
         if (!dev)
                 return -EINVAL;
 
-        pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
+        pci_read_config_dword(dev, 0x1BC + slot * 4, &reg);
         return sprintf(buf, "0x%08x\n", reg);
 }
 
-#define SHOW_CACHE_DISABLE(index)                                       \
+#define SHOW_CACHE_DISABLE(slot)                                        \
 static ssize_t                                                          \
-show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)   \
+show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf)    \
 {                                                                       \
-        return show_cache_disable(this_leaf, buf, index);               \
+        return show_cache_disable(this_leaf, buf, slot);                \
 }
 SHOW_CACHE_DISABLE(0)
 SHOW_CACHE_DISABLE(1)
 
+static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
+                                 unsigned slot, unsigned long idx)
+{
+        int i;
+
+        idx |= BIT(30);
+
+        /*
+         *  disable index in all 4 subcaches
+         */
+        for (i = 0; i < 4; i++) {
+                u32 reg = idx | (i << 20);
+
+                if (!l3->subcaches[i])
+                        continue;
+
+                pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
+
+                /*
+                 * We need to WBINVD on a core on the node containing the L3
+                 * cache which indices we disable therefore a simple wbinvd()
+                 * is not sufficient.
+                 */
+                wbinvd_on_cpu(cpu);
+
+                reg |= BIT(31);
+                pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
+        }
+}
+
+
 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
-        const char *buf, size_t count, unsigned int index)
+                                   const char *buf, size_t count,
+                                   unsigned int slot)
 {
+        struct pci_dev *dev = this_leaf->l3->dev;
         int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-        int node = amd_get_nb_id(cpu);
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
         unsigned long val = 0;
 
 #define SUBCACHE_MASK   (3UL << 20)
 #define SUBCACHE_INDEX  0xfff
 
-        if (!this_leaf->can_disable)
+        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
                 return -EINVAL;
 
         if (!capable(CAP_SYS_ADMIN))
@@ -400,26 +477,20 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 
         /* do not allow writes outside of allowed bits */
         if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
-            ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
+            ((val & SUBCACHE_INDEX) > this_leaf->l3->indices))
                 return -EINVAL;
 
-        val |= BIT(30);
-        pci_write_config_dword(dev, 0x1BC + index * 4, val);
-        /*
-         * We need to WBINVD on a core on the node containing the L3 cache which
-         * indices we disable therefore a simple wbinvd() is not sufficient.
-         */
-        wbinvd_on_cpu(cpu);
-        pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
+        amd_l3_disable_index(this_leaf->l3, cpu, slot, val);
+
         return count;
 }
 
-#define STORE_CACHE_DISABLE(index)                                      \
+#define STORE_CACHE_DISABLE(slot)                                       \
 static ssize_t                                                          \
-store_cache_disable_##index(struct _cpuid4_info *this_leaf,             \
+store_cache_disable_##slot(struct _cpuid4_info *this_leaf,              \
                             const char *buf, size_t count)              \
 {                                                                       \
-        return store_cache_disable(this_leaf, buf, count, index);       \
+        return store_cache_disable(this_leaf, buf, count, slot);        \
 }
 STORE_CACHE_DISABLE(0)
 STORE_CACHE_DISABLE(1)
@@ -447,8 +518,7 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
 
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
                 amd_cpuid4(index, &eax, &ebx, &ecx);
-                if (boot_cpu_data.x86 >= 0x10)
-                        amd_check_l3_disable(index, this_leaf);
+                amd_check_l3_disable(index, this_leaf);
         } else {
                 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
         }
@@ -705,6 +775,7 @@ static void __cpuinit free_cache_attributes(unsigned int cpu)
         for (i = 0; i < num_cache_leaves; i++)
                 cache_remove_shared_cpu_map(cpu, i);
 
+        kfree(per_cpu(ici_cpuid4_info, cpu)->l3);
         kfree(per_cpu(ici_cpuid4_info, cpu));
         per_cpu(ici_cpuid4_info, cpu) = NULL;
 }
@@ -989,7 +1060,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
 
                 this_leaf = CPUID4_INFO_IDX(cpu, i);
 
-                if (this_leaf->can_disable)
+                if (this_leaf->l3 && this_leaf->l3->can_disable)
                         ktype_cache.default_attrs = default_l3_attrs;
                 else
                         ktype_cache.default_attrs = default_attrs;