1 files changed, 33 insertions, 0 deletions

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index a135239badb7..2cbbf88d8f2c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -20,6 +20,7 @@
 #include <asm/processor.h>
 #include <asm/debugreg.h>
 #include <asm/sections.h>
+#include <asm/vsyscall.h>
 #include <linux/topology.h>
 #include <linux/cpumask.h>
 #include <asm/pgtable.h>
@@ -953,6 +954,38 @@ static void vgetcpu_set_mode(void)
         else
                 vgetcpu_mode = VGETCPU_LSL;
 }
+
+/* May not be __init: called during resume */
+static void syscall32_cpu_init(void)
+{
+        /* Load these always in case some future AMD CPU supports
+           SYSENTER from compat mode too. */
+        wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
+        wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
+        wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
+
+        wrmsrl(MSR_CSTAR, ia32_cstar_target);
+}
+#endif
+
+#ifdef CONFIG_X86_32
+void enable_sep_cpu(void)
+{
+        int cpu = get_cpu();
+        struct tss_struct *tss = &per_cpu(init_tss, cpu);
+
+        if (!boot_cpu_has(X86_FEATURE_SEP)) {
+                put_cpu();
+                return;
+        }
+
+        tss->x86_tss.ss1 = __KERNEL_CS;
+        tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss;
+        wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
+        wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0);
+        wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0);
+        put_cpu();
+}
 #endif
 
 void __init identify_boot_cpu(void)