1 files changed, 26 insertions, 12 deletions

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c6049650c093..2346c95c6ab1 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -19,6 +19,7 @@
 #include <asm/archrandom.h>
 #include <asm/hypervisor.h>
 #include <asm/processor.h>
+#include <asm/tlbflush.h>
 #include <asm/debugreg.h>
 #include <asm/sections.h>
 #include <asm/vsyscall.h>
@@ -278,7 +279,7 @@ __setup("nosmep", setup_disable_smep);
 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
 {
         if (cpu_has(c, X86_FEATURE_SMEP))
-                set_in_cr4(X86_CR4_SMEP);
+                cr4_set_bits(X86_CR4_SMEP);
 }
 
 static __init int setup_disable_smap(char *arg)
@@ -298,9 +299,9 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
 
         if (cpu_has(c, X86_FEATURE_SMAP)) {
 #ifdef CONFIG_X86_SMAP
-                set_in_cr4(X86_CR4_SMAP);
+                cr4_set_bits(X86_CR4_SMAP);
 #else
-                clear_in_cr4(X86_CR4_SMAP);
+                cr4_clear_bits(X86_CR4_SMAP);
 #endif
         }
 }
@@ -491,17 +492,18 @@ u16 __read_mostly tlb_lld_2m[NR_INFO];
 u16 __read_mostly tlb_lld_4m[NR_INFO];
 u16 __read_mostly tlb_lld_1g[NR_INFO];
 
-void cpu_detect_tlb(struct cpuinfo_x86 *c)
+static void cpu_detect_tlb(struct cpuinfo_x86 *c)
 {
         if (this_cpu->c_detect_tlb)
                 this_cpu->c_detect_tlb(c);
 
-        printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
-                "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
+        pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
-                tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
-                tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
-                tlb_lld_1g[ENTRIES]);
+                tlb_lli_4m[ENTRIES]);
+
+        pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
+                tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
+                tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
 }
 
 void detect_ht(struct cpuinfo_x86 *c)
@@ -1294,6 +1296,12 @@ void cpu_init(void)
         wait_for_master_cpu(cpu);
 
         /*
+         * Initialize the CR4 shadow before doing anything that could
+         * try to read it.
+         */
+        cr4_init_shadow();
+
+        /*
          * Load microcode on this cpu if a valid microcode is available.
          * This is early microcode loading procedure.
          */
@@ -1312,7 +1320,7 @@ void cpu_init(void)
 
         pr_debug("Initializing CPU#%d\n", cpu);
 
-        clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+        cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
         /*
          * Initialize the per-CPU GDT with the boot GDT,
@@ -1332,7 +1340,7 @@ void cpu_init(void)
         barrier();
 
         x86_configure_nx();
-        enable_x2apic();
+        x2apic_setup();
 
         /*
          * set up and load the per-CPU TSS
@@ -1388,12 +1396,18 @@ void cpu_init(void)
 
         wait_for_master_cpu(cpu);
 
+        /*
+         * Initialize the CR4 shadow before doing anything that could
+         * try to read it.
+         */
+        cr4_init_shadow();
+
         show_ucode_info_early();
 
         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
 
         if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)
-                clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+                cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
         load_current_idt();
         switch_to_new_gdt(cpu);