diff options
Diffstat (limited to 'arch/x86/kernel/cpu/amd.c')
-rw-r--r-- | arch/x86/kernel/cpu/amd.c | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 245866828294..81a07ca65d44 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -24,43 +24,6 @@ | |||
24 | extern void vide(void); | 24 | extern void vide(void); |
25 | __asm__(".align 4\nvide: ret"); | 25 | __asm__(".align 4\nvide: ret"); |
26 | 26 | ||
27 | #ifdef CONFIG_X86_LOCAL_APIC | ||
28 | #define ENABLE_C1E_MASK 0x18000000 | ||
29 | #define CPUID_PROCESSOR_SIGNATURE 1 | ||
30 | #define CPUID_XFAM 0x0ff00000 | ||
31 | #define CPUID_XFAM_K8 0x00000000 | ||
32 | #define CPUID_XFAM_10H 0x00100000 | ||
33 | #define CPUID_XFAM_11H 0x00200000 | ||
34 | #define CPUID_XMOD 0x000f0000 | ||
35 | #define CPUID_XMOD_REV_F 0x00040000 | ||
36 | |||
37 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ | ||
38 | static __cpuinit int amd_apic_timer_broken(void) | ||
39 | { | ||
40 | u32 lo, hi; | ||
41 | u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); | ||
42 | switch (eax & CPUID_XFAM) { | ||
43 | case CPUID_XFAM_K8: | ||
44 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) | ||
45 | break; | ||
46 | case CPUID_XFAM_10H: | ||
47 | case CPUID_XFAM_11H: | ||
48 | rdmsr(MSR_K8_ENABLE_C1E, lo, hi); | ||
49 | if (lo & ENABLE_C1E_MASK) { | ||
50 | if (smp_processor_id() != boot_cpu_physical_apicid) | ||
51 | printk(KERN_INFO "AMD C1E detected late. " | ||
52 | " Force timer broadcast.\n"); | ||
53 | return 1; | ||
54 | } | ||
55 | break; | ||
56 | default: | ||
57 | /* err on the side of caution */ | ||
58 | return 1; | ||
59 | } | ||
60 | return 0; | ||
61 | } | ||
62 | #endif | ||
63 | |||
64 | int force_mwait __cpuinitdata; | 27 | int force_mwait __cpuinitdata; |
65 | 28 | ||
66 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) | 29 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
@@ -297,11 +260,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |||
297 | num_cache_leaves = 3; | 260 | num_cache_leaves = 3; |
298 | } | 261 | } |
299 | 262 | ||
300 | #ifdef CONFIG_X86_LOCAL_APIC | ||
301 | if (amd_apic_timer_broken()) | ||
302 | local_apic_timer_disabled = 1; | ||
303 | #endif | ||
304 | |||
305 | /* K6s reports MCEs but don't actually have all the MSRs */ | 263 | /* K6s reports MCEs but don't actually have all the MSRs */ |
306 | if (c->x86 < 6) | 264 | if (c->x86 < 6) |
307 | clear_cpu_cap(c, X86_FEATURE_MCE); | 265 | clear_cpu_cap(c, X86_FEATURE_MCE); |